1 /* $Id: hfc_2bds0.c,v 1.18.2.6 2004/02/11 13:21:33 keil Exp $
3 * specific routines for CCD's HFC 2BDS0
6 * Copyright by Karsten Keil <keil@isdn4linux.de>
8 * This software may be used and distributed according to the terms
9 * of the GNU General Public License, incorporated herein by reference.
13 #include <linux/init.h>
15 #include "hfc_2bds0.h"
17 #include <linux/interrupt.h>
23 #define byteout(addr,val) outb(val,addr)
24 #define bytein(addr) inb(addr)
27 dummyf(struct IsdnCardState
*cs
, u_char
* data
, int size
)
29 printk(KERN_WARNING
"HiSax: hfcd dummy fifo called\n");
33 ReadReg(struct IsdnCardState
*cs
, int data
, u_char reg
)
38 if (cs
->hw
.hfcD
.cip
!= reg
) {
39 cs
->hw
.hfcD
.cip
= reg
;
40 byteout(cs
->hw
.hfcD
.addr
| 1, reg
);
42 ret
= bytein(cs
->hw
.hfcD
.addr
);
44 if (cs
->debug
& L1_DEB_HSCX_FIFO
&& (data
!= 2))
45 debugl1(cs
, "t3c RD %02x %02x", reg
, ret
);
48 ret
= bytein(cs
->hw
.hfcD
.addr
| 1);
53 WriteReg(struct IsdnCardState
*cs
, int data
, u_char reg
, u_char value
)
55 if (cs
->hw
.hfcD
.cip
!= reg
) {
56 cs
->hw
.hfcD
.cip
= reg
;
57 byteout(cs
->hw
.hfcD
.addr
| 1, reg
);
60 byteout(cs
->hw
.hfcD
.addr
, value
);
62 if (cs
->debug
& L1_DEB_HSCX_FIFO
&& (data
!= HFCD_DATA_NODEB
))
63 debugl1(cs
, "t3c W%c %02x %02x", data
? 'D' : 'C', reg
, value
);
67 /* Interface functions */
70 readreghfcd(struct IsdnCardState
*cs
, u_char offset
)
72 return(ReadReg(cs
, HFCD_DATA
, offset
));
76 writereghfcd(struct IsdnCardState
*cs
, u_char offset
, u_char value
)
78 WriteReg(cs
, HFCD_DATA
, offset
, value
);
82 WaitForBusy(struct IsdnCardState
*cs
)
86 while (!(ReadReg(cs
, HFCD_DATA
, HFCD_STAT
) & HFCD_BUSY
) && to
) {
91 printk(KERN_WARNING
"HiSax: WaitForBusy timeout\n");
96 WaitNoBusy(struct IsdnCardState
*cs
)
100 while ((ReadReg(cs
, HFCD_STATUS
, HFCD_STATUS
) & HFCD_BUSY
) && to
) {
105 printk(KERN_WARNING
"HiSax: WaitNoBusy timeout\n");
110 SelFiFo(struct IsdnCardState
*cs
, u_char FiFo
)
114 if (cs
->hw
.hfcD
.fifo
== FiFo
)
117 case 0: cip
= HFCB_FIFO
| HFCB_Z1
| HFCB_SEND
| HFCB_B1
;
119 case 1: cip
= HFCB_FIFO
| HFCB_Z1
| HFCB_REC
| HFCB_B1
;
121 case 2: cip
= HFCB_FIFO
| HFCB_Z1
| HFCB_SEND
| HFCB_B2
;
123 case 3: cip
= HFCB_FIFO
| HFCB_Z1
| HFCB_REC
| HFCB_B2
;
125 case 4: cip
= HFCD_FIFO
| HFCD_Z1
| HFCD_SEND
;
127 case 5: cip
= HFCD_FIFO
| HFCD_Z1
| HFCD_REC
;
130 debugl1(cs
, "SelFiFo Error");
133 cs
->hw
.hfcD
.fifo
= FiFo
;
135 cs
->BC_Write_Reg(cs
, HFCD_DATA
, cip
, 0);
141 GetFreeFifoBytes_B(struct BCState
*bcs
)
145 if (bcs
->hw
.hfc
.f1
== bcs
->hw
.hfc
.f2
)
146 return (bcs
->cs
->hw
.hfcD
.bfifosize
);
147 s
= bcs
->hw
.hfc
.send
[bcs
->hw
.hfc
.f1
] - bcs
->hw
.hfc
.send
[bcs
->hw
.hfc
.f2
];
149 s
+= bcs
->cs
->hw
.hfcD
.bfifosize
;
150 s
= bcs
->cs
->hw
.hfcD
.bfifosize
- s
;
155 GetFreeFifoBytes_D(struct IsdnCardState
*cs
)
159 if (cs
->hw
.hfcD
.f1
== cs
->hw
.hfcD
.f2
)
160 return (cs
->hw
.hfcD
.dfifosize
);
161 s
= cs
->hw
.hfcD
.send
[cs
->hw
.hfcD
.f1
] - cs
->hw
.hfcD
.send
[cs
->hw
.hfcD
.f2
];
163 s
+= cs
->hw
.hfcD
.dfifosize
;
164 s
= cs
->hw
.hfcD
.dfifosize
- s
;
169 ReadZReg(struct IsdnCardState
*cs
, u_char reg
)
174 val
= 256 * ReadReg(cs
, HFCD_DATA
, reg
| HFCB_Z_HIGH
);
176 val
+= ReadReg(cs
, HFCD_DATA
, reg
| HFCB_Z_LOW
);
180 static struct sk_buff
181 *hfc_empty_fifo(struct BCState
*bcs
, int count
)
185 struct IsdnCardState
*cs
= bcs
->cs
;
190 if ((cs
->debug
& L1_DEB_HSCX
) && !(cs
->debug
& L1_DEB_HSCX_FIFO
))
191 debugl1(cs
, "hfc_empty_fifo");
193 if (count
> HSCX_BUFMAX
+ 3) {
194 if (cs
->debug
& L1_DEB_WARN
)
195 debugl1(cs
, "hfc_empty_fifo: incoming packet too large");
196 cip
= HFCB_FIFO
| HFCB_FIFO_OUT
| HFCB_REC
| HFCB_CHANNEL(bcs
->channel
);
197 while (idx
++ < count
) {
199 ReadReg(cs
, HFCD_DATA_NODEB
, cip
);
202 } else if (count
< 4) {
203 if (cs
->debug
& L1_DEB_WARN
)
204 debugl1(cs
, "hfc_empty_fifo: incoming packet too small");
205 cip
= HFCB_FIFO
| HFCB_FIFO_OUT
| HFCB_REC
| HFCB_CHANNEL(bcs
->channel
);
206 #ifdef ERROR_STATISTIC
209 while ((idx
++ < count
) && WaitNoBusy(cs
))
210 ReadReg(cs
, HFCD_DATA_NODEB
, cip
);
212 } else if (!(skb
= dev_alloc_skb(count
- 3)))
213 printk(KERN_WARNING
"HFC: receive out of memory\n");
215 ptr
= skb_put(skb
, count
- 3);
217 cip
= HFCB_FIFO
| HFCB_FIFO_OUT
| HFCB_REC
| HFCB_CHANNEL(bcs
->channel
);
218 while (idx
< (count
- 3)) {
221 *ptr
= ReadReg(cs
, HFCD_DATA_NODEB
, cip
);
225 if (idx
!= count
- 3) {
226 debugl1(cs
, "RFIFO BUSY error");
227 printk(KERN_WARNING
"HFC FIFO channel %d BUSY Error\n", bcs
->channel
);
228 dev_kfree_skb_irq(skb
);
232 chksum
= (ReadReg(cs
, HFCD_DATA
, cip
) << 8);
234 chksum
+= ReadReg(cs
, HFCD_DATA
, cip
);
236 stat
= ReadReg(cs
, HFCD_DATA
, cip
);
237 if (cs
->debug
& L1_DEB_HSCX
)
238 debugl1(cs
, "hfc_empty_fifo %d chksum %x stat %x",
239 bcs
->channel
, chksum
, stat
);
241 debugl1(cs
, "FIFO CRC error");
242 dev_kfree_skb_irq(skb
);
244 #ifdef ERROR_STATISTIC
252 stat
= ReadReg(cs
, HFCD_DATA
, HFCB_FIFO
| HFCB_F2_INC
|
253 HFCB_REC
| HFCB_CHANNEL(bcs
->channel
));
259 hfc_fill_fifo(struct BCState
*bcs
)
261 struct IsdnCardState
*cs
= bcs
->cs
;
268 if (bcs
->tx_skb
->len
<= 0)
270 SelFiFo(cs
, HFCB_SEND
| HFCB_CHANNEL(bcs
->channel
));
271 cip
= HFCB_FIFO
| HFCB_F1
| HFCB_SEND
| HFCB_CHANNEL(bcs
->channel
);
273 bcs
->hw
.hfc
.f1
= ReadReg(cs
, HFCD_DATA
, cip
);
275 cip
= HFCB_FIFO
| HFCB_F2
| HFCB_SEND
| HFCB_CHANNEL(bcs
->channel
);
277 bcs
->hw
.hfc
.f2
= ReadReg(cs
, HFCD_DATA
, cip
);
278 bcs
->hw
.hfc
.send
[bcs
->hw
.hfc
.f1
] = ReadZReg(cs
, HFCB_FIFO
| HFCB_Z1
| HFCB_SEND
| HFCB_CHANNEL(bcs
->channel
));
279 if (cs
->debug
& L1_DEB_HSCX
)
280 debugl1(cs
, "hfc_fill_fifo %d f1(%d) f2(%d) z1(%x)",
281 bcs
->channel
, bcs
->hw
.hfc
.f1
, bcs
->hw
.hfc
.f2
,
282 bcs
->hw
.hfc
.send
[bcs
->hw
.hfc
.f1
]);
283 fcnt
= bcs
->hw
.hfc
.f1
- bcs
->hw
.hfc
.f2
;
287 if (cs
->debug
& L1_DEB_HSCX
)
288 debugl1(cs
, "hfc_fill_fifo more as 30 frames");
291 count
= GetFreeFifoBytes_B(bcs
);
292 if (cs
->debug
& L1_DEB_HSCX
)
293 debugl1(cs
, "hfc_fill_fifo %d count(%ld/%d),%lx",
294 bcs
->channel
, bcs
->tx_skb
->len
,
295 count
, current
->state
);
296 if (count
< bcs
->tx_skb
->len
) {
297 if (cs
->debug
& L1_DEB_HSCX
)
298 debugl1(cs
, "hfc_fill_fifo no fifo mem");
301 cip
= HFCB_FIFO
| HFCB_FIFO_IN
| HFCB_SEND
| HFCB_CHANNEL(bcs
->channel
);
305 WriteReg(cs
, HFCD_DATA_NODEB
, cip
, bcs
->tx_skb
->data
[idx
++]);
306 while (idx
< bcs
->tx_skb
->len
) {
309 WriteReg(cs
, HFCD_DATA_NODEB
, cip
, bcs
->tx_skb
->data
[idx
]);
312 if (idx
!= bcs
->tx_skb
->len
) {
313 debugl1(cs
, "FIFO Send BUSY error");
314 printk(KERN_WARNING
"HFC S FIFO channel %d BUSY Error\n", bcs
->channel
);
316 bcs
->tx_cnt
-= bcs
->tx_skb
->len
;
317 if (test_bit(FLG_LLI_L1WAKEUP
,&bcs
->st
->lli
.flag
) &&
318 (PACKET_NOACK
!= bcs
->tx_skb
->pkt_type
)) {
320 spin_lock_irqsave(&bcs
->aclock
, flags
);
321 bcs
->ackcnt
+= bcs
->tx_skb
->len
;
322 spin_unlock_irqrestore(&bcs
->aclock
, flags
);
323 schedule_event(bcs
, B_ACKPENDING
);
325 dev_kfree_skb_any(bcs
->tx_skb
);
330 ReadReg(cs
, HFCD_DATA
, HFCB_FIFO
| HFCB_F1_INC
| HFCB_SEND
| HFCB_CHANNEL(bcs
->channel
));
332 test_and_clear_bit(BC_FLG_BUSY
, &bcs
->Flag
);
337 hfc_send_data(struct BCState
*bcs
)
339 struct IsdnCardState
*cs
= bcs
->cs
;
341 if (!test_and_set_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
)) {
343 test_and_clear_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
);
345 debugl1(cs
,"send_data %d blocked", bcs
->channel
);
349 main_rec_2bds0(struct BCState
*bcs
)
351 struct IsdnCardState
*cs
= bcs
->cs
;
354 int receive
, count
= 5;
359 if (test_and_set_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
)) {
360 debugl1(cs
,"rec_data %d blocked", bcs
->channel
);
363 SelFiFo(cs
, HFCB_REC
| HFCB_CHANNEL(bcs
->channel
));
364 cip
= HFCB_FIFO
| HFCB_F1
| HFCB_REC
| HFCB_CHANNEL(bcs
->channel
);
366 f1
= ReadReg(cs
, HFCD_DATA
, cip
);
367 cip
= HFCB_FIFO
| HFCB_F2
| HFCB_REC
| HFCB_CHANNEL(bcs
->channel
);
369 f2
= ReadReg(cs
, HFCD_DATA
, cip
);
371 if (cs
->debug
& L1_DEB_HSCX
)
372 debugl1(cs
, "hfc rec %d f1(%d) f2(%d)",
373 bcs
->channel
, f1
, f2
);
374 z1
= ReadZReg(cs
, HFCB_FIFO
| HFCB_Z1
| HFCB_REC
| HFCB_CHANNEL(bcs
->channel
));
375 z2
= ReadZReg(cs
, HFCB_FIFO
| HFCB_Z2
| HFCB_REC
| HFCB_CHANNEL(bcs
->channel
));
378 rcnt
+= cs
->hw
.hfcD
.bfifosize
;
380 if (cs
->debug
& L1_DEB_HSCX
)
381 debugl1(cs
, "hfc rec %d z1(%x) z2(%x) cnt(%d)",
382 bcs
->channel
, z1
, z2
, rcnt
);
383 if ((skb
= hfc_empty_fifo(bcs
, rcnt
))) {
384 skb_queue_tail(&bcs
->rqueue
, skb
);
385 schedule_event(bcs
, B_RCVBUFREADY
);
396 test_and_clear_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
);
397 if (count
&& receive
)
403 mode_2bs0(struct BCState
*bcs
, int mode
, int bc
)
405 struct IsdnCardState
*cs
= bcs
->cs
;
407 if (cs
->debug
& L1_DEB_HSCX
)
408 debugl1(cs
, "HFCD bchannel mode %d bchan %d/%d",
409 mode
, bc
, bcs
->channel
);
415 cs
->hw
.hfcD
.conn
|= 0x18;
416 cs
->hw
.hfcD
.sctrl
&= ~SCTRL_B2_ENA
;
418 cs
->hw
.hfcD
.conn
|= 0x3;
419 cs
->hw
.hfcD
.sctrl
&= ~SCTRL_B1_ENA
;
422 case (L1_MODE_TRANS
):
424 cs
->hw
.hfcD
.ctmt
|= 2;
425 cs
->hw
.hfcD
.conn
&= ~0x18;
426 cs
->hw
.hfcD
.sctrl
|= SCTRL_B2_ENA
;
428 cs
->hw
.hfcD
.ctmt
|= 1;
429 cs
->hw
.hfcD
.conn
&= ~0x3;
430 cs
->hw
.hfcD
.sctrl
|= SCTRL_B1_ENA
;
435 cs
->hw
.hfcD
.ctmt
&= ~2;
436 cs
->hw
.hfcD
.conn
&= ~0x18;
437 cs
->hw
.hfcD
.sctrl
|= SCTRL_B2_ENA
;
439 cs
->hw
.hfcD
.ctmt
&= ~1;
440 cs
->hw
.hfcD
.conn
&= ~0x3;
441 cs
->hw
.hfcD
.sctrl
|= SCTRL_B1_ENA
;
445 WriteReg(cs
, HFCD_DATA
, HFCD_SCTRL
, cs
->hw
.hfcD
.sctrl
);
446 WriteReg(cs
, HFCD_DATA
, HFCD_CTMT
, cs
->hw
.hfcD
.ctmt
);
447 WriteReg(cs
, HFCD_DATA
, HFCD_CONN
, cs
->hw
.hfcD
.conn
);
451 hfc_l2l1(struct PStack
*st
, int pr
, void *arg
)
453 struct BCState
*bcs
= st
->l1
.bcs
;
454 struct sk_buff
*skb
= arg
;
458 case (PH_DATA
| REQUEST
):
459 spin_lock_irqsave(&bcs
->cs
->lock
, flags
);
461 skb_queue_tail(&bcs
->squeue
, skb
);
464 // test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
465 bcs
->cs
->BC_Send_Data(bcs
);
467 spin_unlock_irqrestore(&bcs
->cs
->lock
, flags
);
469 case (PH_PULL
| INDICATION
):
470 spin_lock_irqsave(&bcs
->cs
->lock
, flags
);
472 printk(KERN_WARNING
"hfc_l2l1: this shouldn't happen\n");
474 // test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
476 bcs
->cs
->BC_Send_Data(bcs
);
478 spin_unlock_irqrestore(&bcs
->cs
->lock
, flags
);
480 case (PH_PULL
| REQUEST
):
482 test_and_clear_bit(FLG_L1_PULL_REQ
, &st
->l1
.Flags
);
483 st
->l1
.l1l2(st
, PH_PULL
| CONFIRM
, NULL
);
485 test_and_set_bit(FLG_L1_PULL_REQ
, &st
->l1
.Flags
);
487 case (PH_ACTIVATE
| REQUEST
):
488 spin_lock_irqsave(&bcs
->cs
->lock
, flags
);
489 test_and_set_bit(BC_FLG_ACTIV
, &bcs
->Flag
);
490 mode_2bs0(bcs
, st
->l1
.mode
, st
->l1
.bc
);
491 spin_unlock_irqrestore(&bcs
->cs
->lock
, flags
);
492 l1_msg_b(st
, pr
, arg
);
494 case (PH_DEACTIVATE
| REQUEST
):
495 l1_msg_b(st
, pr
, arg
);
497 case (PH_DEACTIVATE
| CONFIRM
):
498 spin_lock_irqsave(&bcs
->cs
->lock
, flags
);
499 test_and_clear_bit(BC_FLG_ACTIV
, &bcs
->Flag
);
500 test_and_clear_bit(BC_FLG_BUSY
, &bcs
->Flag
);
501 mode_2bs0(bcs
, 0, st
->l1
.bc
);
502 spin_unlock_irqrestore(&bcs
->cs
->lock
, flags
);
503 st
->l1
.l1l2(st
, PH_DEACTIVATE
| CONFIRM
, NULL
);
509 close_2bs0(struct BCState
*bcs
)
511 mode_2bs0(bcs
, 0, bcs
->channel
);
512 if (test_and_clear_bit(BC_FLG_INIT
, &bcs
->Flag
)) {
513 skb_queue_purge(&bcs
->rqueue
);
514 skb_queue_purge(&bcs
->squeue
);
516 dev_kfree_skb_any(bcs
->tx_skb
);
518 test_and_clear_bit(BC_FLG_BUSY
, &bcs
->Flag
);
524 open_hfcstate(struct IsdnCardState
*cs
, struct BCState
*bcs
)
526 if (!test_and_set_bit(BC_FLG_INIT
, &bcs
->Flag
)) {
527 skb_queue_head_init(&bcs
->rqueue
);
528 skb_queue_head_init(&bcs
->squeue
);
531 test_and_clear_bit(BC_FLG_BUSY
, &bcs
->Flag
);
538 setstack_2b(struct PStack
*st
, struct BCState
*bcs
)
540 bcs
->channel
= st
->l1
.bc
;
541 if (open_hfcstate(st
->l1
.hardware
, bcs
))
544 st
->l2
.l2l1
= hfc_l2l1
;
545 setstack_manager(st
);
552 hfcd_bh(struct IsdnCardState
*cs
)
556 if (test_and_clear_bit(D_L1STATECHANGE
, &cs
->event
)) {
557 switch (cs
->dc
.hfcd
.ph_state
) {
559 l1_msg(cs
, HW_RESET
| INDICATION
, NULL
);
562 l1_msg(cs
, HW_DEACTIVATE
| INDICATION
, NULL
);
565 l1_msg(cs
, HW_RSYNC
| INDICATION
, NULL
);
568 l1_msg(cs
, HW_INFO2
| INDICATION
, NULL
);
571 l1_msg(cs
, HW_INFO4_P8
| INDICATION
, NULL
);
577 if (test_and_clear_bit(D_RCVBUFREADY
, &cs
->event
))
578 DChannel_proc_rcv(cs
);
579 if (test_and_clear_bit(D_XMTBUFREADY
, &cs
->event
))
580 DChannel_proc_xmt(cs
);
584 int receive_dmsg(struct IsdnCardState
*cs
)
589 u_char stat
, cip
, f1
, f2
;
594 if (test_and_set_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
)) {
595 debugl1(cs
, "rec_dmsg blocked");
598 SelFiFo(cs
, 4 | HFCD_REC
);
599 cip
= HFCD_FIFO
| HFCD_F1
| HFCD_REC
;
601 f1
= cs
->readisac(cs
, cip
) & 0xf;
602 cip
= HFCD_FIFO
| HFCD_F2
| HFCD_REC
;
604 f2
= cs
->readisac(cs
, cip
) & 0xf;
605 while ((f1
!= f2
) && count
--) {
606 z1
= ReadZReg(cs
, HFCD_FIFO
| HFCD_Z1
| HFCD_REC
);
607 z2
= ReadZReg(cs
, HFCD_FIFO
| HFCD_Z2
| HFCD_REC
);
610 rcnt
+= cs
->hw
.hfcD
.dfifosize
;
612 if (cs
->debug
& L1_DEB_ISAC
)
613 debugl1(cs
, "hfcd recd f1(%d) f2(%d) z1(%x) z2(%x) cnt(%d)",
614 f1
, f2
, z1
, z2
, rcnt
);
616 cip
= HFCD_FIFO
| HFCD_FIFO_OUT
| HFCD_REC
;
617 if (rcnt
> MAX_DFRAME_LEN
+ 3) {
618 if (cs
->debug
& L1_DEB_WARN
)
619 debugl1(cs
, "empty_fifo d: incoming packet too large");
621 if (!(WaitNoBusy(cs
)))
623 ReadReg(cs
, HFCD_DATA_NODEB
, cip
);
626 } else if (rcnt
< 4) {
627 if (cs
->debug
& L1_DEB_WARN
)
628 debugl1(cs
, "empty_fifo d: incoming packet too small");
629 while ((idx
++ < rcnt
) && WaitNoBusy(cs
))
630 ReadReg(cs
, HFCD_DATA_NODEB
, cip
);
631 } else if ((skb
= dev_alloc_skb(rcnt
- 3))) {
632 ptr
= skb_put(skb
, rcnt
- 3);
633 while (idx
< (rcnt
- 3)) {
634 if (!(WaitNoBusy(cs
)))
636 *ptr
= ReadReg(cs
, HFCD_DATA_NODEB
, cip
);
640 if (idx
!= (rcnt
- 3)) {
641 debugl1(cs
, "RFIFO D BUSY error");
642 printk(KERN_WARNING
"HFC DFIFO channel BUSY Error\n");
643 dev_kfree_skb_irq(skb
);
645 #ifdef ERROR_STATISTIC
650 chksum
= (ReadReg(cs
, HFCD_DATA
, cip
) << 8);
652 chksum
+= ReadReg(cs
, HFCD_DATA
, cip
);
654 stat
= ReadReg(cs
, HFCD_DATA
, cip
);
655 if (cs
->debug
& L1_DEB_ISAC
)
656 debugl1(cs
, "empty_dfifo chksum %x stat %x",
659 debugl1(cs
, "FIFO CRC error");
660 dev_kfree_skb_irq(skb
);
662 #ifdef ERROR_STATISTIC
666 skb_queue_tail(&cs
->rq
, skb
);
667 schedule_event(cs
, D_RCVBUFREADY
);
671 printk(KERN_WARNING
"HFC: D receive out of memory\n");
673 cip
= HFCD_FIFO
| HFCD_F2_INC
| HFCD_REC
;
675 stat
= ReadReg(cs
, HFCD_DATA
, cip
);
677 cip
= HFCD_FIFO
| HFCD_F2
| HFCD_REC
;
679 f2
= cs
->readisac(cs
, cip
) & 0xf;
681 test_and_clear_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
);
686 hfc_fill_dfifo(struct IsdnCardState
*cs
)
694 if (cs
->tx_skb
->len
<= 0)
697 SelFiFo(cs
, 4 | HFCD_SEND
);
698 cip
= HFCD_FIFO
| HFCD_F1
| HFCD_SEND
;
700 cs
->hw
.hfcD
.f1
= ReadReg(cs
, HFCD_DATA
, cip
) & 0xf;
702 cip
= HFCD_FIFO
| HFCD_F2
| HFCD_SEND
;
703 cs
->hw
.hfcD
.f2
= ReadReg(cs
, HFCD_DATA
, cip
) & 0xf;
704 cs
->hw
.hfcD
.send
[cs
->hw
.hfcD
.f1
] = ReadZReg(cs
, HFCD_FIFO
| HFCD_Z1
| HFCD_SEND
);
705 if (cs
->debug
& L1_DEB_ISAC
)
706 debugl1(cs
, "hfc_fill_Dfifo f1(%d) f2(%d) z1(%x)",
707 cs
->hw
.hfcD
.f1
, cs
->hw
.hfcD
.f2
,
708 cs
->hw
.hfcD
.send
[cs
->hw
.hfcD
.f1
]);
709 fcnt
= cs
->hw
.hfcD
.f1
- cs
->hw
.hfcD
.f2
;
713 if (cs
->debug
& L1_DEB_HSCX
)
714 debugl1(cs
, "hfc_fill_Dfifo more as 14 frames");
717 count
= GetFreeFifoBytes_D(cs
);
718 if (cs
->debug
& L1_DEB_ISAC
)
719 debugl1(cs
, "hfc_fill_Dfifo count(%ld/%d)",
720 cs
->tx_skb
->len
, count
);
721 if (count
< cs
->tx_skb
->len
) {
722 if (cs
->debug
& L1_DEB_ISAC
)
723 debugl1(cs
, "hfc_fill_Dfifo no fifo mem");
726 cip
= HFCD_FIFO
| HFCD_FIFO_IN
| HFCD_SEND
;
730 WriteReg(cs
, HFCD_DATA_NODEB
, cip
, cs
->tx_skb
->data
[idx
++]);
731 while (idx
< cs
->tx_skb
->len
) {
732 if (!(WaitNoBusy(cs
)))
734 WriteReg(cs
, HFCD_DATA_NODEB
, cip
, cs
->tx_skb
->data
[idx
]);
737 if (idx
!= cs
->tx_skb
->len
) {
738 debugl1(cs
, "DFIFO Send BUSY error");
739 printk(KERN_WARNING
"HFC S DFIFO channel BUSY Error\n");
743 ReadReg(cs
, HFCD_DATA
, HFCD_FIFO
| HFCD_F1_INC
| HFCD_SEND
);
744 dev_kfree_skb_any(cs
->tx_skb
);
751 struct BCState
*Sel_BCS(struct IsdnCardState
*cs
, int channel
)
753 if (cs
->bcs
[0].mode
&& (cs
->bcs
[0].channel
== channel
))
755 else if (cs
->bcs
[1].mode
&& (cs
->bcs
[1].channel
== channel
))
762 hfc2bds0_interrupt(struct IsdnCardState
*cs
, u_char val
)
768 if (cs
->debug
& L1_DEB_ISAC
)
769 debugl1(cs
, "HFCD irq %x %s", val
,
770 test_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
) ?
771 "locked" : "unlocked");
772 val
&= cs
->hw
.hfcD
.int_m1
;
773 if (val
& 0x40) { /* TE state machine irq */
774 exval
= cs
->readisac(cs
, HFCD_STATES
) & 0xf;
775 if (cs
->debug
& L1_DEB_ISAC
)
776 debugl1(cs
, "ph_state chg %d->%d", cs
->dc
.hfcd
.ph_state
,
778 cs
->dc
.hfcd
.ph_state
= exval
;
779 schedule_event(cs
, D_L1STATECHANGE
);
783 if (test_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
)) {
784 cs
->hw
.hfcD
.int_s1
|= val
;
787 if (cs
->hw
.hfcD
.int_s1
& 0x18) {
789 val
= cs
->hw
.hfcD
.int_s1
;
790 cs
->hw
.hfcD
.int_s1
= exval
;
793 if (!(bcs
=Sel_BCS(cs
, 0))) {
795 debugl1(cs
, "hfcd spurious 0x08 IRQ");
800 if (!(bcs
=Sel_BCS(cs
, 1))) {
802 debugl1(cs
, "hfcd spurious 0x10 IRQ");
807 if (!(bcs
=Sel_BCS(cs
, 0))) {
809 debugl1(cs
, "hfcd spurious 0x01 IRQ");
812 if (!test_and_set_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
)) {
814 test_and_clear_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
);
816 debugl1(cs
,"fill_data %d blocked", bcs
->channel
);
818 if ((bcs
->tx_skb
= skb_dequeue(&bcs
->squeue
))) {
819 if (!test_and_set_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
)) {
821 test_and_clear_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
);
823 debugl1(cs
,"fill_data %d blocked", bcs
->channel
);
825 schedule_event(bcs
, B_XMTBUFREADY
);
831 if (!(bcs
=Sel_BCS(cs
, 1))) {
833 debugl1(cs
, "hfcd spurious 0x02 IRQ");
836 if (!test_and_set_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
)) {
838 test_and_clear_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
);
840 debugl1(cs
,"fill_data %d blocked", bcs
->channel
);
842 if ((bcs
->tx_skb
= skb_dequeue(&bcs
->squeue
))) {
843 if (!test_and_set_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
)) {
845 test_and_clear_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
);
847 debugl1(cs
,"fill_data %d blocked", bcs
->channel
);
849 schedule_event(bcs
, B_XMTBUFREADY
);
854 if (val
& 0x20) { /* receive dframe */
857 if (val
& 0x04) { /* dframe transmitted */
858 if (test_and_clear_bit(FLG_DBUSY_TIMER
, &cs
->HW_Flags
))
859 del_timer(&cs
->dbusytimer
);
860 if (test_and_clear_bit(FLG_L1_DBUSY
, &cs
->HW_Flags
))
861 schedule_event(cs
, D_CLEARBUSY
);
863 if (cs
->tx_skb
->len
) {
864 if (!test_and_set_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
)) {
866 test_and_clear_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
);
868 debugl1(cs
, "hfc_fill_dfifo irq blocked");
872 dev_kfree_skb_irq(cs
->tx_skb
);
877 if ((cs
->tx_skb
= skb_dequeue(&cs
->sq
))) {
879 if (!test_and_set_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
)) {
881 test_and_clear_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
);
883 debugl1(cs
, "hfc_fill_dfifo irq blocked");
886 schedule_event(cs
, D_XMTBUFREADY
);
889 if (cs
->hw
.hfcD
.int_s1
&& count
--) {
890 val
= cs
->hw
.hfcD
.int_s1
;
891 cs
->hw
.hfcD
.int_s1
= 0;
892 if (cs
->debug
& L1_DEB_ISAC
)
893 debugl1(cs
, "HFCD irq %x loop %d", val
, 15-count
);
900 HFCD_l1hw(struct PStack
*st
, int pr
, void *arg
)
902 struct IsdnCardState
*cs
= (struct IsdnCardState
*) st
->l1
.hardware
;
903 struct sk_buff
*skb
= arg
;
907 case (PH_DATA
| REQUEST
):
908 if (cs
->debug
& DEB_DLOG_HEX
)
909 LogFrame(cs
, skb
->data
, skb
->len
);
910 if (cs
->debug
& DEB_DLOG_VERBOSE
)
911 dlogframe(cs
, skb
, 0);
912 spin_lock_irqsave(&cs
->lock
, flags
);
914 skb_queue_tail(&cs
->sq
, skb
);
915 #ifdef L2FRAME_DEBUG /* psa */
916 if (cs
->debug
& L1_DEB_LAPD
)
917 Logl2Frame(cs
, skb
, "PH_DATA Queued", 0);
922 #ifdef L2FRAME_DEBUG /* psa */
923 if (cs
->debug
& L1_DEB_LAPD
)
924 Logl2Frame(cs
, skb
, "PH_DATA", 0);
926 if (!test_and_set_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
)) {
928 test_and_clear_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
);
930 debugl1(cs
, "hfc_fill_dfifo blocked");
933 spin_unlock_irqrestore(&cs
->lock
, flags
);
935 case (PH_PULL
| INDICATION
):
936 spin_lock_irqsave(&cs
->lock
, flags
);
938 if (cs
->debug
& L1_DEB_WARN
)
939 debugl1(cs
, " l2l1 tx_skb exist this shouldn't happen");
940 skb_queue_tail(&cs
->sq
, skb
);
941 spin_unlock_irqrestore(&cs
->lock
, flags
);
944 if (cs
->debug
& DEB_DLOG_HEX
)
945 LogFrame(cs
, skb
->data
, skb
->len
);
946 if (cs
->debug
& DEB_DLOG_VERBOSE
)
947 dlogframe(cs
, skb
, 0);
950 #ifdef L2FRAME_DEBUG /* psa */
951 if (cs
->debug
& L1_DEB_LAPD
)
952 Logl2Frame(cs
, skb
, "PH_DATA_PULLED", 0);
954 if (!test_and_set_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
)) {
956 test_and_clear_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
);
958 debugl1(cs
, "hfc_fill_dfifo blocked");
959 spin_unlock_irqrestore(&cs
->lock
, flags
);
961 case (PH_PULL
| REQUEST
):
962 #ifdef L2FRAME_DEBUG /* psa */
963 if (cs
->debug
& L1_DEB_LAPD
)
964 debugl1(cs
, "-> PH_REQUEST_PULL");
967 test_and_clear_bit(FLG_L1_PULL_REQ
, &st
->l1
.Flags
);
968 st
->l1
.l1l2(st
, PH_PULL
| CONFIRM
, NULL
);
970 test_and_set_bit(FLG_L1_PULL_REQ
, &st
->l1
.Flags
);
972 case (HW_RESET
| REQUEST
):
973 spin_lock_irqsave(&cs
->lock
, flags
);
974 cs
->writeisac(cs
, HFCD_STATES
, HFCD_LOAD_STATE
| 3); /* HFC ST 3 */
976 cs
->writeisac(cs
, HFCD_STATES
, 3); /* HFC ST 2 */
977 cs
->hw
.hfcD
.mst_m
|= HFCD_MASTER
;
978 cs
->writeisac(cs
, HFCD_MST_MODE
, cs
->hw
.hfcD
.mst_m
);
979 cs
->writeisac(cs
, HFCD_STATES
, HFCD_ACTIVATE
| HFCD_DO_ACTION
);
980 spin_unlock_irqrestore(&cs
->lock
, flags
);
981 l1_msg(cs
, HW_POWERUP
| CONFIRM
, NULL
);
983 case (HW_ENABLE
| REQUEST
):
984 spin_lock_irqsave(&cs
->lock
, flags
);
985 cs
->writeisac(cs
, HFCD_STATES
, HFCD_ACTIVATE
| HFCD_DO_ACTION
);
986 spin_unlock_irqrestore(&cs
->lock
, flags
);
988 case (HW_DEACTIVATE
| REQUEST
):
989 spin_lock_irqsave(&cs
->lock
, flags
);
990 cs
->hw
.hfcD
.mst_m
&= ~HFCD_MASTER
;
991 cs
->writeisac(cs
, HFCD_MST_MODE
, cs
->hw
.hfcD
.mst_m
);
992 spin_unlock_irqrestore(&cs
->lock
, flags
);
994 case (HW_INFO3
| REQUEST
):
995 spin_lock_irqsave(&cs
->lock
, flags
);
996 cs
->hw
.hfcD
.mst_m
|= HFCD_MASTER
;
997 cs
->writeisac(cs
, HFCD_MST_MODE
, cs
->hw
.hfcD
.mst_m
);
998 spin_unlock_irqrestore(&cs
->lock
, flags
);
1001 if (cs
->debug
& L1_DEB_WARN
)
1002 debugl1(cs
, "hfcd_l1hw unknown pr %4x", pr
);
1008 setstack_hfcd(struct PStack
*st
, struct IsdnCardState
*cs
)
1010 st
->l1
.l1hw
= HFCD_l1hw
;
1014 hfc_dbusy_timer(struct IsdnCardState
*cs
)
1018 static unsigned int __init
1019 *init_send_hfcd(int cnt
)
1023 if (!(send
= kmalloc(cnt
* sizeof(unsigned int), GFP_ATOMIC
))) {
1025 "HiSax: No memory for hfcd.send\n");
1028 for (i
= 0; i
< cnt
; i
++)
1034 init2bds0(struct IsdnCardState
*cs
)
1036 cs
->setstack_d
= setstack_hfcd
;
1037 if (!cs
->hw
.hfcD
.send
)
1038 cs
->hw
.hfcD
.send
= init_send_hfcd(16);
1039 if (!cs
->bcs
[0].hw
.hfc
.send
)
1040 cs
->bcs
[0].hw
.hfc
.send
= init_send_hfcd(32);
1041 if (!cs
->bcs
[1].hw
.hfc
.send
)
1042 cs
->bcs
[1].hw
.hfc
.send
= init_send_hfcd(32);
1043 cs
->BC_Send_Data
= &hfc_send_data
;
1044 cs
->bcs
[0].BC_SetStack
= setstack_2b
;
1045 cs
->bcs
[1].BC_SetStack
= setstack_2b
;
1046 cs
->bcs
[0].BC_Close
= close_2bs0
;
1047 cs
->bcs
[1].BC_Close
= close_2bs0
;
1048 mode_2bs0(cs
->bcs
, 0, 0);
1049 mode_2bs0(cs
->bcs
+ 1, 0, 1);
1053 release2bds0(struct IsdnCardState
*cs
)
1055 kfree(cs
->bcs
[0].hw
.hfc
.send
);
1056 cs
->bcs
[0].hw
.hfc
.send
= NULL
;
1057 kfree(cs
->bcs
[1].hw
.hfc
.send
);
1058 cs
->bcs
[1].hw
.hfc
.send
= NULL
;
1059 kfree(cs
->hw
.hfcD
.send
);
1060 cs
->hw
.hfcD
.send
= NULL
;
1064 set_cs_func(struct IsdnCardState
*cs
)
1066 cs
->readisac
= &readreghfcd
;
1067 cs
->writeisac
= &writereghfcd
;
1068 cs
->readisacfifo
= &dummyf
;
1069 cs
->writeisacfifo
= &dummyf
;
1070 cs
->BC_Read_Reg
= &ReadReg
;
1071 cs
->BC_Write_Reg
= &WriteReg
;
1072 cs
->dbusytimer
.function
= (void *) hfc_dbusy_timer
;
1073 cs
->dbusytimer
.data
= (long) cs
;
1074 init_timer(&cs
->dbusytimer
);
1075 INIT_WORK(&cs
->tqueue
, (void *)(void *) hfcd_bh
, cs
);