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[PATCH] Represent laptop_mode as jiffies internally
[linux-2.6/verdex.git] / drivers / isdn / hisax / hfc_pci.c
blob91d25acb5ede07f39d8859204e5b6daa9f150315
1 /* $Id: hfc_pci.c,v 1.48.2.4 2004/02/11 13:21:33 keil Exp $
2 *
3 * low level driver for CCD´s hfc-pci based cards
4 *
5 * Author Werner Cornelius
6 * based on existing driver for CCD hfc ISA cards
7 * Copyright by Werner Cornelius <werner@isdn4linux.de>
8 * by Karsten Keil <keil@isdn4linux.de>
9 *
10 * This software may be used and distributed according to the terms
11 * of the GNU General Public License, incorporated herein by reference.
12 *
13 * For changes and modifications please read
14 * Documentation/isdn/HiSax.cert
15 *
16 */
17
18 #include <linux/init.h>
19 #include <linux/config.h>
20 #include "hisax.h"
21 #include "hfc_pci.h"
22 #include "isdnl1.h"
23 #include <linux/pci.h>
24 #include <linux/interrupt.h>
25
26 extern const char *CardType[];
27
28 static const char *hfcpci_revision = "$Revision: 1.48.2.4 $";
29
30 /* table entry in the PCI devices list */
31 typedef struct {
32 int vendor_id;
33 int device_id;
34 char *vendor_name;
35 char *card_name;
36 } PCI_ENTRY;
37
38 #define NT_T1_COUNT 20 /* number of 3.125ms interrupts for G2 timeout */
39 #define CLKDEL_TE 0x0e /* CLKDEL in TE mode */
40 #define CLKDEL_NT 0x6c /* CLKDEL in NT mode */
41
42 static const PCI_ENTRY id_list[] =
43 {
44 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_2BD0, "CCD/Billion/Asuscom", "2BD0"},
45 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B000, "Billion", "B000"},
46 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B006, "Billion", "B006"},
47 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B007, "Billion", "B007"},
48 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B008, "Billion", "B008"},
49 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B009, "Billion", "B009"},
50 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B00A, "Billion", "B00A"},
51 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B00B, "Billion", "B00B"},
52 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B00C, "Billion", "B00C"},
53 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B100, "Seyeon", "B100"},
54 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B700, "Primux II S0", "B700"},
55 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B701, "Primux II S0 NT", "B701"},
56 {PCI_VENDOR_ID_ABOCOM, PCI_DEVICE_ID_ABOCOM_2BD1, "Abocom/Magitek", "2BD1"},
57 {PCI_VENDOR_ID_ASUSTEK, PCI_DEVICE_ID_ASUSTEK_0675, "Asuscom/Askey", "675"},
58 {PCI_VENDOR_ID_BERKOM, PCI_DEVICE_ID_BERKOM_T_CONCEPT, "German telekom", "T-Concept"},
59 {PCI_VENDOR_ID_BERKOM, PCI_DEVICE_ID_BERKOM_A1T, "German telekom", "A1T"},
60 {PCI_VENDOR_ID_ANIGMA, PCI_DEVICE_ID_ANIGMA_MC145575, "Motorola MC145575", "MC145575"},
61 {PCI_VENDOR_ID_ZOLTRIX, PCI_DEVICE_ID_ZOLTRIX_2BD0, "Zoltrix", "2BD0"},
62 {PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_DF_M_IOM2_E,"Digi International", "Digi DataFire Micro V IOM2 (Europe)"},
63 {PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_DF_M_E,"Digi International", "Digi DataFire Micro V (Europe)"},
64 {PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_DF_M_IOM2_A,"Digi International", "Digi DataFire Micro V IOM2 (North America)"},
65 {PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_DF_M_A,"Digi International", "Digi DataFire Micro V (North America)"},
66 {PCI_VENDOR_ID_SITECOM, PCI_DEVICE_ID_SITECOM_DC105V2, "Sitecom Europe", "DC-105 ISDN PCI"},
67 {0, 0, NULL, NULL},
68 };
69
70
71 #ifdef CONFIG_PCI
72
73 /******************************************/
74 /* free hardware resources used by driver */
75 /******************************************/
76 static void
77 release_io_hfcpci(struct IsdnCardState *cs)
78 {
79 printk(KERN_INFO "HiSax: release hfcpci at %p\n",
80 cs->hw.hfcpci.pci_io);
81 cs->hw.hfcpci.int_m2 = 0; /* interrupt output off ! */
82 Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2);
83 Write_hfc(cs, HFCPCI_CIRM, HFCPCI_RESET); /* Reset On */
84 mdelay(10);
85 Write_hfc(cs, HFCPCI_CIRM, 0); /* Reset Off */
86 mdelay(10);
87 Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2);
88 pci_write_config_word(cs->hw.hfcpci.dev, PCI_COMMAND, 0); /* disable memory mapped ports + busmaster */
89 del_timer(&cs->hw.hfcpci.timer);
90 kfree(cs->hw.hfcpci.share_start);
91 cs->hw.hfcpci.share_start = NULL;
92 iounmap((void *)cs->hw.hfcpci.pci_io);
93 }
94
95 /********************************************************************************/
96 /* function called to reset the HFC PCI chip. A complete software reset of chip */
97 /* and fifos is done. */
98 /********************************************************************************/
99 static void
100 reset_hfcpci(struct IsdnCardState *cs)
101 {
102 pci_write_config_word(cs->hw.hfcpci.dev, PCI_COMMAND, PCI_ENA_MEMIO); /* enable memory mapped ports, disable busmaster */
103 cs->hw.hfcpci.int_m2 = 0; /* interrupt output off ! */
104 Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2);
105
106 printk(KERN_INFO "HFC_PCI: resetting card\n");
107 pci_write_config_word(cs->hw.hfcpci.dev, PCI_COMMAND, PCI_ENA_MEMIO + PCI_ENA_MASTER); /* enable memory ports + busmaster */
108 Write_hfc(cs, HFCPCI_CIRM, HFCPCI_RESET); /* Reset On */
109 mdelay(10);
110 Write_hfc(cs, HFCPCI_CIRM, 0); /* Reset Off */
111 mdelay(10);
112 if (Read_hfc(cs, HFCPCI_STATUS) & 2)
113 printk(KERN_WARNING "HFC-PCI init bit busy\n");
114
115 cs->hw.hfcpci.fifo_en = 0x30; /* only D fifos enabled */
116 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en);
117
118 cs->hw.hfcpci.trm = 0 + HFCPCI_BTRANS_THRESMASK; /* no echo connect , threshold */
119 Write_hfc(cs, HFCPCI_TRM, cs->hw.hfcpci.trm);
120
121 Write_hfc(cs, HFCPCI_CLKDEL, CLKDEL_TE); /* ST-Bit delay for TE-Mode */
122 cs->hw.hfcpci.sctrl_e = HFCPCI_AUTO_AWAKE;
123 Write_hfc(cs, HFCPCI_SCTRL_E, cs->hw.hfcpci.sctrl_e); /* S/T Auto awake */
124 cs->hw.hfcpci.bswapped = 0; /* no exchange */
125 cs->hw.hfcpci.nt_mode = 0; /* we are in TE mode */
126 cs->hw.hfcpci.ctmt = HFCPCI_TIM3_125 | HFCPCI_AUTO_TIMER;
127 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt);
128
129 cs->hw.hfcpci.int_m1 = HFCPCI_INTS_DTRANS | HFCPCI_INTS_DREC |
130 HFCPCI_INTS_L1STATE | HFCPCI_INTS_TIMER;
131 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
132
133 /* Clear already pending ints */
134 if (Read_hfc(cs, HFCPCI_INT_S1));
135
136 Write_hfc(cs, HFCPCI_STATES, HFCPCI_LOAD_STATE | 2); /* HFC ST 2 */
137 udelay(10);
138 Write_hfc(cs, HFCPCI_STATES, 2); /* HFC ST 2 */
139 cs->hw.hfcpci.mst_m = HFCPCI_MASTER; /* HFC Master Mode */
140
141 Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m);
142 cs->hw.hfcpci.sctrl = 0x40; /* set tx_lo mode, error in datasheet ! */
143 Write_hfc(cs, HFCPCI_SCTRL, cs->hw.hfcpci.sctrl);
144 cs->hw.hfcpci.sctrl_r = 0;
145 Write_hfc(cs, HFCPCI_SCTRL_R, cs->hw.hfcpci.sctrl_r);
146
147 /* Init GCI/IOM2 in master mode */
148 /* Slots 0 and 1 are set for B-chan 1 and 2 */
149 /* D- and monitor/CI channel are not enabled */
150 /* STIO1 is used as output for data, B1+B2 from ST->IOM+HFC */
151 /* STIO2 is used as data input, B1+B2 from IOM->ST */
152 /* ST B-channel send disabled -> continous 1s */
153 /* The IOM slots are always enabled */
154 cs->hw.hfcpci.conn = 0x36; /* set data flow directions */
155 Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn);
156 Write_hfc(cs, HFCPCI_B1_SSL, 0x80); /* B1-Slot 0 STIO1 out enabled */
157 Write_hfc(cs, HFCPCI_B2_SSL, 0x81); /* B2-Slot 1 STIO1 out enabled */
158 Write_hfc(cs, HFCPCI_B1_RSL, 0x80); /* B1-Slot 0 STIO2 in enabled */
159 Write_hfc(cs, HFCPCI_B2_RSL, 0x81); /* B2-Slot 1 STIO2 in enabled */
160
161 /* Finally enable IRQ output */
162 cs->hw.hfcpci.int_m2 = HFCPCI_IRQ_ENABLE;
163 Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2);
164 if (Read_hfc(cs, HFCPCI_INT_S1));
165 }
166
167 /***************************************************/
168 /* Timer function called when kernel timer expires */
169 /***************************************************/
170 static void
171 hfcpci_Timer(struct IsdnCardState *cs)
172 {
173 cs->hw.hfcpci.timer.expires = jiffies + 75;
174 /* WD RESET */
175 /* WriteReg(cs, HFCD_DATA, HFCD_CTMT, cs->hw.hfcpci.ctmt | 0x80);
176 add_timer(&cs->hw.hfcpci.timer);
177 */
178 }
179
180
181 /*********************************/
182 /* schedule a new D-channel task */
183 /*********************************/
184 static void
185 sched_event_D_pci(struct IsdnCardState *cs, int event)
186 {
187 test_and_set_bit(event, &cs->event);
188 schedule_work(&cs->tqueue);
189 }
190
191 /*********************************/
192 /* schedule a new b_channel task */
193 /*********************************/
194 static void
195 hfcpci_sched_event(struct BCState *bcs, int event)
196 {
197 test_and_set_bit(event, &bcs->event);
198 schedule_work(&bcs->tqueue);
199 }
200
201 /************************************************/
202 /* select a b-channel entry matching and active */
203 /************************************************/
204 static
205 struct BCState *
206 Sel_BCS(struct IsdnCardState *cs, int channel)
207 {
208 if (cs->bcs[0].mode && (cs->bcs[0].channel == channel))
209 return (&cs->bcs[0]);
210 else if (cs->bcs[1].mode && (cs->bcs[1].channel == channel))
211 return (&cs->bcs[1]);
212 else
213 return (NULL);
214 }
215
216 /***************************************/
217 /* clear the desired B-channel rx fifo */
218 /***************************************/
219 static void hfcpci_clear_fifo_rx(struct IsdnCardState *cs, int fifo)
220 { u_char fifo_state;
221 bzfifo_type *bzr;
222
223 if (fifo) {
224 bzr = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b2;
225 fifo_state = cs->hw.hfcpci.fifo_en & HFCPCI_FIFOEN_B2RX;
226 } else {
227 bzr = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b1;
228 fifo_state = cs->hw.hfcpci.fifo_en & HFCPCI_FIFOEN_B1RX;
229 }
230 if (fifo_state)
231 cs->hw.hfcpci.fifo_en ^= fifo_state;
232 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en);
233 cs->hw.hfcpci.last_bfifo_cnt[fifo] = 0;
234 bzr->za[MAX_B_FRAMES].z1 = B_FIFO_SIZE + B_SUB_VAL - 1;
235 bzr->za[MAX_B_FRAMES].z2 = bzr->za[MAX_B_FRAMES].z1;
236 bzr->f1 = MAX_B_FRAMES;
237 bzr->f2 = bzr->f1; /* init F pointers to remain constant */
238 if (fifo_state)
239 cs->hw.hfcpci.fifo_en |= fifo_state;
240 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en);
241 }
242
243 /***************************************/
244 /* clear the desired B-channel tx fifo */
245 /***************************************/
246 static void hfcpci_clear_fifo_tx(struct IsdnCardState *cs, int fifo)
247 { u_char fifo_state;
248 bzfifo_type *bzt;
249
250 if (fifo) {
251 bzt = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txbz_b2;
252 fifo_state = cs->hw.hfcpci.fifo_en & HFCPCI_FIFOEN_B2TX;
253 } else {
254 bzt = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txbz_b1;
255 fifo_state = cs->hw.hfcpci.fifo_en & HFCPCI_FIFOEN_B1TX;
256 }
257 if (fifo_state)
258 cs->hw.hfcpci.fifo_en ^= fifo_state;
259 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en);
260 bzt->za[MAX_B_FRAMES].z1 = B_FIFO_SIZE + B_SUB_VAL - 1;
261 bzt->za[MAX_B_FRAMES].z2 = bzt->za[MAX_B_FRAMES].z1;
262 bzt->f1 = MAX_B_FRAMES;
263 bzt->f2 = bzt->f1; /* init F pointers to remain constant */
264 if (fifo_state)
265 cs->hw.hfcpci.fifo_en |= fifo_state;
266 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en);
267 }
268
269 /*********************************************/
270 /* read a complete B-frame out of the buffer */
271 /*********************************************/
272 static struct sk_buff
273 *
274 hfcpci_empty_fifo(struct BCState *bcs, bzfifo_type * bz, u_char * bdata, int count)
275 {
276 u_char *ptr, *ptr1, new_f2;
277 struct sk_buff *skb;
278 struct IsdnCardState *cs = bcs->cs;
279 int total, maxlen, new_z2;
280 z_type *zp;
281
282 if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
283 debugl1(cs, "hfcpci_empty_fifo");
284 zp = &bz->za[bz->f2]; /* point to Z-Regs */
285 new_z2 = zp->z2 + count; /* new position in fifo */
286 if (new_z2 >= (B_FIFO_SIZE + B_SUB_VAL))
287 new_z2 -= B_FIFO_SIZE; /* buffer wrap */
288 new_f2 = (bz->f2 + 1) & MAX_B_FRAMES;
289 if ((count > HSCX_BUFMAX + 3) || (count < 4) ||
290 (*(bdata + (zp->z1 - B_SUB_VAL)))) {
291 if (cs->debug & L1_DEB_WARN)
292 debugl1(cs, "hfcpci_empty_fifo: incoming packet invalid length %d or crc", count);
293 #ifdef ERROR_STATISTIC
294 bcs->err_inv++;
295 #endif
296 bz->za[new_f2].z2 = new_z2;
297 bz->f2 = new_f2; /* next buffer */
298 skb = NULL;
299 } else if (!(skb = dev_alloc_skb(count - 3)))
300 printk(KERN_WARNING "HFCPCI: receive out of memory\n");
301 else {
302 total = count;
303 count -= 3;
304 ptr = skb_put(skb, count);
305
306 if (zp->z2 + count <= B_FIFO_SIZE + B_SUB_VAL)
307 maxlen = count; /* complete transfer */
308 else
309 maxlen = B_FIFO_SIZE + B_SUB_VAL - zp->z2; /* maximum */
310
311 ptr1 = bdata + (zp->z2 - B_SUB_VAL); /* start of data */
312 memcpy(ptr, ptr1, maxlen); /* copy data */
313 count -= maxlen;
314
315 if (count) { /* rest remaining */
316 ptr += maxlen;
317 ptr1 = bdata; /* start of buffer */
318 memcpy(ptr, ptr1, count); /* rest */
319 }
320 bz->za[new_f2].z2 = new_z2;
321 bz->f2 = new_f2; /* next buffer */
322
323 }
324 return (skb);
325 }
326
327 /*******************************/
328 /* D-channel receive procedure */
329 /*******************************/
330 static
331 int
332 receive_dmsg(struct IsdnCardState *cs)
333 {
334 struct sk_buff *skb;
335 int maxlen;
336 int rcnt, total;
337 int count = 5;
338 u_char *ptr, *ptr1;
339 dfifo_type *df;
340 z_type *zp;
341
342 df = &((fifo_area *) (cs->hw.hfcpci.fifos))->d_chan.d_rx;
343 if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
344 debugl1(cs, "rec_dmsg blocked");
345 return (1);
346 }
347 while (((df->f1 & D_FREG_MASK) != (df->f2 & D_FREG_MASK)) && count--) {
348 zp = &df->za[df->f2 & D_FREG_MASK];
349 rcnt = zp->z1 - zp->z2;
350 if (rcnt < 0)
351 rcnt += D_FIFO_SIZE;
352 rcnt++;
353 if (cs->debug & L1_DEB_ISAC)
354 debugl1(cs, "hfcpci recd f1(%d) f2(%d) z1(%x) z2(%x) cnt(%d)",
355 df->f1, df->f2, zp->z1, zp->z2, rcnt);
356
357 if ((rcnt > MAX_DFRAME_LEN + 3) || (rcnt < 4) ||
358 (df->data[zp->z1])) {
359 if (cs->debug & L1_DEB_WARN)
360 debugl1(cs, "empty_fifo hfcpci paket inv. len %d or crc %d", rcnt, df->data[zp->z1]);
361 #ifdef ERROR_STATISTIC
362 cs->err_rx++;
363 #endif
364 df->f2 = ((df->f2 + 1) & MAX_D_FRAMES) | (MAX_D_FRAMES + 1); /* next buffer */
365 df->za[df->f2 & D_FREG_MASK].z2 = (zp->z2 + rcnt) & (D_FIFO_SIZE - 1);
366 } else if ((skb = dev_alloc_skb(rcnt - 3))) {
367 total = rcnt;
368 rcnt -= 3;
369 ptr = skb_put(skb, rcnt);
370
371 if (zp->z2 + rcnt <= D_FIFO_SIZE)
372 maxlen = rcnt; /* complete transfer */
373 else
374 maxlen = D_FIFO_SIZE - zp->z2; /* maximum */
375
376 ptr1 = df->data + zp->z2; /* start of data */
377 memcpy(ptr, ptr1, maxlen); /* copy data */
378 rcnt -= maxlen;
379
380 if (rcnt) { /* rest remaining */
381 ptr += maxlen;
382 ptr1 = df->data; /* start of buffer */
383 memcpy(ptr, ptr1, rcnt); /* rest */
384 }
385 df->f2 = ((df->f2 + 1) & MAX_D_FRAMES) | (MAX_D_FRAMES + 1); /* next buffer */
386 df->za[df->f2 & D_FREG_MASK].z2 = (zp->z2 + total) & (D_FIFO_SIZE - 1);
387
388 skb_queue_tail(&cs->rq, skb);
389 sched_event_D_pci(cs, D_RCVBUFREADY);
390 } else
391 printk(KERN_WARNING "HFC-PCI: D receive out of memory\n");
392 }
393 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
394 return (1);
395 }
396
397 /*******************************************************************************/
398 /* check for transparent receive data and read max one threshold size if avail */
399 /*******************************************************************************/
400 static int
401 hfcpci_empty_fifo_trans(struct BCState *bcs, bzfifo_type * bz, u_char * bdata)
402 {
403 unsigned short *z1r, *z2r;
404 int new_z2, fcnt, maxlen;
405 struct sk_buff *skb;
406 u_char *ptr, *ptr1;
407
408 z1r = &bz->za[MAX_B_FRAMES].z1; /* pointer to z reg */
409 z2r = z1r + 1;
410
411 if (!(fcnt = *z1r - *z2r))
412 return (0); /* no data avail */
413
414 if (fcnt <= 0)
415 fcnt += B_FIFO_SIZE; /* bytes actually buffered */
416 if (fcnt > HFCPCI_BTRANS_THRESHOLD)
417 fcnt = HFCPCI_BTRANS_THRESHOLD; /* limit size */
418
419 new_z2 = *z2r + fcnt; /* new position in fifo */
420 if (new_z2 >= (B_FIFO_SIZE + B_SUB_VAL))
421 new_z2 -= B_FIFO_SIZE; /* buffer wrap */
422
423 if (!(skb = dev_alloc_skb(fcnt)))
424 printk(KERN_WARNING "HFCPCI: receive out of memory\n");
425 else {
426 ptr = skb_put(skb, fcnt);
427 if (*z2r + fcnt <= B_FIFO_SIZE + B_SUB_VAL)
428 maxlen = fcnt; /* complete transfer */
429 else
430 maxlen = B_FIFO_SIZE + B_SUB_VAL - *z2r; /* maximum */
431
432 ptr1 = bdata + (*z2r - B_SUB_VAL); /* start of data */
433 memcpy(ptr, ptr1, maxlen); /* copy data */
434 fcnt -= maxlen;
435
436 if (fcnt) { /* rest remaining */
437 ptr += maxlen;
438 ptr1 = bdata; /* start of buffer */
439 memcpy(ptr, ptr1, fcnt); /* rest */
440 }
441 skb_queue_tail(&bcs->rqueue, skb);
442 hfcpci_sched_event(bcs, B_RCVBUFREADY);
443 }
444
445 *z2r = new_z2; /* new position */
446 return (1);
447 } /* hfcpci_empty_fifo_trans */
448
449 /**********************************/
450 /* B-channel main receive routine */
451 /**********************************/
452 static void
453 main_rec_hfcpci(struct BCState *bcs)
454 {
455 struct IsdnCardState *cs = bcs->cs;
456 int rcnt, real_fifo;
457 int receive, count = 5;
458 struct sk_buff *skb;
459 bzfifo_type *bz;
460 u_char *bdata;
461 z_type *zp;
462
463
464 if ((bcs->channel) && (!cs->hw.hfcpci.bswapped)) {
465 bz = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b2;
466 bdata = ((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxdat_b2;
467 real_fifo = 1;
468 } else {
469 bz = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b1;
470 bdata = ((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxdat_b1;
471 real_fifo = 0;
472 }
473 Begin:
474 count--;
475 if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
476 debugl1(cs, "rec_data %d blocked", bcs->channel);
477 return;
478 }
479 if (bz->f1 != bz->f2) {
480 if (cs->debug & L1_DEB_HSCX)
481 debugl1(cs, "hfcpci rec %d f1(%d) f2(%d)",
482 bcs->channel, bz->f1, bz->f2);
483 zp = &bz->za[bz->f2];
484
485 rcnt = zp->z1 - zp->z2;
486 if (rcnt < 0)
487 rcnt += B_FIFO_SIZE;
488 rcnt++;
489 if (cs->debug & L1_DEB_HSCX)
490 debugl1(cs, "hfcpci rec %d z1(%x) z2(%x) cnt(%d)",
491 bcs->channel, zp->z1, zp->z2, rcnt);
492 if ((skb = hfcpci_empty_fifo(bcs, bz, bdata, rcnt))) {
493 skb_queue_tail(&bcs->rqueue, skb);
494 hfcpci_sched_event(bcs, B_RCVBUFREADY);
495 }
496 rcnt = bz->f1 - bz->f2;
497 if (rcnt < 0)
498 rcnt += MAX_B_FRAMES + 1;
499 if (cs->hw.hfcpci.last_bfifo_cnt[real_fifo] > rcnt + 1) {
500 rcnt = 0;
501 hfcpci_clear_fifo_rx(cs, real_fifo);
502 }
503 cs->hw.hfcpci.last_bfifo_cnt[real_fifo] = rcnt;
504 if (rcnt > 1)
505 receive = 1;
506 else
507 receive = 0;
508 } else if (bcs->mode == L1_MODE_TRANS)
509 receive = hfcpci_empty_fifo_trans(bcs, bz, bdata);
510 else
511 receive = 0;
512 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
513 if (count && receive)
514 goto Begin;
515 return;
516 }
517
518 /**************************/
519 /* D-channel send routine */
520 /**************************/
521 static void
522 hfcpci_fill_dfifo(struct IsdnCardState *cs)
523 {
524 int fcnt;
525 int count, new_z1, maxlen;
526 dfifo_type *df;
527 u_char *src, *dst, new_f1;
528
529 if (!cs->tx_skb)
530 return;
531 if (cs->tx_skb->len <= 0)
532 return;
533
534 df = &((fifo_area *) (cs->hw.hfcpci.fifos))->d_chan.d_tx;
535
536 if (cs->debug & L1_DEB_ISAC)
537 debugl1(cs, "hfcpci_fill_Dfifo f1(%d) f2(%d) z1(f1)(%x)",
538 df->f1, df->f2,
539 df->za[df->f1 & D_FREG_MASK].z1);
540 fcnt = df->f1 - df->f2; /* frame count actually buffered */
541 if (fcnt < 0)
542 fcnt += (MAX_D_FRAMES + 1); /* if wrap around */
543 if (fcnt > (MAX_D_FRAMES - 1)) {
544 if (cs->debug & L1_DEB_ISAC)
545 debugl1(cs, "hfcpci_fill_Dfifo more as 14 frames");
546 #ifdef ERROR_STATISTIC
547 cs->err_tx++;
548 #endif
549 return;
550 }
551 /* now determine free bytes in FIFO buffer */
552 count = df->za[df->f2 & D_FREG_MASK].z2 - df->za[df->f1 & D_FREG_MASK].z1 - 1;
553 if (count <= 0)
554 count += D_FIFO_SIZE; /* count now contains available bytes */
555
556 if (cs->debug & L1_DEB_ISAC)
557 debugl1(cs, "hfcpci_fill_Dfifo count(%ld/%d)",
558 cs->tx_skb->len, count);
559 if (count < cs->tx_skb->len) {
560 if (cs->debug & L1_DEB_ISAC)
561 debugl1(cs, "hfcpci_fill_Dfifo no fifo mem");
562 return;
563 }
564 count = cs->tx_skb->len; /* get frame len */
565 new_z1 = (df->za[df->f1 & D_FREG_MASK].z1 + count) & (D_FIFO_SIZE - 1);
566 new_f1 = ((df->f1 + 1) & D_FREG_MASK) | (D_FREG_MASK + 1);
567 src = cs->tx_skb->data; /* source pointer */
568 dst = df->data + df->za[df->f1 & D_FREG_MASK].z1;
569 maxlen = D_FIFO_SIZE - df->za[df->f1 & D_FREG_MASK].z1; /* end fifo */
570 if (maxlen > count)
571 maxlen = count; /* limit size */
572 memcpy(dst, src, maxlen); /* first copy */
573
574 count -= maxlen; /* remaining bytes */
575 if (count) {
576 dst = df->data; /* start of buffer */
577 src += maxlen; /* new position */
578 memcpy(dst, src, count);
579 }
580 df->za[new_f1 & D_FREG_MASK].z1 = new_z1; /* for next buffer */
581 df->za[df->f1 & D_FREG_MASK].z1 = new_z1; /* new pos actual buffer */
582 df->f1 = new_f1; /* next frame */
583
584 dev_kfree_skb_any(cs->tx_skb);
585 cs->tx_skb = NULL;
586 return;
587 }
588
589 /**************************/
590 /* B-channel send routine */
591 /**************************/
592 static void
593 hfcpci_fill_fifo(struct BCState *bcs)
594 {
595 struct IsdnCardState *cs = bcs->cs;
596 int maxlen, fcnt;
597 int count, new_z1;
598 bzfifo_type *bz;
599 u_char *bdata;
600 u_char new_f1, *src, *dst;
601 unsigned short *z1t, *z2t;
602
603 if (!bcs->tx_skb)
604 return;
605 if (bcs->tx_skb->len <= 0)
606 return;
607
608 if ((bcs->channel) && (!cs->hw.hfcpci.bswapped)) {
609 bz = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txbz_b2;
610 bdata = ((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txdat_b2;
611 } else {
612 bz = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txbz_b1;
613 bdata = ((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txdat_b1;
614 }
615
616 if (bcs->mode == L1_MODE_TRANS) {
617 z1t = &bz->za[MAX_B_FRAMES].z1;
618 z2t = z1t + 1;
619 if (cs->debug & L1_DEB_HSCX)
620 debugl1(cs, "hfcpci_fill_fifo_trans %d z1(%x) z2(%x)",
621 bcs->channel, *z1t, *z2t);
622 fcnt = *z2t - *z1t;
623 if (fcnt <= 0)
624 fcnt += B_FIFO_SIZE; /* fcnt contains available bytes in fifo */
625 fcnt = B_FIFO_SIZE - fcnt; /* remaining bytes to send */
626
627 while ((fcnt < 2 * HFCPCI_BTRANS_THRESHOLD) && (bcs->tx_skb)) {
628 if (bcs->tx_skb->len < B_FIFO_SIZE - fcnt) {
629 /* data is suitable for fifo */
630 count = bcs->tx_skb->len;
631
632 new_z1 = *z1t + count; /* new buffer Position */
633 if (new_z1 >= (B_FIFO_SIZE + B_SUB_VAL))
634 new_z1 -= B_FIFO_SIZE; /* buffer wrap */
635 src = bcs->tx_skb->data; /* source pointer */
636 dst = bdata + (*z1t - B_SUB_VAL);
637 maxlen = (B_FIFO_SIZE + B_SUB_VAL) - *z1t; /* end of fifo */
638 if (maxlen > count)
639 maxlen = count; /* limit size */
640 memcpy(dst, src, maxlen); /* first copy */
641
642 count -= maxlen; /* remaining bytes */
643 if (count) {
644 dst = bdata; /* start of buffer */
645 src += maxlen; /* new position */
646 memcpy(dst, src, count);
647 }
648 bcs->tx_cnt -= bcs->tx_skb->len;
649 fcnt += bcs->tx_skb->len;
650 *z1t = new_z1; /* now send data */
651 } else if (cs->debug & L1_DEB_HSCX)
652 debugl1(cs, "hfcpci_fill_fifo_trans %d frame length %d discarded",
653 bcs->channel, bcs->tx_skb->len);
654
655 if (test_bit(FLG_LLI_L1WAKEUP,&bcs->st->lli.flag) &&
656 (PACKET_NOACK != bcs->tx_skb->pkt_type)) {
657 u_long flags;
658 spin_lock_irqsave(&bcs->aclock, flags);
659 bcs->ackcnt += bcs->tx_skb->len;
660 spin_unlock_irqrestore(&bcs->aclock, flags);
661 schedule_event(bcs, B_ACKPENDING);
662 }
663
664 dev_kfree_skb_any(bcs->tx_skb);
665 bcs->tx_skb = skb_dequeue(&bcs->squeue); /* fetch next data */
666 }
667 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
668 return;
669 }
670 if (cs->debug & L1_DEB_HSCX)
671 debugl1(cs, "hfcpci_fill_fifo_hdlc %d f1(%d) f2(%d) z1(f1)(%x)",
672 bcs->channel, bz->f1, bz->f2,
673 bz->za[bz->f1].z1);
674
675 fcnt = bz->f1 - bz->f2; /* frame count actually buffered */
676 if (fcnt < 0)
677 fcnt += (MAX_B_FRAMES + 1); /* if wrap around */
678 if (fcnt > (MAX_B_FRAMES - 1)) {
679 if (cs->debug & L1_DEB_HSCX)
680 debugl1(cs, "hfcpci_fill_Bfifo more as 14 frames");
681 return;
682 }
683 /* now determine free bytes in FIFO buffer */
684 count = bz->za[bz->f2].z2 - bz->za[bz->f1].z1 - 1;
685 if (count <= 0)
686 count += B_FIFO_SIZE; /* count now contains available bytes */
687
688 if (cs->debug & L1_DEB_HSCX)
689 debugl1(cs, "hfcpci_fill_fifo %d count(%ld/%d),%lx",
690 bcs->channel, bcs->tx_skb->len,
691 count, current->state);
692
693 if (count < bcs->tx_skb->len) {
694 if (cs->debug & L1_DEB_HSCX)
695 debugl1(cs, "hfcpci_fill_fifo no fifo mem");
696 return;
697 }
698 count = bcs->tx_skb->len; /* get frame len */
699 new_z1 = bz->za[bz->f1].z1 + count; /* new buffer Position */
700 if (new_z1 >= (B_FIFO_SIZE + B_SUB_VAL))
701 new_z1 -= B_FIFO_SIZE; /* buffer wrap */
702
703 new_f1 = ((bz->f1 + 1) & MAX_B_FRAMES);
704 src = bcs->tx_skb->data; /* source pointer */
705 dst = bdata + (bz->za[bz->f1].z1 - B_SUB_VAL);
706 maxlen = (B_FIFO_SIZE + B_SUB_VAL) - bz->za[bz->f1].z1; /* end fifo */
707 if (maxlen > count)
708 maxlen = count; /* limit size */
709 memcpy(dst, src, maxlen); /* first copy */
710
711 count -= maxlen; /* remaining bytes */
712 if (count) {
713 dst = bdata; /* start of buffer */
714 src += maxlen; /* new position */
715 memcpy(dst, src, count);
716 }
717 bcs->tx_cnt -= bcs->tx_skb->len;
718 if (test_bit(FLG_LLI_L1WAKEUP,&bcs->st->lli.flag) &&
719 (PACKET_NOACK != bcs->tx_skb->pkt_type)) {
720 u_long flags;
721 spin_lock_irqsave(&bcs->aclock, flags);
722 bcs->ackcnt += bcs->tx_skb->len;
723 spin_unlock_irqrestore(&bcs->aclock, flags);
724 schedule_event(bcs, B_ACKPENDING);
725 }
726
727 bz->za[new_f1].z1 = new_z1; /* for next buffer */
728 bz->f1 = new_f1; /* next frame */
729
730 dev_kfree_skb_any(bcs->tx_skb);
731 bcs->tx_skb = NULL;
732 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
733 return;
734 }
735
736 /**********************************************/
737 /* D-channel l1 state call for leased NT-mode */
738 /**********************************************/
739 static void
740 dch_nt_l2l1(struct PStack *st, int pr, void *arg)
741 {
742 struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware;
743
744 switch (pr) {
745 case (PH_DATA | REQUEST):
746 case (PH_PULL | REQUEST):
747 case (PH_PULL | INDICATION):
748 st->l1.l1hw(st, pr, arg);
749 break;
750 case (PH_ACTIVATE | REQUEST):
751 st->l1.l1l2(st, PH_ACTIVATE | CONFIRM, NULL);
752 break;
753 case (PH_TESTLOOP | REQUEST):
754 if (1 & (long) arg)
755 debugl1(cs, "PH_TEST_LOOP B1");
756 if (2 & (long) arg)
757 debugl1(cs, "PH_TEST_LOOP B2");
758 if (!(3 & (long) arg))
759 debugl1(cs, "PH_TEST_LOOP DISABLED");
760 st->l1.l1hw(st, HW_TESTLOOP | REQUEST, arg);
761 break;
762 default:
763 if (cs->debug)
764 debugl1(cs, "dch_nt_l2l1 msg %04X unhandled", pr);
765 break;
766 }
767 }
768
769
770
771 /***********************/
772 /* set/reset echo mode */
773 /***********************/
774 static int
775 hfcpci_auxcmd(struct IsdnCardState *cs, isdn_ctrl * ic)
776 {
777 u_long flags;
778 int i = *(unsigned int *) ic->parm.num;
779
780 if ((ic->arg == 98) &&
781 (!(cs->hw.hfcpci.int_m1 & (HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC + HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC)))) {
782 spin_lock_irqsave(&cs->lock, flags);
783 Write_hfc(cs, HFCPCI_CLKDEL, CLKDEL_NT); /* ST-Bit delay for NT-Mode */
784 Write_hfc(cs, HFCPCI_STATES, HFCPCI_LOAD_STATE | 0); /* HFC ST G0 */
785 udelay(10);
786 cs->hw.hfcpci.sctrl |= SCTRL_MODE_NT;
787 Write_hfc(cs, HFCPCI_SCTRL, cs->hw.hfcpci.sctrl); /* set NT-mode */
788 udelay(10);
789 Write_hfc(cs, HFCPCI_STATES, HFCPCI_LOAD_STATE | 1); /* HFC ST G1 */
790 udelay(10);
791 Write_hfc(cs, HFCPCI_STATES, 1 | HFCPCI_ACTIVATE | HFCPCI_DO_ACTION);
792 cs->dc.hfcpci.ph_state = 1;
793 cs->hw.hfcpci.nt_mode = 1;
794 cs->hw.hfcpci.nt_timer = 0;
795 cs->stlist->l2.l2l1 = dch_nt_l2l1;
796 spin_unlock_irqrestore(&cs->lock, flags);
797 debugl1(cs, "NT mode activated");
798 return (0);
799 }
800 if ((cs->chanlimit > 1) || (cs->hw.hfcpci.bswapped) ||
801 (cs->hw.hfcpci.nt_mode) || (ic->arg != 12))
802 return (-EINVAL);
803
804 spin_lock_irqsave(&cs->lock, flags);
805 if (i) {
806 cs->logecho = 1;
807 cs->hw.hfcpci.trm |= 0x20; /* enable echo chan */
808 cs->hw.hfcpci.int_m1 |= HFCPCI_INTS_B2REC;
809 cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B2RX;
810 } else {
811 cs->logecho = 0;
812 cs->hw.hfcpci.trm &= ~0x20; /* disable echo chan */
813 cs->hw.hfcpci.int_m1 &= ~HFCPCI_INTS_B2REC;
814 cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B2RX;
815 }
816 cs->hw.hfcpci.sctrl_r &= ~SCTRL_B2_ENA;
817 cs->hw.hfcpci.sctrl &= ~SCTRL_B2_ENA;
818 cs->hw.hfcpci.conn |= 0x10; /* B2-IOM -> B2-ST */
819 cs->hw.hfcpci.ctmt &= ~2;
820 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt);
821 Write_hfc(cs, HFCPCI_SCTRL_R, cs->hw.hfcpci.sctrl_r);
822 Write_hfc(cs, HFCPCI_SCTRL, cs->hw.hfcpci.sctrl);
823 Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn);
824 Write_hfc(cs, HFCPCI_TRM, cs->hw.hfcpci.trm);
825 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en);
826 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
827 spin_unlock_irqrestore(&cs->lock, flags);
828 return (0);
829 } /* hfcpci_auxcmd */
830
831 /*****************************/
832 /* E-channel receive routine */
833 /*****************************/
834 static void
835 receive_emsg(struct IsdnCardState *cs)
836 {
837 int rcnt;
838 int receive, count = 5;
839 bzfifo_type *bz;
840 u_char *bdata;
841 z_type *zp;
842 u_char *ptr, *ptr1, new_f2;
843 int total, maxlen, new_z2;
844 u_char e_buffer[256];
845
846 bz = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b2;
847 bdata = ((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxdat_b2;
848 Begin:
849 count--;
850 if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
851 debugl1(cs, "echo_rec_data blocked");
852 return;
853 }
854 if (bz->f1 != bz->f2) {
855 if (cs->debug & L1_DEB_ISAC)
856 debugl1(cs, "hfcpci e_rec f1(%d) f2(%d)",
857 bz->f1, bz->f2);
858 zp = &bz->za[bz->f2];
859
860 rcnt = zp->z1 - zp->z2;
861 if (rcnt < 0)
862 rcnt += B_FIFO_SIZE;
863 rcnt++;
864 if (cs->debug & L1_DEB_ISAC)
865 debugl1(cs, "hfcpci e_rec z1(%x) z2(%x) cnt(%d)",
866 zp->z1, zp->z2, rcnt);
867 new_z2 = zp->z2 + rcnt; /* new position in fifo */
868 if (new_z2 >= (B_FIFO_SIZE + B_SUB_VAL))
869 new_z2 -= B_FIFO_SIZE; /* buffer wrap */
870 new_f2 = (bz->f2 + 1) & MAX_B_FRAMES;
871 if ((rcnt > 256 + 3) || (count < 4) ||
872 (*(bdata + (zp->z1 - B_SUB_VAL)))) {
873 if (cs->debug & L1_DEB_WARN)
874 debugl1(cs, "hfcpci_empty_echan: incoming packet invalid length %d or crc", rcnt);
875 bz->za[new_f2].z2 = new_z2;
876 bz->f2 = new_f2; /* next buffer */
877 } else {
878 total = rcnt;
879 rcnt -= 3;
880 ptr = e_buffer;
881
882 if (zp->z2 <= B_FIFO_SIZE + B_SUB_VAL)
883 maxlen = rcnt; /* complete transfer */
884 else
885 maxlen = B_FIFO_SIZE + B_SUB_VAL - zp->z2; /* maximum */
886
887 ptr1 = bdata + (zp->z2 - B_SUB_VAL); /* start of data */
888 memcpy(ptr, ptr1, maxlen); /* copy data */
889 rcnt -= maxlen;
890
891 if (rcnt) { /* rest remaining */
892 ptr += maxlen;
893 ptr1 = bdata; /* start of buffer */
894 memcpy(ptr, ptr1, rcnt); /* rest */
895 }
896 bz->za[new_f2].z2 = new_z2;
897 bz->f2 = new_f2; /* next buffer */
898 if (cs->debug & DEB_DLOG_HEX) {
899 ptr = cs->dlog;
900 if ((total - 3) < MAX_DLOG_SPACE / 3 - 10) {
901 *ptr++ = 'E';
902 *ptr++ = 'C';
903 *ptr++ = 'H';
904 *ptr++ = 'O';
905 *ptr++ = ':';
906 ptr += QuickHex(ptr, e_buffer, total - 3);
907 ptr--;
908 *ptr++ = '\n';
909 *ptr = 0;
910 HiSax_putstatus(cs, NULL, cs->dlog);
911 } else
912 HiSax_putstatus(cs, "LogEcho: ", "warning Frame too big (%d)", total - 3);
913 }
914 }
915
916 rcnt = bz->f1 - bz->f2;
917 if (rcnt < 0)
918 rcnt += MAX_B_FRAMES + 1;
919 if (rcnt > 1)
920 receive = 1;
921 else
922 receive = 0;
923 } else
924 receive = 0;
925 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
926 if (count && receive)
927 goto Begin;
928 return;
929 } /* receive_emsg */
930
931 /*********************/
932 /* Interrupt handler */
933 /*********************/
934 static irqreturn_t
935 hfcpci_interrupt(int intno, void *dev_id, struct pt_regs *regs)
936 {
937 u_long flags;
938 struct IsdnCardState *cs = dev_id;
939 u_char exval;
940 struct BCState *bcs;
941 int count = 15;
942 u_char val, stat;
943
944 if (!(cs->hw.hfcpci.int_m2 & 0x08)) {
945 debugl1(cs, "HFC-PCI: int_m2 %x not initialised", cs->hw.hfcpci.int_m2);
946 return IRQ_NONE; /* not initialised */
947 }
948 spin_lock_irqsave(&cs->lock, flags);
949 if (HFCPCI_ANYINT & (stat = Read_hfc(cs, HFCPCI_STATUS))) {
950 val = Read_hfc(cs, HFCPCI_INT_S1);
951 if (cs->debug & L1_DEB_ISAC)
952 debugl1(cs, "HFC-PCI: stat(%02x) s1(%02x)", stat, val);
953 } else {
954 spin_unlock_irqrestore(&cs->lock, flags);
955 return IRQ_NONE;
956 }
957 if (cs->debug & L1_DEB_ISAC)
958 debugl1(cs, "HFC-PCI irq %x %s", val,
959 test_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags) ?
960 "locked" : "unlocked");
961 val &= cs->hw.hfcpci.int_m1;
962 if (val & 0x40) { /* state machine irq */
963 exval = Read_hfc(cs, HFCPCI_STATES) & 0xf;
964 if (cs->debug & L1_DEB_ISAC)
965 debugl1(cs, "ph_state chg %d->%d", cs->dc.hfcpci.ph_state,
966 exval);
967 cs->dc.hfcpci.ph_state = exval;
968 sched_event_D_pci(cs, D_L1STATECHANGE);
969 val &= ~0x40;
970 }
971 if (val & 0x80) { /* timer irq */
972 if (cs->hw.hfcpci.nt_mode) {
973 if ((--cs->hw.hfcpci.nt_timer) < 0)
974 sched_event_D_pci(cs, D_L1STATECHANGE);
975 }
976 val &= ~0x80;
977 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt | HFCPCI_CLTIMER);
978 }
979 while (val) {
980 if (test_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
981 cs->hw.hfcpci.int_s1 |= val;
982 spin_unlock_irqrestore(&cs->lock, flags);
983 return IRQ_HANDLED;
984 }
985 if (cs->hw.hfcpci.int_s1 & 0x18) {
986 exval = val;
987 val = cs->hw.hfcpci.int_s1;
988 cs->hw.hfcpci.int_s1 = exval;
989 }
990 if (val & 0x08) {
991 if (!(bcs = Sel_BCS(cs, cs->hw.hfcpci.bswapped ? 1 : 0))) {
992 if (cs->debug)
993 debugl1(cs, "hfcpci spurious 0x08 IRQ");
994 } else
995 main_rec_hfcpci(bcs);
996 }
997 if (val & 0x10) {
998 if (cs->logecho)
999 receive_emsg(cs);
1000 else if (!(bcs = Sel_BCS(cs, 1))) {
1001 if (cs->debug)
1002 debugl1(cs, "hfcpci spurious 0x10 IRQ");
1003 } else
1004 main_rec_hfcpci(bcs);
1005 }
1006 if (val & 0x01) {
1007 if (!(bcs = Sel_BCS(cs, cs->hw.hfcpci.bswapped ? 1 : 0))) {
1008 if (cs->debug)
1009 debugl1(cs, "hfcpci spurious 0x01 IRQ");
1010 } else {
1011 if (bcs->tx_skb) {
1012 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1013 hfcpci_fill_fifo(bcs);
1014 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1015 } else
1016 debugl1(cs, "fill_data %d blocked", bcs->channel);
1017 } else {
1018 if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
1019 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1020 hfcpci_fill_fifo(bcs);
1021 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1022 } else
1023 debugl1(cs, "fill_data %d blocked", bcs->channel);
1024 } else {
1025 hfcpci_sched_event(bcs, B_XMTBUFREADY);
1026 }
1027 }
1028 }
1029 }
1030 if (val & 0x02) {
1031 if (!(bcs = Sel_BCS(cs, 1))) {
1032 if (cs->debug)
1033 debugl1(cs, "hfcpci spurious 0x02 IRQ");
1034 } else {
1035 if (bcs->tx_skb) {
1036 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1037 hfcpci_fill_fifo(bcs);
1038 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1039 } else
1040 debugl1(cs, "fill_data %d blocked", bcs->channel);
1041 } else {
1042 if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
1043 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1044 hfcpci_fill_fifo(bcs);
1045 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1046 } else
1047 debugl1(cs, "fill_data %d blocked", bcs->channel);
1048 } else {
1049 hfcpci_sched_event(bcs, B_XMTBUFREADY);
1050 }
1051 }
1052 }
1053 }
1054 if (val & 0x20) { /* receive dframe */
1055 receive_dmsg(cs);
1056 }
1057 if (val & 0x04) { /* dframe transmitted */
1058 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
1059 del_timer(&cs->dbusytimer);
1060 if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
1061 sched_event_D_pci(cs, D_CLEARBUSY);
1062 if (cs->tx_skb) {
1063 if (cs->tx_skb->len) {
1064 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1065 hfcpci_fill_dfifo(cs);
1066 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1067 } else {
1068 debugl1(cs, "hfcpci_fill_dfifo irq blocked");
1069 }
1070 goto afterXPR;
1071 } else {
1072 dev_kfree_skb_irq(cs->tx_skb);
1073 cs->tx_cnt = 0;
1074 cs->tx_skb = NULL;
1075 }
1076 }
1077 if ((cs->tx_skb = skb_dequeue(&cs->sq))) {
1078 cs->tx_cnt = 0;
1079 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1080 hfcpci_fill_dfifo(cs);
1081 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1082 } else {
1083 debugl1(cs, "hfcpci_fill_dfifo irq blocked");
1084 }
1085 } else
1086 sched_event_D_pci(cs, D_XMTBUFREADY);
1087 }
1088 afterXPR:
1089 if (cs->hw.hfcpci.int_s1 && count--) {
1090 val = cs->hw.hfcpci.int_s1;
1091 cs->hw.hfcpci.int_s1 = 0;
1092 if (cs->debug & L1_DEB_ISAC)
1093 debugl1(cs, "HFC-PCI irq %x loop %d", val, 15 - count);
1094 } else
1095 val = 0;
1096 }
1097 spin_unlock_irqrestore(&cs->lock, flags);
1098 return IRQ_HANDLED;
1099 }
1100
1101 /********************************************************************/
1102 /* timer callback for D-chan busy resolution. Currently no function */
1103 /********************************************************************/
1104 static void
1105 hfcpci_dbusy_timer(struct IsdnCardState *cs)
1106 {
1107 }
1108
1109 /*************************************/
1110 /* Layer 1 D-channel hardware access */
1111 /*************************************/
1112 static void
1113 HFCPCI_l1hw(struct PStack *st, int pr, void *arg)
1114 {
1115 u_long flags;
1116 struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware;
1117 struct sk_buff *skb = arg;
1118
1119 switch (pr) {
1120 case (PH_DATA | REQUEST):
1121 if (cs->debug & DEB_DLOG_HEX)
1122 LogFrame(cs, skb->data, skb->len);
1123 if (cs->debug & DEB_DLOG_VERBOSE)
1124 dlogframe(cs, skb, 0);
1125 spin_lock_irqsave(&cs->lock, flags);
1126 if (cs->tx_skb) {
1127 skb_queue_tail(&cs->sq, skb);
1128 #ifdef L2FRAME_DEBUG /* psa */
1129 if (cs->debug & L1_DEB_LAPD)
1130 Logl2Frame(cs, skb, "PH_DATA Queued", 0);
1131 #endif
1132 } else {
1133 cs->tx_skb = skb;
1134 cs->tx_cnt = 0;
1135 #ifdef L2FRAME_DEBUG /* psa */
1136 if (cs->debug & L1_DEB_LAPD)
1137 Logl2Frame(cs, skb, "PH_DATA", 0);
1138 #endif
1139 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1140 hfcpci_fill_dfifo(cs);
1141 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1142 } else
1143 debugl1(cs, "hfcpci_fill_dfifo blocked");
1144
1145 }
1146 spin_unlock_irqrestore(&cs->lock, flags);
1147 break;
1148 case (PH_PULL | INDICATION):
1149 spin_lock_irqsave(&cs->lock, flags);
1150 if (cs->tx_skb) {
1151 if (cs->debug & L1_DEB_WARN)
1152 debugl1(cs, " l2l1 tx_skb exist this shouldn't happen");
1153 skb_queue_tail(&cs->sq, skb);
1154 spin_unlock_irqrestore(&cs->lock, flags);
1155 break;
1156 }
1157 if (cs->debug & DEB_DLOG_HEX)
1158 LogFrame(cs, skb->data, skb->len);
1159 if (cs->debug & DEB_DLOG_VERBOSE)
1160 dlogframe(cs, skb, 0);
1161 cs->tx_skb = skb;
1162 cs->tx_cnt = 0;
1163 #ifdef L2FRAME_DEBUG /* psa */
1164 if (cs->debug & L1_DEB_LAPD)
1165 Logl2Frame(cs, skb, "PH_DATA_PULLED", 0);
1166 #endif
1167 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1168 hfcpci_fill_dfifo(cs);
1169 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1170 } else
1171 debugl1(cs, "hfcpci_fill_dfifo blocked");
1172 spin_unlock_irqrestore(&cs->lock, flags);
1173 break;
1174 case (PH_PULL | REQUEST):
1175 #ifdef L2FRAME_DEBUG /* psa */
1176 if (cs->debug & L1_DEB_LAPD)
1177 debugl1(cs, "-> PH_REQUEST_PULL");
1178 #endif
1179 if (!cs->tx_skb) {
1180 test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
1181 st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
1182 } else
1183 test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
1184 break;
1185 case (HW_RESET | REQUEST):
1186 spin_lock_irqsave(&cs->lock, flags);
1187 Write_hfc(cs, HFCPCI_STATES, HFCPCI_LOAD_STATE | 3); /* HFC ST 3 */
1188 udelay(6);
1189 Write_hfc(cs, HFCPCI_STATES, 3); /* HFC ST 2 */
1190 cs->hw.hfcpci.mst_m |= HFCPCI_MASTER;
1191 Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m);
1192 Write_hfc(cs, HFCPCI_STATES, HFCPCI_ACTIVATE | HFCPCI_DO_ACTION);
1193 spin_unlock_irqrestore(&cs->lock, flags);
1194 l1_msg(cs, HW_POWERUP | CONFIRM, NULL);
1195 break;
1196 case (HW_ENABLE | REQUEST):
1197 spin_lock_irqsave(&cs->lock, flags);
1198 Write_hfc(cs, HFCPCI_STATES, HFCPCI_DO_ACTION);
1199 spin_unlock_irqrestore(&cs->lock, flags);
1200 break;
1201 case (HW_DEACTIVATE | REQUEST):
1202 spin_lock_irqsave(&cs->lock, flags);
1203 cs->hw.hfcpci.mst_m &= ~HFCPCI_MASTER;
1204 Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m);
1205 spin_unlock_irqrestore(&cs->lock, flags);
1206 break;
1207 case (HW_INFO3 | REQUEST):
1208 spin_lock_irqsave(&cs->lock, flags);
1209 cs->hw.hfcpci.mst_m |= HFCPCI_MASTER;
1210 Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m);
1211 spin_unlock_irqrestore(&cs->lock, flags);
1212 break;
1213 case (HW_TESTLOOP | REQUEST):
1214 spin_lock_irqsave(&cs->lock, flags);
1215 switch ((int) arg) {
1216 case (1):
1217 Write_hfc(cs, HFCPCI_B1_SSL, 0x80); /* tx slot */
1218 Write_hfc(cs, HFCPCI_B1_RSL, 0x80); /* rx slot */
1219 cs->hw.hfcpci.conn = (cs->hw.hfcpci.conn & ~7) | 1;
1220 Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn);
1221 break;
1222
1223 case (2):
1224 Write_hfc(cs, HFCPCI_B2_SSL, 0x81); /* tx slot */
1225 Write_hfc(cs, HFCPCI_B2_RSL, 0x81); /* rx slot */
1226 cs->hw.hfcpci.conn = (cs->hw.hfcpci.conn & ~0x38) | 0x08;
1227 Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn);
1228 break;
1229
1230 default:
1231 spin_unlock_irqrestore(&cs->lock, flags);
1232 if (cs->debug & L1_DEB_WARN)
1233 debugl1(cs, "hfcpci_l1hw loop invalid %4x", (int) arg);
1234 return;
1235 }
1236 cs->hw.hfcpci.trm |= 0x80; /* enable IOM-loop */
1237 Write_hfc(cs, HFCPCI_TRM, cs->hw.hfcpci.trm);
1238 spin_unlock_irqrestore(&cs->lock, flags);
1239 break;
1240 default:
1241 if (cs->debug & L1_DEB_WARN)
1242 debugl1(cs, "hfcpci_l1hw unknown pr %4x", pr);
1243 break;
1244 }
1245 }
1246
1247 /***********************************************/
1248 /* called during init setting l1 stack pointer */
1249 /***********************************************/
1250 static void
1251 setstack_hfcpci(struct PStack *st, struct IsdnCardState *cs)
1252 {
1253 st->l1.l1hw = HFCPCI_l1hw;
1254 }
1255
1256 /**************************************/
1257 /* send B-channel data if not blocked */
1258 /**************************************/
1259 static void
1260 hfcpci_send_data(struct BCState *bcs)
1261 {
1262 struct IsdnCardState *cs = bcs->cs;
1263
1264 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1265 hfcpci_fill_fifo(bcs);
1266 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1267 } else
1268 debugl1(cs, "send_data %d blocked", bcs->channel);
1269 }
1270
1271 /***************************************************************/
1272 /* activate/deactivate hardware for selected channels and mode */
1273 /***************************************************************/
1274 static void
1275 mode_hfcpci(struct BCState *bcs, int mode, int bc)
1276 {
1277 struct IsdnCardState *cs = bcs->cs;
1278 int fifo2;
1279
1280 if (cs->debug & L1_DEB_HSCX)
1281 debugl1(cs, "HFCPCI bchannel mode %d bchan %d/%d",
1282 mode, bc, bcs->channel);
1283 bcs->mode = mode;
1284 bcs->channel = bc;
1285 fifo2 = bc;
1286 if (cs->chanlimit > 1) {
1287 cs->hw.hfcpci.bswapped = 0; /* B1 and B2 normal mode */
1288 cs->hw.hfcpci.sctrl_e &= ~0x80;
1289 } else {
1290 if (bc) {
1291 if (mode != L1_MODE_NULL) {
1292 cs->hw.hfcpci.bswapped = 1; /* B1 and B2 exchanged */
1293 cs->hw.hfcpci.sctrl_e |= 0x80;
1294 } else {
1295 cs->hw.hfcpci.bswapped = 0; /* B1 and B2 normal mode */
1296 cs->hw.hfcpci.sctrl_e &= ~0x80;
1297 }
1298 fifo2 = 0;
1299 } else {
1300 cs->hw.hfcpci.bswapped = 0; /* B1 and B2 normal mode */
1301 cs->hw.hfcpci.sctrl_e &= ~0x80;
1302 }
1303 }
1304 switch (mode) {
1305 case (L1_MODE_NULL):
1306 if (bc) {
1307 cs->hw.hfcpci.sctrl &= ~SCTRL_B2_ENA;
1308 cs->hw.hfcpci.sctrl_r &= ~SCTRL_B2_ENA;
1309 } else {
1310 cs->hw.hfcpci.sctrl &= ~SCTRL_B1_ENA;
1311 cs->hw.hfcpci.sctrl_r &= ~SCTRL_B1_ENA;
1312 }
1313 if (fifo2) {
1314 cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B2;
1315 cs->hw.hfcpci.int_m1 &= ~(HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC);
1316 } else {
1317 cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B1;
1318 cs->hw.hfcpci.int_m1 &= ~(HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC);
1319 }
1320 break;
1321 case (L1_MODE_TRANS):
1322 hfcpci_clear_fifo_rx(cs, fifo2);
1323 hfcpci_clear_fifo_tx(cs, fifo2);
1324 if (bc) {
1325 cs->hw.hfcpci.sctrl |= SCTRL_B2_ENA;
1326 cs->hw.hfcpci.sctrl_r |= SCTRL_B2_ENA;
1327 } else {
1328 cs->hw.hfcpci.sctrl |= SCTRL_B1_ENA;
1329 cs->hw.hfcpci.sctrl_r |= SCTRL_B1_ENA;
1330 }
1331 if (fifo2) {
1332 cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B2;
1333 cs->hw.hfcpci.int_m1 |= (HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC);
1334 cs->hw.hfcpci.ctmt |= 2;
1335 cs->hw.hfcpci.conn &= ~0x18;
1336 } else {
1337 cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B1;
1338 cs->hw.hfcpci.int_m1 |= (HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC);
1339 cs->hw.hfcpci.ctmt |= 1;
1340 cs->hw.hfcpci.conn &= ~0x03;
1341 }
1342 break;
1343 case (L1_MODE_HDLC):
1344 hfcpci_clear_fifo_rx(cs, fifo2);
1345 hfcpci_clear_fifo_tx(cs, fifo2);
1346 if (bc) {
1347 cs->hw.hfcpci.sctrl |= SCTRL_B2_ENA;
1348 cs->hw.hfcpci.sctrl_r |= SCTRL_B2_ENA;
1349 } else {
1350 cs->hw.hfcpci.sctrl |= SCTRL_B1_ENA;
1351 cs->hw.hfcpci.sctrl_r |= SCTRL_B1_ENA;
1352 }
1353 if (fifo2) {
1354 cs->hw.hfcpci.last_bfifo_cnt[1] = 0;
1355 cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B2;
1356 cs->hw.hfcpci.int_m1 |= (HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC);
1357 cs->hw.hfcpci.ctmt &= ~2;
1358 cs->hw.hfcpci.conn &= ~0x18;
1359 } else {
1360 cs->hw.hfcpci.last_bfifo_cnt[0] = 0;
1361 cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B1;
1362 cs->hw.hfcpci.int_m1 |= (HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC);
1363 cs->hw.hfcpci.ctmt &= ~1;
1364 cs->hw.hfcpci.conn &= ~0x03;
1365 }
1366 break;
1367 case (L1_MODE_EXTRN):
1368 if (bc) {
1369 cs->hw.hfcpci.conn |= 0x10;
1370 cs->hw.hfcpci.sctrl |= SCTRL_B2_ENA;
1371 cs->hw.hfcpci.sctrl_r |= SCTRL_B2_ENA;
1372 cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B2;
1373 cs->hw.hfcpci.int_m1 &= ~(HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC);
1374 } else {
1375 cs->hw.hfcpci.conn |= 0x02;
1376 cs->hw.hfcpci.sctrl |= SCTRL_B1_ENA;
1377 cs->hw.hfcpci.sctrl_r |= SCTRL_B1_ENA;
1378 cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B1;
1379 cs->hw.hfcpci.int_m1 &= ~(HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC);
1380 }
1381 break;
1382 }
1383 Write_hfc(cs, HFCPCI_SCTRL_E, cs->hw.hfcpci.sctrl_e);
1384 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
1385 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en);
1386 Write_hfc(cs, HFCPCI_SCTRL, cs->hw.hfcpci.sctrl);
1387 Write_hfc(cs, HFCPCI_SCTRL_R, cs->hw.hfcpci.sctrl_r);
1388 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt);
1389 Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn);
1390 }
1391
1392 /******************************/
1393 /* Layer2 -> Layer 1 Transfer */
1394 /******************************/
1395 static void
1396 hfcpci_l2l1(struct PStack *st, int pr, void *arg)
1397 {
1398 struct BCState *bcs = st->l1.bcs;
1399 u_long flags;
1400 struct sk_buff *skb = arg;
1401
1402 switch (pr) {
1403 case (PH_DATA | REQUEST):
1404 spin_lock_irqsave(&bcs->cs->lock, flags);
1405 if (bcs->tx_skb) {
1406 skb_queue_tail(&bcs->squeue, skb);
1407 } else {
1408 bcs->tx_skb = skb;
1409 // test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
1410 bcs->cs->BC_Send_Data(bcs);
1411 }
1412 spin_unlock_irqrestore(&bcs->cs->lock, flags);
1413 break;
1414 case (PH_PULL | INDICATION):
1415 spin_lock_irqsave(&bcs->cs->lock, flags);
1416 if (bcs->tx_skb) {
1417 spin_unlock_irqrestore(&bcs->cs->lock, flags);
1418 printk(KERN_WARNING "hfc_l2l1: this shouldn't happen\n");
1419 break;
1420 }
1421 // test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
1422 bcs->tx_skb = skb;
1423 bcs->cs->BC_Send_Data(bcs);
1424 spin_unlock_irqrestore(&bcs->cs->lock, flags);
1425 break;
1426 case (PH_PULL | REQUEST):
1427 if (!bcs->tx_skb) {
1428 test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
1429 st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
1430 } else
1431 test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
1432 break;
1433 case (PH_ACTIVATE | REQUEST):
1434 spin_lock_irqsave(&bcs->cs->lock, flags);
1435 test_and_set_bit(BC_FLG_ACTIV, &bcs->Flag);
1436 mode_hfcpci(bcs, st->l1.mode, st->l1.bc);
1437 spin_unlock_irqrestore(&bcs->cs->lock, flags);
1438 l1_msg_b(st, pr, arg);
1439 break;
1440 case (PH_DEACTIVATE | REQUEST):
1441 l1_msg_b(st, pr, arg);
1442 break;
1443 case (PH_DEACTIVATE | CONFIRM):
1444 spin_lock_irqsave(&bcs->cs->lock, flags);
1445 test_and_clear_bit(BC_FLG_ACTIV, &bcs->Flag);
1446 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
1447 mode_hfcpci(bcs, 0, st->l1.bc);
1448 spin_unlock_irqrestore(&bcs->cs->lock, flags);
1449 st->l1.l1l2(st, PH_DEACTIVATE | CONFIRM, NULL);
1450 break;
1451 }
1452 }
1453
1454 /******************************************/
1455 /* deactivate B-channel access and queues */
1456 /******************************************/
1457 static void
1458 close_hfcpci(struct BCState *bcs)
1459 {
1460 mode_hfcpci(bcs, 0, bcs->channel);
1461 if (test_and_clear_bit(BC_FLG_INIT, &bcs->Flag)) {
1462 skb_queue_purge(&bcs->rqueue);
1463 skb_queue_purge(&bcs->squeue);
1464 if (bcs->tx_skb) {
1465 dev_kfree_skb_any(bcs->tx_skb);
1466 bcs->tx_skb = NULL;
1467 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
1468 }
1469 }
1470 }
1471
1472 /*************************************/
1473 /* init B-channel queues and control */
1474 /*************************************/
1475 static int
1476 open_hfcpcistate(struct IsdnCardState *cs, struct BCState *bcs)
1477 {
1478 if (!test_and_set_bit(BC_FLG_INIT, &bcs->Flag)) {
1479 skb_queue_head_init(&bcs->rqueue);
1480 skb_queue_head_init(&bcs->squeue);
1481 }
1482 bcs->tx_skb = NULL;
1483 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
1484 bcs->event = 0;
1485 bcs->tx_cnt = 0;
1486 return (0);
1487 }
1488
1489 /*********************************/
1490 /* inits the stack for B-channel */
1491 /*********************************/
1492 static int
1493 setstack_2b(struct PStack *st, struct BCState *bcs)
1494 {
1495 bcs->channel = st->l1.bc;
1496 if (open_hfcpcistate(st->l1.hardware, bcs))
1497 return (-1);
1498 st->l1.bcs = bcs;
1499 st->l2.l2l1 = hfcpci_l2l1;
1500 setstack_manager(st);
1501 bcs->st = st;
1502 setstack_l1_B(st);
1503 return (0);
1504 }
1505
1506 /***************************/
1507 /* handle L1 state changes */
1508 /***************************/
1509 static void
1510 hfcpci_bh(struct IsdnCardState *cs)
1511 {
1512 u_long flags;
1513 // struct PStack *stptr;
1514
1515 if (!cs)
1516 return;
1517 if (test_and_clear_bit(D_L1STATECHANGE, &cs->event)) {
1518 if (!cs->hw.hfcpci.nt_mode)
1519 switch (cs->dc.hfcpci.ph_state) {
1520 case (0):
1521 l1_msg(cs, HW_RESET | INDICATION, NULL);
1522 break;
1523 case (3):
1524 l1_msg(cs, HW_DEACTIVATE | INDICATION, NULL);
1525 break;
1526 case (8):
1527 l1_msg(cs, HW_RSYNC | INDICATION, NULL);
1528 break;
1529 case (6):
1530 l1_msg(cs, HW_INFO2 | INDICATION, NULL);
1531 break;
1532 case (7):
1533 l1_msg(cs, HW_INFO4_P8 | INDICATION, NULL);
1534 break;
1535 default:
1536 break;
1537 } else {
1538 spin_lock_irqsave(&cs->lock, flags);
1539 switch (cs->dc.hfcpci.ph_state) {
1540 case (2):
1541 if (cs->hw.hfcpci.nt_timer < 0) {
1542 cs->hw.hfcpci.nt_timer = 0;
1543 cs->hw.hfcpci.int_m1 &= ~HFCPCI_INTS_TIMER;
1544 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
1545 /* Clear already pending ints */
1546 if (Read_hfc(cs, HFCPCI_INT_S1));
1547 Write_hfc(cs, HFCPCI_STATES, 4 | HFCPCI_LOAD_STATE);
1548 udelay(10);
1549 Write_hfc(cs, HFCPCI_STATES, 4);
1550 cs->dc.hfcpci.ph_state = 4;
1551 } else {
1552 cs->hw.hfcpci.int_m1 |= HFCPCI_INTS_TIMER;
1553 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
1554 cs->hw.hfcpci.ctmt &= ~HFCPCI_AUTO_TIMER;
1555 cs->hw.hfcpci.ctmt |= HFCPCI_TIM3_125;
1556 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt | HFCPCI_CLTIMER);
1557 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt | HFCPCI_CLTIMER);
1558 cs->hw.hfcpci.nt_timer = NT_T1_COUNT;
1559 Write_hfc(cs, HFCPCI_STATES, 2 | HFCPCI_NT_G2_G3); /* allow G2 -> G3 transition */
1560 }
1561 break;
1562 case (1):
1563 case (3):
1564 case (4):
1565 cs->hw.hfcpci.nt_timer = 0;
1566 cs->hw.hfcpci.int_m1 &= ~HFCPCI_INTS_TIMER;
1567 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
1568 break;
1569 default:
1570 break;
1571 }
1572 spin_unlock_irqrestore(&cs->lock, flags);
1573 }
1574 }
1575 if (test_and_clear_bit(D_RCVBUFREADY, &cs->event))
1576 DChannel_proc_rcv(cs);
1577 if (test_and_clear_bit(D_XMTBUFREADY, &cs->event))
1578 DChannel_proc_xmt(cs);
1579 }
1580
1581
1582 /********************************/
1583 /* called for card init message */
1584 /********************************/
1585 static void __init
1586 inithfcpci(struct IsdnCardState *cs)
1587 {
1588 cs->bcs[0].BC_SetStack = setstack_2b;
1589 cs->bcs[1].BC_SetStack = setstack_2b;
1590 cs->bcs[0].BC_Close = close_hfcpci;
1591 cs->bcs[1].BC_Close = close_hfcpci;
1592 cs->dbusytimer.function = (void *) hfcpci_dbusy_timer;
1593 cs->dbusytimer.data = (long) cs;
1594 init_timer(&cs->dbusytimer);
1595 mode_hfcpci(cs->bcs, 0, 0);
1596 mode_hfcpci(cs->bcs + 1, 0, 1);
1597 }
1598
1599
1600
1601 /*******************************************/
1602 /* handle card messages from control layer */
1603 /*******************************************/
1604 static int
1605 hfcpci_card_msg(struct IsdnCardState *cs, int mt, void *arg)
1606 {
1607 u_long flags;
1608
1609 if (cs->debug & L1_DEB_ISAC)
1610 debugl1(cs, "HFCPCI: card_msg %x", mt);
1611 switch (mt) {
1612 case CARD_RESET:
1613 spin_lock_irqsave(&cs->lock, flags);
1614 reset_hfcpci(cs);
1615 spin_unlock_irqrestore(&cs->lock, flags);
1616 return (0);
1617 case CARD_RELEASE:
1618 release_io_hfcpci(cs);
1619 return (0);
1620 case CARD_INIT:
1621 spin_lock_irqsave(&cs->lock, flags);
1622 inithfcpci(cs);
1623 reset_hfcpci(cs);
1624 spin_unlock_irqrestore(&cs->lock, flags);
1625 msleep(80); /* Timeout 80ms */
1626 /* now switch timer interrupt off */
1627 spin_lock_irqsave(&cs->lock, flags);
1628 cs->hw.hfcpci.int_m1 &= ~HFCPCI_INTS_TIMER;
1629 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
1630 /* reinit mode reg */
1631 Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m);
1632 spin_unlock_irqrestore(&cs->lock, flags);
1633 return (0);
1634 case CARD_TEST:
1635 return (0);
1636 }
1637 return (0);
1638 }
1639
1640
1641 /* this variable is used as card index when more than one cards are present */
1642 static struct pci_dev *dev_hfcpci __initdata = NULL;
1643
1644 #endif /* CONFIG_PCI */
1645
1646 int __init
1647 setup_hfcpci(struct IsdnCard *card)
1648 {
1649 u_long flags;
1650 struct IsdnCardState *cs = card->cs;
1651 char tmp[64];
1652 int i;
1653 struct pci_dev *tmp_hfcpci = NULL;
1654
1655 #ifdef __BIG_ENDIAN
1656 #error "not running on big endian machines now"
1657 #endif
1658 strcpy(tmp, hfcpci_revision);
1659 printk(KERN_INFO "HiSax: HFC-PCI driver Rev. %s\n", HiSax_getrev(tmp));
1660 #ifdef CONFIG_PCI
1661 cs->hw.hfcpci.int_s1 = 0;
1662 cs->dc.hfcpci.ph_state = 0;
1663 cs->hw.hfcpci.fifo = 255;
1664 if (cs->typ == ISDN_CTYPE_HFC_PCI) {
1665 i = 0;
1666 while (id_list[i].vendor_id) {
1667 tmp_hfcpci = pci_find_device(id_list[i].vendor_id,
1668 id_list[i].device_id,
1669 dev_hfcpci);
1670 i++;
1671 if (tmp_hfcpci) {
1672 if (pci_enable_device(tmp_hfcpci))
1673 continue;
1674 pci_set_master(tmp_hfcpci);
1675 if ((card->para[0]) && (card->para[0] != (tmp_hfcpci->resource[ 0].start & PCI_BASE_ADDRESS_IO_MASK)))
1676 continue;
1677 else
1678 break;
1679 }
1680 }
1681
1682 if (tmp_hfcpci) {
1683 i--;
1684 dev_hfcpci = tmp_hfcpci; /* old device */
1685 cs->hw.hfcpci.dev = dev_hfcpci;
1686 cs->irq = dev_hfcpci->irq;
1687 if (!cs->irq) {
1688 printk(KERN_WARNING "HFC-PCI: No IRQ for PCI card found\n");
1689 return (0);
1690 }
1691 cs->hw.hfcpci.pci_io = (char *) dev_hfcpci->resource[ 1].start;
1692 printk(KERN_INFO "HiSax: HFC-PCI card manufacturer: %s card name: %s\n", id_list[i].vendor_name, id_list[i].card_name);
1693 } else {
1694 printk(KERN_WARNING "HFC-PCI: No PCI card found\n");
1695 return (0);
1696 }
1697 if (!cs->hw.hfcpci.pci_io) {
1698 printk(KERN_WARNING "HFC-PCI: No IO-Mem for PCI card found\n");
1699 return (0);
1700 }
1701 /* Allocate memory for FIFOS */
1702 /* Because the HFC-PCI needs a 32K physical alignment, we */
1703 /* need to allocate the double mem and align the address */
1704 if (!(cs->hw.hfcpci.share_start = kmalloc(65536, GFP_KERNEL))) {
1705 printk(KERN_WARNING "HFC-PCI: Error allocating memory for FIFO!\n");
1706 return 0;
1707 }
1708 cs->hw.hfcpci.fifos = (void *)
1709 (((ulong) cs->hw.hfcpci.share_start) & ~0x7FFF) + 0x8000;
1710 pci_write_config_dword(cs->hw.hfcpci.dev, 0x80, (u_int) virt_to_bus(cs->hw.hfcpci.fifos));
1711 cs->hw.hfcpci.pci_io = ioremap((ulong) cs->hw.hfcpci.pci_io, 256);
1712 printk(KERN_INFO
1713 "HFC-PCI: defined at mem %#x fifo %#x(%#x) IRQ %d HZ %d\n",
1714 (u_int) cs->hw.hfcpci.pci_io,
1715 (u_int) cs->hw.hfcpci.fifos,
1716 (u_int) virt_to_bus(cs->hw.hfcpci.fifos),
1717 cs->irq, HZ);
1718 spin_lock_irqsave(&cs->lock, flags);
1719 pci_write_config_word(cs->hw.hfcpci.dev, PCI_COMMAND, PCI_ENA_MEMIO); /* enable memory mapped ports, disable busmaster */
1720 cs->hw.hfcpci.int_m2 = 0; /* disable alle interrupts */
1721 cs->hw.hfcpci.int_m1 = 0;
1722 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
1723 Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2);
1724 /* At this point the needed PCI config is done */
1725 /* fifos are still not enabled */
1726 INIT_WORK(&cs->tqueue, (void *)(void *) hfcpci_bh, cs);
1727 cs->setstack_d = setstack_hfcpci;
1728 cs->BC_Send_Data = &hfcpci_send_data;
1729 cs->readisac = NULL;
1730 cs->writeisac = NULL;
1731 cs->readisacfifo = NULL;
1732 cs->writeisacfifo = NULL;
1733 cs->BC_Read_Reg = NULL;
1734 cs->BC_Write_Reg = NULL;
1735 cs->irq_func = &hfcpci_interrupt;
1736 cs->irq_flags |= SA_SHIRQ;
1737 cs->hw.hfcpci.timer.function = (void *) hfcpci_Timer;
1738 cs->hw.hfcpci.timer.data = (long) cs;
1739 init_timer(&cs->hw.hfcpci.timer);
1740 cs->cardmsg = &hfcpci_card_msg;
1741 cs->auxcmd = &hfcpci_auxcmd;
1742 spin_unlock_irqrestore(&cs->lock, flags);
1743 return (1);
1744 } else
1745 return (0); /* no valid card type */
1746 #else
1747 printk(KERN_WARNING "HFC-PCI: NO_PCI_BIOS\n");
1748 return (0);
1749 #endif /* CONFIG_PCI */
1750 }
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