?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
[PATCH] Represent laptop_mode as jiffies internally
[linux-2.6/verdex.git] / drivers / serial / m32r_sio.c
blobe9c10c0a30fc057c9c47c49caadd3e557bbbd6a9
1 /*
2 * m32r_sio.c
3 *
4 * Driver for M32R serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 * Based on drivers/serial/8250.c.
8 *
9 * Copyright (C) 2001 Russell King.
10 * Copyright (C) 2004 Hirokazu Takata <takata at linux-m32r.org>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 */
17
18 /*
19 * A note about mapbase / membase
20 *
21 * mapbase is the physical address of the IO port. Currently, we don't
22 * support this very well, and it may well be dropped from this driver
23 * in future. As such, mapbase should be NULL.
24 *
25 * membase is an 'ioremapped' cookie. This is compatible with the old
26 * serial.c driver, and is currently the preferred form.
27 */
28 #include <linux/config.h>
29
30 #if defined(CONFIG_SERIAL_M32R_SIO_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
31 #define SUPPORT_SYSRQ
32 #endif
33
34 #include <linux/module.h>
35 #include <linux/tty.h>
36 #include <linux/ioport.h>
37 #include <linux/init.h>
38 #include <linux/console.h>
39 #include <linux/sysrq.h>
40 #include <linux/serial.h>
41 #include <linux/serialP.h>
42 #include <linux/delay.h>
43
44 #include <asm/m32r.h>
45 #include <asm/io.h>
46 #include <asm/irq.h>
47
48 #define PORT_M32R_BASE PORT_M32R_SIO
49 #define PORT_INDEX(x) (x - PORT_M32R_BASE + 1)
50 #define BAUD_RATE 115200
51
52 #include <linux/serial_core.h>
53 #include "m32r_sio.h"
54 #include "m32r_sio_reg.h"
55
56 /*
57 * Debugging.
58 */
59 #if 0
60 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
61 #else
62 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
63 #endif
64
65 #if 0
66 #define DEBUG_INTR(fmt...) printk(fmt)
67 #else
68 #define DEBUG_INTR(fmt...) do { } while (0)
69 #endif
70
71 #define PASS_LIMIT 256
72
73 /*
74 * We default to IRQ0 for the "no irq" hack. Some
75 * machine types want others as well - they're free
76 * to redefine this in their header file.
77 */
78 #define is_real_interrupt(irq) ((irq) != 0)
79
80 #include <asm/serial.h>
81
82 /* Standard COM flags */
83 #define STD_COM_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST)
84
85 /*
86 * SERIAL_PORT_DFNS tells us about built-in ports that have no
87 * standard enumeration mechanism. Platforms that can find all
88 * serial ports via mechanisms like ACPI or PCI need not supply it.
89 */
90 #undef SERIAL_PORT_DFNS
91 #if defined(CONFIG_PLAT_USRV)
92
93 #define SERIAL_PORT_DFNS \
94 /* UART CLK PORT IRQ FLAGS */ \
95 { 0, BASE_BAUD, 0x3F8, PLD_IRQ_UART0, STD_COM_FLAGS }, /* ttyS0 */ \
96 { 0, BASE_BAUD, 0x2F8, PLD_IRQ_UART1, STD_COM_FLAGS }, /* ttyS1 */
97
98 #else /* !CONFIG_PLAT_USRV */
99
100 #if defined(CONFIG_SERIAL_M32R_PLDSIO)
101 #define SERIAL_PORT_DFNS \
102 { 0, BASE_BAUD, ((unsigned long)PLD_ESIO0CR), PLD_IRQ_SIO0_RCV, \
103 STD_COM_FLAGS }, /* ttyS0 */
104 #else
105 #define SERIAL_PORT_DFNS \
106 { 0, BASE_BAUD, M32R_SIO_OFFSET, M32R_IRQ_SIO0_R, \
107 STD_COM_FLAGS }, /* ttyS0 */
108 #endif
109
110 #endif /* !CONFIG_PLAT_USRV */
111
112 static struct old_serial_port old_serial_port[] = {
113 SERIAL_PORT_DFNS /* defined in asm/serial.h */
114 };
115
116 #define UART_NR ARRAY_SIZE(old_serial_port)
117
118 struct uart_sio_port {
119 struct uart_port port;
120 struct timer_list timer; /* "no irq" timer */
121 struct list_head list; /* ports on this IRQ */
122 unsigned short rev;
123 unsigned char acr;
124 unsigned char ier;
125 unsigned char lcr;
126 unsigned char mcr_mask; /* mask of user bits */
127 unsigned char mcr_force; /* mask of forced bits */
128 unsigned char lsr_break_flag;
129
130 /*
131 * We provide a per-port pm hook.
132 */
133 void (*pm)(struct uart_port *port,
134 unsigned int state, unsigned int old);
135 };
136
137 struct irq_info {
138 spinlock_t lock;
139 struct list_head *head;
140 };
141
142 static struct irq_info irq_lists[NR_IRQS];
143
144 /*
145 * Here we define the default xmit fifo size used for each type of UART.
146 */
147 static const struct serial_uart_config uart_config[] = {
148 [PORT_UNKNOWN] = {
149 .name = "unknown",
150 .dfl_xmit_fifo_size = 1,
151 .flags = 0,
152 },
153 [PORT_INDEX(PORT_M32R_SIO)] = {
154 .name = "M32RSIO",
155 .dfl_xmit_fifo_size = 1,
156 .flags = 0,
157 },
158 };
159
160 #ifdef CONFIG_SERIAL_M32R_PLDSIO
161
162 #define __sio_in(x) inw((unsigned long)(x))
163 #define __sio_out(v,x) outw((v),(unsigned long)(x))
164
165 static inline void sio_set_baud_rate(unsigned long baud)
166 {
167 unsigned short sbaud;
168 sbaud = (boot_cpu_data.bus_clock / (baud * 4))-1;
169 __sio_out(sbaud, PLD_ESIO0BAUR);
170 }
171
172 static void sio_reset(void)
173 {
174 unsigned short tmp;
175
176 tmp = __sio_in(PLD_ESIO0RXB);
177 tmp = __sio_in(PLD_ESIO0RXB);
178 tmp = __sio_in(PLD_ESIO0CR);
179 sio_set_baud_rate(BAUD_RATE);
180 __sio_out(0x0300, PLD_ESIO0CR);
181 __sio_out(0x0003, PLD_ESIO0CR);
182 }
183
184 static void sio_init(void)
185 {
186 unsigned short tmp;
187
188 tmp = __sio_in(PLD_ESIO0RXB);
189 tmp = __sio_in(PLD_ESIO0RXB);
190 tmp = __sio_in(PLD_ESIO0CR);
191 __sio_out(0x0300, PLD_ESIO0CR);
192 __sio_out(0x0003, PLD_ESIO0CR);
193 }
194
195 static void sio_error(int *status)
196 {
197 printk("SIO0 error[%04x]\n", *status);
198 do {
199 sio_init();
200 } while ((*status = __sio_in(PLD_ESIO0CR)) != 3);
201 }
202
203 #else /* not CONFIG_SERIAL_M32R_PLDSIO */
204
205 #define __sio_in(x) inl(x)
206 #define __sio_out(v,x) outl((v),(x))
207
208 static inline void sio_set_baud_rate(unsigned long baud)
209 {
210 unsigned long i, j;
211
212 i = boot_cpu_data.bus_clock / (baud * 16);
213 j = (boot_cpu_data.bus_clock - (i * baud * 16)) / baud;
214 i -= 1;
215 j = (j + 1) >> 1;
216
217 __sio_out(i, M32R_SIO0_BAUR_PORTL);
218 __sio_out(j, M32R_SIO0_RBAUR_PORTL);
219 }
220
221 static void sio_reset(void)
222 {
223 __sio_out(0x00000300, M32R_SIO0_CR_PORTL); /* init status */
224 __sio_out(0x00000800, M32R_SIO0_MOD1_PORTL); /* 8bit */
225 __sio_out(0x00000080, M32R_SIO0_MOD0_PORTL); /* 1stop non */
226 sio_set_baud_rate(BAUD_RATE);
227 __sio_out(0x00000000, M32R_SIO0_TRCR_PORTL);
228 __sio_out(0x00000003, M32R_SIO0_CR_PORTL); /* RXCEN */
229 }
230
231 static void sio_init(void)
232 {
233 unsigned int tmp;
234
235 tmp = __sio_in(M32R_SIO0_RXB_PORTL);
236 tmp = __sio_in(M32R_SIO0_RXB_PORTL);
237 tmp = __sio_in(M32R_SIO0_STS_PORTL);
238 __sio_out(0x00000003, M32R_SIO0_CR_PORTL);
239 }
240
241 static void sio_error(int *status)
242 {
243 printk("SIO0 error[%04x]\n", *status);
244 do {
245 sio_init();
246 } while ((*status = __sio_in(M32R_SIO0_CR_PORTL)) != 3);
247 }
248
249 #endif /* CONFIG_SERIAL_M32R_PLDSIO */
250
251 static unsigned int sio_in(struct uart_sio_port *up, int offset)
252 {
253 return __sio_in(up->port.iobase + offset);
254 }
255
256 static void sio_out(struct uart_sio_port *up, int offset, int value)
257 {
258 __sio_out(value, up->port.iobase + offset);
259 }
260
261 static unsigned int serial_in(struct uart_sio_port *up, int offset)
262 {
263 if (!offset)
264 return 0;
265
266 return __sio_in(offset);
267 }
268
269 static void serial_out(struct uart_sio_port *up, int offset, int value)
270 {
271 if (!offset)
272 return;
273
274 __sio_out(value, offset);
275 }
276
277 static void m32r_sio_stop_tx(struct uart_port *port)
278 {
279 struct uart_sio_port *up = (struct uart_sio_port *)port;
280
281 if (up->ier & UART_IER_THRI) {
282 up->ier &= ~UART_IER_THRI;
283 serial_out(up, UART_IER, up->ier);
284 }
285 }
286
287 static void m32r_sio_start_tx(struct uart_port *port)
288 {
289 #ifdef CONFIG_SERIAL_M32R_PLDSIO
290 struct uart_sio_port *up = (struct uart_sio_port *)port;
291 struct circ_buf *xmit = &up->port.info->xmit;
292
293 if (!(up->ier & UART_IER_THRI)) {
294 up->ier |= UART_IER_THRI;
295 serial_out(up, UART_IER, up->ier);
296 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
297 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
298 up->port.icount.tx++;
299 }
300 while((serial_in(up, UART_LSR) & UART_EMPTY) != UART_EMPTY);
301 #else
302 struct uart_sio_port *up = (struct uart_sio_port *)port;
303
304 if (!(up->ier & UART_IER_THRI)) {
305 up->ier |= UART_IER_THRI;
306 serial_out(up, UART_IER, up->ier);
307 }
308 #endif
309 }
310
311 static void m32r_sio_stop_rx(struct uart_port *port)
312 {
313 struct uart_sio_port *up = (struct uart_sio_port *)port;
314
315 up->ier &= ~UART_IER_RLSI;
316 up->port.read_status_mask &= ~UART_LSR_DR;
317 serial_out(up, UART_IER, up->ier);
318 }
319
320 static void m32r_sio_enable_ms(struct uart_port *port)
321 {
322 struct uart_sio_port *up = (struct uart_sio_port *)port;
323
324 up->ier |= UART_IER_MSI;
325 serial_out(up, UART_IER, up->ier);
326 }
327
328 static void receive_chars(struct uart_sio_port *up, int *status,
329 struct pt_regs *regs)
330 {
331 struct tty_struct *tty = up->port.info->tty;
332 unsigned char ch;
333 unsigned char flag;
334 int max_count = 256;
335
336 do {
337 ch = sio_in(up, SIORXB);
338 flag = TTY_NORMAL;
339 up->port.icount.rx++;
340
341 if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE |
342 UART_LSR_FE | UART_LSR_OE))) {
343 /*
344 * For statistics only
345 */
346 if (*status & UART_LSR_BI) {
347 *status &= ~(UART_LSR_FE | UART_LSR_PE);
348 up->port.icount.brk++;
349 /*
350 * We do the SysRQ and SAK checking
351 * here because otherwise the break
352 * may get masked by ignore_status_mask
353 * or read_status_mask.
354 */
355 if (uart_handle_break(&up->port))
356 goto ignore_char;
357 } else if (*status & UART_LSR_PE)
358 up->port.icount.parity++;
359 else if (*status & UART_LSR_FE)
360 up->port.icount.frame++;
361 if (*status & UART_LSR_OE)
362 up->port.icount.overrun++;
363
364 /*
365 * Mask off conditions which should be ingored.
366 */
367 *status &= up->port.read_status_mask;
368
369 if (up->port.line == up->port.cons->index) {
370 /* Recover the break flag from console xmit */
371 *status |= up->lsr_break_flag;
372 up->lsr_break_flag = 0;
373 }
374
375 if (*status & UART_LSR_BI) {
376 DEBUG_INTR("handling break....");
377 flag = TTY_BREAK;
378 } else if (*status & UART_LSR_PE)
379 flag = TTY_PARITY;
380 else if (*status & UART_LSR_FE)
381 flag = TTY_FRAME;
382 }
383 if (uart_handle_sysrq_char(&up->port, ch, regs))
384 goto ignore_char;
385 if ((*status & up->port.ignore_status_mask) == 0)
386 tty_insert_flip_char(tty, ch, flag);
387
388 if (*status & UART_LSR_OE) {
389 /*
390 * Overrun is special, since it's reported
391 * immediately, and doesn't affect the current
392 * character.
393 */
394 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
395 }
396 ignore_char:
397 *status = serial_in(up, UART_LSR);
398 } while ((*status & UART_LSR_DR) && (max_count-- > 0));
399 tty_flip_buffer_push(tty);
400 }
401
402 static void transmit_chars(struct uart_sio_port *up)
403 {
404 struct circ_buf *xmit = &up->port.info->xmit;
405 int count;
406
407 if (up->port.x_char) {
408 #ifndef CONFIG_SERIAL_M32R_PLDSIO /* XXX */
409 serial_out(up, UART_TX, up->port.x_char);
410 #endif
411 up->port.icount.tx++;
412 up->port.x_char = 0;
413 return;
414 }
415 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
416 m32r_sio_stop_tx(&up->port);
417 return;
418 }
419
420 count = up->port.fifosize;
421 do {
422 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
423 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
424 up->port.icount.tx++;
425 if (uart_circ_empty(xmit))
426 break;
427 while (!serial_in(up, UART_LSR) & UART_LSR_THRE);
428
429 } while (--count > 0);
430
431 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
432 uart_write_wakeup(&up->port);
433
434 DEBUG_INTR("THRE...");
435
436 if (uart_circ_empty(xmit))
437 m32r_sio_stop_tx(&up->port);
438 }
439
440 /*
441 * This handles the interrupt from one port.
442 */
443 static inline void m32r_sio_handle_port(struct uart_sio_port *up,
444 unsigned int status, struct pt_regs *regs)
445 {
446 DEBUG_INTR("status = %x...", status);
447
448 if (status & 0x04)
449 receive_chars(up, &status, regs);
450 if (status & 0x01)
451 transmit_chars(up);
452 }
453
454 /*
455 * This is the serial driver's interrupt routine.
456 *
457 * Arjan thinks the old way was overly complex, so it got simplified.
458 * Alan disagrees, saying that need the complexity to handle the weird
459 * nature of ISA shared interrupts. (This is a special exception.)
460 *
461 * In order to handle ISA shared interrupts properly, we need to check
462 * that all ports have been serviced, and therefore the ISA interrupt
463 * line has been de-asserted.
464 *
465 * This means we need to loop through all ports. checking that they
466 * don't have an interrupt pending.
467 */
468 static irqreturn_t m32r_sio_interrupt(int irq, void *dev_id,
469 struct pt_regs *regs)
470 {
471 struct irq_info *i = dev_id;
472 struct list_head *l, *end = NULL;
473 int pass_counter = 0;
474
475 DEBUG_INTR("m32r_sio_interrupt(%d)...", irq);
476
477 #ifdef CONFIG_SERIAL_M32R_PLDSIO
478 // if (irq == PLD_IRQ_SIO0_SND)
479 // irq = PLD_IRQ_SIO0_RCV;
480 #else
481 if (irq == M32R_IRQ_SIO0_S)
482 irq = M32R_IRQ_SIO0_R;
483 #endif
484
485 spin_lock(&i->lock);
486
487 l = i->head;
488 do {
489 struct uart_sio_port *up;
490 unsigned int sts;
491
492 up = list_entry(l, struct uart_sio_port, list);
493
494 sts = sio_in(up, SIOSTS);
495 if (sts & 0x5) {
496 spin_lock(&up->port.lock);
497 m32r_sio_handle_port(up, sts, regs);
498 spin_unlock(&up->port.lock);
499
500 end = NULL;
501 } else if (end == NULL)
502 end = l;
503
504 l = l->next;
505
506 if (l == i->head && pass_counter++ > PASS_LIMIT) {
507 if (sts & 0xe0)
508 sio_error(&sts);
509 break;
510 }
511 } while (l != end);
512
513 spin_unlock(&i->lock);
514
515 DEBUG_INTR("end.\n");
516
517 return IRQ_HANDLED;
518 }
519
520 /*
521 * To support ISA shared interrupts, we need to have one interrupt
522 * handler that ensures that the IRQ line has been deasserted
523 * before returning. Failing to do this will result in the IRQ
524 * line being stuck active, and, since ISA irqs are edge triggered,
525 * no more IRQs will be seen.
526 */
527 static void serial_do_unlink(struct irq_info *i, struct uart_sio_port *up)
528 {
529 spin_lock_irq(&i->lock);
530
531 if (!list_empty(i->head)) {
532 if (i->head == &up->list)
533 i->head = i->head->next;
534 list_del(&up->list);
535 } else {
536 BUG_ON(i->head != &up->list);
537 i->head = NULL;
538 }
539
540 spin_unlock_irq(&i->lock);
541 }
542
543 static int serial_link_irq_chain(struct uart_sio_port *up)
544 {
545 struct irq_info *i = irq_lists + up->port.irq;
546 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? SA_SHIRQ : 0;
547
548 spin_lock_irq(&i->lock);
549
550 if (i->head) {
551 list_add(&up->list, i->head);
552 spin_unlock_irq(&i->lock);
553
554 ret = 0;
555 } else {
556 INIT_LIST_HEAD(&up->list);
557 i->head = &up->list;
558 spin_unlock_irq(&i->lock);
559
560 ret = request_irq(up->port.irq, m32r_sio_interrupt,
561 irq_flags, "SIO0-RX", i);
562 ret |= request_irq(up->port.irq + 1, m32r_sio_interrupt,
563 irq_flags, "SIO0-TX", i);
564 if (ret < 0)
565 serial_do_unlink(i, up);
566 }
567
568 return ret;
569 }
570
571 static void serial_unlink_irq_chain(struct uart_sio_port *up)
572 {
573 struct irq_info *i = irq_lists + up->port.irq;
574
575 BUG_ON(i->head == NULL);
576
577 if (list_empty(i->head)) {
578 free_irq(up->port.irq, i);
579 free_irq(up->port.irq + 1, i);
580 }
581
582 serial_do_unlink(i, up);
583 }
584
585 /*
586 * This function is used to handle ports that do not have an interrupt.
587 */
588 static void m32r_sio_timeout(unsigned long data)
589 {
590 struct uart_sio_port *up = (struct uart_sio_port *)data;
591 unsigned int timeout;
592 unsigned int sts;
593
594 sts = sio_in(up, SIOSTS);
595 if (sts & 0x5) {
596 spin_lock(&up->port.lock);
597 m32r_sio_handle_port(up, sts, NULL);
598 spin_unlock(&up->port.lock);
599 }
600
601 timeout = up->port.timeout;
602 timeout = timeout > 6 ? (timeout / 2 - 2) : 1;
603 mod_timer(&up->timer, jiffies + timeout);
604 }
605
606 static unsigned int m32r_sio_tx_empty(struct uart_port *port)
607 {
608 struct uart_sio_port *up = (struct uart_sio_port *)port;
609 unsigned long flags;
610 unsigned int ret;
611
612 spin_lock_irqsave(&up->port.lock, flags);
613 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
614 spin_unlock_irqrestore(&up->port.lock, flags);
615
616 return ret;
617 }
618
619 static unsigned int m32r_sio_get_mctrl(struct uart_port *port)
620 {
621 return 0;
622 }
623
624 static void m32r_sio_set_mctrl(struct uart_port *port, unsigned int mctrl)
625 {
626
627 }
628
629 static void m32r_sio_break_ctl(struct uart_port *port, int break_state)
630 {
631
632 }
633
634 static int m32r_sio_startup(struct uart_port *port)
635 {
636 struct uart_sio_port *up = (struct uart_sio_port *)port;
637 int retval;
638
639 sio_init();
640
641 /*
642 * If the "interrupt" for this port doesn't correspond with any
643 * hardware interrupt, we use a timer-based system. The original
644 * driver used to do this with IRQ0.
645 */
646 if (!is_real_interrupt(up->port.irq)) {
647 unsigned int timeout = up->port.timeout;
648
649 timeout = timeout > 6 ? (timeout / 2 - 2) : 1;
650
651 up->timer.data = (unsigned long)up;
652 mod_timer(&up->timer, jiffies + timeout);
653 } else {
654 retval = serial_link_irq_chain(up);
655 if (retval)
656 return retval;
657 }
658
659 /*
660 * Finally, enable interrupts. Note: Modem status interrupts
661 * are set via set_termios(), which will be occurring imminently
662 * anyway, so we don't enable them here.
663 * - M32R_SIO: 0x0c
664 * - M32R_PLDSIO: 0x04
665 */
666 up->ier = UART_IER_MSI | UART_IER_RLSI | UART_IER_RDI;
667 sio_out(up, SIOTRCR, up->ier);
668
669 /*
670 * And clear the interrupt registers again for luck.
671 */
672 sio_reset();
673
674 return 0;
675 }
676
677 static void m32r_sio_shutdown(struct uart_port *port)
678 {
679 struct uart_sio_port *up = (struct uart_sio_port *)port;
680
681 /*
682 * Disable interrupts from this port
683 */
684 up->ier = 0;
685 sio_out(up, SIOTRCR, 0);
686
687 /*
688 * Disable break condition and FIFOs
689 */
690
691 sio_init();
692
693 if (!is_real_interrupt(up->port.irq))
694 del_timer_sync(&up->timer);
695 else
696 serial_unlink_irq_chain(up);
697 }
698
699 static unsigned int m32r_sio_get_divisor(struct uart_port *port,
700 unsigned int baud)
701 {
702 return uart_get_divisor(port, baud);
703 }
704
705 static void m32r_sio_set_termios(struct uart_port *port,
706 struct termios *termios, struct termios *old)
707 {
708 struct uart_sio_port *up = (struct uart_sio_port *)port;
709 unsigned char cval = 0;
710 unsigned long flags;
711 unsigned int baud, quot;
712
713 switch (termios->c_cflag & CSIZE) {
714 case CS5:
715 cval = UART_LCR_WLEN5;
716 break;
717 case CS6:
718 cval = UART_LCR_WLEN6;
719 break;
720 case CS7:
721 cval = UART_LCR_WLEN7;
722 break;
723 default:
724 case CS8:
725 cval = UART_LCR_WLEN8;
726 break;
727 }
728
729 if (termios->c_cflag & CSTOPB)
730 cval |= UART_LCR_STOP;
731 if (termios->c_cflag & PARENB)
732 cval |= UART_LCR_PARITY;
733 if (!(termios->c_cflag & PARODD))
734 cval |= UART_LCR_EPAR;
735 #ifdef CMSPAR
736 if (termios->c_cflag & CMSPAR)
737 cval |= UART_LCR_SPAR;
738 #endif
739
740 /*
741 * Ask the core to calculate the divisor for us.
742 */
743 #ifdef CONFIG_SERIAL_M32R_PLDSIO
744 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/4);
745 #else
746 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
747 #endif
748 quot = m32r_sio_get_divisor(port, baud);
749
750 /*
751 * Ok, we're now changing the port state. Do it with
752 * interrupts disabled.
753 */
754 spin_lock_irqsave(&up->port.lock, flags);
755
756 sio_set_baud_rate(baud);
757
758 /*
759 * Update the per-port timeout.
760 */
761 uart_update_timeout(port, termios->c_cflag, baud);
762
763 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
764 if (termios->c_iflag & INPCK)
765 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
766 if (termios->c_iflag & (BRKINT | PARMRK))
767 up->port.read_status_mask |= UART_LSR_BI;
768
769 /*
770 * Characteres to ignore
771 */
772 up->port.ignore_status_mask = 0;
773 if (termios->c_iflag & IGNPAR)
774 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
775 if (termios->c_iflag & IGNBRK) {
776 up->port.ignore_status_mask |= UART_LSR_BI;
777 /*
778 * If we're ignoring parity and break indicators,
779 * ignore overruns too (for real raw support).
780 */
781 if (termios->c_iflag & IGNPAR)
782 up->port.ignore_status_mask |= UART_LSR_OE;
783 }
784
785 /*
786 * ignore all characters if CREAD is not set
787 */
788 if ((termios->c_cflag & CREAD) == 0)
789 up->port.ignore_status_mask |= UART_LSR_DR;
790
791 /*
792 * CTS flow control flag and modem status interrupts
793 */
794 up->ier &= ~UART_IER_MSI;
795 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
796 up->ier |= UART_IER_MSI;
797
798 serial_out(up, UART_IER, up->ier);
799
800 up->lcr = cval; /* Save LCR */
801 spin_unlock_irqrestore(&up->port.lock, flags);
802 }
803
804 static void m32r_sio_pm(struct uart_port *port, unsigned int state,
805 unsigned int oldstate)
806 {
807 struct uart_sio_port *up = (struct uart_sio_port *)port;
808
809 if (up->pm)
810 up->pm(port, state, oldstate);
811 }
812
813 /*
814 * Resource handling. This is complicated by the fact that resources
815 * depend on the port type. Maybe we should be claiming the standard
816 * 8250 ports, and then trying to get other resources as necessary?
817 */
818 static int
819 m32r_sio_request_std_resource(struct uart_sio_port *up, struct resource **res)
820 {
821 unsigned int size = 8 << up->port.regshift;
822 #ifndef CONFIG_SERIAL_M32R_PLDSIO
823 unsigned long start;
824 #endif
825 int ret = 0;
826
827 switch (up->port.iotype) {
828 case UPIO_MEM:
829 if (up->port.mapbase) {
830 #ifdef CONFIG_SERIAL_M32R_PLDSIO
831 *res = request_mem_region(up->port.mapbase, size, "serial");
832 #else
833 start = up->port.mapbase;
834 *res = request_mem_region(start, size, "serial");
835 #endif
836 if (!*res)
837 ret = -EBUSY;
838 }
839 break;
840
841 case UPIO_PORT:
842 *res = request_region(up->port.iobase, size, "serial");
843 if (!*res)
844 ret = -EBUSY;
845 break;
846 }
847 return ret;
848 }
849
850 static void m32r_sio_release_port(struct uart_port *port)
851 {
852 struct uart_sio_port *up = (struct uart_sio_port *)port;
853 unsigned long start, offset = 0, size = 0;
854
855 size <<= up->port.regshift;
856
857 switch (up->port.iotype) {
858 case UPIO_MEM:
859 if (up->port.mapbase) {
860 /*
861 * Unmap the area.
862 */
863 iounmap(up->port.membase);
864 up->port.membase = NULL;
865
866 start = up->port.mapbase;
867
868 if (size)
869 release_mem_region(start + offset, size);
870 release_mem_region(start, 8 << up->port.regshift);
871 }
872 break;
873
874 case UPIO_PORT:
875 start = up->port.iobase;
876
877 if (size)
878 release_region(start + offset, size);
879 release_region(start + offset, 8 << up->port.regshift);
880 break;
881
882 default:
883 break;
884 }
885 }
886
887 static int m32r_sio_request_port(struct uart_port *port)
888 {
889 struct uart_sio_port *up = (struct uart_sio_port *)port;
890 struct resource *res = NULL;
891 int ret = 0;
892
893 ret = m32r_sio_request_std_resource(up, &res);
894
895 /*
896 * If we have a mapbase, then request that as well.
897 */
898 if (ret == 0 && up->port.flags & UPF_IOREMAP) {
899 int size = res->end - res->start + 1;
900
901 up->port.membase = ioremap(up->port.mapbase, size);
902 if (!up->port.membase)
903 ret = -ENOMEM;
904 }
905
906 if (ret < 0) {
907 if (res)
908 release_resource(res);
909 }
910
911 return ret;
912 }
913
914 static void m32r_sio_config_port(struct uart_port *port, int flags)
915 {
916 struct uart_sio_port *up = (struct uart_sio_port *)port;
917
918 spin_lock_irqsave(&up->port.lock, flags);
919
920 up->port.type = (PORT_M32R_SIO - PORT_M32R_BASE + 1);
921 up->port.fifosize = uart_config[up->port.type].dfl_xmit_fifo_size;
922
923 spin_unlock_irqrestore(&up->port.lock, flags);
924 }
925
926 static int
927 m32r_sio_verify_port(struct uart_port *port, struct serial_struct *ser)
928 {
929 if (ser->irq >= NR_IRQS || ser->irq < 0 ||
930 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
931 ser->type >= ARRAY_SIZE(uart_config))
932 return -EINVAL;
933 return 0;
934 }
935
936 static const char *
937 m32r_sio_type(struct uart_port *port)
938 {
939 int type = port->type;
940
941 if (type >= ARRAY_SIZE(uart_config))
942 type = 0;
943 return uart_config[type].name;
944 }
945
946 static struct uart_ops m32r_sio_pops = {
947 .tx_empty = m32r_sio_tx_empty,
948 .set_mctrl = m32r_sio_set_mctrl,
949 .get_mctrl = m32r_sio_get_mctrl,
950 .stop_tx = m32r_sio_stop_tx,
951 .start_tx = m32r_sio_start_tx,
952 .stop_rx = m32r_sio_stop_rx,
953 .enable_ms = m32r_sio_enable_ms,
954 .break_ctl = m32r_sio_break_ctl,
955 .startup = m32r_sio_startup,
956 .shutdown = m32r_sio_shutdown,
957 .set_termios = m32r_sio_set_termios,
958 .pm = m32r_sio_pm,
959 .type = m32r_sio_type,
960 .release_port = m32r_sio_release_port,
961 .request_port = m32r_sio_request_port,
962 .config_port = m32r_sio_config_port,
963 .verify_port = m32r_sio_verify_port,
964 };
965
966 static struct uart_sio_port m32r_sio_ports[UART_NR];
967
968 static void __init m32r_sio_init_ports(void)
969 {
970 struct uart_sio_port *up;
971 static int first = 1;
972 int i;
973
974 if (!first)
975 return;
976 first = 0;
977
978 for (i = 0, up = m32r_sio_ports; i < ARRAY_SIZE(old_serial_port);
979 i++, up++) {
980 up->port.iobase = old_serial_port[i].port;
981 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
982 up->port.uartclk = old_serial_port[i].baud_base * 16;
983 up->port.flags = old_serial_port[i].flags;
984 up->port.membase = old_serial_port[i].iomem_base;
985 up->port.iotype = old_serial_port[i].io_type;
986 up->port.regshift = old_serial_port[i].iomem_reg_shift;
987 up->port.ops = &m32r_sio_pops;
988 }
989 }
990
991 static void __init m32r_sio_register_ports(struct uart_driver *drv)
992 {
993 int i;
994
995 m32r_sio_init_ports();
996
997 for (i = 0; i < UART_NR; i++) {
998 struct uart_sio_port *up = &m32r_sio_ports[i];
999
1000 up->port.line = i;
1001 up->port.ops = &m32r_sio_pops;
1002 init_timer(&up->timer);
1003 up->timer.function = m32r_sio_timeout;
1004
1005 /*
1006 * ALPHA_KLUDGE_MCR needs to be killed.
1007 */
1008 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
1009 up->mcr_force = ALPHA_KLUDGE_MCR;
1010
1011 uart_add_one_port(drv, &up->port);
1012 }
1013 }
1014
1015 #ifdef CONFIG_SERIAL_M32R_SIO_CONSOLE
1016
1017 /*
1018 * Wait for transmitter & holding register to empty
1019 */
1020 static inline void wait_for_xmitr(struct uart_sio_port *up)
1021 {
1022 unsigned int status, tmout = 10000;
1023
1024 /* Wait up to 10ms for the character(s) to be sent. */
1025 do {
1026 status = sio_in(up, SIOSTS);
1027
1028 if (--tmout == 0)
1029 break;
1030 udelay(1);
1031 } while ((status & UART_EMPTY) != UART_EMPTY);
1032
1033 /* Wait up to 1s for flow control if necessary */
1034 if (up->port.flags & UPF_CONS_FLOW) {
1035 tmout = 1000000;
1036 while (--tmout)
1037 udelay(1);
1038 }
1039 }
1040
1041 static void m32r_sio_console_putchar(struct uart_port *port, int ch)
1042 {
1043 struct uart_sio_port *up = (struct uart_sio_port *)port;
1044
1045 wait_for_xmitr(up);
1046 sio_out(up, SIOTXB, ch);
1047 }
1048
1049 /*
1050 * Print a string to the serial port trying not to disturb
1051 * any possible real use of the port...
1052 *
1053 * The console_lock must be held when we get here.
1054 */
1055 static void m32r_sio_console_write(struct console *co, const char *s,
1056 unsigned int count)
1057 {
1058 struct uart_sio_port *up = &m32r_sio_ports[co->index];
1059 unsigned int ier;
1060 int i;
1061
1062 /*
1063 * First save the UER then disable the interrupts
1064 */
1065 ier = sio_in(up, SIOTRCR);
1066 sio_out(up, SIOTRCR, 0);
1067
1068 uart_console_write(&up->port, s, count, m32r_sio_console_putchar);
1069
1070 /*
1071 * Finally, wait for transmitter to become empty
1072 * and restore the IER
1073 */
1074 wait_for_xmitr(up);
1075 sio_out(up, SIOTRCR, ier);
1076 }
1077
1078 static int __init m32r_sio_console_setup(struct console *co, char *options)
1079 {
1080 struct uart_port *port;
1081 int baud = 9600;
1082 int bits = 8;
1083 int parity = 'n';
1084 int flow = 'n';
1085
1086 /*
1087 * Check whether an invalid uart number has been specified, and
1088 * if so, search for the first available port that does have
1089 * console support.
1090 */
1091 if (co->index >= UART_NR)
1092 co->index = 0;
1093 port = &m32r_sio_ports[co->index].port;
1094
1095 /*
1096 * Temporary fix.
1097 */
1098 spin_lock_init(&port->lock);
1099
1100 if (options)
1101 uart_parse_options(options, &baud, &parity, &bits, &flow);
1102
1103 return uart_set_options(port, co, baud, parity, bits, flow);
1104 }
1105
1106 static struct uart_driver m32r_sio_reg;
1107 static struct console m32r_sio_console = {
1108 .name = "ttyS",
1109 .write = m32r_sio_console_write,
1110 .device = uart_console_device,
1111 .setup = m32r_sio_console_setup,
1112 .flags = CON_PRINTBUFFER,
1113 .index = -1,
1114 .data = &m32r_sio_reg,
1115 };
1116
1117 static int __init m32r_sio_console_init(void)
1118 {
1119 sio_reset();
1120 sio_init();
1121 m32r_sio_init_ports();
1122 register_console(&m32r_sio_console);
1123 return 0;
1124 }
1125 console_initcall(m32r_sio_console_init);
1126
1127 #define M32R_SIO_CONSOLE &m32r_sio_console
1128 #else
1129 #define M32R_SIO_CONSOLE NULL
1130 #endif
1131
1132 static struct uart_driver m32r_sio_reg = {
1133 .owner = THIS_MODULE,
1134 .driver_name = "sio",
1135 .devfs_name = "tts/",
1136 .dev_name = "ttyS",
1137 .major = TTY_MAJOR,
1138 .minor = 64,
1139 .nr = UART_NR,
1140 .cons = M32R_SIO_CONSOLE,
1141 };
1142
1143 /**
1144 * m32r_sio_suspend_port - suspend one serial port
1145 * @line: serial line number
1146 *
1147 * Suspend one serial port.
1148 */
1149 void m32r_sio_suspend_port(int line)
1150 {
1151 uart_suspend_port(&m32r_sio_reg, &m32r_sio_ports[line].port);
1152 }
1153
1154 /**
1155 * m32r_sio_resume_port - resume one serial port
1156 * @line: serial line number
1157 *
1158 * Resume one serial port.
1159 */
1160 void m32r_sio_resume_port(int line)
1161 {
1162 uart_resume_port(&m32r_sio_reg, &m32r_sio_ports[line].port);
1163 }
1164
1165 static int __init m32r_sio_init(void)
1166 {
1167 int ret, i;
1168
1169 printk(KERN_INFO "Serial: M32R SIO driver $Revision: 1.11 $ ");
1170
1171 for (i = 0; i < NR_IRQS; i++)
1172 spin_lock_init(&irq_lists[i].lock);
1173
1174 ret = uart_register_driver(&m32r_sio_reg);
1175 if (ret >= 0)
1176 m32r_sio_register_ports(&m32r_sio_reg);
1177
1178 return ret;
1179 }
1180
1181 static void __exit m32r_sio_exit(void)
1182 {
1183 int i;
1184
1185 for (i = 0; i < UART_NR; i++)
1186 uart_remove_one_port(&m32r_sio_reg, &m32r_sio_ports[i].port);
1187
1188 uart_unregister_driver(&m32r_sio_reg);
1189 }
1190
1191 module_init(m32r_sio_init);
1192 module_exit(m32r_sio_exit);
1193
1194 EXPORT_SYMBOL(m32r_sio_suspend_port);
1195 EXPORT_SYMBOL(m32r_sio_resume_port);
1196
1197 MODULE_LICENSE("GPL");
1198 MODULE_DESCRIPTION("Generic M32R SIO serial driver $Revision: 1.11 $");
Verdex Pro support