2 * Copyright (C) 2004 Benjamin Herrenschmuidt (benh@kernel.crashing.org),
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
13 #include <linux/kernel.h>
14 #include <linux/pci.h>
15 #include <linux/delay.h>
16 #include <linux/string.h>
17 #include <linux/init.h>
18 #include <linux/bootmem.h>
20 #include <asm/sections.h>
23 #include <asm/pci-bridge.h>
24 #include <asm/machdep.h>
25 #include <asm/iommu.h>
26 #include <asm/ppc-pci.h>
31 #define DBG(x...) printk(x)
36 static struct pci_controller
*u3_agp
, *u3_ht
;
38 static int __init
fixup_one_level_bus_range(struct device_node
*node
, int higher
)
40 for (; node
!= 0;node
= node
->sibling
) {
42 const unsigned int *class_code
;
45 /* For PCI<->PCI bridges or CardBus bridges, we go down */
46 class_code
= get_property(node
, "class-code", NULL
);
47 if (!class_code
|| ((*class_code
>> 8) != PCI_CLASS_BRIDGE_PCI
&&
48 (*class_code
>> 8) != PCI_CLASS_BRIDGE_CARDBUS
))
50 bus_range
= get_property(node
, "bus-range", &len
);
51 if (bus_range
!= NULL
&& len
> 2 * sizeof(int)) {
52 if (bus_range
[1] > higher
)
53 higher
= bus_range
[1];
55 higher
= fixup_one_level_bus_range(node
->child
, higher
);
60 /* This routine fixes the "bus-range" property of all bridges in the
61 * system since they tend to have their "last" member wrong on macs
63 * Note that the bus numbers manipulated here are OF bus numbers, they
64 * are not Linux bus numbers.
66 static void __init
fixup_bus_range(struct device_node
*bridge
)
69 struct property
*prop
;
72 /* Lookup the "bus-range" property for the hose */
73 prop
= of_find_property(bridge
, "bus-range", &len
);
74 if (prop
== NULL
|| prop
->value
== NULL
|| len
< 2 * sizeof(int)) {
75 printk(KERN_WARNING
"Can't get bus-range for %s\n",
79 bus_range
= (int *)prop
->value
;
80 bus_range
[1] = fixup_one_level_bus_range(bridge
->child
, bus_range
[1]);
84 #define U3_AGP_CFA0(devfn, off) \
85 ((1 << (unsigned long)PCI_SLOT(dev_fn)) \
86 | (((unsigned long)PCI_FUNC(dev_fn)) << 8) \
87 | (((unsigned long)(off)) & 0xFCUL))
89 #define U3_AGP_CFA1(bus, devfn, off) \
90 ((((unsigned long)(bus)) << 16) \
91 |(((unsigned long)(devfn)) << 8) \
92 |(((unsigned long)(off)) & 0xFCUL) \
95 static unsigned long u3_agp_cfg_access(struct pci_controller
* hose
,
96 u8 bus
, u8 dev_fn
, u8 offset
)
100 if (bus
== hose
->first_busno
) {
101 if (dev_fn
< (11 << 3))
103 caddr
= U3_AGP_CFA0(dev_fn
, offset
);
105 caddr
= U3_AGP_CFA1(bus
, dev_fn
, offset
);
107 /* Uninorth will return garbage if we don't read back the value ! */
109 out_le32(hose
->cfg_addr
, caddr
);
110 } while (in_le32(hose
->cfg_addr
) != caddr
);
113 return ((unsigned long)hose
->cfg_data
) + offset
;
116 static int u3_agp_read_config(struct pci_bus
*bus
, unsigned int devfn
,
117 int offset
, int len
, u32
*val
)
119 struct pci_controller
*hose
;
122 hose
= pci_bus_to_host(bus
);
124 return PCIBIOS_DEVICE_NOT_FOUND
;
126 addr
= u3_agp_cfg_access(hose
, bus
->number
, devfn
, offset
);
128 return PCIBIOS_DEVICE_NOT_FOUND
;
130 * Note: the caller has already checked that offset is
131 * suitably aligned and that len is 1, 2 or 4.
135 *val
= in_8((u8
*)addr
);
138 *val
= in_le16((u16
*)addr
);
141 *val
= in_le32((u32
*)addr
);
144 return PCIBIOS_SUCCESSFUL
;
147 static int u3_agp_write_config(struct pci_bus
*bus
, unsigned int devfn
,
148 int offset
, int len
, u32 val
)
150 struct pci_controller
*hose
;
153 hose
= pci_bus_to_host(bus
);
155 return PCIBIOS_DEVICE_NOT_FOUND
;
157 addr
= u3_agp_cfg_access(hose
, bus
->number
, devfn
, offset
);
159 return PCIBIOS_DEVICE_NOT_FOUND
;
161 * Note: the caller has already checked that offset is
162 * suitably aligned and that len is 1, 2 or 4.
166 out_8((u8
*)addr
, val
);
167 (void) in_8((u8
*)addr
);
170 out_le16((u16
*)addr
, val
);
171 (void) in_le16((u16
*)addr
);
174 out_le32((u32
*)addr
, val
);
175 (void) in_le32((u32
*)addr
);
178 return PCIBIOS_SUCCESSFUL
;
181 static struct pci_ops u3_agp_pci_ops
=
188 #define U3_HT_CFA0(devfn, off) \
189 ((((unsigned long)devfn) << 8) | offset)
190 #define U3_HT_CFA1(bus, devfn, off) \
191 (U3_HT_CFA0(devfn, off) \
192 + (((unsigned long)bus) << 16) \
195 static unsigned long u3_ht_cfg_access(struct pci_controller
* hose
,
196 u8 bus
, u8 devfn
, u8 offset
)
198 if (bus
== hose
->first_busno
) {
199 if (PCI_SLOT(devfn
) == 0)
201 return ((unsigned long)hose
->cfg_data
) + U3_HT_CFA0(devfn
, offset
);
203 return ((unsigned long)hose
->cfg_data
) + U3_HT_CFA1(bus
, devfn
, offset
);
206 static int u3_ht_read_config(struct pci_bus
*bus
, unsigned int devfn
,
207 int offset
, int len
, u32
*val
)
209 struct pci_controller
*hose
;
212 hose
= pci_bus_to_host(bus
);
214 return PCIBIOS_DEVICE_NOT_FOUND
;
216 addr
= u3_ht_cfg_access(hose
, bus
->number
, devfn
, offset
);
218 return PCIBIOS_DEVICE_NOT_FOUND
;
221 * Note: the caller has already checked that offset is
222 * suitably aligned and that len is 1, 2 or 4.
226 *val
= in_8((u8
*)addr
);
229 *val
= in_le16((u16
*)addr
);
232 *val
= in_le32((u32
*)addr
);
235 return PCIBIOS_SUCCESSFUL
;
238 static int u3_ht_write_config(struct pci_bus
*bus
, unsigned int devfn
,
239 int offset
, int len
, u32 val
)
241 struct pci_controller
*hose
;
244 hose
= pci_bus_to_host(bus
);
246 return PCIBIOS_DEVICE_NOT_FOUND
;
248 addr
= u3_ht_cfg_access(hose
, bus
->number
, devfn
, offset
);
250 return PCIBIOS_DEVICE_NOT_FOUND
;
252 * Note: the caller has already checked that offset is
253 * suitably aligned and that len is 1, 2 or 4.
257 out_8((u8
*)addr
, val
);
258 (void) in_8((u8
*)addr
);
261 out_le16((u16
*)addr
, val
);
262 (void) in_le16((u16
*)addr
);
265 out_le32((u32
*)addr
, val
);
266 (void) in_le32((u32
*)addr
);
269 return PCIBIOS_SUCCESSFUL
;
272 static struct pci_ops u3_ht_pci_ops
=
278 static void __init
setup_u3_agp(struct pci_controller
* hose
)
280 /* On G5, we move AGP up to high bus number so we don't need
281 * to reassign bus numbers for HT. If we ever have P2P bridges
282 * on AGP, we'll have to move pci_assign_all_buses to the
283 * pci_controller structure so we enable it for AGP and not for
285 * We hard code the address because of the different size of
286 * the reg address cell, we shall fix that by killing struct
287 * reg_property and using some accessor functions instead
289 hose
->first_busno
= 0xf0;
290 hose
->last_busno
= 0xff;
291 hose
->ops
= &u3_agp_pci_ops
;
292 hose
->cfg_addr
= ioremap(0xf0000000 + 0x800000, 0x1000);
293 hose
->cfg_data
= ioremap(0xf0000000 + 0xc00000, 0x1000);
298 static void __init
setup_u3_ht(struct pci_controller
* hose
)
300 hose
->ops
= &u3_ht_pci_ops
;
302 /* We hard code the address because of the different size of
303 * the reg address cell, we shall fix that by killing struct
304 * reg_property and using some accessor functions instead
306 hose
->cfg_data
= (volatile unsigned char *)ioremap(0xf2000000, 0x02000000);
308 hose
->first_busno
= 0;
309 hose
->last_busno
= 0xef;
314 static int __init
add_bridge(struct device_node
*dev
)
317 struct pci_controller
*hose
;
319 const int *bus_range
;
322 DBG("Adding PCI host bridge %s\n", dev
->full_name
);
324 bus_range
= get_property(dev
, "bus-range", &len
);
325 if (bus_range
== NULL
|| len
< 2 * sizeof(int)) {
326 printk(KERN_WARNING
"Can't get bus-range for %s, assume bus 0\n",
330 hose
= pcibios_alloc_controller(dev
);
333 hose
->first_busno
= bus_range
? bus_range
[0] : 0;
334 hose
->last_busno
= bus_range
? bus_range
[1] : 0xff;
337 if (device_is_compatible(dev
, "u3-agp")) {
339 disp_name
= "U3-AGP";
341 } else if (device_is_compatible(dev
, "u3-ht")) {
346 printk(KERN_INFO
"Found %s PCI host bridge. Firmware bus number: %d->%d\n",
347 disp_name
, hose
->first_busno
, hose
->last_busno
);
349 /* Interpret the "ranges" property */
350 /* This also maps the I/O region and sets isa_io/mem_base */
351 pci_process_bridge_OF_ranges(hose
, dev
, primary
);
352 pci_setup_phb_io(hose
, primary
);
354 /* Fixup "bus-range" OF property */
355 fixup_bus_range(dev
);
361 void __init
maple_pcibios_fixup(void)
363 struct pci_dev
*dev
= NULL
;
365 DBG(" -> maple_pcibios_fixup\n");
367 for_each_pci_dev(dev
)
368 pci_read_irq_line(dev
);
370 DBG(" <- maple_pcibios_fixup\n");
373 static void __init
maple_fixup_phb_resources(void)
375 struct pci_controller
*hose
, *tmp
;
377 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
) {
378 unsigned long offset
= (unsigned long)hose
->io_base_virt
- pci_io_base
;
379 hose
->io_resource
.start
+= offset
;
380 hose
->io_resource
.end
+= offset
;
381 printk(KERN_INFO
"PCI Host %d, io start: %llx; io end: %llx\n",
383 (unsigned long long)hose
->io_resource
.start
,
384 (unsigned long long)hose
->io_resource
.end
);
388 void __init
maple_pci_init(void)
390 struct device_node
*np
, *root
;
391 struct device_node
*ht
= NULL
;
393 /* Probe root PCI hosts, that is on U3 the AGP host and the
394 * HyperTransport host. That one is actually "kept" around
395 * and actually added last as it's resource management relies
396 * on the AGP resources to have been setup first
398 root
= of_find_node_by_path("/");
400 printk(KERN_CRIT
"maple_find_bridges: can't find root of device tree\n");
403 for (np
= NULL
; (np
= of_get_next_child(root
, np
)) != NULL
;) {
404 if (np
->name
== NULL
)
406 if (strcmp(np
->name
, "pci") == 0) {
407 if (add_bridge(np
) == 0)
410 if (strcmp(np
->name
, "ht") == 0) {
417 /* Now setup the HyperTransport host if we found any
419 if (ht
&& add_bridge(ht
) != 0)
422 /* Fixup the IO resources on our host bridges as the common code
423 * does it only for childs of the host bridges
425 maple_fixup_phb_resources();
427 /* Setup the linkage between OF nodes and PHBs */
430 /* Fixup the PCI<->OF mapping for U3 AGP due to bus renumbering. We
431 * assume there is no P2P bridge on the AGP bus, which should be a
432 * safe assumptions hopefully.
435 struct device_node
*np
= u3_agp
->arch_data
;
436 PCI_DN(np
)->busno
= 0xf0;
437 for (np
= np
->child
; np
; np
= np
->sibling
)
438 PCI_DN(np
)->busno
= 0xf0;
441 /* Tell pci.c to not change any resource allocations. */
445 int maple_pci_get_legacy_ide_irq(struct pci_dev
*pdev
, int channel
)
447 struct device_node
*np
;
448 unsigned int defirq
= channel
? 15 : 14;
451 if (pdev
->vendor
!= PCI_VENDOR_ID_AMD
||
452 pdev
->device
!= PCI_DEVICE_ID_AMD_8111_IDE
)
455 np
= pci_device_to_OF_node(pdev
);
458 irq
= irq_of_parse_and_map(np
, channel
& 0x1);
460 printk("Failed to map onboard IDE interrupt for channel %d\n",
467 /* XXX: To remove once all firmwares are ok */
468 static void fixup_maple_ide(struct pci_dev
* dev
)
470 #if 0 /* Enable this to enable IDE port 0 */
474 pci_read_config_byte(dev
, 0x40, &v
);
476 pci_write_config_byte(dev
, 0x40, v
);
479 #if 0 /* fix bus master base */
480 pci_write_config_dword(dev
, 0x20, 0xcc01);
481 printk("old ide resource: %lx -> %lx \n",
482 dev
->resource
[4].start
, dev
->resource
[4].end
);
483 dev
->resource
[4].start
= 0xcc00;
484 dev
->resource
[4].end
= 0xcc10;
486 #if 1 /* Enable this to fixup IDE sense/polarity of irqs in IO-APICs */
488 struct pci_dev
*apicdev
;
491 apicdev
= pci_get_slot (dev
->bus
, PCI_DEVFN(5,0));
493 printk("IDE Fixup IRQ: Can't find IO-APIC !\n");
495 pci_write_config_byte(apicdev
, 0xf2, 0x10 + 2*14);
496 pci_read_config_dword(apicdev
, 0xf4, &v
);
498 pci_write_config_dword(apicdev
, 0xf4, v
);
499 pci_write_config_byte(apicdev
, 0xf2, 0x10 + 2*15);
500 pci_read_config_dword(apicdev
, 0xf4, &v
);
502 pci_write_config_dword(apicdev
, 0xf4, v
);
503 pci_dev_put(apicdev
);
508 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8111_IDE
,