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[SUNLANCE]: Mark sparc_lance_probe_one as __devinit.
[linux-2.6/verdex.git] / drivers / net / tg3.c
blobaaf45b907a786aaa9028e60fcf6d38668653ad6d
1 /*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005 Broadcom Corporation.
8 *
9 * Firmware is:
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
16 */
17
18
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/types.h>
23 #include <linux/compiler.h>
24 #include <linux/slab.h>
25 #include <linux/delay.h>
26 #include <linux/in.h>
27 #include <linux/init.h>
28 #include <linux/ioport.h>
29 #include <linux/pci.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/mii.h>
35 #include <linux/if_vlan.h>
36 #include <linux/ip.h>
37 #include <linux/tcp.h>
38 #include <linux/workqueue.h>
39 #include <linux/prefetch.h>
40 #include <linux/dma-mapping.h>
41
42 #include <net/checksum.h>
43
44 #include <asm/system.h>
45 #include <asm/io.h>
46 #include <asm/byteorder.h>
47 #include <asm/uaccess.h>
48
49 #ifdef CONFIG_SPARC64
50 #include <asm/idprom.h>
51 #include <asm/oplib.h>
52 #include <asm/pbm.h>
53 #endif
54
55 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
56 #define TG3_VLAN_TAG_USED 1
57 #else
58 #define TG3_VLAN_TAG_USED 0
59 #endif
60
61 #ifdef NETIF_F_TSO
62 #define TG3_TSO_SUPPORT 1
63 #else
64 #define TG3_TSO_SUPPORT 0
65 #endif
66
67 #include "tg3.h"
68
69 #define DRV_MODULE_NAME "tg3"
70 #define PFX DRV_MODULE_NAME ": "
71 #define DRV_MODULE_VERSION "3.65"
72 #define DRV_MODULE_RELDATE "August 07, 2006"
73
74 #define TG3_DEF_MAC_MODE 0
75 #define TG3_DEF_RX_MODE 0
76 #define TG3_DEF_TX_MODE 0
77 #define TG3_DEF_MSG_ENABLE \
78 (NETIF_MSG_DRV | \
79 NETIF_MSG_PROBE | \
80 NETIF_MSG_LINK | \
81 NETIF_MSG_TIMER | \
82 NETIF_MSG_IFDOWN | \
83 NETIF_MSG_IFUP | \
84 NETIF_MSG_RX_ERR | \
85 NETIF_MSG_TX_ERR)
86
87 /* length of time before we decide the hardware is borked,
88 * and dev->tx_timeout() should be called to fix the problem
89 */
90 #define TG3_TX_TIMEOUT (5 * HZ)
91
92 /* hardware minimum and maximum for a single frame's data payload */
93 #define TG3_MIN_MTU 60
94 #define TG3_MAX_MTU(tp) \
95 ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
96
97 /* These numbers seem to be hard coded in the NIC firmware somehow.
98 * You can't change the ring sizes, but you can change where you place
99 * them in the NIC onboard memory.
100 */
101 #define TG3_RX_RING_SIZE 512
102 #define TG3_DEF_RX_RING_PENDING 200
103 #define TG3_RX_JUMBO_RING_SIZE 256
104 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
105
106 /* Do not place this n-ring entries value into the tp struct itself,
107 * we really want to expose these constants to GCC so that modulo et
108 * al. operations are done with shifts and masks instead of with
109 * hw multiply/modulo instructions. Another solution would be to
110 * replace things like '% foo' with '& (foo - 1)'.
111 */
112 #define TG3_RX_RCB_RING_SIZE(tp) \
113 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
114
115 #define TG3_TX_RING_SIZE 512
116 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
117
118 #define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
119 TG3_RX_RING_SIZE)
120 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
121 TG3_RX_JUMBO_RING_SIZE)
122 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
123 TG3_RX_RCB_RING_SIZE(tp))
124 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
125 TG3_TX_RING_SIZE)
126 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
127
128 #define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64)
129 #define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64)
130
131 /* minimum number of free TX descriptors required to wake up TX process */
132 #define TG3_TX_WAKEUP_THRESH (TG3_TX_RING_SIZE / 4)
133
134 /* number of ETHTOOL_GSTATS u64's */
135 #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
136
137 #define TG3_NUM_TEST 6
138
139 static char version[] __devinitdata =
140 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
141
142 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
143 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
144 MODULE_LICENSE("GPL");
145 MODULE_VERSION(DRV_MODULE_VERSION);
146
147 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
148 module_param(tg3_debug, int, 0);
149 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
150
151 static struct pci_device_id tg3_pci_tbl[] = {
152 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
153 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
154 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
155 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
156 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
157 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
158 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
159 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
160 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
161 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
162 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
163 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
164 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
165 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
166 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
167 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
168 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
169 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
170 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
171 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
172 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
173 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
174 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
175 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
176 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
200 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
201 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
202 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
203 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
204 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
205 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
206 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
207 {}
208 };
209
210 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
211
212 static const struct {
213 const char string[ETH_GSTRING_LEN];
214 } ethtool_stats_keys[TG3_NUM_STATS] = {
215 { "rx_octets" },
216 { "rx_fragments" },
217 { "rx_ucast_packets" },
218 { "rx_mcast_packets" },
219 { "rx_bcast_packets" },
220 { "rx_fcs_errors" },
221 { "rx_align_errors" },
222 { "rx_xon_pause_rcvd" },
223 { "rx_xoff_pause_rcvd" },
224 { "rx_mac_ctrl_rcvd" },
225 { "rx_xoff_entered" },
226 { "rx_frame_too_long_errors" },
227 { "rx_jabbers" },
228 { "rx_undersize_packets" },
229 { "rx_in_length_errors" },
230 { "rx_out_length_errors" },
231 { "rx_64_or_less_octet_packets" },
232 { "rx_65_to_127_octet_packets" },
233 { "rx_128_to_255_octet_packets" },
234 { "rx_256_to_511_octet_packets" },
235 { "rx_512_to_1023_octet_packets" },
236 { "rx_1024_to_1522_octet_packets" },
237 { "rx_1523_to_2047_octet_packets" },
238 { "rx_2048_to_4095_octet_packets" },
239 { "rx_4096_to_8191_octet_packets" },
240 { "rx_8192_to_9022_octet_packets" },
241
242 { "tx_octets" },
243 { "tx_collisions" },
244
245 { "tx_xon_sent" },
246 { "tx_xoff_sent" },
247 { "tx_flow_control" },
248 { "tx_mac_errors" },
249 { "tx_single_collisions" },
250 { "tx_mult_collisions" },
251 { "tx_deferred" },
252 { "tx_excessive_collisions" },
253 { "tx_late_collisions" },
254 { "tx_collide_2times" },
255 { "tx_collide_3times" },
256 { "tx_collide_4times" },
257 { "tx_collide_5times" },
258 { "tx_collide_6times" },
259 { "tx_collide_7times" },
260 { "tx_collide_8times" },
261 { "tx_collide_9times" },
262 { "tx_collide_10times" },
263 { "tx_collide_11times" },
264 { "tx_collide_12times" },
265 { "tx_collide_13times" },
266 { "tx_collide_14times" },
267 { "tx_collide_15times" },
268 { "tx_ucast_packets" },
269 { "tx_mcast_packets" },
270 { "tx_bcast_packets" },
271 { "tx_carrier_sense_errors" },
272 { "tx_discards" },
273 { "tx_errors" },
274
275 { "dma_writeq_full" },
276 { "dma_write_prioq_full" },
277 { "rxbds_empty" },
278 { "rx_discards" },
279 { "rx_errors" },
280 { "rx_threshold_hit" },
281
282 { "dma_readq_full" },
283 { "dma_read_prioq_full" },
284 { "tx_comp_queue_full" },
285
286 { "ring_set_send_prod_index" },
287 { "ring_status_update" },
288 { "nic_irqs" },
289 { "nic_avoided_irqs" },
290 { "nic_tx_threshold_hit" }
291 };
292
293 static const struct {
294 const char string[ETH_GSTRING_LEN];
295 } ethtool_test_keys[TG3_NUM_TEST] = {
296 { "nvram test (online) " },
297 { "link test (online) " },
298 { "register test (offline)" },
299 { "memory test (offline)" },
300 { "loopback test (offline)" },
301 { "interrupt test (offline)" },
302 };
303
304 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
305 {
306 writel(val, tp->regs + off);
307 }
308
309 static u32 tg3_read32(struct tg3 *tp, u32 off)
310 {
311 return (readl(tp->regs + off));
312 }
313
314 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
315 {
316 unsigned long flags;
317
318 spin_lock_irqsave(&tp->indirect_lock, flags);
319 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
320 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
321 spin_unlock_irqrestore(&tp->indirect_lock, flags);
322 }
323
324 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
325 {
326 writel(val, tp->regs + off);
327 readl(tp->regs + off);
328 }
329
330 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
331 {
332 unsigned long flags;
333 u32 val;
334
335 spin_lock_irqsave(&tp->indirect_lock, flags);
336 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
337 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
338 spin_unlock_irqrestore(&tp->indirect_lock, flags);
339 return val;
340 }
341
342 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
343 {
344 unsigned long flags;
345
346 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
347 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
348 TG3_64BIT_REG_LOW, val);
349 return;
350 }
351 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
352 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
353 TG3_64BIT_REG_LOW, val);
354 return;
355 }
356
357 spin_lock_irqsave(&tp->indirect_lock, flags);
358 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
359 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
360 spin_unlock_irqrestore(&tp->indirect_lock, flags);
361
362 /* In indirect mode when disabling interrupts, we also need
363 * to clear the interrupt bit in the GRC local ctrl register.
364 */
365 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
366 (val == 0x1)) {
367 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
368 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
369 }
370 }
371
372 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
373 {
374 unsigned long flags;
375 u32 val;
376
377 spin_lock_irqsave(&tp->indirect_lock, flags);
378 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
379 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
380 spin_unlock_irqrestore(&tp->indirect_lock, flags);
381 return val;
382 }
383
384 /* usec_wait specifies the wait time in usec when writing to certain registers
385 * where it is unsafe to read back the register without some delay.
386 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
387 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
388 */
389 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
390 {
391 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
392 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
393 /* Non-posted methods */
394 tp->write32(tp, off, val);
395 else {
396 /* Posted method */
397 tg3_write32(tp, off, val);
398 if (usec_wait)
399 udelay(usec_wait);
400 tp->read32(tp, off);
401 }
402 /* Wait again after the read for the posted method to guarantee that
403 * the wait time is met.
404 */
405 if (usec_wait)
406 udelay(usec_wait);
407 }
408
409 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
410 {
411 tp->write32_mbox(tp, off, val);
412 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
413 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
414 tp->read32_mbox(tp, off);
415 }
416
417 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
418 {
419 void __iomem *mbox = tp->regs + off;
420 writel(val, mbox);
421 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
422 writel(val, mbox);
423 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
424 readl(mbox);
425 }
426
427 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
428 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
429 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
430 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
431 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
432
433 #define tw32(reg,val) tp->write32(tp, reg, val)
434 #define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
435 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
436 #define tr32(reg) tp->read32(tp, reg)
437
438 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
439 {
440 unsigned long flags;
441
442 spin_lock_irqsave(&tp->indirect_lock, flags);
443 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
444 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
445 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
446
447 /* Always leave this as zero. */
448 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
449 } else {
450 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
451 tw32_f(TG3PCI_MEM_WIN_DATA, val);
452
453 /* Always leave this as zero. */
454 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
455 }
456 spin_unlock_irqrestore(&tp->indirect_lock, flags);
457 }
458
459 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
460 {
461 unsigned long flags;
462
463 spin_lock_irqsave(&tp->indirect_lock, flags);
464 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
465 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
466 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
467
468 /* Always leave this as zero. */
469 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
470 } else {
471 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
472 *val = tr32(TG3PCI_MEM_WIN_DATA);
473
474 /* Always leave this as zero. */
475 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
476 }
477 spin_unlock_irqrestore(&tp->indirect_lock, flags);
478 }
479
480 static void tg3_disable_ints(struct tg3 *tp)
481 {
482 tw32(TG3PCI_MISC_HOST_CTRL,
483 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
484 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
485 }
486
487 static inline void tg3_cond_int(struct tg3 *tp)
488 {
489 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
490 (tp->hw_status->status & SD_STATUS_UPDATED))
491 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
492 }
493
494 static void tg3_enable_ints(struct tg3 *tp)
495 {
496 tp->irq_sync = 0;
497 wmb();
498
499 tw32(TG3PCI_MISC_HOST_CTRL,
500 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
501 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
502 (tp->last_tag << 24));
503 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
504 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
505 (tp->last_tag << 24));
506 tg3_cond_int(tp);
507 }
508
509 static inline unsigned int tg3_has_work(struct tg3 *tp)
510 {
511 struct tg3_hw_status *sblk = tp->hw_status;
512 unsigned int work_exists = 0;
513
514 /* check for phy events */
515 if (!(tp->tg3_flags &
516 (TG3_FLAG_USE_LINKCHG_REG |
517 TG3_FLAG_POLL_SERDES))) {
518 if (sblk->status & SD_STATUS_LINK_CHG)
519 work_exists = 1;
520 }
521 /* check for RX/TX work to do */
522 if (sblk->idx[0].tx_consumer != tp->tx_cons ||
523 sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
524 work_exists = 1;
525
526 return work_exists;
527 }
528
529 /* tg3_restart_ints
530 * similar to tg3_enable_ints, but it accurately determines whether there
531 * is new work pending and can return without flushing the PIO write
532 * which reenables interrupts
533 */
534 static void tg3_restart_ints(struct tg3 *tp)
535 {
536 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
537 tp->last_tag << 24);
538 mmiowb();
539
540 /* When doing tagged status, this work check is unnecessary.
541 * The last_tag we write above tells the chip which piece of
542 * work we've completed.
543 */
544 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
545 tg3_has_work(tp))
546 tw32(HOSTCC_MODE, tp->coalesce_mode |
547 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
548 }
549
550 static inline void tg3_netif_stop(struct tg3 *tp)
551 {
552 tp->dev->trans_start = jiffies; /* prevent tx timeout */
553 netif_poll_disable(tp->dev);
554 netif_tx_disable(tp->dev);
555 }
556
557 static inline void tg3_netif_start(struct tg3 *tp)
558 {
559 netif_wake_queue(tp->dev);
560 /* NOTE: unconditional netif_wake_queue is only appropriate
561 * so long as all callers are assured to have free tx slots
562 * (such as after tg3_init_hw)
563 */
564 netif_poll_enable(tp->dev);
565 tp->hw_status->status |= SD_STATUS_UPDATED;
566 tg3_enable_ints(tp);
567 }
568
569 static void tg3_switch_clocks(struct tg3 *tp)
570 {
571 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
572 u32 orig_clock_ctrl;
573
574 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
575 return;
576
577 orig_clock_ctrl = clock_ctrl;
578 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
579 CLOCK_CTRL_CLKRUN_OENABLE |
580 0x1f);
581 tp->pci_clock_ctrl = clock_ctrl;
582
583 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
584 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
585 tw32_wait_f(TG3PCI_CLOCK_CTRL,
586 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
587 }
588 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
589 tw32_wait_f(TG3PCI_CLOCK_CTRL,
590 clock_ctrl |
591 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
592 40);
593 tw32_wait_f(TG3PCI_CLOCK_CTRL,
594 clock_ctrl | (CLOCK_CTRL_ALTCLK),
595 40);
596 }
597 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
598 }
599
600 #define PHY_BUSY_LOOPS 5000
601
602 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
603 {
604 u32 frame_val;
605 unsigned int loops;
606 int ret;
607
608 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
609 tw32_f(MAC_MI_MODE,
610 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
611 udelay(80);
612 }
613
614 *val = 0x0;
615
616 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
617 MI_COM_PHY_ADDR_MASK);
618 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
619 MI_COM_REG_ADDR_MASK);
620 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
621
622 tw32_f(MAC_MI_COM, frame_val);
623
624 loops = PHY_BUSY_LOOPS;
625 while (loops != 0) {
626 udelay(10);
627 frame_val = tr32(MAC_MI_COM);
628
629 if ((frame_val & MI_COM_BUSY) == 0) {
630 udelay(5);
631 frame_val = tr32(MAC_MI_COM);
632 break;
633 }
634 loops -= 1;
635 }
636
637 ret = -EBUSY;
638 if (loops != 0) {
639 *val = frame_val & MI_COM_DATA_MASK;
640 ret = 0;
641 }
642
643 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
644 tw32_f(MAC_MI_MODE, tp->mi_mode);
645 udelay(80);
646 }
647
648 return ret;
649 }
650
651 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
652 {
653 u32 frame_val;
654 unsigned int loops;
655 int ret;
656
657 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
658 tw32_f(MAC_MI_MODE,
659 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
660 udelay(80);
661 }
662
663 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
664 MI_COM_PHY_ADDR_MASK);
665 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
666 MI_COM_REG_ADDR_MASK);
667 frame_val |= (val & MI_COM_DATA_MASK);
668 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
669
670 tw32_f(MAC_MI_COM, frame_val);
671
672 loops = PHY_BUSY_LOOPS;
673 while (loops != 0) {
674 udelay(10);
675 frame_val = tr32(MAC_MI_COM);
676 if ((frame_val & MI_COM_BUSY) == 0) {
677 udelay(5);
678 frame_val = tr32(MAC_MI_COM);
679 break;
680 }
681 loops -= 1;
682 }
683
684 ret = -EBUSY;
685 if (loops != 0)
686 ret = 0;
687
688 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
689 tw32_f(MAC_MI_MODE, tp->mi_mode);
690 udelay(80);
691 }
692
693 return ret;
694 }
695
696 static void tg3_phy_set_wirespeed(struct tg3 *tp)
697 {
698 u32 val;
699
700 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
701 return;
702
703 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
704 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
705 tg3_writephy(tp, MII_TG3_AUX_CTRL,
706 (val | (1 << 15) | (1 << 4)));
707 }
708
709 static int tg3_bmcr_reset(struct tg3 *tp)
710 {
711 u32 phy_control;
712 int limit, err;
713
714 /* OK, reset it, and poll the BMCR_RESET bit until it
715 * clears or we time out.
716 */
717 phy_control = BMCR_RESET;
718 err = tg3_writephy(tp, MII_BMCR, phy_control);
719 if (err != 0)
720 return -EBUSY;
721
722 limit = 5000;
723 while (limit--) {
724 err = tg3_readphy(tp, MII_BMCR, &phy_control);
725 if (err != 0)
726 return -EBUSY;
727
728 if ((phy_control & BMCR_RESET) == 0) {
729 udelay(40);
730 break;
731 }
732 udelay(10);
733 }
734 if (limit <= 0)
735 return -EBUSY;
736
737 return 0;
738 }
739
740 static int tg3_wait_macro_done(struct tg3 *tp)
741 {
742 int limit = 100;
743
744 while (limit--) {
745 u32 tmp32;
746
747 if (!tg3_readphy(tp, 0x16, &tmp32)) {
748 if ((tmp32 & 0x1000) == 0)
749 break;
750 }
751 }
752 if (limit <= 0)
753 return -EBUSY;
754
755 return 0;
756 }
757
758 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
759 {
760 static const u32 test_pat[4][6] = {
761 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
762 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
763 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
764 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
765 };
766 int chan;
767
768 for (chan = 0; chan < 4; chan++) {
769 int i;
770
771 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
772 (chan * 0x2000) | 0x0200);
773 tg3_writephy(tp, 0x16, 0x0002);
774
775 for (i = 0; i < 6; i++)
776 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
777 test_pat[chan][i]);
778
779 tg3_writephy(tp, 0x16, 0x0202);
780 if (tg3_wait_macro_done(tp)) {
781 *resetp = 1;
782 return -EBUSY;
783 }
784
785 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
786 (chan * 0x2000) | 0x0200);
787 tg3_writephy(tp, 0x16, 0x0082);
788 if (tg3_wait_macro_done(tp)) {
789 *resetp = 1;
790 return -EBUSY;
791 }
792
793 tg3_writephy(tp, 0x16, 0x0802);
794 if (tg3_wait_macro_done(tp)) {
795 *resetp = 1;
796 return -EBUSY;
797 }
798
799 for (i = 0; i < 6; i += 2) {
800 u32 low, high;
801
802 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
803 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
804 tg3_wait_macro_done(tp)) {
805 *resetp = 1;
806 return -EBUSY;
807 }
808 low &= 0x7fff;
809 high &= 0x000f;
810 if (low != test_pat[chan][i] ||
811 high != test_pat[chan][i+1]) {
812 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
813 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
814 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
815
816 return -EBUSY;
817 }
818 }
819 }
820
821 return 0;
822 }
823
824 static int tg3_phy_reset_chanpat(struct tg3 *tp)
825 {
826 int chan;
827
828 for (chan = 0; chan < 4; chan++) {
829 int i;
830
831 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
832 (chan * 0x2000) | 0x0200);
833 tg3_writephy(tp, 0x16, 0x0002);
834 for (i = 0; i < 6; i++)
835 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
836 tg3_writephy(tp, 0x16, 0x0202);
837 if (tg3_wait_macro_done(tp))
838 return -EBUSY;
839 }
840
841 return 0;
842 }
843
844 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
845 {
846 u32 reg32, phy9_orig;
847 int retries, do_phy_reset, err;
848
849 retries = 10;
850 do_phy_reset = 1;
851 do {
852 if (do_phy_reset) {
853 err = tg3_bmcr_reset(tp);
854 if (err)
855 return err;
856 do_phy_reset = 0;
857 }
858
859 /* Disable transmitter and interrupt. */
860 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
861 continue;
862
863 reg32 |= 0x3000;
864 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
865
866 /* Set full-duplex, 1000 mbps. */
867 tg3_writephy(tp, MII_BMCR,
868 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
869
870 /* Set to master mode. */
871 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
872 continue;
873
874 tg3_writephy(tp, MII_TG3_CTRL,
875 (MII_TG3_CTRL_AS_MASTER |
876 MII_TG3_CTRL_ENABLE_AS_MASTER));
877
878 /* Enable SM_DSP_CLOCK and 6dB. */
879 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
880
881 /* Block the PHY control access. */
882 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
883 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
884
885 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
886 if (!err)
887 break;
888 } while (--retries);
889
890 err = tg3_phy_reset_chanpat(tp);
891 if (err)
892 return err;
893
894 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
895 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
896
897 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
898 tg3_writephy(tp, 0x16, 0x0000);
899
900 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
901 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
902 /* Set Extended packet length bit for jumbo frames */
903 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
904 }
905 else {
906 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
907 }
908
909 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
910
911 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
912 reg32 &= ~0x3000;
913 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
914 } else if (!err)
915 err = -EBUSY;
916
917 return err;
918 }
919
920 static void tg3_link_report(struct tg3 *);
921
922 /* This will reset the tigon3 PHY if there is no valid
923 * link unless the FORCE argument is non-zero.
924 */
925 static int tg3_phy_reset(struct tg3 *tp)
926 {
927 u32 phy_status;
928 int err;
929
930 err = tg3_readphy(tp, MII_BMSR, &phy_status);
931 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
932 if (err != 0)
933 return -EBUSY;
934
935 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
936 netif_carrier_off(tp->dev);
937 tg3_link_report(tp);
938 }
939
940 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
941 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
942 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
943 err = tg3_phy_reset_5703_4_5(tp);
944 if (err)
945 return err;
946 goto out;
947 }
948
949 err = tg3_bmcr_reset(tp);
950 if (err)
951 return err;
952
953 out:
954 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
955 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
956 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
957 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
958 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
959 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
960 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
961 }
962 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
963 tg3_writephy(tp, 0x1c, 0x8d68);
964 tg3_writephy(tp, 0x1c, 0x8d68);
965 }
966 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
967 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
968 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
969 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
970 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
971 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
972 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
973 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
974 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
975 }
976 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
977 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
978 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
979 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
980 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
981 }
982 /* Set Extended packet length bit (bit 14) on all chips that */
983 /* support jumbo frames */
984 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
985 /* Cannot do read-modify-write on 5401 */
986 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
987 } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
988 u32 phy_reg;
989
990 /* Set bit 14 with read-modify-write to preserve other bits */
991 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
992 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
993 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
994 }
995
996 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
997 * jumbo frames transmission.
998 */
999 if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1000 u32 phy_reg;
1001
1002 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1003 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1004 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1005 }
1006
1007 tg3_phy_set_wirespeed(tp);
1008 return 0;
1009 }
1010
1011 static void tg3_frob_aux_power(struct tg3 *tp)
1012 {
1013 struct tg3 *tp_peer = tp;
1014
1015 if ((tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) != 0)
1016 return;
1017
1018 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1019 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1020 struct net_device *dev_peer;
1021
1022 dev_peer = pci_get_drvdata(tp->pdev_peer);
1023 /* remove_one() may have been run on the peer. */
1024 if (!dev_peer)
1025 tp_peer = tp;
1026 else
1027 tp_peer = netdev_priv(dev_peer);
1028 }
1029
1030 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1031 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1032 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1033 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1034 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1035 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1036 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1037 (GRC_LCLCTRL_GPIO_OE0 |
1038 GRC_LCLCTRL_GPIO_OE1 |
1039 GRC_LCLCTRL_GPIO_OE2 |
1040 GRC_LCLCTRL_GPIO_OUTPUT0 |
1041 GRC_LCLCTRL_GPIO_OUTPUT1),
1042 100);
1043 } else {
1044 u32 no_gpio2;
1045 u32 grc_local_ctrl = 0;
1046
1047 if (tp_peer != tp &&
1048 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1049 return;
1050
1051 /* Workaround to prevent overdrawing Amps. */
1052 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1053 ASIC_REV_5714) {
1054 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1055 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1056 grc_local_ctrl, 100);
1057 }
1058
1059 /* On 5753 and variants, GPIO2 cannot be used. */
1060 no_gpio2 = tp->nic_sram_data_cfg &
1061 NIC_SRAM_DATA_CFG_NO_GPIO2;
1062
1063 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1064 GRC_LCLCTRL_GPIO_OE1 |
1065 GRC_LCLCTRL_GPIO_OE2 |
1066 GRC_LCLCTRL_GPIO_OUTPUT1 |
1067 GRC_LCLCTRL_GPIO_OUTPUT2;
1068 if (no_gpio2) {
1069 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1070 GRC_LCLCTRL_GPIO_OUTPUT2);
1071 }
1072 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1073 grc_local_ctrl, 100);
1074
1075 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1076
1077 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1078 grc_local_ctrl, 100);
1079
1080 if (!no_gpio2) {
1081 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
1082 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1083 grc_local_ctrl, 100);
1084 }
1085 }
1086 } else {
1087 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1088 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1089 if (tp_peer != tp &&
1090 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1091 return;
1092
1093 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1094 (GRC_LCLCTRL_GPIO_OE1 |
1095 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1096
1097 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1098 GRC_LCLCTRL_GPIO_OE1, 100);
1099
1100 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1101 (GRC_LCLCTRL_GPIO_OE1 |
1102 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1103 }
1104 }
1105 }
1106
1107 static int tg3_setup_phy(struct tg3 *, int);
1108
1109 #define RESET_KIND_SHUTDOWN 0
1110 #define RESET_KIND_INIT 1
1111 #define RESET_KIND_SUSPEND 2
1112
1113 static void tg3_write_sig_post_reset(struct tg3 *, int);
1114 static int tg3_halt_cpu(struct tg3 *, u32);
1115 static int tg3_nvram_lock(struct tg3 *);
1116 static void tg3_nvram_unlock(struct tg3 *);
1117
1118 static void tg3_power_down_phy(struct tg3 *tp)
1119 {
1120 /* The PHY should not be powered down on some chips because
1121 * of bugs.
1122 */
1123 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1124 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1125 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
1126 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1127 return;
1128 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1129 }
1130
1131 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1132 {
1133 u32 misc_host_ctrl;
1134 u16 power_control, power_caps;
1135 int pm = tp->pm_cap;
1136
1137 /* Make sure register accesses (indirect or otherwise)
1138 * will function correctly.
1139 */
1140 pci_write_config_dword(tp->pdev,
1141 TG3PCI_MISC_HOST_CTRL,
1142 tp->misc_host_ctrl);
1143
1144 pci_read_config_word(tp->pdev,
1145 pm + PCI_PM_CTRL,
1146 &power_control);
1147 power_control |= PCI_PM_CTRL_PME_STATUS;
1148 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1149 switch (state) {
1150 case PCI_D0:
1151 power_control |= 0;
1152 pci_write_config_word(tp->pdev,
1153 pm + PCI_PM_CTRL,
1154 power_control);
1155 udelay(100); /* Delay after power state change */
1156
1157 /* Switch out of Vaux if it is not a LOM */
1158 if (!(tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
1159 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1160
1161 return 0;
1162
1163 case PCI_D1:
1164 power_control |= 1;
1165 break;
1166
1167 case PCI_D2:
1168 power_control |= 2;
1169 break;
1170
1171 case PCI_D3hot:
1172 power_control |= 3;
1173 break;
1174
1175 default:
1176 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1177 "requested.\n",
1178 tp->dev->name, state);
1179 return -EINVAL;
1180 };
1181
1182 power_control |= PCI_PM_CTRL_PME_ENABLE;
1183
1184 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1185 tw32(TG3PCI_MISC_HOST_CTRL,
1186 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1187
1188 if (tp->link_config.phy_is_low_power == 0) {
1189 tp->link_config.phy_is_low_power = 1;
1190 tp->link_config.orig_speed = tp->link_config.speed;
1191 tp->link_config.orig_duplex = tp->link_config.duplex;
1192 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1193 }
1194
1195 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1196 tp->link_config.speed = SPEED_10;
1197 tp->link_config.duplex = DUPLEX_HALF;
1198 tp->link_config.autoneg = AUTONEG_ENABLE;
1199 tg3_setup_phy(tp, 0);
1200 }
1201
1202 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1203 int i;
1204 u32 val;
1205
1206 for (i = 0; i < 200; i++) {
1207 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
1208 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1209 break;
1210 msleep(1);
1211 }
1212 }
1213 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
1214 WOL_DRV_STATE_SHUTDOWN |
1215 WOL_DRV_WOL | WOL_SET_MAGIC_PKT);
1216
1217 pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1218
1219 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1220 u32 mac_mode;
1221
1222 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1223 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1224 udelay(40);
1225
1226 mac_mode = MAC_MODE_PORT_MODE_MII;
1227
1228 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 ||
1229 !(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB))
1230 mac_mode |= MAC_MODE_LINK_POLARITY;
1231 } else {
1232 mac_mode = MAC_MODE_PORT_MODE_TBI;
1233 }
1234
1235 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1236 tw32(MAC_LED_CTRL, tp->led_ctrl);
1237
1238 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1239 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1240 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1241
1242 tw32_f(MAC_MODE, mac_mode);
1243 udelay(100);
1244
1245 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1246 udelay(10);
1247 }
1248
1249 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1250 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1251 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1252 u32 base_val;
1253
1254 base_val = tp->pci_clock_ctrl;
1255 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1256 CLOCK_CTRL_TXCLK_DISABLE);
1257
1258 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
1259 CLOCK_CTRL_PWRDOWN_PLL133, 40);
1260 } else if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
1261 /* do nothing */
1262 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1263 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1264 u32 newbits1, newbits2;
1265
1266 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1267 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1268 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1269 CLOCK_CTRL_TXCLK_DISABLE |
1270 CLOCK_CTRL_ALTCLK);
1271 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1272 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1273 newbits1 = CLOCK_CTRL_625_CORE;
1274 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1275 } else {
1276 newbits1 = CLOCK_CTRL_ALTCLK;
1277 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1278 }
1279
1280 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
1281 40);
1282
1283 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
1284 40);
1285
1286 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1287 u32 newbits3;
1288
1289 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1290 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1291 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1292 CLOCK_CTRL_TXCLK_DISABLE |
1293 CLOCK_CTRL_44MHZ_CORE);
1294 } else {
1295 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1296 }
1297
1298 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1299 tp->pci_clock_ctrl | newbits3, 40);
1300 }
1301 }
1302
1303 if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
1304 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1305 /* Turn off the PHY */
1306 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1307 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1308 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1309 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1310 tg3_power_down_phy(tp);
1311 }
1312 }
1313
1314 tg3_frob_aux_power(tp);
1315
1316 /* Workaround for unstable PLL clock */
1317 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1318 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1319 u32 val = tr32(0x7d00);
1320
1321 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1322 tw32(0x7d00, val);
1323 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1324 int err;
1325
1326 err = tg3_nvram_lock(tp);
1327 tg3_halt_cpu(tp, RX_CPU_BASE);
1328 if (!err)
1329 tg3_nvram_unlock(tp);
1330 }
1331 }
1332
1333 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1334
1335 /* Finally, set the new power state. */
1336 pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
1337 udelay(100); /* Delay after power state change */
1338
1339 return 0;
1340 }
1341
1342 static void tg3_link_report(struct tg3 *tp)
1343 {
1344 if (!netif_carrier_ok(tp->dev)) {
1345 printk(KERN_INFO PFX "%s: Link is down.\n", tp->dev->name);
1346 } else {
1347 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1348 tp->dev->name,
1349 (tp->link_config.active_speed == SPEED_1000 ?
1350 1000 :
1351 (tp->link_config.active_speed == SPEED_100 ?
1352 100 : 10)),
1353 (tp->link_config.active_duplex == DUPLEX_FULL ?
1354 "full" : "half"));
1355
1356 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
1357 "%s for RX.\n",
1358 tp->dev->name,
1359 (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
1360 (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
1361 }
1362 }
1363
1364 static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1365 {
1366 u32 new_tg3_flags = 0;
1367 u32 old_rx_mode = tp->rx_mode;
1368 u32 old_tx_mode = tp->tx_mode;
1369
1370 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
1371
1372 /* Convert 1000BaseX flow control bits to 1000BaseT
1373 * bits before resolving flow control.
1374 */
1375 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
1376 local_adv &= ~(ADVERTISE_PAUSE_CAP |
1377 ADVERTISE_PAUSE_ASYM);
1378 remote_adv &= ~(LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1379
1380 if (local_adv & ADVERTISE_1000XPAUSE)
1381 local_adv |= ADVERTISE_PAUSE_CAP;
1382 if (local_adv & ADVERTISE_1000XPSE_ASYM)
1383 local_adv |= ADVERTISE_PAUSE_ASYM;
1384 if (remote_adv & LPA_1000XPAUSE)
1385 remote_adv |= LPA_PAUSE_CAP;
1386 if (remote_adv & LPA_1000XPAUSE_ASYM)
1387 remote_adv |= LPA_PAUSE_ASYM;
1388 }
1389
1390 if (local_adv & ADVERTISE_PAUSE_CAP) {
1391 if (local_adv & ADVERTISE_PAUSE_ASYM) {
1392 if (remote_adv & LPA_PAUSE_CAP)
1393 new_tg3_flags |=
1394 (TG3_FLAG_RX_PAUSE |
1395 TG3_FLAG_TX_PAUSE);
1396 else if (remote_adv & LPA_PAUSE_ASYM)
1397 new_tg3_flags |=
1398 (TG3_FLAG_RX_PAUSE);
1399 } else {
1400 if (remote_adv & LPA_PAUSE_CAP)
1401 new_tg3_flags |=
1402 (TG3_FLAG_RX_PAUSE |
1403 TG3_FLAG_TX_PAUSE);
1404 }
1405 } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1406 if ((remote_adv & LPA_PAUSE_CAP) &&
1407 (remote_adv & LPA_PAUSE_ASYM))
1408 new_tg3_flags |= TG3_FLAG_TX_PAUSE;
1409 }
1410
1411 tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
1412 tp->tg3_flags |= new_tg3_flags;
1413 } else {
1414 new_tg3_flags = tp->tg3_flags;
1415 }
1416
1417 if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
1418 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1419 else
1420 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1421
1422 if (old_rx_mode != tp->rx_mode) {
1423 tw32_f(MAC_RX_MODE, tp->rx_mode);
1424 }
1425
1426 if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
1427 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1428 else
1429 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1430
1431 if (old_tx_mode != tp->tx_mode) {
1432 tw32_f(MAC_TX_MODE, tp->tx_mode);
1433 }
1434 }
1435
1436 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1437 {
1438 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1439 case MII_TG3_AUX_STAT_10HALF:
1440 *speed = SPEED_10;
1441 *duplex = DUPLEX_HALF;
1442 break;
1443
1444 case MII_TG3_AUX_STAT_10FULL:
1445 *speed = SPEED_10;
1446 *duplex = DUPLEX_FULL;
1447 break;
1448
1449 case MII_TG3_AUX_STAT_100HALF:
1450 *speed = SPEED_100;
1451 *duplex = DUPLEX_HALF;
1452 break;
1453
1454 case MII_TG3_AUX_STAT_100FULL:
1455 *speed = SPEED_100;
1456 *duplex = DUPLEX_FULL;
1457 break;
1458
1459 case MII_TG3_AUX_STAT_1000HALF:
1460 *speed = SPEED_1000;
1461 *duplex = DUPLEX_HALF;
1462 break;
1463
1464 case MII_TG3_AUX_STAT_1000FULL:
1465 *speed = SPEED_1000;
1466 *duplex = DUPLEX_FULL;
1467 break;
1468
1469 default:
1470 *speed = SPEED_INVALID;
1471 *duplex = DUPLEX_INVALID;
1472 break;
1473 };
1474 }
1475
1476 static void tg3_phy_copper_begin(struct tg3 *tp)
1477 {
1478 u32 new_adv;
1479 int i;
1480
1481 if (tp->link_config.phy_is_low_power) {
1482 /* Entering low power mode. Disable gigabit and
1483 * 100baseT advertisements.
1484 */
1485 tg3_writephy(tp, MII_TG3_CTRL, 0);
1486
1487 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1488 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1489 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1490 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1491
1492 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1493 } else if (tp->link_config.speed == SPEED_INVALID) {
1494 tp->link_config.advertising =
1495 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
1496 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
1497 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
1498 ADVERTISED_Autoneg | ADVERTISED_MII);
1499
1500 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1501 tp->link_config.advertising &=
1502 ~(ADVERTISED_1000baseT_Half |
1503 ADVERTISED_1000baseT_Full);
1504
1505 new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1506 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1507 new_adv |= ADVERTISE_10HALF;
1508 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1509 new_adv |= ADVERTISE_10FULL;
1510 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1511 new_adv |= ADVERTISE_100HALF;
1512 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1513 new_adv |= ADVERTISE_100FULL;
1514 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1515
1516 if (tp->link_config.advertising &
1517 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1518 new_adv = 0;
1519 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1520 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1521 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1522 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1523 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1524 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1525 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1526 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1527 MII_TG3_CTRL_ENABLE_AS_MASTER);
1528 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1529 } else {
1530 tg3_writephy(tp, MII_TG3_CTRL, 0);
1531 }
1532 } else {
1533 /* Asking for a specific link mode. */
1534 if (tp->link_config.speed == SPEED_1000) {
1535 new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1536 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1537
1538 if (tp->link_config.duplex == DUPLEX_FULL)
1539 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1540 else
1541 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1542 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1543 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1544 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1545 MII_TG3_CTRL_ENABLE_AS_MASTER);
1546 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1547 } else {
1548 tg3_writephy(tp, MII_TG3_CTRL, 0);
1549
1550 new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1551 if (tp->link_config.speed == SPEED_100) {
1552 if (tp->link_config.duplex == DUPLEX_FULL)
1553 new_adv |= ADVERTISE_100FULL;
1554 else
1555 new_adv |= ADVERTISE_100HALF;
1556 } else {
1557 if (tp->link_config.duplex == DUPLEX_FULL)
1558 new_adv |= ADVERTISE_10FULL;
1559 else
1560 new_adv |= ADVERTISE_10HALF;
1561 }
1562 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1563 }
1564 }
1565
1566 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1567 tp->link_config.speed != SPEED_INVALID) {
1568 u32 bmcr, orig_bmcr;
1569
1570 tp->link_config.active_speed = tp->link_config.speed;
1571 tp->link_config.active_duplex = tp->link_config.duplex;
1572
1573 bmcr = 0;
1574 switch (tp->link_config.speed) {
1575 default:
1576 case SPEED_10:
1577 break;
1578
1579 case SPEED_100:
1580 bmcr |= BMCR_SPEED100;
1581 break;
1582
1583 case SPEED_1000:
1584 bmcr |= TG3_BMCR_SPEED1000;
1585 break;
1586 };
1587
1588 if (tp->link_config.duplex == DUPLEX_FULL)
1589 bmcr |= BMCR_FULLDPLX;
1590
1591 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
1592 (bmcr != orig_bmcr)) {
1593 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1594 for (i = 0; i < 1500; i++) {
1595 u32 tmp;
1596
1597 udelay(10);
1598 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
1599 tg3_readphy(tp, MII_BMSR, &tmp))
1600 continue;
1601 if (!(tmp & BMSR_LSTATUS)) {
1602 udelay(40);
1603 break;
1604 }
1605 }
1606 tg3_writephy(tp, MII_BMCR, bmcr);
1607 udelay(40);
1608 }
1609 } else {
1610 tg3_writephy(tp, MII_BMCR,
1611 BMCR_ANENABLE | BMCR_ANRESTART);
1612 }
1613 }
1614
1615 static int tg3_init_5401phy_dsp(struct tg3 *tp)
1616 {
1617 int err;
1618
1619 /* Turn off tap power management. */
1620 /* Set Extended packet length bit */
1621 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1622
1623 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1624 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1625
1626 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1627 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1628
1629 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1630 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
1631
1632 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1633 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
1634
1635 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1636 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
1637
1638 udelay(40);
1639
1640 return err;
1641 }
1642
1643 static int tg3_copper_is_advertising_all(struct tg3 *tp)
1644 {
1645 u32 adv_reg, all_mask;
1646
1647 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
1648 return 0;
1649
1650 all_mask = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1651 ADVERTISE_100HALF | ADVERTISE_100FULL);
1652 if ((adv_reg & all_mask) != all_mask)
1653 return 0;
1654 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1655 u32 tg3_ctrl;
1656
1657 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
1658 return 0;
1659
1660 all_mask = (MII_TG3_CTRL_ADV_1000_HALF |
1661 MII_TG3_CTRL_ADV_1000_FULL);
1662 if ((tg3_ctrl & all_mask) != all_mask)
1663 return 0;
1664 }
1665 return 1;
1666 }
1667
1668 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1669 {
1670 int current_link_up;
1671 u32 bmsr, dummy;
1672 u16 current_speed;
1673 u8 current_duplex;
1674 int i, err;
1675
1676 tw32(MAC_EVENT, 0);
1677
1678 tw32_f(MAC_STATUS,
1679 (MAC_STATUS_SYNC_CHANGED |
1680 MAC_STATUS_CFG_CHANGED |
1681 MAC_STATUS_MI_COMPLETION |
1682 MAC_STATUS_LNKSTATE_CHANGED));
1683 udelay(40);
1684
1685 tp->mi_mode = MAC_MI_MODE_BASE;
1686 tw32_f(MAC_MI_MODE, tp->mi_mode);
1687 udelay(80);
1688
1689 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
1690
1691 /* Some third-party PHYs need to be reset on link going
1692 * down.
1693 */
1694 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1695 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1696 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
1697 netif_carrier_ok(tp->dev)) {
1698 tg3_readphy(tp, MII_BMSR, &bmsr);
1699 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1700 !(bmsr & BMSR_LSTATUS))
1701 force_reset = 1;
1702 }
1703 if (force_reset)
1704 tg3_phy_reset(tp);
1705
1706 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1707 tg3_readphy(tp, MII_BMSR, &bmsr);
1708 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
1709 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
1710 bmsr = 0;
1711
1712 if (!(bmsr & BMSR_LSTATUS)) {
1713 err = tg3_init_5401phy_dsp(tp);
1714 if (err)
1715 return err;
1716
1717 tg3_readphy(tp, MII_BMSR, &bmsr);
1718 for (i = 0; i < 1000; i++) {
1719 udelay(10);
1720 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1721 (bmsr & BMSR_LSTATUS)) {
1722 udelay(40);
1723 break;
1724 }
1725 }
1726
1727 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
1728 !(bmsr & BMSR_LSTATUS) &&
1729 tp->link_config.active_speed == SPEED_1000) {
1730 err = tg3_phy_reset(tp);
1731 if (!err)
1732 err = tg3_init_5401phy_dsp(tp);
1733 if (err)
1734 return err;
1735 }
1736 }
1737 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1738 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
1739 /* 5701 {A0,B0} CRC bug workaround */
1740 tg3_writephy(tp, 0x15, 0x0a75);
1741 tg3_writephy(tp, 0x1c, 0x8c68);
1742 tg3_writephy(tp, 0x1c, 0x8d68);
1743 tg3_writephy(tp, 0x1c, 0x8c68);
1744 }
1745
1746 /* Clear pending interrupts... */
1747 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1748 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1749
1750 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
1751 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
1752 else
1753 tg3_writephy(tp, MII_TG3_IMASK, ~0);
1754
1755 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1756 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1757 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
1758 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1759 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
1760 else
1761 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
1762 }
1763
1764 current_link_up = 0;
1765 current_speed = SPEED_INVALID;
1766 current_duplex = DUPLEX_INVALID;
1767
1768 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
1769 u32 val;
1770
1771 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
1772 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
1773 if (!(val & (1 << 10))) {
1774 val |= (1 << 10);
1775 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1776 goto relink;
1777 }
1778 }
1779
1780 bmsr = 0;
1781 for (i = 0; i < 100; i++) {
1782 tg3_readphy(tp, MII_BMSR, &bmsr);
1783 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1784 (bmsr & BMSR_LSTATUS))
1785 break;
1786 udelay(40);
1787 }
1788
1789 if (bmsr & BMSR_LSTATUS) {
1790 u32 aux_stat, bmcr;
1791
1792 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
1793 for (i = 0; i < 2000; i++) {
1794 udelay(10);
1795 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
1796 aux_stat)
1797 break;
1798 }
1799
1800 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
1801 &current_speed,
1802 &current_duplex);
1803
1804 bmcr = 0;
1805 for (i = 0; i < 200; i++) {
1806 tg3_readphy(tp, MII_BMCR, &bmcr);
1807 if (tg3_readphy(tp, MII_BMCR, &bmcr))
1808 continue;
1809 if (bmcr && bmcr != 0x7fff)
1810 break;
1811 udelay(10);
1812 }
1813
1814 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
1815 if (bmcr & BMCR_ANENABLE) {
1816 current_link_up = 1;
1817
1818 /* Force autoneg restart if we are exiting
1819 * low power mode.
1820 */
1821 if (!tg3_copper_is_advertising_all(tp))
1822 current_link_up = 0;
1823 } else {
1824 current_link_up = 0;
1825 }
1826 } else {
1827 if (!(bmcr & BMCR_ANENABLE) &&
1828 tp->link_config.speed == current_speed &&
1829 tp->link_config.duplex == current_duplex) {
1830 current_link_up = 1;
1831 } else {
1832 current_link_up = 0;
1833 }
1834 }
1835
1836 tp->link_config.active_speed = current_speed;
1837 tp->link_config.active_duplex = current_duplex;
1838 }
1839
1840 if (current_link_up == 1 &&
1841 (tp->link_config.active_duplex == DUPLEX_FULL) &&
1842 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
1843 u32 local_adv, remote_adv;
1844
1845 if (tg3_readphy(tp, MII_ADVERTISE, &local_adv))
1846 local_adv = 0;
1847 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1848
1849 if (tg3_readphy(tp, MII_LPA, &remote_adv))
1850 remote_adv = 0;
1851
1852 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1853
1854 /* If we are not advertising full pause capability,
1855 * something is wrong. Bring the link down and reconfigure.
1856 */
1857 if (local_adv != ADVERTISE_PAUSE_CAP) {
1858 current_link_up = 0;
1859 } else {
1860 tg3_setup_flow_control(tp, local_adv, remote_adv);
1861 }
1862 }
1863 relink:
1864 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1865 u32 tmp;
1866
1867 tg3_phy_copper_begin(tp);
1868
1869 tg3_readphy(tp, MII_BMSR, &tmp);
1870 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
1871 (tmp & BMSR_LSTATUS))
1872 current_link_up = 1;
1873 }
1874
1875 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
1876 if (current_link_up == 1) {
1877 if (tp->link_config.active_speed == SPEED_100 ||
1878 tp->link_config.active_speed == SPEED_10)
1879 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
1880 else
1881 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1882 } else
1883 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1884
1885 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
1886 if (tp->link_config.active_duplex == DUPLEX_HALF)
1887 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
1888
1889 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1890 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
1891 if ((tp->led_ctrl == LED_CTRL_MODE_PHY_2) ||
1892 (current_link_up == 1 &&
1893 tp->link_config.active_speed == SPEED_10))
1894 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1895 } else {
1896 if (current_link_up == 1)
1897 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1898 }
1899
1900 /* ??? Without this setting Netgear GA302T PHY does not
1901 * ??? send/receive packets...
1902 */
1903 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
1904 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
1905 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
1906 tw32_f(MAC_MI_MODE, tp->mi_mode);
1907 udelay(80);
1908 }
1909
1910 tw32_f(MAC_MODE, tp->mac_mode);
1911 udelay(40);
1912
1913 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
1914 /* Polled via timer. */
1915 tw32_f(MAC_EVENT, 0);
1916 } else {
1917 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
1918 }
1919 udelay(40);
1920
1921 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
1922 current_link_up == 1 &&
1923 tp->link_config.active_speed == SPEED_1000 &&
1924 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
1925 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
1926 udelay(120);
1927 tw32_f(MAC_STATUS,
1928 (MAC_STATUS_SYNC_CHANGED |
1929 MAC_STATUS_CFG_CHANGED));
1930 udelay(40);
1931 tg3_write_mem(tp,
1932 NIC_SRAM_FIRMWARE_MBOX,
1933 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
1934 }
1935
1936 if (current_link_up != netif_carrier_ok(tp->dev)) {
1937 if (current_link_up)
1938 netif_carrier_on(tp->dev);
1939 else
1940 netif_carrier_off(tp->dev);
1941 tg3_link_report(tp);
1942 }
1943
1944 return 0;
1945 }
1946
1947 struct tg3_fiber_aneginfo {
1948 int state;
1949 #define ANEG_STATE_UNKNOWN 0
1950 #define ANEG_STATE_AN_ENABLE 1
1951 #define ANEG_STATE_RESTART_INIT 2
1952 #define ANEG_STATE_RESTART 3
1953 #define ANEG_STATE_DISABLE_LINK_OK 4
1954 #define ANEG_STATE_ABILITY_DETECT_INIT 5
1955 #define ANEG_STATE_ABILITY_DETECT 6
1956 #define ANEG_STATE_ACK_DETECT_INIT 7
1957 #define ANEG_STATE_ACK_DETECT 8
1958 #define ANEG_STATE_COMPLETE_ACK_INIT 9
1959 #define ANEG_STATE_COMPLETE_ACK 10
1960 #define ANEG_STATE_IDLE_DETECT_INIT 11
1961 #define ANEG_STATE_IDLE_DETECT 12
1962 #define ANEG_STATE_LINK_OK 13
1963 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
1964 #define ANEG_STATE_NEXT_PAGE_WAIT 15
1965
1966 u32 flags;
1967 #define MR_AN_ENABLE 0x00000001
1968 #define MR_RESTART_AN 0x00000002
1969 #define MR_AN_COMPLETE 0x00000004
1970 #define MR_PAGE_RX 0x00000008
1971 #define MR_NP_LOADED 0x00000010
1972 #define MR_TOGGLE_TX 0x00000020
1973 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
1974 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
1975 #define MR_LP_ADV_SYM_PAUSE 0x00000100
1976 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
1977 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
1978 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
1979 #define MR_LP_ADV_NEXT_PAGE 0x00001000
1980 #define MR_TOGGLE_RX 0x00002000
1981 #define MR_NP_RX 0x00004000
1982
1983 #define MR_LINK_OK 0x80000000
1984
1985 unsigned long link_time, cur_time;
1986
1987 u32 ability_match_cfg;
1988 int ability_match_count;
1989
1990 char ability_match, idle_match, ack_match;
1991
1992 u32 txconfig, rxconfig;
1993 #define ANEG_CFG_NP 0x00000080
1994 #define ANEG_CFG_ACK 0x00000040
1995 #define ANEG_CFG_RF2 0x00000020
1996 #define ANEG_CFG_RF1 0x00000010
1997 #define ANEG_CFG_PS2 0x00000001
1998 #define ANEG_CFG_PS1 0x00008000
1999 #define ANEG_CFG_HD 0x00004000
2000 #define ANEG_CFG_FD 0x00002000
2001 #define ANEG_CFG_INVAL 0x00001f06
2002
2003 };
2004 #define ANEG_OK 0
2005 #define ANEG_DONE 1
2006 #define ANEG_TIMER_ENAB 2
2007 #define ANEG_FAILED -1
2008
2009 #define ANEG_STATE_SETTLE_TIME 10000
2010
2011 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
2012 struct tg3_fiber_aneginfo *ap)
2013 {
2014 unsigned long delta;
2015 u32 rx_cfg_reg;
2016 int ret;
2017
2018 if (ap->state == ANEG_STATE_UNKNOWN) {
2019 ap->rxconfig = 0;
2020 ap->link_time = 0;
2021 ap->cur_time = 0;
2022 ap->ability_match_cfg = 0;
2023 ap->ability_match_count = 0;
2024 ap->ability_match = 0;
2025 ap->idle_match = 0;
2026 ap->ack_match = 0;
2027 }
2028 ap->cur_time++;
2029
2030 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
2031 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
2032
2033 if (rx_cfg_reg != ap->ability_match_cfg) {
2034 ap->ability_match_cfg = rx_cfg_reg;
2035 ap->ability_match = 0;
2036 ap->ability_match_count = 0;
2037 } else {
2038 if (++ap->ability_match_count > 1) {
2039 ap->ability_match = 1;
2040 ap->ability_match_cfg = rx_cfg_reg;
2041 }
2042 }
2043 if (rx_cfg_reg & ANEG_CFG_ACK)
2044 ap->ack_match = 1;
2045 else
2046 ap->ack_match = 0;
2047
2048 ap->idle_match = 0;
2049 } else {
2050 ap->idle_match = 1;
2051 ap->ability_match_cfg = 0;
2052 ap->ability_match_count = 0;
2053 ap->ability_match = 0;
2054 ap->ack_match = 0;
2055
2056 rx_cfg_reg = 0;
2057 }
2058
2059 ap->rxconfig = rx_cfg_reg;
2060 ret = ANEG_OK;
2061
2062 switch(ap->state) {
2063 case ANEG_STATE_UNKNOWN:
2064 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2065 ap->state = ANEG_STATE_AN_ENABLE;
2066
2067 /* fallthru */
2068 case ANEG_STATE_AN_ENABLE:
2069 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2070 if (ap->flags & MR_AN_ENABLE) {
2071 ap->link_time = 0;
2072 ap->cur_time = 0;
2073 ap->ability_match_cfg = 0;
2074 ap->ability_match_count = 0;
2075 ap->ability_match = 0;
2076 ap->idle_match = 0;
2077 ap->ack_match = 0;
2078
2079 ap->state = ANEG_STATE_RESTART_INIT;
2080 } else {
2081 ap->state = ANEG_STATE_DISABLE_LINK_OK;
2082 }
2083 break;
2084
2085 case ANEG_STATE_RESTART_INIT:
2086 ap->link_time = ap->cur_time;
2087 ap->flags &= ~(MR_NP_LOADED);
2088 ap->txconfig = 0;
2089 tw32(MAC_TX_AUTO_NEG, 0);
2090 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2091 tw32_f(MAC_MODE, tp->mac_mode);
2092 udelay(40);
2093
2094 ret = ANEG_TIMER_ENAB;
2095 ap->state = ANEG_STATE_RESTART;
2096
2097 /* fallthru */
2098 case ANEG_STATE_RESTART:
2099 delta = ap->cur_time - ap->link_time;
2100 if (delta > ANEG_STATE_SETTLE_TIME) {
2101 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2102 } else {
2103 ret = ANEG_TIMER_ENAB;
2104 }
2105 break;
2106
2107 case ANEG_STATE_DISABLE_LINK_OK:
2108 ret = ANEG_DONE;
2109 break;
2110
2111 case ANEG_STATE_ABILITY_DETECT_INIT:
2112 ap->flags &= ~(MR_TOGGLE_TX);
2113 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
2114 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2115 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2116 tw32_f(MAC_MODE, tp->mac_mode);
2117 udelay(40);
2118
2119 ap->state = ANEG_STATE_ABILITY_DETECT;
2120 break;
2121
2122 case ANEG_STATE_ABILITY_DETECT:
2123 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2124 ap->state = ANEG_STATE_ACK_DETECT_INIT;
2125 }
2126 break;
2127
2128 case ANEG_STATE_ACK_DETECT_INIT:
2129 ap->txconfig |= ANEG_CFG_ACK;
2130 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2131 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2132 tw32_f(MAC_MODE, tp->mac_mode);
2133 udelay(40);
2134
2135 ap->state = ANEG_STATE_ACK_DETECT;
2136
2137 /* fallthru */
2138 case ANEG_STATE_ACK_DETECT:
2139 if (ap->ack_match != 0) {
2140 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2141 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2142 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2143 } else {
2144 ap->state = ANEG_STATE_AN_ENABLE;
2145 }
2146 } else if (ap->ability_match != 0 &&
2147 ap->rxconfig == 0) {
2148 ap->state = ANEG_STATE_AN_ENABLE;
2149 }
2150 break;
2151
2152 case ANEG_STATE_COMPLETE_ACK_INIT:
2153 if (ap->rxconfig & ANEG_CFG_INVAL) {
2154 ret = ANEG_FAILED;
2155 break;
2156 }
2157 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2158 MR_LP_ADV_HALF_DUPLEX |
2159 MR_LP_ADV_SYM_PAUSE |
2160 MR_LP_ADV_ASYM_PAUSE |
2161 MR_LP_ADV_REMOTE_FAULT1 |
2162 MR_LP_ADV_REMOTE_FAULT2 |
2163 MR_LP_ADV_NEXT_PAGE |
2164 MR_TOGGLE_RX |
2165 MR_NP_RX);
2166 if (ap->rxconfig & ANEG_CFG_FD)
2167 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2168 if (ap->rxconfig & ANEG_CFG_HD)
2169 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2170 if (ap->rxconfig & ANEG_CFG_PS1)
2171 ap->flags |= MR_LP_ADV_SYM_PAUSE;
2172 if (ap->rxconfig & ANEG_CFG_PS2)
2173 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2174 if (ap->rxconfig & ANEG_CFG_RF1)
2175 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2176 if (ap->rxconfig & ANEG_CFG_RF2)
2177 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2178 if (ap->rxconfig & ANEG_CFG_NP)
2179 ap->flags |= MR_LP_ADV_NEXT_PAGE;
2180
2181 ap->link_time = ap->cur_time;
2182
2183 ap->flags ^= (MR_TOGGLE_TX);
2184 if (ap->rxconfig & 0x0008)
2185 ap->flags |= MR_TOGGLE_RX;
2186 if (ap->rxconfig & ANEG_CFG_NP)
2187 ap->flags |= MR_NP_RX;
2188 ap->flags |= MR_PAGE_RX;
2189
2190 ap->state = ANEG_STATE_COMPLETE_ACK;
2191 ret = ANEG_TIMER_ENAB;
2192 break;
2193
2194 case ANEG_STATE_COMPLETE_ACK:
2195 if (ap->ability_match != 0 &&
2196 ap->rxconfig == 0) {
2197 ap->state = ANEG_STATE_AN_ENABLE;
2198 break;
2199 }
2200 delta = ap->cur_time - ap->link_time;
2201 if (delta > ANEG_STATE_SETTLE_TIME) {
2202 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2203 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2204 } else {
2205 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2206 !(ap->flags & MR_NP_RX)) {
2207 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2208 } else {
2209 ret = ANEG_FAILED;
2210 }
2211 }
2212 }
2213 break;
2214
2215 case ANEG_STATE_IDLE_DETECT_INIT:
2216 ap->link_time = ap->cur_time;
2217 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2218 tw32_f(MAC_MODE, tp->mac_mode);
2219 udelay(40);
2220
2221 ap->state = ANEG_STATE_IDLE_DETECT;
2222 ret = ANEG_TIMER_ENAB;
2223 break;
2224
2225 case ANEG_STATE_IDLE_DETECT:
2226 if (ap->ability_match != 0 &&
2227 ap->rxconfig == 0) {
2228 ap->state = ANEG_STATE_AN_ENABLE;
2229 break;
2230 }
2231 delta = ap->cur_time - ap->link_time;
2232 if (delta > ANEG_STATE_SETTLE_TIME) {
2233 /* XXX another gem from the Broadcom driver :( */
2234 ap->state = ANEG_STATE_LINK_OK;
2235 }
2236 break;
2237
2238 case ANEG_STATE_LINK_OK:
2239 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2240 ret = ANEG_DONE;
2241 break;
2242
2243 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2244 /* ??? unimplemented */
2245 break;
2246
2247 case ANEG_STATE_NEXT_PAGE_WAIT:
2248 /* ??? unimplemented */
2249 break;
2250
2251 default:
2252 ret = ANEG_FAILED;
2253 break;
2254 };
2255
2256 return ret;
2257 }
2258
2259 static int fiber_autoneg(struct tg3 *tp, u32 *flags)
2260 {
2261 int res = 0;
2262 struct tg3_fiber_aneginfo aninfo;
2263 int status = ANEG_FAILED;
2264 unsigned int tick;
2265 u32 tmp;
2266
2267 tw32_f(MAC_TX_AUTO_NEG, 0);
2268
2269 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2270 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2271 udelay(40);
2272
2273 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2274 udelay(40);
2275
2276 memset(&aninfo, 0, sizeof(aninfo));
2277 aninfo.flags |= MR_AN_ENABLE;
2278 aninfo.state = ANEG_STATE_UNKNOWN;
2279 aninfo.cur_time = 0;
2280 tick = 0;
2281 while (++tick < 195000) {
2282 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2283 if (status == ANEG_DONE || status == ANEG_FAILED)
2284 break;
2285
2286 udelay(1);
2287 }
2288
2289 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2290 tw32_f(MAC_MODE, tp->mac_mode);
2291 udelay(40);
2292
2293 *flags = aninfo.flags;
2294
2295 if (status == ANEG_DONE &&
2296 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2297 MR_LP_ADV_FULL_DUPLEX)))
2298 res = 1;
2299
2300 return res;
2301 }
2302
2303 static void tg3_init_bcm8002(struct tg3 *tp)
2304 {
2305 u32 mac_status = tr32(MAC_STATUS);
2306 int i;
2307
2308 /* Reset when initting first time or we have a link. */
2309 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2310 !(mac_status & MAC_STATUS_PCS_SYNCED))
2311 return;
2312
2313 /* Set PLL lock range. */
2314 tg3_writephy(tp, 0x16, 0x8007);
2315
2316 /* SW reset */
2317 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2318
2319 /* Wait for reset to complete. */
2320 /* XXX schedule_timeout() ... */
2321 for (i = 0; i < 500; i++)
2322 udelay(10);
2323
2324 /* Config mode; select PMA/Ch 1 regs. */
2325 tg3_writephy(tp, 0x10, 0x8411);
2326
2327 /* Enable auto-lock and comdet, select txclk for tx. */
2328 tg3_writephy(tp, 0x11, 0x0a10);
2329
2330 tg3_writephy(tp, 0x18, 0x00a0);
2331 tg3_writephy(tp, 0x16, 0x41ff);
2332
2333 /* Assert and deassert POR. */
2334 tg3_writephy(tp, 0x13, 0x0400);
2335 udelay(40);
2336 tg3_writephy(tp, 0x13, 0x0000);
2337
2338 tg3_writephy(tp, 0x11, 0x0a50);
2339 udelay(40);
2340 tg3_writephy(tp, 0x11, 0x0a10);
2341
2342 /* Wait for signal to stabilize */
2343 /* XXX schedule_timeout() ... */
2344 for (i = 0; i < 15000; i++)
2345 udelay(10);
2346
2347 /* Deselect the channel register so we can read the PHYID
2348 * later.
2349 */
2350 tg3_writephy(tp, 0x10, 0x8011);
2351 }
2352
2353 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2354 {
2355 u32 sg_dig_ctrl, sg_dig_status;
2356 u32 serdes_cfg, expected_sg_dig_ctrl;
2357 int workaround, port_a;
2358 int current_link_up;
2359
2360 serdes_cfg = 0;
2361 expected_sg_dig_ctrl = 0;
2362 workaround = 0;
2363 port_a = 1;
2364 current_link_up = 0;
2365
2366 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2367 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2368 workaround = 1;
2369 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2370 port_a = 0;
2371
2372 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2373 /* preserve bits 20-23 for voltage regulator */
2374 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2375 }
2376
2377 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2378
2379 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2380 if (sg_dig_ctrl & (1 << 31)) {
2381 if (workaround) {
2382 u32 val = serdes_cfg;
2383
2384 if (port_a)
2385 val |= 0xc010000;
2386 else
2387 val |= 0x4010000;
2388 tw32_f(MAC_SERDES_CFG, val);
2389 }
2390 tw32_f(SG_DIG_CTRL, 0x01388400);
2391 }
2392 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2393 tg3_setup_flow_control(tp, 0, 0);
2394 current_link_up = 1;
2395 }
2396 goto out;
2397 }
2398
2399 /* Want auto-negotiation. */
2400 expected_sg_dig_ctrl = 0x81388400;
2401
2402 /* Pause capability */
2403 expected_sg_dig_ctrl |= (1 << 11);
2404
2405 /* Asymettric pause */
2406 expected_sg_dig_ctrl |= (1 << 12);
2407
2408 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
2409 if (workaround)
2410 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2411 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
2412 udelay(5);
2413 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2414
2415 tp->tg3_flags2 |= TG3_FLG2_PHY_JUST_INITTED;
2416 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2417 MAC_STATUS_SIGNAL_DET)) {
2418 int i;
2419
2420 /* Giver time to negotiate (~200ms) */
2421 for (i = 0; i < 40000; i++) {
2422 sg_dig_status = tr32(SG_DIG_STATUS);
2423 if (sg_dig_status & (0x3))
2424 break;
2425 udelay(5);
2426 }
2427 mac_status = tr32(MAC_STATUS);
2428
2429 if ((sg_dig_status & (1 << 1)) &&
2430 (mac_status & MAC_STATUS_PCS_SYNCED)) {
2431 u32 local_adv, remote_adv;
2432
2433 local_adv = ADVERTISE_PAUSE_CAP;
2434 remote_adv = 0;
2435 if (sg_dig_status & (1 << 19))
2436 remote_adv |= LPA_PAUSE_CAP;
2437 if (sg_dig_status & (1 << 20))
2438 remote_adv |= LPA_PAUSE_ASYM;
2439
2440 tg3_setup_flow_control(tp, local_adv, remote_adv);
2441 current_link_up = 1;
2442 tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2443 } else if (!(sg_dig_status & (1 << 1))) {
2444 if (tp->tg3_flags2 & TG3_FLG2_PHY_JUST_INITTED)
2445 tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2446 else {
2447 if (workaround) {
2448 u32 val = serdes_cfg;
2449
2450 if (port_a)
2451 val |= 0xc010000;
2452 else
2453 val |= 0x4010000;
2454
2455 tw32_f(MAC_SERDES_CFG, val);
2456 }
2457
2458 tw32_f(SG_DIG_CTRL, 0x01388400);
2459 udelay(40);
2460
2461 /* Link parallel detection - link is up */
2462 /* only if we have PCS_SYNC and not */
2463 /* receiving config code words */
2464 mac_status = tr32(MAC_STATUS);
2465 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2466 !(mac_status & MAC_STATUS_RCVD_CFG)) {
2467 tg3_setup_flow_control(tp, 0, 0);
2468 current_link_up = 1;
2469 }
2470 }
2471 }
2472 }
2473
2474 out:
2475 return current_link_up;
2476 }
2477
2478 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2479 {
2480 int current_link_up = 0;
2481
2482 if (!(mac_status & MAC_STATUS_PCS_SYNCED)) {
2483 tp->tg3_flags &= ~TG3_FLAG_GOT_SERDES_FLOWCTL;
2484 goto out;
2485 }
2486
2487 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2488 u32 flags;
2489 int i;
2490
2491 if (fiber_autoneg(tp, &flags)) {
2492 u32 local_adv, remote_adv;
2493
2494 local_adv = ADVERTISE_PAUSE_CAP;
2495 remote_adv = 0;
2496 if (flags & MR_LP_ADV_SYM_PAUSE)
2497 remote_adv |= LPA_PAUSE_CAP;
2498 if (flags & MR_LP_ADV_ASYM_PAUSE)
2499 remote_adv |= LPA_PAUSE_ASYM;
2500
2501 tg3_setup_flow_control(tp, local_adv, remote_adv);
2502
2503 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2504 current_link_up = 1;
2505 }
2506 for (i = 0; i < 30; i++) {
2507 udelay(20);
2508 tw32_f(MAC_STATUS,
2509 (MAC_STATUS_SYNC_CHANGED |
2510 MAC_STATUS_CFG_CHANGED));
2511 udelay(40);
2512 if ((tr32(MAC_STATUS) &
2513 (MAC_STATUS_SYNC_CHANGED |
2514 MAC_STATUS_CFG_CHANGED)) == 0)
2515 break;
2516 }
2517
2518 mac_status = tr32(MAC_STATUS);
2519 if (current_link_up == 0 &&
2520 (mac_status & MAC_STATUS_PCS_SYNCED) &&
2521 !(mac_status & MAC_STATUS_RCVD_CFG))
2522 current_link_up = 1;
2523 } else {
2524 /* Forcing 1000FD link up. */
2525 current_link_up = 1;
2526 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2527
2528 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2529 udelay(40);
2530 }
2531
2532 out:
2533 return current_link_up;
2534 }
2535
2536 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2537 {
2538 u32 orig_pause_cfg;
2539 u16 orig_active_speed;
2540 u8 orig_active_duplex;
2541 u32 mac_status;
2542 int current_link_up;
2543 int i;
2544
2545 orig_pause_cfg =
2546 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2547 TG3_FLAG_TX_PAUSE));
2548 orig_active_speed = tp->link_config.active_speed;
2549 orig_active_duplex = tp->link_config.active_duplex;
2550
2551 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2552 netif_carrier_ok(tp->dev) &&
2553 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2554 mac_status = tr32(MAC_STATUS);
2555 mac_status &= (MAC_STATUS_PCS_SYNCED |
2556 MAC_STATUS_SIGNAL_DET |
2557 MAC_STATUS_CFG_CHANGED |
2558 MAC_STATUS_RCVD_CFG);
2559 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2560 MAC_STATUS_SIGNAL_DET)) {
2561 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2562 MAC_STATUS_CFG_CHANGED));
2563 return 0;
2564 }
2565 }
2566
2567 tw32_f(MAC_TX_AUTO_NEG, 0);
2568
2569 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2570 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2571 tw32_f(MAC_MODE, tp->mac_mode);
2572 udelay(40);
2573
2574 if (tp->phy_id == PHY_ID_BCM8002)
2575 tg3_init_bcm8002(tp);
2576
2577 /* Enable link change event even when serdes polling. */
2578 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2579 udelay(40);
2580
2581 current_link_up = 0;
2582 mac_status = tr32(MAC_STATUS);
2583
2584 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
2585 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
2586 else
2587 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2588
2589 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2590 tw32_f(MAC_MODE, tp->mac_mode);
2591 udelay(40);
2592
2593 tp->hw_status->status =
2594 (SD_STATUS_UPDATED |
2595 (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
2596
2597 for (i = 0; i < 100; i++) {
2598 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2599 MAC_STATUS_CFG_CHANGED));
2600 udelay(5);
2601 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
2602 MAC_STATUS_CFG_CHANGED)) == 0)
2603 break;
2604 }
2605
2606 mac_status = tr32(MAC_STATUS);
2607 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2608 current_link_up = 0;
2609 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2610 tw32_f(MAC_MODE, (tp->mac_mode |
2611 MAC_MODE_SEND_CONFIGS));
2612 udelay(1);
2613 tw32_f(MAC_MODE, tp->mac_mode);
2614 }
2615 }
2616
2617 if (current_link_up == 1) {
2618 tp->link_config.active_speed = SPEED_1000;
2619 tp->link_config.active_duplex = DUPLEX_FULL;
2620 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2621 LED_CTRL_LNKLED_OVERRIDE |
2622 LED_CTRL_1000MBPS_ON));
2623 } else {
2624 tp->link_config.active_speed = SPEED_INVALID;
2625 tp->link_config.active_duplex = DUPLEX_INVALID;
2626 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2627 LED_CTRL_LNKLED_OVERRIDE |
2628 LED_CTRL_TRAFFIC_OVERRIDE));
2629 }
2630
2631 if (current_link_up != netif_carrier_ok(tp->dev)) {
2632 if (current_link_up)
2633 netif_carrier_on(tp->dev);
2634 else
2635 netif_carrier_off(tp->dev);
2636 tg3_link_report(tp);
2637 } else {
2638 u32 now_pause_cfg =
2639 tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2640 TG3_FLAG_TX_PAUSE);
2641 if (orig_pause_cfg != now_pause_cfg ||
2642 orig_active_speed != tp->link_config.active_speed ||
2643 orig_active_duplex != tp->link_config.active_duplex)
2644 tg3_link_report(tp);
2645 }
2646
2647 return 0;
2648 }
2649
2650 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
2651 {
2652 int current_link_up, err = 0;
2653 u32 bmsr, bmcr;
2654 u16 current_speed;
2655 u8 current_duplex;
2656
2657 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2658 tw32_f(MAC_MODE, tp->mac_mode);
2659 udelay(40);
2660
2661 tw32(MAC_EVENT, 0);
2662
2663 tw32_f(MAC_STATUS,
2664 (MAC_STATUS_SYNC_CHANGED |
2665 MAC_STATUS_CFG_CHANGED |
2666 MAC_STATUS_MI_COMPLETION |
2667 MAC_STATUS_LNKSTATE_CHANGED));
2668 udelay(40);
2669
2670 if (force_reset)
2671 tg3_phy_reset(tp);
2672
2673 current_link_up = 0;
2674 current_speed = SPEED_INVALID;
2675 current_duplex = DUPLEX_INVALID;
2676
2677 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2678 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2679 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
2680 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2681 bmsr |= BMSR_LSTATUS;
2682 else
2683 bmsr &= ~BMSR_LSTATUS;
2684 }
2685
2686 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
2687
2688 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2689 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2690 /* do nothing, just check for link up at the end */
2691 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2692 u32 adv, new_adv;
2693
2694 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2695 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
2696 ADVERTISE_1000XPAUSE |
2697 ADVERTISE_1000XPSE_ASYM |
2698 ADVERTISE_SLCT);
2699
2700 /* Always advertise symmetric PAUSE just like copper */
2701 new_adv |= ADVERTISE_1000XPAUSE;
2702
2703 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2704 new_adv |= ADVERTISE_1000XHALF;
2705 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2706 new_adv |= ADVERTISE_1000XFULL;
2707
2708 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
2709 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2710 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
2711 tg3_writephy(tp, MII_BMCR, bmcr);
2712
2713 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2714 tp->tg3_flags2 |= TG3_FLG2_PHY_JUST_INITTED;
2715 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2716
2717 return err;
2718 }
2719 } else {
2720 u32 new_bmcr;
2721
2722 bmcr &= ~BMCR_SPEED1000;
2723 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
2724
2725 if (tp->link_config.duplex == DUPLEX_FULL)
2726 new_bmcr |= BMCR_FULLDPLX;
2727
2728 if (new_bmcr != bmcr) {
2729 /* BMCR_SPEED1000 is a reserved bit that needs
2730 * to be set on write.
2731 */
2732 new_bmcr |= BMCR_SPEED1000;
2733
2734 /* Force a linkdown */
2735 if (netif_carrier_ok(tp->dev)) {
2736 u32 adv;
2737
2738 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2739 adv &= ~(ADVERTISE_1000XFULL |
2740 ADVERTISE_1000XHALF |
2741 ADVERTISE_SLCT);
2742 tg3_writephy(tp, MII_ADVERTISE, adv);
2743 tg3_writephy(tp, MII_BMCR, bmcr |
2744 BMCR_ANRESTART |
2745 BMCR_ANENABLE);
2746 udelay(10);
2747 netif_carrier_off(tp->dev);
2748 }
2749 tg3_writephy(tp, MII_BMCR, new_bmcr);
2750 bmcr = new_bmcr;
2751 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2752 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2753 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2754 ASIC_REV_5714) {
2755 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2756 bmsr |= BMSR_LSTATUS;
2757 else
2758 bmsr &= ~BMSR_LSTATUS;
2759 }
2760 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2761 }
2762 }
2763
2764 if (bmsr & BMSR_LSTATUS) {
2765 current_speed = SPEED_1000;
2766 current_link_up = 1;
2767 if (bmcr & BMCR_FULLDPLX)
2768 current_duplex = DUPLEX_FULL;
2769 else
2770 current_duplex = DUPLEX_HALF;
2771
2772 if (bmcr & BMCR_ANENABLE) {
2773 u32 local_adv, remote_adv, common;
2774
2775 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
2776 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
2777 common = local_adv & remote_adv;
2778 if (common & (ADVERTISE_1000XHALF |
2779 ADVERTISE_1000XFULL)) {
2780 if (common & ADVERTISE_1000XFULL)
2781 current_duplex = DUPLEX_FULL;
2782 else
2783 current_duplex = DUPLEX_HALF;
2784
2785 tg3_setup_flow_control(tp, local_adv,
2786 remote_adv);
2787 }
2788 else
2789 current_link_up = 0;
2790 }
2791 }
2792
2793 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2794 if (tp->link_config.active_duplex == DUPLEX_HALF)
2795 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2796
2797 tw32_f(MAC_MODE, tp->mac_mode);
2798 udelay(40);
2799
2800 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2801
2802 tp->link_config.active_speed = current_speed;
2803 tp->link_config.active_duplex = current_duplex;
2804
2805 if (current_link_up != netif_carrier_ok(tp->dev)) {
2806 if (current_link_up)
2807 netif_carrier_on(tp->dev);
2808 else {
2809 netif_carrier_off(tp->dev);
2810 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2811 }
2812 tg3_link_report(tp);
2813 }
2814 return err;
2815 }
2816
2817 static void tg3_serdes_parallel_detect(struct tg3 *tp)
2818 {
2819 if (tp->tg3_flags2 & TG3_FLG2_PHY_JUST_INITTED) {
2820 /* Give autoneg time to complete. */
2821 tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2822 return;
2823 }
2824 if (!netif_carrier_ok(tp->dev) &&
2825 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
2826 u32 bmcr;
2827
2828 tg3_readphy(tp, MII_BMCR, &bmcr);
2829 if (bmcr & BMCR_ANENABLE) {
2830 u32 phy1, phy2;
2831
2832 /* Select shadow register 0x1f */
2833 tg3_writephy(tp, 0x1c, 0x7c00);
2834 tg3_readphy(tp, 0x1c, &phy1);
2835
2836 /* Select expansion interrupt status register */
2837 tg3_writephy(tp, 0x17, 0x0f01);
2838 tg3_readphy(tp, 0x15, &phy2);
2839 tg3_readphy(tp, 0x15, &phy2);
2840
2841 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
2842 /* We have signal detect and not receiving
2843 * config code words, link is up by parallel
2844 * detection.
2845 */
2846
2847 bmcr &= ~BMCR_ANENABLE;
2848 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
2849 tg3_writephy(tp, MII_BMCR, bmcr);
2850 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
2851 }
2852 }
2853 }
2854 else if (netif_carrier_ok(tp->dev) &&
2855 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
2856 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2857 u32 phy2;
2858
2859 /* Select expansion interrupt status register */
2860 tg3_writephy(tp, 0x17, 0x0f01);
2861 tg3_readphy(tp, 0x15, &phy2);
2862 if (phy2 & 0x20) {
2863 u32 bmcr;
2864
2865 /* Config code words received, turn on autoneg. */
2866 tg3_readphy(tp, MII_BMCR, &bmcr);
2867 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
2868
2869 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2870
2871 }
2872 }
2873 }
2874
2875 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
2876 {
2877 int err;
2878
2879 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2880 err = tg3_setup_fiber_phy(tp, force_reset);
2881 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
2882 err = tg3_setup_fiber_mii_phy(tp, force_reset);
2883 } else {
2884 err = tg3_setup_copper_phy(tp, force_reset);
2885 }
2886
2887 if (tp->link_config.active_speed == SPEED_1000 &&
2888 tp->link_config.active_duplex == DUPLEX_HALF)
2889 tw32(MAC_TX_LENGTHS,
2890 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2891 (6 << TX_LENGTHS_IPG_SHIFT) |
2892 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2893 else
2894 tw32(MAC_TX_LENGTHS,
2895 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2896 (6 << TX_LENGTHS_IPG_SHIFT) |
2897 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2898
2899 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2900 if (netif_carrier_ok(tp->dev)) {
2901 tw32(HOSTCC_STAT_COAL_TICKS,
2902 tp->coal.stats_block_coalesce_usecs);
2903 } else {
2904 tw32(HOSTCC_STAT_COAL_TICKS, 0);
2905 }
2906 }
2907
2908 return err;
2909 }
2910
2911 /* This is called whenever we suspect that the system chipset is re-
2912 * ordering the sequence of MMIO to the tx send mailbox. The symptom
2913 * is bogus tx completions. We try to recover by setting the
2914 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
2915 * in the workqueue.
2916 */
2917 static void tg3_tx_recover(struct tg3 *tp)
2918 {
2919 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
2920 tp->write32_tx_mbox == tg3_write_indirect_mbox);
2921
2922 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
2923 "mapped I/O cycles to the network device, attempting to "
2924 "recover. Please report the problem to the driver maintainer "
2925 "and include system chipset information.\n", tp->dev->name);
2926
2927 spin_lock(&tp->lock);
2928 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
2929 spin_unlock(&tp->lock);
2930 }
2931
2932 static inline u32 tg3_tx_avail(struct tg3 *tp)
2933 {
2934 smp_mb();
2935 return (tp->tx_pending -
2936 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
2937 }
2938
2939 /* Tigon3 never reports partial packet sends. So we do not
2940 * need special logic to handle SKBs that have not had all
2941 * of their frags sent yet, like SunGEM does.
2942 */
2943 static void tg3_tx(struct tg3 *tp)
2944 {
2945 u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
2946 u32 sw_idx = tp->tx_cons;
2947
2948 while (sw_idx != hw_idx) {
2949 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
2950 struct sk_buff *skb = ri->skb;
2951 int i, tx_bug = 0;
2952
2953 if (unlikely(skb == NULL)) {
2954 tg3_tx_recover(tp);
2955 return;
2956 }
2957
2958 pci_unmap_single(tp->pdev,
2959 pci_unmap_addr(ri, mapping),
2960 skb_headlen(skb),
2961 PCI_DMA_TODEVICE);
2962
2963 ri->skb = NULL;
2964
2965 sw_idx = NEXT_TX(sw_idx);
2966
2967 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2968 ri = &tp->tx_buffers[sw_idx];
2969 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
2970 tx_bug = 1;
2971
2972 pci_unmap_page(tp->pdev,
2973 pci_unmap_addr(ri, mapping),
2974 skb_shinfo(skb)->frags[i].size,
2975 PCI_DMA_TODEVICE);
2976
2977 sw_idx = NEXT_TX(sw_idx);
2978 }
2979
2980 dev_kfree_skb(skb);
2981
2982 if (unlikely(tx_bug)) {
2983 tg3_tx_recover(tp);
2984 return;
2985 }
2986 }
2987
2988 tp->tx_cons = sw_idx;
2989
2990 /* Need to make the tx_cons update visible to tg3_start_xmit()
2991 * before checking for netif_queue_stopped(). Without the
2992 * memory barrier, there is a small possibility that tg3_start_xmit()
2993 * will miss it and cause the queue to be stopped forever.
2994 */
2995 smp_mb();
2996
2997 if (unlikely(netif_queue_stopped(tp->dev) &&
2998 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH))) {
2999 netif_tx_lock(tp->dev);
3000 if (netif_queue_stopped(tp->dev) &&
3001 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH))
3002 netif_wake_queue(tp->dev);
3003 netif_tx_unlock(tp->dev);
3004 }
3005 }
3006
3007 /* Returns size of skb allocated or < 0 on error.
3008 *
3009 * We only need to fill in the address because the other members
3010 * of the RX descriptor are invariant, see tg3_init_rings.
3011 *
3012 * Note the purposeful assymetry of cpu vs. chip accesses. For
3013 * posting buffers we only dirty the first cache line of the RX
3014 * descriptor (containing the address). Whereas for the RX status
3015 * buffers the cpu only reads the last cacheline of the RX descriptor
3016 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
3017 */
3018 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
3019 int src_idx, u32 dest_idx_unmasked)
3020 {
3021 struct tg3_rx_buffer_desc *desc;
3022 struct ring_info *map, *src_map;
3023 struct sk_buff *skb;
3024 dma_addr_t mapping;
3025 int skb_size, dest_idx;
3026
3027 src_map = NULL;
3028 switch (opaque_key) {
3029 case RXD_OPAQUE_RING_STD:
3030 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3031 desc = &tp->rx_std[dest_idx];
3032 map = &tp->rx_std_buffers[dest_idx];
3033 if (src_idx >= 0)
3034 src_map = &tp->rx_std_buffers[src_idx];
3035 skb_size = tp->rx_pkt_buf_sz;
3036 break;
3037
3038 case RXD_OPAQUE_RING_JUMBO:
3039 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3040 desc = &tp->rx_jumbo[dest_idx];
3041 map = &tp->rx_jumbo_buffers[dest_idx];
3042 if (src_idx >= 0)
3043 src_map = &tp->rx_jumbo_buffers[src_idx];
3044 skb_size = RX_JUMBO_PKT_BUF_SZ;
3045 break;
3046
3047 default:
3048 return -EINVAL;
3049 };
3050
3051 /* Do not overwrite any of the map or rp information
3052 * until we are sure we can commit to a new buffer.
3053 *
3054 * Callers depend upon this behavior and assume that
3055 * we leave everything unchanged if we fail.
3056 */
3057 skb = netdev_alloc_skb(tp->dev, skb_size);
3058 if (skb == NULL)
3059 return -ENOMEM;
3060
3061 skb_reserve(skb, tp->rx_offset);
3062
3063 mapping = pci_map_single(tp->pdev, skb->data,
3064 skb_size - tp->rx_offset,
3065 PCI_DMA_FROMDEVICE);
3066
3067 map->skb = skb;
3068 pci_unmap_addr_set(map, mapping, mapping);
3069
3070 if (src_map != NULL)
3071 src_map->skb = NULL;
3072
3073 desc->addr_hi = ((u64)mapping >> 32);
3074 desc->addr_lo = ((u64)mapping & 0xffffffff);
3075
3076 return skb_size;
3077 }
3078
3079 /* We only need to move over in the address because the other
3080 * members of the RX descriptor are invariant. See notes above
3081 * tg3_alloc_rx_skb for full details.
3082 */
3083 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
3084 int src_idx, u32 dest_idx_unmasked)
3085 {
3086 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
3087 struct ring_info *src_map, *dest_map;
3088 int dest_idx;
3089
3090 switch (opaque_key) {
3091 case RXD_OPAQUE_RING_STD:
3092 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3093 dest_desc = &tp->rx_std[dest_idx];
3094 dest_map = &tp->rx_std_buffers[dest_idx];
3095 src_desc = &tp->rx_std[src_idx];
3096 src_map = &tp->rx_std_buffers[src_idx];
3097 break;
3098
3099 case RXD_OPAQUE_RING_JUMBO:
3100 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3101 dest_desc = &tp->rx_jumbo[dest_idx];
3102 dest_map = &tp->rx_jumbo_buffers[dest_idx];
3103 src_desc = &tp->rx_jumbo[src_idx];
3104 src_map = &tp->rx_jumbo_buffers[src_idx];
3105 break;
3106
3107 default:
3108 return;
3109 };
3110
3111 dest_map->skb = src_map->skb;
3112 pci_unmap_addr_set(dest_map, mapping,
3113 pci_unmap_addr(src_map, mapping));
3114 dest_desc->addr_hi = src_desc->addr_hi;
3115 dest_desc->addr_lo = src_desc->addr_lo;
3116
3117 src_map->skb = NULL;
3118 }
3119
3120 #if TG3_VLAN_TAG_USED
3121 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
3122 {
3123 return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
3124 }
3125 #endif
3126
3127 /* The RX ring scheme is composed of multiple rings which post fresh
3128 * buffers to the chip, and one special ring the chip uses to report
3129 * status back to the host.
3130 *
3131 * The special ring reports the status of received packets to the
3132 * host. The chip does not write into the original descriptor the
3133 * RX buffer was obtained from. The chip simply takes the original
3134 * descriptor as provided by the host, updates the status and length
3135 * field, then writes this into the next status ring entry.
3136 *
3137 * Each ring the host uses to post buffers to the chip is described
3138 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
3139 * it is first placed into the on-chip ram. When the packet's length
3140 * is known, it walks down the TG3_BDINFO entries to select the ring.
3141 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
3142 * which is within the range of the new packet's length is chosen.
3143 *
3144 * The "separate ring for rx status" scheme may sound queer, but it makes
3145 * sense from a cache coherency perspective. If only the host writes
3146 * to the buffer post rings, and only the chip writes to the rx status
3147 * rings, then cache lines never move beyond shared-modified state.
3148 * If both the host and chip were to write into the same ring, cache line
3149 * eviction could occur since both entities want it in an exclusive state.
3150 */
3151 static int tg3_rx(struct tg3 *tp, int budget)
3152 {
3153 u32 work_mask, rx_std_posted = 0;
3154 u32 sw_idx = tp->rx_rcb_ptr;
3155 u16 hw_idx;
3156 int received;
3157
3158 hw_idx = tp->hw_status->idx[0].rx_producer;
3159 /*
3160 * We need to order the read of hw_idx and the read of
3161 * the opaque cookie.
3162 */
3163 rmb();
3164 work_mask = 0;
3165 received = 0;
3166 while (sw_idx != hw_idx && budget > 0) {
3167 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
3168 unsigned int len;
3169 struct sk_buff *skb;
3170 dma_addr_t dma_addr;
3171 u32 opaque_key, desc_idx, *post_ptr;
3172
3173 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
3174 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
3175 if (opaque_key == RXD_OPAQUE_RING_STD) {
3176 dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
3177 mapping);
3178 skb = tp->rx_std_buffers[desc_idx].skb;
3179 post_ptr = &tp->rx_std_ptr;
3180 rx_std_posted++;
3181 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
3182 dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
3183 mapping);
3184 skb = tp->rx_jumbo_buffers[desc_idx].skb;
3185 post_ptr = &tp->rx_jumbo_ptr;
3186 }
3187 else {
3188 goto next_pkt_nopost;
3189 }
3190
3191 work_mask |= opaque_key;
3192
3193 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
3194 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
3195 drop_it:
3196 tg3_recycle_rx(tp, opaque_key,
3197 desc_idx, *post_ptr);
3198 drop_it_no_recycle:
3199 /* Other statistics kept track of by card. */
3200 tp->net_stats.rx_dropped++;
3201 goto next_pkt;
3202 }
3203
3204 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
3205
3206 if (len > RX_COPY_THRESHOLD
3207 && tp->rx_offset == 2
3208 /* rx_offset != 2 iff this is a 5701 card running
3209 * in PCI-X mode [see tg3_get_invariants()] */
3210 ) {
3211 int skb_size;
3212
3213 skb_size = tg3_alloc_rx_skb(tp, opaque_key,
3214 desc_idx, *post_ptr);
3215 if (skb_size < 0)
3216 goto drop_it;
3217
3218 pci_unmap_single(tp->pdev, dma_addr,
3219 skb_size - tp->rx_offset,
3220 PCI_DMA_FROMDEVICE);
3221
3222 skb_put(skb, len);
3223 } else {
3224 struct sk_buff *copy_skb;
3225
3226 tg3_recycle_rx(tp, opaque_key,
3227 desc_idx, *post_ptr);
3228
3229 copy_skb = netdev_alloc_skb(tp->dev, len + 2);
3230 if (copy_skb == NULL)
3231 goto drop_it_no_recycle;
3232
3233 skb_reserve(copy_skb, 2);
3234 skb_put(copy_skb, len);
3235 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3236 memcpy(copy_skb->data, skb->data, len);
3237 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3238
3239 /* We'll reuse the original ring buffer. */
3240 skb = copy_skb;
3241 }
3242
3243 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
3244 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
3245 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
3246 >> RXD_TCPCSUM_SHIFT) == 0xffff))
3247 skb->ip_summed = CHECKSUM_UNNECESSARY;
3248 else
3249 skb->ip_summed = CHECKSUM_NONE;
3250
3251 skb->protocol = eth_type_trans(skb, tp->dev);
3252 #if TG3_VLAN_TAG_USED
3253 if (tp->vlgrp != NULL &&
3254 desc->type_flags & RXD_FLAG_VLAN) {
3255 tg3_vlan_rx(tp, skb,
3256 desc->err_vlan & RXD_VLAN_MASK);
3257 } else
3258 #endif
3259 netif_receive_skb(skb);
3260
3261 tp->dev->last_rx = jiffies;
3262 received++;
3263 budget--;
3264
3265 next_pkt:
3266 (*post_ptr)++;
3267
3268 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
3269 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
3270
3271 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
3272 TG3_64BIT_REG_LOW, idx);
3273 work_mask &= ~RXD_OPAQUE_RING_STD;
3274 rx_std_posted = 0;
3275 }
3276 next_pkt_nopost:
3277 sw_idx++;
3278 sw_idx %= TG3_RX_RCB_RING_SIZE(tp);
3279
3280 /* Refresh hw_idx to see if there is new work */
3281 if (sw_idx == hw_idx) {
3282 hw_idx = tp->hw_status->idx[0].rx_producer;
3283 rmb();
3284 }
3285 }
3286
3287 /* ACK the status ring. */
3288 tp->rx_rcb_ptr = sw_idx;
3289 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
3290
3291 /* Refill RX ring(s). */
3292 if (work_mask & RXD_OPAQUE_RING_STD) {
3293 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
3294 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
3295 sw_idx);
3296 }
3297 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
3298 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
3299 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
3300 sw_idx);
3301 }
3302 mmiowb();
3303
3304 return received;
3305 }
3306
3307 static int tg3_poll(struct net_device *netdev, int *budget)
3308 {
3309 struct tg3 *tp = netdev_priv(netdev);
3310 struct tg3_hw_status *sblk = tp->hw_status;
3311 int done;
3312
3313 /* handle link change and other phy events */
3314 if (!(tp->tg3_flags &
3315 (TG3_FLAG_USE_LINKCHG_REG |
3316 TG3_FLAG_POLL_SERDES))) {
3317 if (sblk->status & SD_STATUS_LINK_CHG) {
3318 sblk->status = SD_STATUS_UPDATED |
3319 (sblk->status & ~SD_STATUS_LINK_CHG);
3320 spin_lock(&tp->lock);
3321 tg3_setup_phy(tp, 0);
3322 spin_unlock(&tp->lock);
3323 }
3324 }
3325
3326 /* run TX completion thread */
3327 if (sblk->idx[0].tx_consumer != tp->tx_cons) {
3328 tg3_tx(tp);
3329 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) {
3330 netif_rx_complete(netdev);
3331 schedule_work(&tp->reset_task);
3332 return 0;
3333 }
3334 }
3335
3336 /* run RX thread, within the bounds set by NAPI.
3337 * All RX "locking" is done by ensuring outside
3338 * code synchronizes with dev->poll()
3339 */
3340 if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) {
3341 int orig_budget = *budget;
3342 int work_done;
3343
3344 if (orig_budget > netdev->quota)
3345 orig_budget = netdev->quota;
3346
3347 work_done = tg3_rx(tp, orig_budget);
3348
3349 *budget -= work_done;
3350 netdev->quota -= work_done;
3351 }
3352
3353 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
3354 tp->last_tag = sblk->status_tag;
3355 rmb();
3356 } else
3357 sblk->status &= ~SD_STATUS_UPDATED;
3358
3359 /* if no more work, tell net stack and NIC we're done */
3360 done = !tg3_has_work(tp);
3361 if (done) {
3362 netif_rx_complete(netdev);
3363 tg3_restart_ints(tp);
3364 }
3365
3366 return (done ? 0 : 1);
3367 }
3368
3369 static void tg3_irq_quiesce(struct tg3 *tp)
3370 {
3371 BUG_ON(tp->irq_sync);
3372
3373 tp->irq_sync = 1;
3374 smp_mb();
3375
3376 synchronize_irq(tp->pdev->irq);
3377 }
3378
3379 static inline int tg3_irq_sync(struct tg3 *tp)
3380 {
3381 return tp->irq_sync;
3382 }
3383
3384 /* Fully shutdown all tg3 driver activity elsewhere in the system.
3385 * If irq_sync is non-zero, then the IRQ handler must be synchronized
3386 * with as well. Most of the time, this is not necessary except when
3387 * shutting down the device.
3388 */
3389 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
3390 {
3391 if (irq_sync)
3392 tg3_irq_quiesce(tp);
3393 spin_lock_bh(&tp->lock);
3394 }
3395
3396 static inline void tg3_full_unlock(struct tg3 *tp)
3397 {
3398 spin_unlock_bh(&tp->lock);
3399 }
3400
3401 /* One-shot MSI handler - Chip automatically disables interrupt
3402 * after sending MSI so driver doesn't have to do it.
3403 */
3404 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id, struct pt_regs *regs)
3405 {
3406 struct net_device *dev = dev_id;
3407 struct tg3 *tp = netdev_priv(dev);
3408
3409 prefetch(tp->hw_status);
3410 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3411
3412 if (likely(!tg3_irq_sync(tp)))
3413 netif_rx_schedule(dev); /* schedule NAPI poll */
3414
3415 return IRQ_HANDLED;
3416 }
3417
3418 /* MSI ISR - No need to check for interrupt sharing and no need to
3419 * flush status block and interrupt mailbox. PCI ordering rules
3420 * guarantee that MSI will arrive after the status block.
3421 */
3422 static irqreturn_t tg3_msi(int irq, void *dev_id, struct pt_regs *regs)
3423 {
3424 struct net_device *dev = dev_id;
3425 struct tg3 *tp = netdev_priv(dev);
3426
3427 prefetch(tp->hw_status);
3428 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3429 /*
3430 * Writing any value to intr-mbox-0 clears PCI INTA# and
3431 * chip-internal interrupt pending events.
3432 * Writing non-zero to intr-mbox-0 additional tells the
3433 * NIC to stop sending us irqs, engaging "in-intr-handler"
3434 * event coalescing.
3435 */
3436 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3437 if (likely(!tg3_irq_sync(tp)))
3438 netif_rx_schedule(dev); /* schedule NAPI poll */
3439
3440 return IRQ_RETVAL(1);
3441 }
3442
3443 static irqreturn_t tg3_interrupt(int irq, void *dev_id, struct pt_regs *regs)
3444 {
3445 struct net_device *dev = dev_id;
3446 struct tg3 *tp = netdev_priv(dev);
3447 struct tg3_hw_status *sblk = tp->hw_status;
3448 unsigned int handled = 1;
3449
3450 /* In INTx mode, it is possible for the interrupt to arrive at
3451 * the CPU before the status block posted prior to the interrupt.
3452 * Reading the PCI State register will confirm whether the
3453 * interrupt is ours and will flush the status block.
3454 */
3455 if ((sblk->status & SD_STATUS_UPDATED) ||
3456 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3457 /*
3458 * Writing any value to intr-mbox-0 clears PCI INTA# and
3459 * chip-internal interrupt pending events.
3460 * Writing non-zero to intr-mbox-0 additional tells the
3461 * NIC to stop sending us irqs, engaging "in-intr-handler"
3462 * event coalescing.
3463 */
3464 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3465 0x00000001);
3466 if (tg3_irq_sync(tp))
3467 goto out;
3468 sblk->status &= ~SD_STATUS_UPDATED;
3469 if (likely(tg3_has_work(tp))) {
3470 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3471 netif_rx_schedule(dev); /* schedule NAPI poll */
3472 } else {
3473 /* No work, shared interrupt perhaps? re-enable
3474 * interrupts, and flush that PCI write
3475 */
3476 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3477 0x00000000);
3478 }
3479 } else { /* shared interrupt */
3480 handled = 0;
3481 }
3482 out:
3483 return IRQ_RETVAL(handled);
3484 }
3485
3486 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id, struct pt_regs *regs)
3487 {
3488 struct net_device *dev = dev_id;
3489 struct tg3 *tp = netdev_priv(dev);
3490 struct tg3_hw_status *sblk = tp->hw_status;
3491 unsigned int handled = 1;
3492
3493 /* In INTx mode, it is possible for the interrupt to arrive at
3494 * the CPU before the status block posted prior to the interrupt.
3495 * Reading the PCI State register will confirm whether the
3496 * interrupt is ours and will flush the status block.
3497 */
3498 if ((sblk->status_tag != tp->last_tag) ||
3499 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3500 /*
3501 * writing any value to intr-mbox-0 clears PCI INTA# and
3502 * chip-internal interrupt pending events.
3503 * writing non-zero to intr-mbox-0 additional tells the
3504 * NIC to stop sending us irqs, engaging "in-intr-handler"
3505 * event coalescing.
3506 */
3507 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3508 0x00000001);
3509 if (tg3_irq_sync(tp))
3510 goto out;
3511 if (netif_rx_schedule_prep(dev)) {
3512 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3513 /* Update last_tag to mark that this status has been
3514 * seen. Because interrupt may be shared, we may be
3515 * racing with tg3_poll(), so only update last_tag
3516 * if tg3_poll() is not scheduled.
3517 */
3518 tp->last_tag = sblk->status_tag;
3519 __netif_rx_schedule(dev);
3520 }
3521 } else { /* shared interrupt */
3522 handled = 0;
3523 }
3524 out:
3525 return IRQ_RETVAL(handled);
3526 }
3527
3528 /* ISR for interrupt test */
3529 static irqreturn_t tg3_test_isr(int irq, void *dev_id,
3530 struct pt_regs *regs)
3531 {
3532 struct net_device *dev = dev_id;
3533 struct tg3 *tp = netdev_priv(dev);
3534 struct tg3_hw_status *sblk = tp->hw_status;
3535
3536 if ((sblk->status & SD_STATUS_UPDATED) ||
3537 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3538 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3539 0x00000001);
3540 return IRQ_RETVAL(1);
3541 }
3542 return IRQ_RETVAL(0);
3543 }
3544
3545 static int tg3_init_hw(struct tg3 *, int);
3546 static int tg3_halt(struct tg3 *, int, int);
3547
3548 /* Restart hardware after configuration changes, self-test, etc.
3549 * Invoked with tp->lock held.
3550 */
3551 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
3552 {
3553 int err;
3554
3555 err = tg3_init_hw(tp, reset_phy);
3556 if (err) {
3557 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
3558 "aborting.\n", tp->dev->name);
3559 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
3560 tg3_full_unlock(tp);
3561 del_timer_sync(&tp->timer);
3562 tp->irq_sync = 0;
3563 netif_poll_enable(tp->dev);
3564 dev_close(tp->dev);
3565 tg3_full_lock(tp, 0);
3566 }
3567 return err;
3568 }
3569
3570 #ifdef CONFIG_NET_POLL_CONTROLLER
3571 static void tg3_poll_controller(struct net_device *dev)
3572 {
3573 struct tg3 *tp = netdev_priv(dev);
3574
3575 tg3_interrupt(tp->pdev->irq, dev, NULL);
3576 }
3577 #endif
3578
3579 static void tg3_reset_task(void *_data)
3580 {
3581 struct tg3 *tp = _data;
3582 unsigned int restart_timer;
3583
3584 tg3_full_lock(tp, 0);
3585 tp->tg3_flags |= TG3_FLAG_IN_RESET_TASK;
3586
3587 if (!netif_running(tp->dev)) {
3588 tp->tg3_flags &= ~TG3_FLAG_IN_RESET_TASK;
3589 tg3_full_unlock(tp);
3590 return;
3591 }
3592
3593 tg3_full_unlock(tp);
3594
3595 tg3_netif_stop(tp);
3596
3597 tg3_full_lock(tp, 1);
3598
3599 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
3600 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
3601
3602 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
3603 tp->write32_tx_mbox = tg3_write32_tx_mbox;
3604 tp->write32_rx_mbox = tg3_write_flush_reg32;
3605 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
3606 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
3607 }
3608
3609 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
3610 if (tg3_init_hw(tp, 1))
3611 goto out;
3612
3613 tg3_netif_start(tp);
3614
3615 if (restart_timer)
3616 mod_timer(&tp->timer, jiffies + 1);
3617
3618 out:
3619 tp->tg3_flags &= ~TG3_FLAG_IN_RESET_TASK;
3620
3621 tg3_full_unlock(tp);
3622 }
3623
3624 static void tg3_tx_timeout(struct net_device *dev)
3625 {
3626 struct tg3 *tp = netdev_priv(dev);
3627
3628 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
3629 dev->name);
3630
3631 schedule_work(&tp->reset_task);
3632 }
3633
3634 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
3635 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
3636 {
3637 u32 base = (u32) mapping & 0xffffffff;
3638
3639 return ((base > 0xffffdcc0) &&
3640 (base + len + 8 < base));
3641 }
3642
3643 /* Test for DMA addresses > 40-bit */
3644 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
3645 int len)
3646 {
3647 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
3648 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
3649 return (((u64) mapping + len) > DMA_40BIT_MASK);
3650 return 0;
3651 #else
3652 return 0;
3653 #endif
3654 }
3655
3656 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
3657
3658 /* Workaround 4GB and 40-bit hardware DMA bugs. */
3659 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
3660 u32 last_plus_one, u32 *start,
3661 u32 base_flags, u32 mss)
3662 {
3663 struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
3664 dma_addr_t new_addr = 0;
3665 u32 entry = *start;
3666 int i, ret = 0;
3667
3668 if (!new_skb) {
3669 ret = -1;
3670 } else {
3671 /* New SKB is guaranteed to be linear. */
3672 entry = *start;
3673 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
3674 PCI_DMA_TODEVICE);
3675 /* Make sure new skb does not cross any 4G boundaries.
3676 * Drop the packet if it does.
3677 */
3678 if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
3679 ret = -1;
3680 dev_kfree_skb(new_skb);
3681 new_skb = NULL;
3682 } else {
3683 tg3_set_txd(tp, entry, new_addr, new_skb->len,
3684 base_flags, 1 | (mss << 1));
3685 *start = NEXT_TX(entry);
3686 }
3687 }
3688
3689 /* Now clean up the sw ring entries. */
3690 i = 0;
3691 while (entry != last_plus_one) {
3692 int len;
3693
3694 if (i == 0)
3695 len = skb_headlen(skb);
3696 else
3697 len = skb_shinfo(skb)->frags[i-1].size;
3698 pci_unmap_single(tp->pdev,
3699 pci_unmap_addr(&tp->tx_buffers[entry], mapping),
3700 len, PCI_DMA_TODEVICE);
3701 if (i == 0) {
3702 tp->tx_buffers[entry].skb = new_skb;
3703 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
3704 } else {
3705 tp->tx_buffers[entry].skb = NULL;
3706 }
3707 entry = NEXT_TX(entry);
3708 i++;
3709 }
3710
3711 dev_kfree_skb(skb);
3712
3713 return ret;
3714 }
3715
3716 static void tg3_set_txd(struct tg3 *tp, int entry,
3717 dma_addr_t mapping, int len, u32 flags,
3718 u32 mss_and_is_end)
3719 {
3720 struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
3721 int is_end = (mss_and_is_end & 0x1);
3722 u32 mss = (mss_and_is_end >> 1);
3723 u32 vlan_tag = 0;
3724
3725 if (is_end)
3726 flags |= TXD_FLAG_END;
3727 if (flags & TXD_FLAG_VLAN) {
3728 vlan_tag = flags >> 16;
3729 flags &= 0xffff;
3730 }
3731 vlan_tag |= (mss << TXD_MSS_SHIFT);
3732
3733 txd->addr_hi = ((u64) mapping >> 32);
3734 txd->addr_lo = ((u64) mapping & 0xffffffff);
3735 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
3736 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
3737 }
3738
3739 /* hard_start_xmit for devices that don't have any bugs and
3740 * support TG3_FLG2_HW_TSO_2 only.
3741 */
3742 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
3743 {
3744 struct tg3 *tp = netdev_priv(dev);
3745 dma_addr_t mapping;
3746 u32 len, entry, base_flags, mss;
3747
3748 len = skb_headlen(skb);
3749
3750 /* We are running in BH disabled context with netif_tx_lock
3751 * and TX reclaim runs via tp->poll inside of a software
3752 * interrupt. Furthermore, IRQ processing runs lockless so we have
3753 * no IRQ context deadlocks to worry about either. Rejoice!
3754 */
3755 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3756 if (!netif_queue_stopped(dev)) {
3757 netif_stop_queue(dev);
3758
3759 /* This is a hard error, log it. */
3760 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
3761 "queue awake!\n", dev->name);
3762 }
3763 return NETDEV_TX_BUSY;
3764 }
3765
3766 entry = tp->tx_prod;
3767 base_flags = 0;
3768 #if TG3_TSO_SUPPORT != 0
3769 mss = 0;
3770 if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
3771 (mss = skb_shinfo(skb)->gso_size) != 0) {
3772 int tcp_opt_len, ip_tcp_len;
3773
3774 if (skb_header_cloned(skb) &&
3775 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
3776 dev_kfree_skb(skb);
3777 goto out_unlock;
3778 }
3779
3780 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
3781 mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
3782 else {
3783 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
3784 ip_tcp_len = (skb->nh.iph->ihl * 4) +
3785 sizeof(struct tcphdr);
3786
3787 skb->nh.iph->check = 0;
3788 skb->nh.iph->tot_len = htons(mss + ip_tcp_len +
3789 tcp_opt_len);
3790 mss |= (ip_tcp_len + tcp_opt_len) << 9;
3791 }
3792
3793 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
3794 TXD_FLAG_CPU_POST_DMA);
3795
3796 skb->h.th->check = 0;
3797
3798 }
3799 else if (skb->ip_summed == CHECKSUM_PARTIAL)
3800 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3801 #else
3802 mss = 0;
3803 if (skb->ip_summed == CHECKSUM_PARTIAL)
3804 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3805 #endif
3806 #if TG3_VLAN_TAG_USED
3807 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
3808 base_flags |= (TXD_FLAG_VLAN |
3809 (vlan_tx_tag_get(skb) << 16));
3810 #endif
3811
3812 /* Queue skb data, a.k.a. the main skb fragment. */
3813 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
3814
3815 tp->tx_buffers[entry].skb = skb;
3816 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3817
3818 tg3_set_txd(tp, entry, mapping, len, base_flags,
3819 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
3820
3821 entry = NEXT_TX(entry);
3822
3823 /* Now loop through additional data fragments, and queue them. */
3824 if (skb_shinfo(skb)->nr_frags > 0) {
3825 unsigned int i, last;
3826
3827 last = skb_shinfo(skb)->nr_frags - 1;
3828 for (i = 0; i <= last; i++) {
3829 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3830
3831 len = frag->size;
3832 mapping = pci_map_page(tp->pdev,
3833 frag->page,
3834 frag->page_offset,
3835 len, PCI_DMA_TODEVICE);
3836
3837 tp->tx_buffers[entry].skb = NULL;
3838 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3839
3840 tg3_set_txd(tp, entry, mapping, len,
3841 base_flags, (i == last) | (mss << 1));
3842
3843 entry = NEXT_TX(entry);
3844 }
3845 }
3846
3847 /* Packets are ready, update Tx producer idx local and on card. */
3848 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3849
3850 tp->tx_prod = entry;
3851 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
3852 netif_stop_queue(dev);
3853 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH)
3854 netif_wake_queue(tp->dev);
3855 }
3856
3857 out_unlock:
3858 mmiowb();
3859
3860 dev->trans_start = jiffies;
3861
3862 return NETDEV_TX_OK;
3863 }
3864
3865 #if TG3_TSO_SUPPORT != 0
3866 static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
3867
3868 /* Use GSO to workaround a rare TSO bug that may be triggered when the
3869 * TSO header is greater than 80 bytes.
3870 */
3871 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
3872 {
3873 struct sk_buff *segs, *nskb;
3874
3875 /* Estimate the number of fragments in the worst case */
3876 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
3877 netif_stop_queue(tp->dev);
3878 return NETDEV_TX_BUSY;
3879 }
3880
3881 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
3882 if (unlikely(IS_ERR(segs)))
3883 goto tg3_tso_bug_end;
3884
3885 do {
3886 nskb = segs;
3887 segs = segs->next;
3888 nskb->next = NULL;
3889 tg3_start_xmit_dma_bug(nskb, tp->dev);
3890 } while (segs);
3891
3892 tg3_tso_bug_end:
3893 dev_kfree_skb(skb);
3894
3895 return NETDEV_TX_OK;
3896 }
3897 #endif
3898
3899 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
3900 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
3901 */
3902 static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
3903 {
3904 struct tg3 *tp = netdev_priv(dev);
3905 dma_addr_t mapping;
3906 u32 len, entry, base_flags, mss;
3907 int would_hit_hwbug;
3908
3909 len = skb_headlen(skb);
3910
3911 /* We are running in BH disabled context with netif_tx_lock
3912 * and TX reclaim runs via tp->poll inside of a software
3913 * interrupt. Furthermore, IRQ processing runs lockless so we have
3914 * no IRQ context deadlocks to worry about either. Rejoice!
3915 */
3916 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3917 if (!netif_queue_stopped(dev)) {
3918 netif_stop_queue(dev);
3919
3920 /* This is a hard error, log it. */
3921 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
3922 "queue awake!\n", dev->name);
3923 }
3924 return NETDEV_TX_BUSY;
3925 }
3926
3927 entry = tp->tx_prod;
3928 base_flags = 0;
3929 if (skb->ip_summed == CHECKSUM_PARTIAL)
3930 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3931 #if TG3_TSO_SUPPORT != 0
3932 mss = 0;
3933 if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
3934 (mss = skb_shinfo(skb)->gso_size) != 0) {
3935 int tcp_opt_len, ip_tcp_len, hdr_len;
3936
3937 if (skb_header_cloned(skb) &&
3938 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
3939 dev_kfree_skb(skb);
3940 goto out_unlock;
3941 }
3942
3943 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
3944 ip_tcp_len = (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
3945
3946 hdr_len = ip_tcp_len + tcp_opt_len;
3947 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
3948 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_1_BUG))
3949 return (tg3_tso_bug(tp, skb));
3950
3951 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
3952 TXD_FLAG_CPU_POST_DMA);
3953
3954 skb->nh.iph->check = 0;
3955 skb->nh.iph->tot_len = htons(mss + hdr_len);
3956 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
3957 skb->h.th->check = 0;
3958 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
3959 }
3960 else {
3961 skb->h.th->check =
3962 ~csum_tcpudp_magic(skb->nh.iph->saddr,
3963 skb->nh.iph->daddr,
3964 0, IPPROTO_TCP, 0);
3965 }
3966
3967 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
3968 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
3969 if (tcp_opt_len || skb->nh.iph->ihl > 5) {
3970 int tsflags;
3971
3972 tsflags = ((skb->nh.iph->ihl - 5) +
3973 (tcp_opt_len >> 2));
3974 mss |= (tsflags << 11);
3975 }
3976 } else {
3977 if (tcp_opt_len || skb->nh.iph->ihl > 5) {
3978 int tsflags;
3979
3980 tsflags = ((skb->nh.iph->ihl - 5) +
3981 (tcp_opt_len >> 2));
3982 base_flags |= tsflags << 12;
3983 }
3984 }
3985 }
3986 #else
3987 mss = 0;
3988 #endif
3989 #if TG3_VLAN_TAG_USED
3990 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
3991 base_flags |= (TXD_FLAG_VLAN |
3992 (vlan_tx_tag_get(skb) << 16));
3993 #endif
3994
3995 /* Queue skb data, a.k.a. the main skb fragment. */
3996 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
3997
3998 tp->tx_buffers[entry].skb = skb;
3999 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4000
4001 would_hit_hwbug = 0;
4002
4003 if (tg3_4g_overflow_test(mapping, len))
4004 would_hit_hwbug = 1;
4005
4006 tg3_set_txd(tp, entry, mapping, len, base_flags,
4007 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4008
4009 entry = NEXT_TX(entry);
4010
4011 /* Now loop through additional data fragments, and queue them. */
4012 if (skb_shinfo(skb)->nr_frags > 0) {
4013 unsigned int i, last;
4014
4015 last = skb_shinfo(skb)->nr_frags - 1;
4016 for (i = 0; i <= last; i++) {
4017 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4018
4019 len = frag->size;
4020 mapping = pci_map_page(tp->pdev,
4021 frag->page,
4022 frag->page_offset,
4023 len, PCI_DMA_TODEVICE);
4024
4025 tp->tx_buffers[entry].skb = NULL;
4026 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4027
4028 if (tg3_4g_overflow_test(mapping, len))
4029 would_hit_hwbug = 1;
4030
4031 if (tg3_40bit_overflow_test(tp, mapping, len))
4032 would_hit_hwbug = 1;
4033
4034 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
4035 tg3_set_txd(tp, entry, mapping, len,
4036 base_flags, (i == last)|(mss << 1));
4037 else
4038 tg3_set_txd(tp, entry, mapping, len,
4039 base_flags, (i == last));
4040
4041 entry = NEXT_TX(entry);
4042 }
4043 }
4044
4045 if (would_hit_hwbug) {
4046 u32 last_plus_one = entry;
4047 u32 start;
4048
4049 start = entry - 1 - skb_shinfo(skb)->nr_frags;
4050 start &= (TG3_TX_RING_SIZE - 1);
4051
4052 /* If the workaround fails due to memory/mapping
4053 * failure, silently drop this packet.
4054 */
4055 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
4056 &start, base_flags, mss))
4057 goto out_unlock;
4058
4059 entry = start;
4060 }
4061
4062 /* Packets are ready, update Tx producer idx local and on card. */
4063 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4064
4065 tp->tx_prod = entry;
4066 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4067 netif_stop_queue(dev);
4068 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH)
4069 netif_wake_queue(tp->dev);
4070 }
4071
4072 out_unlock:
4073 mmiowb();
4074
4075 dev->trans_start = jiffies;
4076
4077 return NETDEV_TX_OK;
4078 }
4079
4080 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
4081 int new_mtu)
4082 {
4083 dev->mtu = new_mtu;
4084
4085 if (new_mtu > ETH_DATA_LEN) {
4086 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4087 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
4088 ethtool_op_set_tso(dev, 0);
4089 }
4090 else
4091 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
4092 } else {
4093 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4094 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
4095 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
4096 }
4097 }
4098
4099 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
4100 {
4101 struct tg3 *tp = netdev_priv(dev);
4102 int err;
4103
4104 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
4105 return -EINVAL;
4106
4107 if (!netif_running(dev)) {
4108 /* We'll just catch it later when the
4109 * device is up'd.
4110 */
4111 tg3_set_mtu(dev, tp, new_mtu);
4112 return 0;
4113 }
4114
4115 tg3_netif_stop(tp);
4116
4117 tg3_full_lock(tp, 1);
4118
4119 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4120
4121 tg3_set_mtu(dev, tp, new_mtu);
4122
4123 err = tg3_restart_hw(tp, 0);
4124
4125 if (!err)
4126 tg3_netif_start(tp);
4127
4128 tg3_full_unlock(tp);
4129
4130 return err;
4131 }
4132
4133 /* Free up pending packets in all rx/tx rings.
4134 *
4135 * The chip has been shut down and the driver detached from
4136 * the networking, so no interrupts or new tx packets will
4137 * end up in the driver. tp->{tx,}lock is not held and we are not
4138 * in an interrupt context and thus may sleep.
4139 */
4140 static void tg3_free_rings(struct tg3 *tp)
4141 {
4142 struct ring_info *rxp;
4143 int i;
4144
4145 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4146 rxp = &tp->rx_std_buffers[i];
4147
4148 if (rxp->skb == NULL)
4149 continue;
4150 pci_unmap_single(tp->pdev,
4151 pci_unmap_addr(rxp, mapping),
4152 tp->rx_pkt_buf_sz - tp->rx_offset,
4153 PCI_DMA_FROMDEVICE);
4154 dev_kfree_skb_any(rxp->skb);
4155 rxp->skb = NULL;
4156 }
4157
4158 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4159 rxp = &tp->rx_jumbo_buffers[i];
4160
4161 if (rxp->skb == NULL)
4162 continue;
4163 pci_unmap_single(tp->pdev,
4164 pci_unmap_addr(rxp, mapping),
4165 RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
4166 PCI_DMA_FROMDEVICE);
4167 dev_kfree_skb_any(rxp->skb);
4168 rxp->skb = NULL;
4169 }
4170
4171 for (i = 0; i < TG3_TX_RING_SIZE; ) {
4172 struct tx_ring_info *txp;
4173 struct sk_buff *skb;
4174 int j;
4175
4176 txp = &tp->tx_buffers[i];
4177 skb = txp->skb;
4178
4179 if (skb == NULL) {
4180 i++;
4181 continue;
4182 }
4183
4184 pci_unmap_single(tp->pdev,
4185 pci_unmap_addr(txp, mapping),
4186 skb_headlen(skb),
4187 PCI_DMA_TODEVICE);
4188 txp->skb = NULL;
4189
4190 i++;
4191
4192 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
4193 txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
4194 pci_unmap_page(tp->pdev,
4195 pci_unmap_addr(txp, mapping),
4196 skb_shinfo(skb)->frags[j].size,
4197 PCI_DMA_TODEVICE);
4198 i++;
4199 }
4200
4201 dev_kfree_skb_any(skb);
4202 }
4203 }
4204
4205 /* Initialize tx/rx rings for packet processing.
4206 *
4207 * The chip has been shut down and the driver detached from
4208 * the networking, so no interrupts or new tx packets will
4209 * end up in the driver. tp->{tx,}lock are held and thus
4210 * we may not sleep.
4211 */
4212 static int tg3_init_rings(struct tg3 *tp)
4213 {
4214 u32 i;
4215
4216 /* Free up all the SKBs. */
4217 tg3_free_rings(tp);
4218
4219 /* Zero out all descriptors. */
4220 memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
4221 memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
4222 memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
4223 memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
4224
4225 tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
4226 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
4227 (tp->dev->mtu > ETH_DATA_LEN))
4228 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
4229
4230 /* Initialize invariants of the rings, we only set this
4231 * stuff once. This works because the card does not
4232 * write into the rx buffer posting rings.
4233 */
4234 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4235 struct tg3_rx_buffer_desc *rxd;
4236
4237 rxd = &tp->rx_std[i];
4238 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
4239 << RXD_LEN_SHIFT;
4240 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
4241 rxd->opaque = (RXD_OPAQUE_RING_STD |
4242 (i << RXD_OPAQUE_INDEX_SHIFT));
4243 }
4244
4245 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4246 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4247 struct tg3_rx_buffer_desc *rxd;
4248
4249 rxd = &tp->rx_jumbo[i];
4250 rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
4251 << RXD_LEN_SHIFT;
4252 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
4253 RXD_FLAG_JUMBO;
4254 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
4255 (i << RXD_OPAQUE_INDEX_SHIFT));
4256 }
4257 }
4258
4259 /* Now allocate fresh SKBs for each rx ring. */
4260 for (i = 0; i < tp->rx_pending; i++) {
4261 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
4262 printk(KERN_WARNING PFX
4263 "%s: Using a smaller RX standard ring, "
4264 "only %d out of %d buffers were allocated "
4265 "successfully.\n",
4266 tp->dev->name, i, tp->rx_pending);
4267 if (i == 0)
4268 return -ENOMEM;
4269 tp->rx_pending = i;
4270 break;
4271 }
4272 }
4273
4274 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4275 for (i = 0; i < tp->rx_jumbo_pending; i++) {
4276 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
4277 -1, i) < 0) {
4278 printk(KERN_WARNING PFX
4279 "%s: Using a smaller RX jumbo ring, "
4280 "only %d out of %d buffers were "
4281 "allocated successfully.\n",
4282 tp->dev->name, i, tp->rx_jumbo_pending);
4283 if (i == 0) {
4284 tg3_free_rings(tp);
4285 return -ENOMEM;
4286 }
4287 tp->rx_jumbo_pending = i;
4288 break;
4289 }
4290 }
4291 }
4292 return 0;
4293 }
4294
4295 /*
4296 * Must not be invoked with interrupt sources disabled and
4297 * the hardware shutdown down.
4298 */
4299 static void tg3_free_consistent(struct tg3 *tp)
4300 {
4301 kfree(tp->rx_std_buffers);
4302 tp->rx_std_buffers = NULL;
4303 if (tp->rx_std) {
4304 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
4305 tp->rx_std, tp->rx_std_mapping);
4306 tp->rx_std = NULL;
4307 }
4308 if (tp->rx_jumbo) {
4309 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4310 tp->rx_jumbo, tp->rx_jumbo_mapping);
4311 tp->rx_jumbo = NULL;
4312 }
4313 if (tp->rx_rcb) {
4314 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4315 tp->rx_rcb, tp->rx_rcb_mapping);
4316 tp->rx_rcb = NULL;
4317 }
4318 if (tp->tx_ring) {
4319 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
4320 tp->tx_ring, tp->tx_desc_mapping);
4321 tp->tx_ring = NULL;
4322 }
4323 if (tp->hw_status) {
4324 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
4325 tp->hw_status, tp->status_mapping);
4326 tp->hw_status = NULL;
4327 }
4328 if (tp->hw_stats) {
4329 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
4330 tp->hw_stats, tp->stats_mapping);
4331 tp->hw_stats = NULL;
4332 }
4333 }
4334
4335 /*
4336 * Must not be invoked with interrupt sources disabled and
4337 * the hardware shutdown down. Can sleep.
4338 */
4339 static int tg3_alloc_consistent(struct tg3 *tp)
4340 {
4341 tp->rx_std_buffers = kmalloc((sizeof(struct ring_info) *
4342 (TG3_RX_RING_SIZE +
4343 TG3_RX_JUMBO_RING_SIZE)) +
4344 (sizeof(struct tx_ring_info) *
4345 TG3_TX_RING_SIZE),
4346 GFP_KERNEL);
4347 if (!tp->rx_std_buffers)
4348 return -ENOMEM;
4349
4350 memset(tp->rx_std_buffers, 0,
4351 (sizeof(struct ring_info) *
4352 (TG3_RX_RING_SIZE +
4353 TG3_RX_JUMBO_RING_SIZE)) +
4354 (sizeof(struct tx_ring_info) *
4355 TG3_TX_RING_SIZE));
4356
4357 tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
4358 tp->tx_buffers = (struct tx_ring_info *)
4359 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
4360
4361 tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
4362 &tp->rx_std_mapping);
4363 if (!tp->rx_std)
4364 goto err_out;
4365
4366 tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4367 &tp->rx_jumbo_mapping);
4368
4369 if (!tp->rx_jumbo)
4370 goto err_out;
4371
4372 tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4373 &tp->rx_rcb_mapping);
4374 if (!tp->rx_rcb)
4375 goto err_out;
4376
4377 tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
4378 &tp->tx_desc_mapping);
4379 if (!tp->tx_ring)
4380 goto err_out;
4381
4382 tp->hw_status = pci_alloc_consistent(tp->pdev,
4383 TG3_HW_STATUS_SIZE,
4384 &tp->status_mapping);
4385 if (!tp->hw_status)
4386 goto err_out;
4387
4388 tp->hw_stats = pci_alloc_consistent(tp->pdev,
4389 sizeof(struct tg3_hw_stats),
4390 &tp->stats_mapping);
4391 if (!tp->hw_stats)
4392 goto err_out;
4393
4394 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4395 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4396
4397 return 0;
4398
4399 err_out:
4400 tg3_free_consistent(tp);
4401 return -ENOMEM;
4402 }
4403
4404 #define MAX_WAIT_CNT 1000
4405
4406 /* To stop a block, clear the enable bit and poll till it
4407 * clears. tp->lock is held.
4408 */
4409 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
4410 {
4411 unsigned int i;
4412 u32 val;
4413
4414 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
4415 switch (ofs) {
4416 case RCVLSC_MODE:
4417 case DMAC_MODE:
4418 case MBFREE_MODE:
4419 case BUFMGR_MODE:
4420 case MEMARB_MODE:
4421 /* We can't enable/disable these bits of the
4422 * 5705/5750, just say success.
4423 */
4424 return 0;
4425
4426 default:
4427 break;
4428 };
4429 }
4430
4431 val = tr32(ofs);
4432 val &= ~enable_bit;
4433 tw32_f(ofs, val);
4434
4435 for (i = 0; i < MAX_WAIT_CNT; i++) {
4436 udelay(100);
4437 val = tr32(ofs);
4438 if ((val & enable_bit) == 0)
4439 break;
4440 }
4441
4442 if (i == MAX_WAIT_CNT && !silent) {
4443 printk(KERN_ERR PFX "tg3_stop_block timed out, "
4444 "ofs=%lx enable_bit=%x\n",
4445 ofs, enable_bit);
4446 return -ENODEV;
4447 }
4448
4449 return 0;
4450 }
4451
4452 /* tp->lock is held. */
4453 static int tg3_abort_hw(struct tg3 *tp, int silent)
4454 {
4455 int i, err;
4456
4457 tg3_disable_ints(tp);
4458
4459 tp->rx_mode &= ~RX_MODE_ENABLE;
4460 tw32_f(MAC_RX_MODE, tp->rx_mode);
4461 udelay(10);
4462
4463 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
4464 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
4465 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
4466 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
4467 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
4468 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
4469
4470 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
4471 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
4472 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
4473 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
4474 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
4475 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
4476 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
4477
4478 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
4479 tw32_f(MAC_MODE, tp->mac_mode);
4480 udelay(40);
4481
4482 tp->tx_mode &= ~TX_MODE_ENABLE;
4483 tw32_f(MAC_TX_MODE, tp->tx_mode);
4484
4485 for (i = 0; i < MAX_WAIT_CNT; i++) {
4486 udelay(100);
4487 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
4488 break;
4489 }
4490 if (i >= MAX_WAIT_CNT) {
4491 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
4492 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
4493 tp->dev->name, tr32(MAC_TX_MODE));
4494 err |= -ENODEV;
4495 }
4496
4497 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
4498 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
4499 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
4500
4501 tw32(FTQ_RESET, 0xffffffff);
4502 tw32(FTQ_RESET, 0x00000000);
4503
4504 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
4505 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
4506
4507 if (tp->hw_status)
4508 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4509 if (tp->hw_stats)
4510 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4511
4512 return err;
4513 }
4514
4515 /* tp->lock is held. */
4516 static int tg3_nvram_lock(struct tg3 *tp)
4517 {
4518 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4519 int i;
4520
4521 if (tp->nvram_lock_cnt == 0) {
4522 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
4523 for (i = 0; i < 8000; i++) {
4524 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
4525 break;
4526 udelay(20);
4527 }
4528 if (i == 8000) {
4529 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
4530 return -ENODEV;
4531 }
4532 }
4533 tp->nvram_lock_cnt++;
4534 }
4535 return 0;
4536 }
4537
4538 /* tp->lock is held. */
4539 static void tg3_nvram_unlock(struct tg3 *tp)
4540 {
4541 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4542 if (tp->nvram_lock_cnt > 0)
4543 tp->nvram_lock_cnt--;
4544 if (tp->nvram_lock_cnt == 0)
4545 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
4546 }
4547 }
4548
4549 /* tp->lock is held. */
4550 static void tg3_enable_nvram_access(struct tg3 *tp)
4551 {
4552 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4553 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4554 u32 nvaccess = tr32(NVRAM_ACCESS);
4555
4556 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
4557 }
4558 }
4559
4560 /* tp->lock is held. */
4561 static void tg3_disable_nvram_access(struct tg3 *tp)
4562 {
4563 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4564 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4565 u32 nvaccess = tr32(NVRAM_ACCESS);
4566
4567 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
4568 }
4569 }
4570
4571 /* tp->lock is held. */
4572 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
4573 {
4574 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
4575 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
4576
4577 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4578 switch (kind) {
4579 case RESET_KIND_INIT:
4580 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4581 DRV_STATE_START);
4582 break;
4583
4584 case RESET_KIND_SHUTDOWN:
4585 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4586 DRV_STATE_UNLOAD);
4587 break;
4588
4589 case RESET_KIND_SUSPEND:
4590 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4591 DRV_STATE_SUSPEND);
4592 break;
4593
4594 default:
4595 break;
4596 };
4597 }
4598 }
4599
4600 /* tp->lock is held. */
4601 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
4602 {
4603 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4604 switch (kind) {
4605 case RESET_KIND_INIT:
4606 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4607 DRV_STATE_START_DONE);
4608 break;
4609
4610 case RESET_KIND_SHUTDOWN:
4611 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4612 DRV_STATE_UNLOAD_DONE);
4613 break;
4614
4615 default:
4616 break;
4617 };
4618 }
4619 }
4620
4621 /* tp->lock is held. */
4622 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
4623 {
4624 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4625 switch (kind) {
4626 case RESET_KIND_INIT:
4627 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4628 DRV_STATE_START);
4629 break;
4630
4631 case RESET_KIND_SHUTDOWN:
4632 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4633 DRV_STATE_UNLOAD);
4634 break;
4635
4636 case RESET_KIND_SUSPEND:
4637 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4638 DRV_STATE_SUSPEND);
4639 break;
4640
4641 default:
4642 break;
4643 };
4644 }
4645 }
4646
4647 static void tg3_stop_fw(struct tg3 *);
4648
4649 /* tp->lock is held. */
4650 static int tg3_chip_reset(struct tg3 *tp)
4651 {
4652 u32 val;
4653 void (*write_op)(struct tg3 *, u32, u32);
4654 int i;
4655
4656 tg3_nvram_lock(tp);
4657
4658 /* No matching tg3_nvram_unlock() after this because
4659 * chip reset below will undo the nvram lock.
4660 */
4661 tp->nvram_lock_cnt = 0;
4662
4663 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
4664 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
4665 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
4666 tw32(GRC_FASTBOOT_PC, 0);
4667
4668 /*
4669 * We must avoid the readl() that normally takes place.
4670 * It locks machines, causes machine checks, and other
4671 * fun things. So, temporarily disable the 5701
4672 * hardware workaround, while we do the reset.
4673 */
4674 write_op = tp->write32;
4675 if (write_op == tg3_write_flush_reg32)
4676 tp->write32 = tg3_write32;
4677
4678 /* do the reset */
4679 val = GRC_MISC_CFG_CORECLK_RESET;
4680
4681 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4682 if (tr32(0x7e2c) == 0x60) {
4683 tw32(0x7e2c, 0x20);
4684 }
4685 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4686 tw32(GRC_MISC_CFG, (1 << 29));
4687 val |= (1 << 29);
4688 }
4689 }
4690
4691 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4692 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
4693 tw32(GRC_MISC_CFG, val);
4694
4695 /* restore 5701 hardware bug workaround write method */
4696 tp->write32 = write_op;
4697
4698 /* Unfortunately, we have to delay before the PCI read back.
4699 * Some 575X chips even will not respond to a PCI cfg access
4700 * when the reset command is given to the chip.
4701 *
4702 * How do these hardware designers expect things to work
4703 * properly if the PCI write is posted for a long period
4704 * of time? It is always necessary to have some method by
4705 * which a register read back can occur to push the write
4706 * out which does the reset.
4707 *
4708 * For most tg3 variants the trick below was working.
4709 * Ho hum...
4710 */
4711 udelay(120);
4712
4713 /* Flush PCI posted writes. The normal MMIO registers
4714 * are inaccessible at this time so this is the only
4715 * way to make this reliably (actually, this is no longer
4716 * the case, see above). I tried to use indirect
4717 * register read/write but this upset some 5701 variants.
4718 */
4719 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
4720
4721 udelay(120);
4722
4723 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4724 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
4725 int i;
4726 u32 cfg_val;
4727
4728 /* Wait for link training to complete. */
4729 for (i = 0; i < 5000; i++)
4730 udelay(100);
4731
4732 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
4733 pci_write_config_dword(tp->pdev, 0xc4,
4734 cfg_val | (1 << 15));
4735 }
4736 /* Set PCIE max payload size and clear error status. */
4737 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
4738 }
4739
4740 /* Re-enable indirect register accesses. */
4741 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
4742 tp->misc_host_ctrl);
4743
4744 /* Set MAX PCI retry to zero. */
4745 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4746 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
4747 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
4748 val |= PCISTATE_RETRY_SAME_DMA;
4749 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
4750
4751 pci_restore_state(tp->pdev);
4752
4753 /* Make sure PCI-X relaxed ordering bit is clear. */
4754 pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
4755 val &= ~PCIX_CAPS_RELAXED_ORDERING;
4756 pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
4757
4758 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4759 u32 val;
4760
4761 /* Chip reset on 5780 will reset MSI enable bit,
4762 * so need to restore it.
4763 */
4764 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
4765 u16 ctrl;
4766
4767 pci_read_config_word(tp->pdev,
4768 tp->msi_cap + PCI_MSI_FLAGS,
4769 &ctrl);
4770 pci_write_config_word(tp->pdev,
4771 tp->msi_cap + PCI_MSI_FLAGS,
4772 ctrl | PCI_MSI_FLAGS_ENABLE);
4773 val = tr32(MSGINT_MODE);
4774 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
4775 }
4776
4777 val = tr32(MEMARB_MODE);
4778 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
4779
4780 } else
4781 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
4782
4783 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
4784 tg3_stop_fw(tp);
4785 tw32(0x5000, 0x400);
4786 }
4787
4788 tw32(GRC_MODE, tp->grc_mode);
4789
4790 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
4791 u32 val = tr32(0xc4);
4792
4793 tw32(0xc4, val | (1 << 15));
4794 }
4795
4796 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
4797 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
4798 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
4799 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
4800 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
4801 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
4802 }
4803
4804 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4805 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
4806 tw32_f(MAC_MODE, tp->mac_mode);
4807 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4808 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
4809 tw32_f(MAC_MODE, tp->mac_mode);
4810 } else
4811 tw32_f(MAC_MODE, 0);
4812 udelay(40);
4813
4814 /* Wait for firmware initialization to complete. */
4815 for (i = 0; i < 100000; i++) {
4816 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
4817 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4818 break;
4819 udelay(10);
4820 }
4821
4822 /* Chip might not be fitted with firmare. Some Sun onboard
4823 * parts are configured like that. So don't signal the timeout
4824 * of the above loop as an error, but do report the lack of
4825 * running firmware once.
4826 */
4827 if (i >= 100000 &&
4828 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
4829 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
4830
4831 printk(KERN_INFO PFX "%s: No firmware running.\n",
4832 tp->dev->name);
4833 }
4834
4835 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
4836 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4837 u32 val = tr32(0x7c00);
4838
4839 tw32(0x7c00, val | (1 << 25));
4840 }
4841
4842 /* Reprobe ASF enable state. */
4843 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
4844 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
4845 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
4846 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
4847 u32 nic_cfg;
4848
4849 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
4850 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
4851 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
4852 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
4853 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
4854 }
4855 }
4856
4857 return 0;
4858 }
4859
4860 /* tp->lock is held. */
4861 static void tg3_stop_fw(struct tg3 *tp)
4862 {
4863 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4864 u32 val;
4865 int i;
4866
4867 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4868 val = tr32(GRC_RX_CPU_EVENT);
4869 val |= (1 << 14);
4870 tw32(GRC_RX_CPU_EVENT, val);
4871
4872 /* Wait for RX cpu to ACK the event. */
4873 for (i = 0; i < 100; i++) {
4874 if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
4875 break;
4876 udelay(1);
4877 }
4878 }
4879 }
4880
4881 /* tp->lock is held. */
4882 static int tg3_halt(struct tg3 *tp, int kind, int silent)
4883 {
4884 int err;
4885
4886 tg3_stop_fw(tp);
4887
4888 tg3_write_sig_pre_reset(tp, kind);
4889
4890 tg3_abort_hw(tp, silent);
4891 err = tg3_chip_reset(tp);
4892
4893 tg3_write_sig_legacy(tp, kind);
4894 tg3_write_sig_post_reset(tp, kind);
4895
4896 if (err)
4897 return err;
4898
4899 return 0;
4900 }
4901
4902 #define TG3_FW_RELEASE_MAJOR 0x0
4903 #define TG3_FW_RELASE_MINOR 0x0
4904 #define TG3_FW_RELEASE_FIX 0x0
4905 #define TG3_FW_START_ADDR 0x08000000
4906 #define TG3_FW_TEXT_ADDR 0x08000000
4907 #define TG3_FW_TEXT_LEN 0x9c0
4908 #define TG3_FW_RODATA_ADDR 0x080009c0
4909 #define TG3_FW_RODATA_LEN 0x60
4910 #define TG3_FW_DATA_ADDR 0x08000a40
4911 #define TG3_FW_DATA_LEN 0x20
4912 #define TG3_FW_SBSS_ADDR 0x08000a60
4913 #define TG3_FW_SBSS_LEN 0xc
4914 #define TG3_FW_BSS_ADDR 0x08000a70
4915 #define TG3_FW_BSS_LEN 0x10
4916
4917 static const u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
4918 0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
4919 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
4920 0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
4921 0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
4922 0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
4923 0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
4924 0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
4925 0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
4926 0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
4927 0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
4928 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
4929 0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
4930 0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
4931 0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
4932 0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
4933 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
4934 0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
4935 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
4936 0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
4937 0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
4938 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
4939 0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
4940 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
4941 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4942 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4943 0, 0, 0, 0, 0, 0,
4944 0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
4945 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4946 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4947 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4948 0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
4949 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
4950 0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
4951 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
4952 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4953 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4954 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
4955 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4956 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4957 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4958 0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
4959 0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
4960 0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
4961 0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
4962 0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
4963 0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
4964 0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
4965 0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
4966 0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
4967 0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
4968 0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
4969 0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
4970 0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
4971 0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
4972 0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
4973 0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
4974 0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
4975 0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
4976 0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
4977 0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
4978 0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
4979 0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
4980 0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
4981 0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
4982 0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
4983 0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
4984 0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
4985 0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
4986 0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
4987 0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
4988 0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
4989 0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
4990 0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
4991 0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
4992 0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
4993 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
4994 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
4995 0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
4996 0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
4997 0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
4998 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
4999 0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
5000 0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
5001 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
5002 0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
5003 0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
5004 0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
5005 0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
5006 0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
5007 0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
5008 0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
5009 };
5010
5011 static const u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
5012 0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
5013 0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
5014 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5015 0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
5016 0x00000000
5017 };
5018
5019 #if 0 /* All zeros, don't eat up space with it. */
5020 u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
5021 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5022 0x00000000, 0x00000000, 0x00000000, 0x00000000
5023 };
5024 #endif
5025
5026 #define RX_CPU_SCRATCH_BASE 0x30000
5027 #define RX_CPU_SCRATCH_SIZE 0x04000
5028 #define TX_CPU_SCRATCH_BASE 0x34000
5029 #define TX_CPU_SCRATCH_SIZE 0x04000
5030
5031 /* tp->lock is held. */
5032 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
5033 {
5034 int i;
5035
5036 BUG_ON(offset == TX_CPU_BASE &&
5037 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
5038
5039 if (offset == RX_CPU_BASE) {
5040 for (i = 0; i < 10000; i++) {
5041 tw32(offset + CPU_STATE, 0xffffffff);
5042 tw32(offset + CPU_MODE, CPU_MODE_HALT);
5043 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5044 break;
5045 }
5046
5047 tw32(offset + CPU_STATE, 0xffffffff);
5048 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
5049 udelay(10);
5050 } else {
5051 for (i = 0; i < 10000; i++) {
5052 tw32(offset + CPU_STATE, 0xffffffff);
5053 tw32(offset + CPU_MODE, CPU_MODE_HALT);
5054 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5055 break;
5056 }
5057 }
5058
5059 if (i >= 10000) {
5060 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
5061 "and %s CPU\n",
5062 tp->dev->name,
5063 (offset == RX_CPU_BASE ? "RX" : "TX"));
5064 return -ENODEV;
5065 }
5066
5067 /* Clear firmware's nvram arbitration. */
5068 if (tp->tg3_flags & TG3_FLAG_NVRAM)
5069 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
5070 return 0;
5071 }
5072
5073 struct fw_info {
5074 unsigned int text_base;
5075 unsigned int text_len;
5076 const u32 *text_data;
5077 unsigned int rodata_base;
5078 unsigned int rodata_len;
5079 const u32 *rodata_data;
5080 unsigned int data_base;
5081 unsigned int data_len;
5082 const u32 *data_data;
5083 };
5084
5085 /* tp->lock is held. */
5086 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
5087 int cpu_scratch_size, struct fw_info *info)
5088 {
5089 int err, lock_err, i;
5090 void (*write_op)(struct tg3 *, u32, u32);
5091
5092 if (cpu_base == TX_CPU_BASE &&
5093 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5094 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
5095 "TX cpu firmware on %s which is 5705.\n",
5096 tp->dev->name);
5097 return -EINVAL;
5098 }
5099
5100 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5101 write_op = tg3_write_mem;
5102 else
5103 write_op = tg3_write_indirect_reg32;
5104
5105 /* It is possible that bootcode is still loading at this point.
5106 * Get the nvram lock first before halting the cpu.
5107 */
5108 lock_err = tg3_nvram_lock(tp);
5109 err = tg3_halt_cpu(tp, cpu_base);
5110 if (!lock_err)
5111 tg3_nvram_unlock(tp);
5112 if (err)
5113 goto out;
5114
5115 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
5116 write_op(tp, cpu_scratch_base + i, 0);
5117 tw32(cpu_base + CPU_STATE, 0xffffffff);
5118 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
5119 for (i = 0; i < (info->text_len / sizeof(u32)); i++)
5120 write_op(tp, (cpu_scratch_base +
5121 (info->text_base & 0xffff) +
5122 (i * sizeof(u32))),
5123 (info->text_data ?
5124 info->text_data[i] : 0));
5125 for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
5126 write_op(tp, (cpu_scratch_base +
5127 (info->rodata_base & 0xffff) +
5128 (i * sizeof(u32))),
5129 (info->rodata_data ?
5130 info->rodata_data[i] : 0));
5131 for (i = 0; i < (info->data_len / sizeof(u32)); i++)
5132 write_op(tp, (cpu_scratch_base +
5133 (info->data_base & 0xffff) +
5134 (i * sizeof(u32))),
5135 (info->data_data ?
5136 info->data_data[i] : 0));
5137
5138 err = 0;
5139
5140 out:
5141 return err;
5142 }
5143
5144 /* tp->lock is held. */
5145 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
5146 {
5147 struct fw_info info;
5148 int err, i;
5149
5150 info.text_base = TG3_FW_TEXT_ADDR;
5151 info.text_len = TG3_FW_TEXT_LEN;
5152 info.text_data = &tg3FwText[0];
5153 info.rodata_base = TG3_FW_RODATA_ADDR;
5154 info.rodata_len = TG3_FW_RODATA_LEN;
5155 info.rodata_data = &tg3FwRodata[0];
5156 info.data_base = TG3_FW_DATA_ADDR;
5157 info.data_len = TG3_FW_DATA_LEN;
5158 info.data_data = NULL;
5159
5160 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
5161 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
5162 &info);
5163 if (err)
5164 return err;
5165
5166 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
5167 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
5168 &info);
5169 if (err)
5170 return err;
5171
5172 /* Now startup only the RX cpu. */
5173 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5174 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
5175
5176 for (i = 0; i < 5; i++) {
5177 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
5178 break;
5179 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5180 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
5181 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
5182 udelay(1000);
5183 }
5184 if (i >= 5) {
5185 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
5186 "to set RX CPU PC, is %08x should be %08x\n",
5187 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
5188 TG3_FW_TEXT_ADDR);
5189 return -ENODEV;
5190 }
5191 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5192 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
5193
5194 return 0;
5195 }
5196
5197 #if TG3_TSO_SUPPORT != 0
5198
5199 #define TG3_TSO_FW_RELEASE_MAJOR 0x1
5200 #define TG3_TSO_FW_RELASE_MINOR 0x6
5201 #define TG3_TSO_FW_RELEASE_FIX 0x0
5202 #define TG3_TSO_FW_START_ADDR 0x08000000
5203 #define TG3_TSO_FW_TEXT_ADDR 0x08000000
5204 #define TG3_TSO_FW_TEXT_LEN 0x1aa0
5205 #define TG3_TSO_FW_RODATA_ADDR 0x08001aa0
5206 #define TG3_TSO_FW_RODATA_LEN 0x60
5207 #define TG3_TSO_FW_DATA_ADDR 0x08001b20
5208 #define TG3_TSO_FW_DATA_LEN 0x30
5209 #define TG3_TSO_FW_SBSS_ADDR 0x08001b50
5210 #define TG3_TSO_FW_SBSS_LEN 0x2c
5211 #define TG3_TSO_FW_BSS_ADDR 0x08001b80
5212 #define TG3_TSO_FW_BSS_LEN 0x894
5213
5214 static const u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
5215 0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
5216 0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
5217 0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5218 0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
5219 0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
5220 0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
5221 0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
5222 0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
5223 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
5224 0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
5225 0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
5226 0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
5227 0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
5228 0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
5229 0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
5230 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
5231 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
5232 0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
5233 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5234 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
5235 0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
5236 0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
5237 0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
5238 0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
5239 0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
5240 0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
5241 0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
5242 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
5243 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
5244 0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5245 0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
5246 0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
5247 0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
5248 0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
5249 0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
5250 0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
5251 0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
5252 0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
5253 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5254 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
5255 0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
5256 0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
5257 0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
5258 0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
5259 0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
5260 0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
5261 0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
5262 0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5263 0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
5264 0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5265 0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
5266 0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
5267 0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
5268 0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
5269 0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
5270 0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
5271 0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
5272 0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
5273 0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
5274 0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
5275 0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
5276 0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
5277 0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
5278 0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
5279 0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
5280 0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
5281 0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
5282 0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
5283 0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
5284 0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
5285 0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
5286 0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
5287 0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
5288 0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
5289 0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
5290 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
5291 0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
5292 0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
5293 0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
5294 0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
5295 0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
5296 0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
5297 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
5298 0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
5299 0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
5300 0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
5301 0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
5302 0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
5303 0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
5304 0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
5305 0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
5306 0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
5307 0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
5308 0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
5309 0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
5310 0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
5311 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
5312 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
5313 0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
5314 0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
5315 0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
5316 0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
5317 0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
5318 0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
5319 0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
5320 0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
5321 0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
5322 0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
5323 0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
5324 0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
5325 0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
5326 0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
5327 0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
5328 0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
5329 0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
5330 0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
5331 0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
5332 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
5333 0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
5334 0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
5335 0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
5336 0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
5337 0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
5338 0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
5339 0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
5340 0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
5341 0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
5342 0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
5343 0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
5344 0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
5345 0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
5346 0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
5347 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
5348 0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
5349 0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
5350 0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
5351 0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
5352 0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
5353 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5354 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
5355 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
5356 0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
5357 0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
5358 0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
5359 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
5360 0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
5361 0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
5362 0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
5363 0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
5364 0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
5365 0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
5366 0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
5367 0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
5368 0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
5369 0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
5370 0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
5371 0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
5372 0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
5373 0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
5374 0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
5375 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
5376 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
5377 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
5378 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
5379 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
5380 0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
5381 0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
5382 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
5383 0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
5384 0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
5385 0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
5386 0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
5387 0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
5388 0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
5389 0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
5390 0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
5391 0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
5392 0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
5393 0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
5394 0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
5395 0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
5396 0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
5397 0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
5398 0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
5399 0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
5400 0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
5401 0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
5402 0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
5403 0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
5404 0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
5405 0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
5406 0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
5407 0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
5408 0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
5409 0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
5410 0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
5411 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
5412 0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
5413 0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
5414 0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
5415 0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
5416 0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
5417 0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
5418 0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
5419 0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
5420 0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
5421 0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
5422 0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
5423 0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
5424 0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
5425 0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
5426 0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
5427 0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
5428 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
5429 0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
5430 0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
5431 0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
5432 0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
5433 0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
5434 0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
5435 0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5436 0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
5437 0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
5438 0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
5439 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
5440 0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
5441 0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
5442 0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
5443 0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
5444 0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
5445 0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
5446 0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
5447 0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
5448 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
5449 0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
5450 0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
5451 0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
5452 0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5453 0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
5454 0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
5455 0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
5456 0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
5457 0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
5458 0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
5459 0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
5460 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
5461 0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
5462 0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
5463 0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
5464 0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
5465 0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
5466 0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
5467 0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
5468 0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
5469 0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
5470 0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
5471 0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
5472 0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
5473 0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
5474 0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
5475 0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
5476 0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
5477 0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
5478 0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
5479 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5480 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
5481 0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
5482 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
5483 0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
5484 0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
5485 0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
5486 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
5487 0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
5488 0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
5489 0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
5490 0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
5491 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
5492 0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
5493 0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
5494 0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
5495 0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
5496 0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
5497 0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
5498 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
5499 };
5500
5501 static const u32 tg3TsoFwRodata[] = {
5502 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5503 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
5504 0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
5505 0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
5506 0x00000000,
5507 };
5508
5509 static const u32 tg3TsoFwData[] = {
5510 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
5511 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5512 0x00000000,
5513 };
5514
5515 /* 5705 needs a special version of the TSO firmware. */
5516 #define TG3_TSO5_FW_RELEASE_MAJOR 0x1
5517 #define TG3_TSO5_FW_RELASE_MINOR 0x2
5518 #define TG3_TSO5_FW_RELEASE_FIX 0x0
5519 #define TG3_TSO5_FW_START_ADDR 0x00010000
5520 #define TG3_TSO5_FW_TEXT_ADDR 0x00010000
5521 #define TG3_TSO5_FW_TEXT_LEN 0xe90
5522 #define TG3_TSO5_FW_RODATA_ADDR 0x00010e90
5523 #define TG3_TSO5_FW_RODATA_LEN 0x50
5524 #define TG3_TSO5_FW_DATA_ADDR 0x00010f00
5525 #define TG3_TSO5_FW_DATA_LEN 0x20
5526 #define TG3_TSO5_FW_SBSS_ADDR 0x00010f20
5527 #define TG3_TSO5_FW_SBSS_LEN 0x28
5528 #define TG3_TSO5_FW_BSS_ADDR 0x00010f50
5529 #define TG3_TSO5_FW_BSS_LEN 0x88
5530
5531 static const u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
5532 0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
5533 0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
5534 0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5535 0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
5536 0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
5537 0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
5538 0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5539 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
5540 0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
5541 0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
5542 0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
5543 0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
5544 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
5545 0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
5546 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
5547 0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
5548 0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
5549 0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
5550 0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
5551 0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
5552 0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
5553 0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
5554 0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
5555 0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
5556 0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
5557 0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
5558 0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
5559 0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
5560 0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
5561 0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
5562 0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5563 0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
5564 0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
5565 0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
5566 0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
5567 0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
5568 0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
5569 0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
5570 0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
5571 0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
5572 0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
5573 0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
5574 0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
5575 0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
5576 0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
5577 0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
5578 0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
5579 0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
5580 0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
5581 0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
5582 0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
5583 0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
5584 0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
5585 0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
5586 0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
5587 0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
5588 0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
5589 0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
5590 0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
5591 0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
5592 0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
5593 0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
5594 0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
5595 0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
5596 0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
5597 0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
5598 0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5599 0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
5600 0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
5601 0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
5602 0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
5603 0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
5604 0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
5605 0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
5606 0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
5607 0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
5608 0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
5609 0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
5610 0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
5611 0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
5612 0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
5613 0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
5614 0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
5615 0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
5616 0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
5617 0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
5618 0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
5619 0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
5620 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
5621 0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
5622 0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
5623 0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
5624 0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
5625 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
5626 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
5627 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
5628 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
5629 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
5630 0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
5631 0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
5632 0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
5633 0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
5634 0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
5635 0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
5636 0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
5637 0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
5638 0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5639 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5640 0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
5641 0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
5642 0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
5643 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
5644 0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
5645 0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
5646 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
5647 0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
5648 0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
5649 0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5650 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5651 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
5652 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
5653 0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
5654 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
5655 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5656 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
5657 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
5658 0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
5659 0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
5660 0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
5661 0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
5662 0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
5663 0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
5664 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
5665 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
5666 0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
5667 0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
5668 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
5669 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
5670 0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
5671 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
5672 0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
5673 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
5674 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
5675 0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
5676 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
5677 0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
5678 0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
5679 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5680 0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
5681 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
5682 0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
5683 0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5684 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
5685 0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
5686 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5687 0x00000000, 0x00000000, 0x00000000,
5688 };
5689
5690 static const u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
5691 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5692 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
5693 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5694 0x00000000, 0x00000000, 0x00000000,
5695 };
5696
5697 static const u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
5698 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
5699 0x00000000, 0x00000000, 0x00000000,
5700 };
5701
5702 /* tp->lock is held. */
5703 static int tg3_load_tso_firmware(struct tg3 *tp)
5704 {
5705 struct fw_info info;
5706 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
5707 int err, i;
5708
5709 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5710 return 0;
5711
5712 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5713 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
5714 info.text_len = TG3_TSO5_FW_TEXT_LEN;
5715 info.text_data = &tg3Tso5FwText[0];
5716 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
5717 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
5718 info.rodata_data = &tg3Tso5FwRodata[0];
5719 info.data_base = TG3_TSO5_FW_DATA_ADDR;
5720 info.data_len = TG3_TSO5_FW_DATA_LEN;
5721 info.data_data = &tg3Tso5FwData[0];
5722 cpu_base = RX_CPU_BASE;
5723 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
5724 cpu_scratch_size = (info.text_len +
5725 info.rodata_len +
5726 info.data_len +
5727 TG3_TSO5_FW_SBSS_LEN +
5728 TG3_TSO5_FW_BSS_LEN);
5729 } else {
5730 info.text_base = TG3_TSO_FW_TEXT_ADDR;
5731 info.text_len = TG3_TSO_FW_TEXT_LEN;
5732 info.text_data = &tg3TsoFwText[0];
5733 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
5734 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
5735 info.rodata_data = &tg3TsoFwRodata[0];
5736 info.data_base = TG3_TSO_FW_DATA_ADDR;
5737 info.data_len = TG3_TSO_FW_DATA_LEN;
5738 info.data_data = &tg3TsoFwData[0];
5739 cpu_base = TX_CPU_BASE;
5740 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
5741 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
5742 }
5743
5744 err = tg3_load_firmware_cpu(tp, cpu_base,
5745 cpu_scratch_base, cpu_scratch_size,
5746 &info);
5747 if (err)
5748 return err;
5749
5750 /* Now startup the cpu. */
5751 tw32(cpu_base + CPU_STATE, 0xffffffff);
5752 tw32_f(cpu_base + CPU_PC, info.text_base);
5753
5754 for (i = 0; i < 5; i++) {
5755 if (tr32(cpu_base + CPU_PC) == info.text_base)
5756 break;
5757 tw32(cpu_base + CPU_STATE, 0xffffffff);
5758 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
5759 tw32_f(cpu_base + CPU_PC, info.text_base);
5760 udelay(1000);
5761 }
5762 if (i >= 5) {
5763 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
5764 "to set CPU PC, is %08x should be %08x\n",
5765 tp->dev->name, tr32(cpu_base + CPU_PC),
5766 info.text_base);
5767 return -ENODEV;
5768 }
5769 tw32(cpu_base + CPU_STATE, 0xffffffff);
5770 tw32_f(cpu_base + CPU_MODE, 0x00000000);
5771 return 0;
5772 }
5773
5774 #endif /* TG3_TSO_SUPPORT != 0 */
5775
5776 /* tp->lock is held. */
5777 static void __tg3_set_mac_addr(struct tg3 *tp)
5778 {
5779 u32 addr_high, addr_low;
5780 int i;
5781
5782 addr_high = ((tp->dev->dev_addr[0] << 8) |
5783 tp->dev->dev_addr[1]);
5784 addr_low = ((tp->dev->dev_addr[2] << 24) |
5785 (tp->dev->dev_addr[3] << 16) |
5786 (tp->dev->dev_addr[4] << 8) |
5787 (tp->dev->dev_addr[5] << 0));
5788 for (i = 0; i < 4; i++) {
5789 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
5790 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
5791 }
5792
5793 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
5794 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
5795 for (i = 0; i < 12; i++) {
5796 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
5797 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
5798 }
5799 }
5800
5801 addr_high = (tp->dev->dev_addr[0] +
5802 tp->dev->dev_addr[1] +
5803 tp->dev->dev_addr[2] +
5804 tp->dev->dev_addr[3] +
5805 tp->dev->dev_addr[4] +
5806 tp->dev->dev_addr[5]) &
5807 TX_BACKOFF_SEED_MASK;
5808 tw32(MAC_TX_BACKOFF_SEED, addr_high);
5809 }
5810
5811 static int tg3_set_mac_addr(struct net_device *dev, void *p)
5812 {
5813 struct tg3 *tp = netdev_priv(dev);
5814 struct sockaddr *addr = p;
5815 int err = 0;
5816
5817 if (!is_valid_ether_addr(addr->sa_data))
5818 return -EINVAL;
5819
5820 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5821
5822 if (!netif_running(dev))
5823 return 0;
5824
5825 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5826 /* Reset chip so that ASF can re-init any MAC addresses it
5827 * needs.
5828 */
5829 tg3_netif_stop(tp);
5830 tg3_full_lock(tp, 1);
5831
5832 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5833 err = tg3_restart_hw(tp, 0);
5834 if (!err)
5835 tg3_netif_start(tp);
5836 tg3_full_unlock(tp);
5837 } else {
5838 spin_lock_bh(&tp->lock);
5839 __tg3_set_mac_addr(tp);
5840 spin_unlock_bh(&tp->lock);
5841 }
5842
5843 return err;
5844 }
5845
5846 /* tp->lock is held. */
5847 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
5848 dma_addr_t mapping, u32 maxlen_flags,
5849 u32 nic_addr)
5850 {
5851 tg3_write_mem(tp,
5852 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
5853 ((u64) mapping >> 32));
5854 tg3_write_mem(tp,
5855 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
5856 ((u64) mapping & 0xffffffff));
5857 tg3_write_mem(tp,
5858 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
5859 maxlen_flags);
5860
5861 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5862 tg3_write_mem(tp,
5863 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
5864 nic_addr);
5865 }
5866
5867 static void __tg3_set_rx_mode(struct net_device *);
5868 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
5869 {
5870 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
5871 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
5872 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
5873 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
5874 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5875 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
5876 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
5877 }
5878 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
5879 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
5880 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5881 u32 val = ec->stats_block_coalesce_usecs;
5882
5883 if (!netif_carrier_ok(tp->dev))
5884 val = 0;
5885
5886 tw32(HOSTCC_STAT_COAL_TICKS, val);
5887 }
5888 }
5889
5890 /* tp->lock is held. */
5891 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
5892 {
5893 u32 val, rdmac_mode;
5894 int i, err, limit;
5895
5896 tg3_disable_ints(tp);
5897
5898 tg3_stop_fw(tp);
5899
5900 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
5901
5902 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
5903 tg3_abort_hw(tp, 1);
5904 }
5905
5906 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) && reset_phy)
5907 tg3_phy_reset(tp);
5908
5909 err = tg3_chip_reset(tp);
5910 if (err)
5911 return err;
5912
5913 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
5914
5915 /* This works around an issue with Athlon chipsets on
5916 * B3 tigon3 silicon. This bit has no effect on any
5917 * other revision. But do not set this on PCI Express
5918 * chips.
5919 */
5920 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
5921 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
5922 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
5923
5924 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
5925 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
5926 val = tr32(TG3PCI_PCISTATE);
5927 val |= PCISTATE_RETRY_SAME_DMA;
5928 tw32(TG3PCI_PCISTATE, val);
5929 }
5930
5931 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
5932 /* Enable some hw fixes. */
5933 val = tr32(TG3PCI_MSI_DATA);
5934 val |= (1 << 26) | (1 << 28) | (1 << 29);
5935 tw32(TG3PCI_MSI_DATA, val);
5936 }
5937
5938 /* Descriptor ring init may make accesses to the
5939 * NIC SRAM area to setup the TX descriptors, so we
5940 * can only do this after the hardware has been
5941 * successfully reset.
5942 */
5943 err = tg3_init_rings(tp);
5944 if (err)
5945 return err;
5946
5947 /* This value is determined during the probe time DMA
5948 * engine test, tg3_test_dma.
5949 */
5950 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
5951
5952 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
5953 GRC_MODE_4X_NIC_SEND_RINGS |
5954 GRC_MODE_NO_TX_PHDR_CSUM |
5955 GRC_MODE_NO_RX_PHDR_CSUM);
5956 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
5957
5958 /* Pseudo-header checksum is done by hardware logic and not
5959 * the offload processers, so make the chip do the pseudo-
5960 * header checksums on receive. For transmit it is more
5961 * convenient to do the pseudo-header checksum in software
5962 * as Linux does that on transmit for us in all cases.
5963 */
5964 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
5965
5966 tw32(GRC_MODE,
5967 tp->grc_mode |
5968 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
5969
5970 /* Setup the timer prescalar register. Clock is always 66Mhz. */
5971 val = tr32(GRC_MISC_CFG);
5972 val &= ~0xff;
5973 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
5974 tw32(GRC_MISC_CFG, val);
5975
5976 /* Initialize MBUF/DESC pool. */
5977 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
5978 /* Do nothing. */
5979 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
5980 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
5981 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
5982 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
5983 else
5984 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
5985 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
5986 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
5987 }
5988 #if TG3_TSO_SUPPORT != 0
5989 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
5990 int fw_len;
5991
5992 fw_len = (TG3_TSO5_FW_TEXT_LEN +
5993 TG3_TSO5_FW_RODATA_LEN +
5994 TG3_TSO5_FW_DATA_LEN +
5995 TG3_TSO5_FW_SBSS_LEN +
5996 TG3_TSO5_FW_BSS_LEN);
5997 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
5998 tw32(BUFMGR_MB_POOL_ADDR,
5999 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
6000 tw32(BUFMGR_MB_POOL_SIZE,
6001 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
6002 }
6003 #endif
6004
6005 if (tp->dev->mtu <= ETH_DATA_LEN) {
6006 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6007 tp->bufmgr_config.mbuf_read_dma_low_water);
6008 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6009 tp->bufmgr_config.mbuf_mac_rx_low_water);
6010 tw32(BUFMGR_MB_HIGH_WATER,
6011 tp->bufmgr_config.mbuf_high_water);
6012 } else {
6013 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6014 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
6015 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6016 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
6017 tw32(BUFMGR_MB_HIGH_WATER,
6018 tp->bufmgr_config.mbuf_high_water_jumbo);
6019 }
6020 tw32(BUFMGR_DMA_LOW_WATER,
6021 tp->bufmgr_config.dma_low_water);
6022 tw32(BUFMGR_DMA_HIGH_WATER,
6023 tp->bufmgr_config.dma_high_water);
6024
6025 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
6026 for (i = 0; i < 2000; i++) {
6027 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
6028 break;
6029 udelay(10);
6030 }
6031 if (i >= 2000) {
6032 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
6033 tp->dev->name);
6034 return -ENODEV;
6035 }
6036
6037 /* Setup replenish threshold. */
6038 val = tp->rx_pending / 8;
6039 if (val == 0)
6040 val = 1;
6041 else if (val > tp->rx_std_max_post)
6042 val = tp->rx_std_max_post;
6043
6044 tw32(RCVBDI_STD_THRESH, val);
6045
6046 /* Initialize TG3_BDINFO's at:
6047 * RCVDBDI_STD_BD: standard eth size rx ring
6048 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
6049 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
6050 *
6051 * like so:
6052 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
6053 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
6054 * ring attribute flags
6055 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
6056 *
6057 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
6058 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
6059 *
6060 * The size of each ring is fixed in the firmware, but the location is
6061 * configurable.
6062 */
6063 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6064 ((u64) tp->rx_std_mapping >> 32));
6065 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6066 ((u64) tp->rx_std_mapping & 0xffffffff));
6067 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
6068 NIC_SRAM_RX_BUFFER_DESC);
6069
6070 /* Don't even try to program the JUMBO/MINI buffer descriptor
6071 * configs on 5705.
6072 */
6073 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6074 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6075 RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
6076 } else {
6077 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6078 RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6079
6080 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
6081 BDINFO_FLAGS_DISABLED);
6082
6083 /* Setup replenish threshold. */
6084 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
6085
6086 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
6087 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6088 ((u64) tp->rx_jumbo_mapping >> 32));
6089 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6090 ((u64) tp->rx_jumbo_mapping & 0xffffffff));
6091 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6092 RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6093 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
6094 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
6095 } else {
6096 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6097 BDINFO_FLAGS_DISABLED);
6098 }
6099
6100 }
6101
6102 /* There is only one send ring on 5705/5750, no need to explicitly
6103 * disable the others.
6104 */
6105 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6106 /* Clear out send RCB ring in SRAM. */
6107 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
6108 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6109 BDINFO_FLAGS_DISABLED);
6110 }
6111
6112 tp->tx_prod = 0;
6113 tp->tx_cons = 0;
6114 tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6115 tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6116
6117 tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
6118 tp->tx_desc_mapping,
6119 (TG3_TX_RING_SIZE <<
6120 BDINFO_FLAGS_MAXLEN_SHIFT),
6121 NIC_SRAM_TX_BUFFER_DESC);
6122
6123 /* There is only one receive return ring on 5705/5750, no need
6124 * to explicitly disable the others.
6125 */
6126 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6127 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
6128 i += TG3_BDINFO_SIZE) {
6129 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6130 BDINFO_FLAGS_DISABLED);
6131 }
6132 }
6133
6134 tp->rx_rcb_ptr = 0;
6135 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
6136
6137 tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
6138 tp->rx_rcb_mapping,
6139 (TG3_RX_RCB_RING_SIZE(tp) <<
6140 BDINFO_FLAGS_MAXLEN_SHIFT),
6141 0);
6142
6143 tp->rx_std_ptr = tp->rx_pending;
6144 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
6145 tp->rx_std_ptr);
6146
6147 tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
6148 tp->rx_jumbo_pending : 0;
6149 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
6150 tp->rx_jumbo_ptr);
6151
6152 /* Initialize MAC address and backoff seed. */
6153 __tg3_set_mac_addr(tp);
6154
6155 /* MTU + ethernet header + FCS + optional VLAN tag */
6156 tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
6157
6158 /* The slot time is changed by tg3_setup_phy if we
6159 * run at gigabit with half duplex.
6160 */
6161 tw32(MAC_TX_LENGTHS,
6162 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6163 (6 << TX_LENGTHS_IPG_SHIFT) |
6164 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
6165
6166 /* Receive rules. */
6167 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
6168 tw32(RCVLPC_CONFIG, 0x0181);
6169
6170 /* Calculate RDMAC_MODE setting early, we need it to determine
6171 * the RCVLPC_STATE_ENABLE mask.
6172 */
6173 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
6174 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
6175 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
6176 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
6177 RDMAC_MODE_LNGREAD_ENAB);
6178 if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
6179 rdmac_mode |= RDMAC_MODE_SPLIT_ENABLE;
6180
6181 /* If statement applies to 5705 and 5750 PCI devices only */
6182 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6183 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6184 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
6185 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
6186 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
6187 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
6188 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
6189 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6190 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
6191 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6192 }
6193 }
6194
6195 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6196 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6197
6198 #if TG3_TSO_SUPPORT != 0
6199 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6200 rdmac_mode |= (1 << 27);
6201 #endif
6202
6203 /* Receive/send statistics. */
6204 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6205 val = tr32(RCVLPC_STATS_ENABLE);
6206 val &= ~RCVLPC_STATSENAB_DACK_FIX;
6207 tw32(RCVLPC_STATS_ENABLE, val);
6208 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
6209 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
6210 val = tr32(RCVLPC_STATS_ENABLE);
6211 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
6212 tw32(RCVLPC_STATS_ENABLE, val);
6213 } else {
6214 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
6215 }
6216 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
6217 tw32(SNDDATAI_STATSENAB, 0xffffff);
6218 tw32(SNDDATAI_STATSCTRL,
6219 (SNDDATAI_SCTRL_ENABLE |
6220 SNDDATAI_SCTRL_FASTUPD));
6221
6222 /* Setup host coalescing engine. */
6223 tw32(HOSTCC_MODE, 0);
6224 for (i = 0; i < 2000; i++) {
6225 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
6226 break;
6227 udelay(10);
6228 }
6229
6230 __tg3_set_coalesce(tp, &tp->coal);
6231
6232 /* set status block DMA address */
6233 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6234 ((u64) tp->status_mapping >> 32));
6235 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6236 ((u64) tp->status_mapping & 0xffffffff));
6237
6238 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6239 /* Status/statistics block address. See tg3_timer,
6240 * the tg3_periodic_fetch_stats call there, and
6241 * tg3_get_stats to see how this works for 5705/5750 chips.
6242 */
6243 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6244 ((u64) tp->stats_mapping >> 32));
6245 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6246 ((u64) tp->stats_mapping & 0xffffffff));
6247 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
6248 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
6249 }
6250
6251 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
6252
6253 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
6254 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
6255 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6256 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
6257
6258 /* Clear statistics/status block in chip, and status block in ram. */
6259 for (i = NIC_SRAM_STATS_BLK;
6260 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
6261 i += sizeof(u32)) {
6262 tg3_write_mem(tp, i, 0);
6263 udelay(40);
6264 }
6265 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
6266
6267 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6268 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
6269 /* reset to prevent losing 1st rx packet intermittently */
6270 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6271 udelay(10);
6272 }
6273
6274 tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
6275 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
6276 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
6277 udelay(40);
6278
6279 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
6280 * If TG3_FLAG_EEPROM_WRITE_PROT is set, we should read the
6281 * register to preserve the GPIO settings for LOMs. The GPIOs,
6282 * whether used as inputs or outputs, are set by boot code after
6283 * reset.
6284 */
6285 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
6286 u32 gpio_mask;
6287
6288 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE2 |
6289 GRC_LCLCTRL_GPIO_OUTPUT0 | GRC_LCLCTRL_GPIO_OUTPUT2;
6290
6291 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
6292 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
6293 GRC_LCLCTRL_GPIO_OUTPUT3;
6294
6295 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6296 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
6297
6298 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
6299
6300 /* GPIO1 must be driven high for eeprom write protect */
6301 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
6302 GRC_LCLCTRL_GPIO_OUTPUT1);
6303 }
6304 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6305 udelay(100);
6306
6307 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
6308 tp->last_tag = 0;
6309
6310 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6311 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
6312 udelay(40);
6313 }
6314
6315 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
6316 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
6317 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
6318 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
6319 WDMAC_MODE_LNGREAD_ENAB);
6320
6321 /* If statement applies to 5705 and 5750 PCI devices only */
6322 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6323 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6324 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
6325 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
6326 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
6327 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
6328 /* nothing */
6329 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6330 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
6331 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
6332 val |= WDMAC_MODE_RX_ACCEL;
6333 }
6334 }
6335
6336 /* Enable host coalescing bug fix */
6337 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) ||
6338 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787))
6339 val |= (1 << 29);
6340
6341 tw32_f(WDMAC_MODE, val);
6342 udelay(40);
6343
6344 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
6345 val = tr32(TG3PCI_X_CAPS);
6346 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
6347 val &= ~PCIX_CAPS_BURST_MASK;
6348 val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
6349 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
6350 val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
6351 val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
6352 if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
6353 val |= (tp->split_mode_max_reqs <<
6354 PCIX_CAPS_SPLIT_SHIFT);
6355 }
6356 tw32(TG3PCI_X_CAPS, val);
6357 }
6358
6359 tw32_f(RDMAC_MODE, rdmac_mode);
6360 udelay(40);
6361
6362 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
6363 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6364 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
6365 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
6366 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
6367 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
6368 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
6369 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
6370 #if TG3_TSO_SUPPORT != 0
6371 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6372 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
6373 #endif
6374 tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
6375 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
6376
6377 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
6378 err = tg3_load_5701_a0_firmware_fix(tp);
6379 if (err)
6380 return err;
6381 }
6382
6383 #if TG3_TSO_SUPPORT != 0
6384 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6385 err = tg3_load_tso_firmware(tp);
6386 if (err)
6387 return err;
6388 }
6389 #endif
6390
6391 tp->tx_mode = TX_MODE_ENABLE;
6392 tw32_f(MAC_TX_MODE, tp->tx_mode);
6393 udelay(100);
6394
6395 tp->rx_mode = RX_MODE_ENABLE;
6396 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6397 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
6398
6399 tw32_f(MAC_RX_MODE, tp->rx_mode);
6400 udelay(10);
6401
6402 if (tp->link_config.phy_is_low_power) {
6403 tp->link_config.phy_is_low_power = 0;
6404 tp->link_config.speed = tp->link_config.orig_speed;
6405 tp->link_config.duplex = tp->link_config.orig_duplex;
6406 tp->link_config.autoneg = tp->link_config.orig_autoneg;
6407 }
6408
6409 tp->mi_mode = MAC_MI_MODE_BASE;
6410 tw32_f(MAC_MI_MODE, tp->mi_mode);
6411 udelay(80);
6412
6413 tw32(MAC_LED_CTRL, tp->led_ctrl);
6414
6415 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
6416 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6417 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6418 udelay(10);
6419 }
6420 tw32_f(MAC_RX_MODE, tp->rx_mode);
6421 udelay(10);
6422
6423 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6424 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
6425 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
6426 /* Set drive transmission level to 1.2V */
6427 /* only if the signal pre-emphasis bit is not set */
6428 val = tr32(MAC_SERDES_CFG);
6429 val &= 0xfffff000;
6430 val |= 0x880;
6431 tw32(MAC_SERDES_CFG, val);
6432 }
6433 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
6434 tw32(MAC_SERDES_CFG, 0x616000);
6435 }
6436
6437 /* Prevent chip from dropping frames when flow control
6438 * is enabled.
6439 */
6440 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
6441
6442 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
6443 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
6444 /* Use hardware link auto-negotiation */
6445 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
6446 }
6447
6448 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
6449 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
6450 u32 tmp;
6451
6452 tmp = tr32(SERDES_RX_CTRL);
6453 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
6454 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
6455 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
6456 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6457 }
6458
6459 err = tg3_setup_phy(tp, reset_phy);
6460 if (err)
6461 return err;
6462
6463 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
6464 u32 tmp;
6465
6466 /* Clear CRC stats. */
6467 if (!tg3_readphy(tp, 0x1e, &tmp)) {
6468 tg3_writephy(tp, 0x1e, tmp | 0x8000);
6469 tg3_readphy(tp, 0x14, &tmp);
6470 }
6471 }
6472
6473 __tg3_set_rx_mode(tp->dev);
6474
6475 /* Initialize receive rules. */
6476 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
6477 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
6478 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
6479 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
6480
6481 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
6482 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6483 limit = 8;
6484 else
6485 limit = 16;
6486 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
6487 limit -= 4;
6488 switch (limit) {
6489 case 16:
6490 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
6491 case 15:
6492 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
6493 case 14:
6494 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
6495 case 13:
6496 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
6497 case 12:
6498 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
6499 case 11:
6500 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
6501 case 10:
6502 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
6503 case 9:
6504 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
6505 case 8:
6506 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
6507 case 7:
6508 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
6509 case 6:
6510 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
6511 case 5:
6512 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
6513 case 4:
6514 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
6515 case 3:
6516 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
6517 case 2:
6518 case 1:
6519
6520 default:
6521 break;
6522 };
6523
6524 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
6525
6526 return 0;
6527 }
6528
6529 /* Called at device open time to get the chip ready for
6530 * packet processing. Invoked with tp->lock held.
6531 */
6532 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
6533 {
6534 int err;
6535
6536 /* Force the chip into D0. */
6537 err = tg3_set_power_state(tp, PCI_D0);
6538 if (err)
6539 goto out;
6540
6541 tg3_switch_clocks(tp);
6542
6543 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
6544
6545 err = tg3_reset_hw(tp, reset_phy);
6546
6547 out:
6548 return err;
6549 }
6550
6551 #define TG3_STAT_ADD32(PSTAT, REG) \
6552 do { u32 __val = tr32(REG); \
6553 (PSTAT)->low += __val; \
6554 if ((PSTAT)->low < __val) \
6555 (PSTAT)->high += 1; \
6556 } while (0)
6557
6558 static void tg3_periodic_fetch_stats(struct tg3 *tp)
6559 {
6560 struct tg3_hw_stats *sp = tp->hw_stats;
6561
6562 if (!netif_carrier_ok(tp->dev))
6563 return;
6564
6565 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
6566 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
6567 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
6568 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
6569 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
6570 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
6571 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
6572 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
6573 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
6574 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
6575 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
6576 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
6577 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
6578
6579 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
6580 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
6581 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
6582 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
6583 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
6584 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
6585 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
6586 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
6587 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
6588 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
6589 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
6590 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
6591 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
6592 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
6593
6594 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
6595 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
6596 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
6597 }
6598
6599 static void tg3_timer(unsigned long __opaque)
6600 {
6601 struct tg3 *tp = (struct tg3 *) __opaque;
6602
6603 if (tp->irq_sync)
6604 goto restart_timer;
6605
6606 spin_lock(&tp->lock);
6607
6608 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
6609 /* All of this garbage is because when using non-tagged
6610 * IRQ status the mailbox/status_block protocol the chip
6611 * uses with the cpu is race prone.
6612 */
6613 if (tp->hw_status->status & SD_STATUS_UPDATED) {
6614 tw32(GRC_LOCAL_CTRL,
6615 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
6616 } else {
6617 tw32(HOSTCC_MODE, tp->coalesce_mode |
6618 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
6619 }
6620
6621 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
6622 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
6623 spin_unlock(&tp->lock);
6624 schedule_work(&tp->reset_task);
6625 return;
6626 }
6627 }
6628
6629 /* This part only runs once per second. */
6630 if (!--tp->timer_counter) {
6631 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6632 tg3_periodic_fetch_stats(tp);
6633
6634 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
6635 u32 mac_stat;
6636 int phy_event;
6637
6638 mac_stat = tr32(MAC_STATUS);
6639
6640 phy_event = 0;
6641 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
6642 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
6643 phy_event = 1;
6644 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
6645 phy_event = 1;
6646
6647 if (phy_event)
6648 tg3_setup_phy(tp, 0);
6649 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
6650 u32 mac_stat = tr32(MAC_STATUS);
6651 int need_setup = 0;
6652
6653 if (netif_carrier_ok(tp->dev) &&
6654 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
6655 need_setup = 1;
6656 }
6657 if (! netif_carrier_ok(tp->dev) &&
6658 (mac_stat & (MAC_STATUS_PCS_SYNCED |
6659 MAC_STATUS_SIGNAL_DET))) {
6660 need_setup = 1;
6661 }
6662 if (need_setup) {
6663 tw32_f(MAC_MODE,
6664 (tp->mac_mode &
6665 ~MAC_MODE_PORT_MODE_MASK));
6666 udelay(40);
6667 tw32_f(MAC_MODE, tp->mac_mode);
6668 udelay(40);
6669 tg3_setup_phy(tp, 0);
6670 }
6671 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
6672 tg3_serdes_parallel_detect(tp);
6673
6674 tp->timer_counter = tp->timer_multiplier;
6675 }
6676
6677 /* Heartbeat is only sent once every 2 seconds. */
6678 if (!--tp->asf_counter) {
6679 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6680 u32 val;
6681
6682 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
6683 FWCMD_NICDRV_ALIVE2);
6684 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
6685 /* 5 seconds timeout */
6686 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
6687 val = tr32(GRC_RX_CPU_EVENT);
6688 val |= (1 << 14);
6689 tw32(GRC_RX_CPU_EVENT, val);
6690 }
6691 tp->asf_counter = tp->asf_multiplier;
6692 }
6693
6694 spin_unlock(&tp->lock);
6695
6696 restart_timer:
6697 tp->timer.expires = jiffies + tp->timer_offset;
6698 add_timer(&tp->timer);
6699 }
6700
6701 static int tg3_request_irq(struct tg3 *tp)
6702 {
6703 irqreturn_t (*fn)(int, void *, struct pt_regs *);
6704 unsigned long flags;
6705 struct net_device *dev = tp->dev;
6706
6707 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6708 fn = tg3_msi;
6709 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
6710 fn = tg3_msi_1shot;
6711 flags = IRQF_SAMPLE_RANDOM;
6712 } else {
6713 fn = tg3_interrupt;
6714 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6715 fn = tg3_interrupt_tagged;
6716 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
6717 }
6718 return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
6719 }
6720
6721 static int tg3_test_interrupt(struct tg3 *tp)
6722 {
6723 struct net_device *dev = tp->dev;
6724 int err, i;
6725 u32 int_mbox = 0;
6726
6727 if (!netif_running(dev))
6728 return -ENODEV;
6729
6730 tg3_disable_ints(tp);
6731
6732 free_irq(tp->pdev->irq, dev);
6733
6734 err = request_irq(tp->pdev->irq, tg3_test_isr,
6735 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
6736 if (err)
6737 return err;
6738
6739 tp->hw_status->status &= ~SD_STATUS_UPDATED;
6740 tg3_enable_ints(tp);
6741
6742 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
6743 HOSTCC_MODE_NOW);
6744
6745 for (i = 0; i < 5; i++) {
6746 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
6747 TG3_64BIT_REG_LOW);
6748 if (int_mbox != 0)
6749 break;
6750 msleep(10);
6751 }
6752
6753 tg3_disable_ints(tp);
6754
6755 free_irq(tp->pdev->irq, dev);
6756
6757 err = tg3_request_irq(tp);
6758
6759 if (err)
6760 return err;
6761
6762 if (int_mbox != 0)
6763 return 0;
6764
6765 return -EIO;
6766 }
6767
6768 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
6769 * successfully restored
6770 */
6771 static int tg3_test_msi(struct tg3 *tp)
6772 {
6773 struct net_device *dev = tp->dev;
6774 int err;
6775 u16 pci_cmd;
6776
6777 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
6778 return 0;
6779
6780 /* Turn off SERR reporting in case MSI terminates with Master
6781 * Abort.
6782 */
6783 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
6784 pci_write_config_word(tp->pdev, PCI_COMMAND,
6785 pci_cmd & ~PCI_COMMAND_SERR);
6786
6787 err = tg3_test_interrupt(tp);
6788
6789 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
6790
6791 if (!err)
6792 return 0;
6793
6794 /* other failures */
6795 if (err != -EIO)
6796 return err;
6797
6798 /* MSI test failed, go back to INTx mode */
6799 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
6800 "switching to INTx mode. Please report this failure to "
6801 "the PCI maintainer and include system chipset information.\n",
6802 tp->dev->name);
6803
6804 free_irq(tp->pdev->irq, dev);
6805 pci_disable_msi(tp->pdev);
6806
6807 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6808
6809 err = tg3_request_irq(tp);
6810 if (err)
6811 return err;
6812
6813 /* Need to reset the chip because the MSI cycle may have terminated
6814 * with Master Abort.
6815 */
6816 tg3_full_lock(tp, 1);
6817
6818 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6819 err = tg3_init_hw(tp, 1);
6820
6821 tg3_full_unlock(tp);
6822
6823 if (err)
6824 free_irq(tp->pdev->irq, dev);
6825
6826 return err;
6827 }
6828
6829 static int tg3_open(struct net_device *dev)
6830 {
6831 struct tg3 *tp = netdev_priv(dev);
6832 int err;
6833
6834 tg3_full_lock(tp, 0);
6835
6836 err = tg3_set_power_state(tp, PCI_D0);
6837 if (err)
6838 return err;
6839
6840 tg3_disable_ints(tp);
6841 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
6842
6843 tg3_full_unlock(tp);
6844
6845 /* The placement of this call is tied
6846 * to the setup and use of Host TX descriptors.
6847 */
6848 err = tg3_alloc_consistent(tp);
6849 if (err)
6850 return err;
6851
6852 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
6853 (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_AX) &&
6854 (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_BX) &&
6855 !((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) &&
6856 (tp->pdev_peer == tp->pdev))) {
6857 /* All MSI supporting chips should support tagged
6858 * status. Assert that this is the case.
6859 */
6860 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
6861 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
6862 "Not using MSI.\n", tp->dev->name);
6863 } else if (pci_enable_msi(tp->pdev) == 0) {
6864 u32 msi_mode;
6865
6866 msi_mode = tr32(MSGINT_MODE);
6867 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
6868 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
6869 }
6870 }
6871 err = tg3_request_irq(tp);
6872
6873 if (err) {
6874 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6875 pci_disable_msi(tp->pdev);
6876 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6877 }
6878 tg3_free_consistent(tp);
6879 return err;
6880 }
6881
6882 tg3_full_lock(tp, 0);
6883
6884 err = tg3_init_hw(tp, 1);
6885 if (err) {
6886 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6887 tg3_free_rings(tp);
6888 } else {
6889 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6890 tp->timer_offset = HZ;
6891 else
6892 tp->timer_offset = HZ / 10;
6893
6894 BUG_ON(tp->timer_offset > HZ);
6895 tp->timer_counter = tp->timer_multiplier =
6896 (HZ / tp->timer_offset);
6897 tp->asf_counter = tp->asf_multiplier =
6898 ((HZ / tp->timer_offset) * 2);
6899
6900 init_timer(&tp->timer);
6901 tp->timer.expires = jiffies + tp->timer_offset;
6902 tp->timer.data = (unsigned long) tp;
6903 tp->timer.function = tg3_timer;
6904 }
6905
6906 tg3_full_unlock(tp);
6907
6908 if (err) {
6909 free_irq(tp->pdev->irq, dev);
6910 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6911 pci_disable_msi(tp->pdev);
6912 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6913 }
6914 tg3_free_consistent(tp);
6915 return err;
6916 }
6917
6918 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6919 err = tg3_test_msi(tp);
6920
6921 if (err) {
6922 tg3_full_lock(tp, 0);
6923
6924 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6925 pci_disable_msi(tp->pdev);
6926 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6927 }
6928 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6929 tg3_free_rings(tp);
6930 tg3_free_consistent(tp);
6931
6932 tg3_full_unlock(tp);
6933
6934 return err;
6935 }
6936
6937 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6938 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
6939 u32 val = tr32(0x7c04);
6940
6941 tw32(0x7c04, val | (1 << 29));
6942 }
6943 }
6944 }
6945
6946 tg3_full_lock(tp, 0);
6947
6948 add_timer(&tp->timer);
6949 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
6950 tg3_enable_ints(tp);
6951
6952 tg3_full_unlock(tp);
6953
6954 netif_start_queue(dev);
6955
6956 return 0;
6957 }
6958
6959 #if 0
6960 /*static*/ void tg3_dump_state(struct tg3 *tp)
6961 {
6962 u32 val32, val32_2, val32_3, val32_4, val32_5;
6963 u16 val16;
6964 int i;
6965
6966 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
6967 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
6968 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
6969 val16, val32);
6970
6971 /* MAC block */
6972 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
6973 tr32(MAC_MODE), tr32(MAC_STATUS));
6974 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
6975 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
6976 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
6977 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
6978 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
6979 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
6980
6981 /* Send data initiator control block */
6982 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
6983 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
6984 printk(" SNDDATAI_STATSCTRL[%08x]\n",
6985 tr32(SNDDATAI_STATSCTRL));
6986
6987 /* Send data completion control block */
6988 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
6989
6990 /* Send BD ring selector block */
6991 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
6992 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
6993
6994 /* Send BD initiator control block */
6995 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
6996 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
6997
6998 /* Send BD completion control block */
6999 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
7000
7001 /* Receive list placement control block */
7002 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
7003 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
7004 printk(" RCVLPC_STATSCTRL[%08x]\n",
7005 tr32(RCVLPC_STATSCTRL));
7006
7007 /* Receive data and receive BD initiator control block */
7008 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
7009 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
7010
7011 /* Receive data completion control block */
7012 printk("DEBUG: RCVDCC_MODE[%08x]\n",
7013 tr32(RCVDCC_MODE));
7014
7015 /* Receive BD initiator control block */
7016 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
7017 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
7018
7019 /* Receive BD completion control block */
7020 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
7021 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
7022
7023 /* Receive list selector control block */
7024 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
7025 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
7026
7027 /* Mbuf cluster free block */
7028 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
7029 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
7030
7031 /* Host coalescing control block */
7032 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
7033 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
7034 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
7035 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7036 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7037 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
7038 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7039 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7040 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
7041 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
7042 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
7043 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
7044
7045 /* Memory arbiter control block */
7046 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
7047 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
7048
7049 /* Buffer manager control block */
7050 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
7051 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
7052 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
7053 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
7054 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
7055 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
7056 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
7057 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
7058
7059 /* Read DMA control block */
7060 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
7061 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
7062
7063 /* Write DMA control block */
7064 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
7065 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
7066
7067 /* DMA completion block */
7068 printk("DEBUG: DMAC_MODE[%08x]\n",
7069 tr32(DMAC_MODE));
7070
7071 /* GRC block */
7072 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
7073 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
7074 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
7075 tr32(GRC_LOCAL_CTRL));
7076
7077 /* TG3_BDINFOs */
7078 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
7079 tr32(RCVDBDI_JUMBO_BD + 0x0),
7080 tr32(RCVDBDI_JUMBO_BD + 0x4),
7081 tr32(RCVDBDI_JUMBO_BD + 0x8),
7082 tr32(RCVDBDI_JUMBO_BD + 0xc));
7083 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
7084 tr32(RCVDBDI_STD_BD + 0x0),
7085 tr32(RCVDBDI_STD_BD + 0x4),
7086 tr32(RCVDBDI_STD_BD + 0x8),
7087 tr32(RCVDBDI_STD_BD + 0xc));
7088 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
7089 tr32(RCVDBDI_MINI_BD + 0x0),
7090 tr32(RCVDBDI_MINI_BD + 0x4),
7091 tr32(RCVDBDI_MINI_BD + 0x8),
7092 tr32(RCVDBDI_MINI_BD + 0xc));
7093
7094 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
7095 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
7096 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
7097 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
7098 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
7099 val32, val32_2, val32_3, val32_4);
7100
7101 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
7102 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
7103 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
7104 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
7105 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
7106 val32, val32_2, val32_3, val32_4);
7107
7108 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
7109 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
7110 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
7111 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
7112 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
7113 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
7114 val32, val32_2, val32_3, val32_4, val32_5);
7115
7116 /* SW status block */
7117 printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
7118 tp->hw_status->status,
7119 tp->hw_status->status_tag,
7120 tp->hw_status->rx_jumbo_consumer,
7121 tp->hw_status->rx_consumer,
7122 tp->hw_status->rx_mini_consumer,
7123 tp->hw_status->idx[0].rx_producer,
7124 tp->hw_status->idx[0].tx_consumer);
7125
7126 /* SW statistics block */
7127 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
7128 ((u32 *)tp->hw_stats)[0],
7129 ((u32 *)tp->hw_stats)[1],
7130 ((u32 *)tp->hw_stats)[2],
7131 ((u32 *)tp->hw_stats)[3]);
7132
7133 /* Mailboxes */
7134 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
7135 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
7136 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
7137 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
7138 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
7139
7140 /* NIC side send descriptors. */
7141 for (i = 0; i < 6; i++) {
7142 unsigned long txd;
7143
7144 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
7145 + (i * sizeof(struct tg3_tx_buffer_desc));
7146 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
7147 i,
7148 readl(txd + 0x0), readl(txd + 0x4),
7149 readl(txd + 0x8), readl(txd + 0xc));
7150 }
7151
7152 /* NIC side RX descriptors. */
7153 for (i = 0; i < 6; i++) {
7154 unsigned long rxd;
7155
7156 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
7157 + (i * sizeof(struct tg3_rx_buffer_desc));
7158 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
7159 i,
7160 readl(rxd + 0x0), readl(rxd + 0x4),
7161 readl(rxd + 0x8), readl(rxd + 0xc));
7162 rxd += (4 * sizeof(u32));
7163 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
7164 i,
7165 readl(rxd + 0x0), readl(rxd + 0x4),
7166 readl(rxd + 0x8), readl(rxd + 0xc));
7167 }
7168
7169 for (i = 0; i < 6; i++) {
7170 unsigned long rxd;
7171
7172 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
7173 + (i * sizeof(struct tg3_rx_buffer_desc));
7174 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
7175 i,
7176 readl(rxd + 0x0), readl(rxd + 0x4),
7177 readl(rxd + 0x8), readl(rxd + 0xc));
7178 rxd += (4 * sizeof(u32));
7179 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
7180 i,
7181 readl(rxd + 0x0), readl(rxd + 0x4),
7182 readl(rxd + 0x8), readl(rxd + 0xc));
7183 }
7184 }
7185 #endif
7186
7187 static struct net_device_stats *tg3_get_stats(struct net_device *);
7188 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
7189
7190 static int tg3_close(struct net_device *dev)
7191 {
7192 struct tg3 *tp = netdev_priv(dev);
7193
7194 /* Calling flush_scheduled_work() may deadlock because
7195 * linkwatch_event() may be on the workqueue and it will try to get
7196 * the rtnl_lock which we are holding.
7197 */
7198 while (tp->tg3_flags & TG3_FLAG_IN_RESET_TASK)
7199 msleep(1);
7200
7201 netif_stop_queue(dev);
7202
7203 del_timer_sync(&tp->timer);
7204
7205 tg3_full_lock(tp, 1);
7206 #if 0
7207 tg3_dump_state(tp);
7208 #endif
7209
7210 tg3_disable_ints(tp);
7211
7212 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7213 tg3_free_rings(tp);
7214 tp->tg3_flags &=
7215 ~(TG3_FLAG_INIT_COMPLETE |
7216 TG3_FLAG_GOT_SERDES_FLOWCTL);
7217
7218 tg3_full_unlock(tp);
7219
7220 free_irq(tp->pdev->irq, dev);
7221 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7222 pci_disable_msi(tp->pdev);
7223 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7224 }
7225
7226 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
7227 sizeof(tp->net_stats_prev));
7228 memcpy(&tp->estats_prev, tg3_get_estats(tp),
7229 sizeof(tp->estats_prev));
7230
7231 tg3_free_consistent(tp);
7232
7233 tg3_set_power_state(tp, PCI_D3hot);
7234
7235 netif_carrier_off(tp->dev);
7236
7237 return 0;
7238 }
7239
7240 static inline unsigned long get_stat64(tg3_stat64_t *val)
7241 {
7242 unsigned long ret;
7243
7244 #if (BITS_PER_LONG == 32)
7245 ret = val->low;
7246 #else
7247 ret = ((u64)val->high << 32) | ((u64)val->low);
7248 #endif
7249 return ret;
7250 }
7251
7252 static unsigned long calc_crc_errors(struct tg3 *tp)
7253 {
7254 struct tg3_hw_stats *hw_stats = tp->hw_stats;
7255
7256 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7257 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
7258 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
7259 u32 val;
7260
7261 spin_lock_bh(&tp->lock);
7262 if (!tg3_readphy(tp, 0x1e, &val)) {
7263 tg3_writephy(tp, 0x1e, val | 0x8000);
7264 tg3_readphy(tp, 0x14, &val);
7265 } else
7266 val = 0;
7267 spin_unlock_bh(&tp->lock);
7268
7269 tp->phy_crc_errors += val;
7270
7271 return tp->phy_crc_errors;
7272 }
7273
7274 return get_stat64(&hw_stats->rx_fcs_errors);
7275 }
7276
7277 #define ESTAT_ADD(member) \
7278 estats->member = old_estats->member + \
7279 get_stat64(&hw_stats->member)
7280
7281 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
7282 {
7283 struct tg3_ethtool_stats *estats = &tp->estats;
7284 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
7285 struct tg3_hw_stats *hw_stats = tp->hw_stats;
7286
7287 if (!hw_stats)
7288 return old_estats;
7289
7290 ESTAT_ADD(rx_octets);
7291 ESTAT_ADD(rx_fragments);
7292 ESTAT_ADD(rx_ucast_packets);
7293 ESTAT_ADD(rx_mcast_packets);
7294 ESTAT_ADD(rx_bcast_packets);
7295 ESTAT_ADD(rx_fcs_errors);
7296 ESTAT_ADD(rx_align_errors);
7297 ESTAT_ADD(rx_xon_pause_rcvd);
7298 ESTAT_ADD(rx_xoff_pause_rcvd);
7299 ESTAT_ADD(rx_mac_ctrl_rcvd);
7300 ESTAT_ADD(rx_xoff_entered);
7301 ESTAT_ADD(rx_frame_too_long_errors);
7302 ESTAT_ADD(rx_jabbers);
7303 ESTAT_ADD(rx_undersize_packets);
7304 ESTAT_ADD(rx_in_length_errors);
7305 ESTAT_ADD(rx_out_length_errors);
7306 ESTAT_ADD(rx_64_or_less_octet_packets);
7307 ESTAT_ADD(rx_65_to_127_octet_packets);
7308 ESTAT_ADD(rx_128_to_255_octet_packets);
7309 ESTAT_ADD(rx_256_to_511_octet_packets);
7310 ESTAT_ADD(rx_512_to_1023_octet_packets);
7311 ESTAT_ADD(rx_1024_to_1522_octet_packets);
7312 ESTAT_ADD(rx_1523_to_2047_octet_packets);
7313 ESTAT_ADD(rx_2048_to_4095_octet_packets);
7314 ESTAT_ADD(rx_4096_to_8191_octet_packets);
7315 ESTAT_ADD(rx_8192_to_9022_octet_packets);
7316
7317 ESTAT_ADD(tx_octets);
7318 ESTAT_ADD(tx_collisions);
7319 ESTAT_ADD(tx_xon_sent);
7320 ESTAT_ADD(tx_xoff_sent);
7321 ESTAT_ADD(tx_flow_control);
7322 ESTAT_ADD(tx_mac_errors);
7323 ESTAT_ADD(tx_single_collisions);
7324 ESTAT_ADD(tx_mult_collisions);
7325 ESTAT_ADD(tx_deferred);
7326 ESTAT_ADD(tx_excessive_collisions);
7327 ESTAT_ADD(tx_late_collisions);
7328 ESTAT_ADD(tx_collide_2times);
7329 ESTAT_ADD(tx_collide_3times);
7330 ESTAT_ADD(tx_collide_4times);
7331 ESTAT_ADD(tx_collide_5times);
7332 ESTAT_ADD(tx_collide_6times);
7333 ESTAT_ADD(tx_collide_7times);
7334 ESTAT_ADD(tx_collide_8times);
7335 ESTAT_ADD(tx_collide_9times);
7336 ESTAT_ADD(tx_collide_10times);
7337 ESTAT_ADD(tx_collide_11times);
7338 ESTAT_ADD(tx_collide_12times);
7339 ESTAT_ADD(tx_collide_13times);
7340 ESTAT_ADD(tx_collide_14times);
7341 ESTAT_ADD(tx_collide_15times);
7342 ESTAT_ADD(tx_ucast_packets);
7343 ESTAT_ADD(tx_mcast_packets);
7344 ESTAT_ADD(tx_bcast_packets);
7345 ESTAT_ADD(tx_carrier_sense_errors);
7346 ESTAT_ADD(tx_discards);
7347 ESTAT_ADD(tx_errors);
7348
7349 ESTAT_ADD(dma_writeq_full);
7350 ESTAT_ADD(dma_write_prioq_full);
7351 ESTAT_ADD(rxbds_empty);
7352 ESTAT_ADD(rx_discards);
7353 ESTAT_ADD(rx_errors);
7354 ESTAT_ADD(rx_threshold_hit);
7355
7356 ESTAT_ADD(dma_readq_full);
7357 ESTAT_ADD(dma_read_prioq_full);
7358 ESTAT_ADD(tx_comp_queue_full);
7359
7360 ESTAT_ADD(ring_set_send_prod_index);
7361 ESTAT_ADD(ring_status_update);
7362 ESTAT_ADD(nic_irqs);
7363 ESTAT_ADD(nic_avoided_irqs);
7364 ESTAT_ADD(nic_tx_threshold_hit);
7365
7366 return estats;
7367 }
7368
7369 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
7370 {
7371 struct tg3 *tp = netdev_priv(dev);
7372 struct net_device_stats *stats = &tp->net_stats;
7373 struct net_device_stats *old_stats = &tp->net_stats_prev;
7374 struct tg3_hw_stats *hw_stats = tp->hw_stats;
7375
7376 if (!hw_stats)
7377 return old_stats;
7378
7379 stats->rx_packets = old_stats->rx_packets +
7380 get_stat64(&hw_stats->rx_ucast_packets) +
7381 get_stat64(&hw_stats->rx_mcast_packets) +
7382 get_stat64(&hw_stats->rx_bcast_packets);
7383
7384 stats->tx_packets = old_stats->tx_packets +
7385 get_stat64(&hw_stats->tx_ucast_packets) +
7386 get_stat64(&hw_stats->tx_mcast_packets) +
7387 get_stat64(&hw_stats->tx_bcast_packets);
7388
7389 stats->rx_bytes = old_stats->rx_bytes +
7390 get_stat64(&hw_stats->rx_octets);
7391 stats->tx_bytes = old_stats->tx_bytes +
7392 get_stat64(&hw_stats->tx_octets);
7393
7394 stats->rx_errors = old_stats->rx_errors +
7395 get_stat64(&hw_stats->rx_errors);
7396 stats->tx_errors = old_stats->tx_errors +
7397 get_stat64(&hw_stats->tx_errors) +
7398 get_stat64(&hw_stats->tx_mac_errors) +
7399 get_stat64(&hw_stats->tx_carrier_sense_errors) +
7400 get_stat64(&hw_stats->tx_discards);
7401
7402 stats->multicast = old_stats->multicast +
7403 get_stat64(&hw_stats->rx_mcast_packets);
7404 stats->collisions = old_stats->collisions +
7405 get_stat64(&hw_stats->tx_collisions);
7406
7407 stats->rx_length_errors = old_stats->rx_length_errors +
7408 get_stat64(&hw_stats->rx_frame_too_long_errors) +
7409 get_stat64(&hw_stats->rx_undersize_packets);
7410
7411 stats->rx_over_errors = old_stats->rx_over_errors +
7412 get_stat64(&hw_stats->rxbds_empty);
7413 stats->rx_frame_errors = old_stats->rx_frame_errors +
7414 get_stat64(&hw_stats->rx_align_errors);
7415 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
7416 get_stat64(&hw_stats->tx_discards);
7417 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
7418 get_stat64(&hw_stats->tx_carrier_sense_errors);
7419
7420 stats->rx_crc_errors = old_stats->rx_crc_errors +
7421 calc_crc_errors(tp);
7422
7423 stats->rx_missed_errors = old_stats->rx_missed_errors +
7424 get_stat64(&hw_stats->rx_discards);
7425
7426 return stats;
7427 }
7428
7429 static inline u32 calc_crc(unsigned char *buf, int len)
7430 {
7431 u32 reg;
7432 u32 tmp;
7433 int j, k;
7434
7435 reg = 0xffffffff;
7436
7437 for (j = 0; j < len; j++) {
7438 reg ^= buf[j];
7439
7440 for (k = 0; k < 8; k++) {
7441 tmp = reg & 0x01;
7442
7443 reg >>= 1;
7444
7445 if (tmp) {
7446 reg ^= 0xedb88320;
7447 }
7448 }
7449 }
7450
7451 return ~reg;
7452 }
7453
7454 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
7455 {
7456 /* accept or reject all multicast frames */
7457 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
7458 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
7459 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
7460 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
7461 }
7462
7463 static void __tg3_set_rx_mode(struct net_device *dev)
7464 {
7465 struct tg3 *tp = netdev_priv(dev);
7466 u32 rx_mode;
7467
7468 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
7469 RX_MODE_KEEP_VLAN_TAG);
7470
7471 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
7472 * flag clear.
7473 */
7474 #if TG3_VLAN_TAG_USED
7475 if (!tp->vlgrp &&
7476 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7477 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7478 #else
7479 /* By definition, VLAN is disabled always in this
7480 * case.
7481 */
7482 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7483 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7484 #endif
7485
7486 if (dev->flags & IFF_PROMISC) {
7487 /* Promiscuous mode. */
7488 rx_mode |= RX_MODE_PROMISC;
7489 } else if (dev->flags & IFF_ALLMULTI) {
7490 /* Accept all multicast. */
7491 tg3_set_multi (tp, 1);
7492 } else if (dev->mc_count < 1) {
7493 /* Reject all multicast. */
7494 tg3_set_multi (tp, 0);
7495 } else {
7496 /* Accept one or more multicast(s). */
7497 struct dev_mc_list *mclist;
7498 unsigned int i;
7499 u32 mc_filter[4] = { 0, };
7500 u32 regidx;
7501 u32 bit;
7502 u32 crc;
7503
7504 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
7505 i++, mclist = mclist->next) {
7506
7507 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
7508 bit = ~crc & 0x7f;
7509 regidx = (bit & 0x60) >> 5;
7510 bit &= 0x1f;
7511 mc_filter[regidx] |= (1 << bit);
7512 }
7513
7514 tw32(MAC_HASH_REG_0, mc_filter[0]);
7515 tw32(MAC_HASH_REG_1, mc_filter[1]);
7516 tw32(MAC_HASH_REG_2, mc_filter[2]);
7517 tw32(MAC_HASH_REG_3, mc_filter[3]);
7518 }
7519
7520 if (rx_mode != tp->rx_mode) {
7521 tp->rx_mode = rx_mode;
7522 tw32_f(MAC_RX_MODE, rx_mode);
7523 udelay(10);
7524 }
7525 }
7526
7527 static void tg3_set_rx_mode(struct net_device *dev)
7528 {
7529 struct tg3 *tp = netdev_priv(dev);
7530
7531 if (!netif_running(dev))
7532 return;
7533
7534 tg3_full_lock(tp, 0);
7535 __tg3_set_rx_mode(dev);
7536 tg3_full_unlock(tp);
7537 }
7538
7539 #define TG3_REGDUMP_LEN (32 * 1024)
7540
7541 static int tg3_get_regs_len(struct net_device *dev)
7542 {
7543 return TG3_REGDUMP_LEN;
7544 }
7545
7546 static void tg3_get_regs(struct net_device *dev,
7547 struct ethtool_regs *regs, void *_p)
7548 {
7549 u32 *p = _p;
7550 struct tg3 *tp = netdev_priv(dev);
7551 u8 *orig_p = _p;
7552 int i;
7553
7554 regs->version = 0;
7555
7556 memset(p, 0, TG3_REGDUMP_LEN);
7557
7558 if (tp->link_config.phy_is_low_power)
7559 return;
7560
7561 tg3_full_lock(tp, 0);
7562
7563 #define __GET_REG32(reg) (*(p)++ = tr32(reg))
7564 #define GET_REG32_LOOP(base,len) \
7565 do { p = (u32 *)(orig_p + (base)); \
7566 for (i = 0; i < len; i += 4) \
7567 __GET_REG32((base) + i); \
7568 } while (0)
7569 #define GET_REG32_1(reg) \
7570 do { p = (u32 *)(orig_p + (reg)); \
7571 __GET_REG32((reg)); \
7572 } while (0)
7573
7574 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
7575 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
7576 GET_REG32_LOOP(MAC_MODE, 0x4f0);
7577 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
7578 GET_REG32_1(SNDDATAC_MODE);
7579 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
7580 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
7581 GET_REG32_1(SNDBDC_MODE);
7582 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
7583 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
7584 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
7585 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
7586 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
7587 GET_REG32_1(RCVDCC_MODE);
7588 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
7589 GET_REG32_LOOP(RCVCC_MODE, 0x14);
7590 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
7591 GET_REG32_1(MBFREE_MODE);
7592 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
7593 GET_REG32_LOOP(MEMARB_MODE, 0x10);
7594 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
7595 GET_REG32_LOOP(RDMAC_MODE, 0x08);
7596 GET_REG32_LOOP(WDMAC_MODE, 0x08);
7597 GET_REG32_1(RX_CPU_MODE);
7598 GET_REG32_1(RX_CPU_STATE);
7599 GET_REG32_1(RX_CPU_PGMCTR);
7600 GET_REG32_1(RX_CPU_HWBKPT);
7601 GET_REG32_1(TX_CPU_MODE);
7602 GET_REG32_1(TX_CPU_STATE);
7603 GET_REG32_1(TX_CPU_PGMCTR);
7604 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
7605 GET_REG32_LOOP(FTQ_RESET, 0x120);
7606 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
7607 GET_REG32_1(DMAC_MODE);
7608 GET_REG32_LOOP(GRC_MODE, 0x4c);
7609 if (tp->tg3_flags & TG3_FLAG_NVRAM)
7610 GET_REG32_LOOP(NVRAM_CMD, 0x24);
7611
7612 #undef __GET_REG32
7613 #undef GET_REG32_LOOP
7614 #undef GET_REG32_1
7615
7616 tg3_full_unlock(tp);
7617 }
7618
7619 static int tg3_get_eeprom_len(struct net_device *dev)
7620 {
7621 struct tg3 *tp = netdev_priv(dev);
7622
7623 return tp->nvram_size;
7624 }
7625
7626 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
7627 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val);
7628
7629 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7630 {
7631 struct tg3 *tp = netdev_priv(dev);
7632 int ret;
7633 u8 *pd;
7634 u32 i, offset, len, val, b_offset, b_count;
7635
7636 if (tp->link_config.phy_is_low_power)
7637 return -EAGAIN;
7638
7639 offset = eeprom->offset;
7640 len = eeprom->len;
7641 eeprom->len = 0;
7642
7643 eeprom->magic = TG3_EEPROM_MAGIC;
7644
7645 if (offset & 3) {
7646 /* adjustments to start on required 4 byte boundary */
7647 b_offset = offset & 3;
7648 b_count = 4 - b_offset;
7649 if (b_count > len) {
7650 /* i.e. offset=1 len=2 */
7651 b_count = len;
7652 }
7653 ret = tg3_nvram_read(tp, offset-b_offset, &val);
7654 if (ret)
7655 return ret;
7656 val = cpu_to_le32(val);
7657 memcpy(data, ((char*)&val) + b_offset, b_count);
7658 len -= b_count;
7659 offset += b_count;
7660 eeprom->len += b_count;
7661 }
7662
7663 /* read bytes upto the last 4 byte boundary */
7664 pd = &data[eeprom->len];
7665 for (i = 0; i < (len - (len & 3)); i += 4) {
7666 ret = tg3_nvram_read(tp, offset + i, &val);
7667 if (ret) {
7668 eeprom->len += i;
7669 return ret;
7670 }
7671 val = cpu_to_le32(val);
7672 memcpy(pd + i, &val, 4);
7673 }
7674 eeprom->len += i;
7675
7676 if (len & 3) {
7677 /* read last bytes not ending on 4 byte boundary */
7678 pd = &data[eeprom->len];
7679 b_count = len & 3;
7680 b_offset = offset + len - b_count;
7681 ret = tg3_nvram_read(tp, b_offset, &val);
7682 if (ret)
7683 return ret;
7684 val = cpu_to_le32(val);
7685 memcpy(pd, ((char*)&val), b_count);
7686 eeprom->len += b_count;
7687 }
7688 return 0;
7689 }
7690
7691 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
7692
7693 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7694 {
7695 struct tg3 *tp = netdev_priv(dev);
7696 int ret;
7697 u32 offset, len, b_offset, odd_len, start, end;
7698 u8 *buf;
7699
7700 if (tp->link_config.phy_is_low_power)
7701 return -EAGAIN;
7702
7703 if (eeprom->magic != TG3_EEPROM_MAGIC)
7704 return -EINVAL;
7705
7706 offset = eeprom->offset;
7707 len = eeprom->len;
7708
7709 if ((b_offset = (offset & 3))) {
7710 /* adjustments to start on required 4 byte boundary */
7711 ret = tg3_nvram_read(tp, offset-b_offset, &start);
7712 if (ret)
7713 return ret;
7714 start = cpu_to_le32(start);
7715 len += b_offset;
7716 offset &= ~3;
7717 if (len < 4)
7718 len = 4;
7719 }
7720
7721 odd_len = 0;
7722 if (len & 3) {
7723 /* adjustments to end on required 4 byte boundary */
7724 odd_len = 1;
7725 len = (len + 3) & ~3;
7726 ret = tg3_nvram_read(tp, offset+len-4, &end);
7727 if (ret)
7728 return ret;
7729 end = cpu_to_le32(end);
7730 }
7731
7732 buf = data;
7733 if (b_offset || odd_len) {
7734 buf = kmalloc(len, GFP_KERNEL);
7735 if (buf == 0)
7736 return -ENOMEM;
7737 if (b_offset)
7738 memcpy(buf, &start, 4);
7739 if (odd_len)
7740 memcpy(buf+len-4, &end, 4);
7741 memcpy(buf + b_offset, data, eeprom->len);
7742 }
7743
7744 ret = tg3_nvram_write_block(tp, offset, len, buf);
7745
7746 if (buf != data)
7747 kfree(buf);
7748
7749 return ret;
7750 }
7751
7752 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7753 {
7754 struct tg3 *tp = netdev_priv(dev);
7755
7756 cmd->supported = (SUPPORTED_Autoneg);
7757
7758 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
7759 cmd->supported |= (SUPPORTED_1000baseT_Half |
7760 SUPPORTED_1000baseT_Full);
7761
7762 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
7763 cmd->supported |= (SUPPORTED_100baseT_Half |
7764 SUPPORTED_100baseT_Full |
7765 SUPPORTED_10baseT_Half |
7766 SUPPORTED_10baseT_Full |
7767 SUPPORTED_MII);
7768 cmd->port = PORT_TP;
7769 } else {
7770 cmd->supported |= SUPPORTED_FIBRE;
7771 cmd->port = PORT_FIBRE;
7772 }
7773
7774 cmd->advertising = tp->link_config.advertising;
7775 if (netif_running(dev)) {
7776 cmd->speed = tp->link_config.active_speed;
7777 cmd->duplex = tp->link_config.active_duplex;
7778 }
7779 cmd->phy_address = PHY_ADDR;
7780 cmd->transceiver = 0;
7781 cmd->autoneg = tp->link_config.autoneg;
7782 cmd->maxtxpkt = 0;
7783 cmd->maxrxpkt = 0;
7784 return 0;
7785 }
7786
7787 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7788 {
7789 struct tg3 *tp = netdev_priv(dev);
7790
7791 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
7792 /* These are the only valid advertisement bits allowed. */
7793 if (cmd->autoneg == AUTONEG_ENABLE &&
7794 (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
7795 ADVERTISED_1000baseT_Full |
7796 ADVERTISED_Autoneg |
7797 ADVERTISED_FIBRE)))
7798 return -EINVAL;
7799 /* Fiber can only do SPEED_1000. */
7800 else if ((cmd->autoneg != AUTONEG_ENABLE) &&
7801 (cmd->speed != SPEED_1000))
7802 return -EINVAL;
7803 /* Copper cannot force SPEED_1000. */
7804 } else if ((cmd->autoneg != AUTONEG_ENABLE) &&
7805 (cmd->speed == SPEED_1000))
7806 return -EINVAL;
7807 else if ((cmd->speed == SPEED_1000) &&
7808 (tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
7809 return -EINVAL;
7810
7811 tg3_full_lock(tp, 0);
7812
7813 tp->link_config.autoneg = cmd->autoneg;
7814 if (cmd->autoneg == AUTONEG_ENABLE) {
7815 tp->link_config.advertising = cmd->advertising;
7816 tp->link_config.speed = SPEED_INVALID;
7817 tp->link_config.duplex = DUPLEX_INVALID;
7818 } else {
7819 tp->link_config.advertising = 0;
7820 tp->link_config.speed = cmd->speed;
7821 tp->link_config.duplex = cmd->duplex;
7822 }
7823
7824 if (netif_running(dev))
7825 tg3_setup_phy(tp, 1);
7826
7827 tg3_full_unlock(tp);
7828
7829 return 0;
7830 }
7831
7832 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
7833 {
7834 struct tg3 *tp = netdev_priv(dev);
7835
7836 strcpy(info->driver, DRV_MODULE_NAME);
7837 strcpy(info->version, DRV_MODULE_VERSION);
7838 strcpy(info->fw_version, tp->fw_ver);
7839 strcpy(info->bus_info, pci_name(tp->pdev));
7840 }
7841
7842 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
7843 {
7844 struct tg3 *tp = netdev_priv(dev);
7845
7846 wol->supported = WAKE_MAGIC;
7847 wol->wolopts = 0;
7848 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
7849 wol->wolopts = WAKE_MAGIC;
7850 memset(&wol->sopass, 0, sizeof(wol->sopass));
7851 }
7852
7853 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
7854 {
7855 struct tg3 *tp = netdev_priv(dev);
7856
7857 if (wol->wolopts & ~WAKE_MAGIC)
7858 return -EINVAL;
7859 if ((wol->wolopts & WAKE_MAGIC) &&
7860 tp->tg3_flags2 & TG3_FLG2_PHY_SERDES &&
7861 !(tp->tg3_flags & TG3_FLAG_SERDES_WOL_CAP))
7862 return -EINVAL;
7863
7864 spin_lock_bh(&tp->lock);
7865 if (wol->wolopts & WAKE_MAGIC)
7866 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
7867 else
7868 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
7869 spin_unlock_bh(&tp->lock);
7870
7871 return 0;
7872 }
7873
7874 static u32 tg3_get_msglevel(struct net_device *dev)
7875 {
7876 struct tg3 *tp = netdev_priv(dev);
7877 return tp->msg_enable;
7878 }
7879
7880 static void tg3_set_msglevel(struct net_device *dev, u32 value)
7881 {
7882 struct tg3 *tp = netdev_priv(dev);
7883 tp->msg_enable = value;
7884 }
7885
7886 #if TG3_TSO_SUPPORT != 0
7887 static int tg3_set_tso(struct net_device *dev, u32 value)
7888 {
7889 struct tg3 *tp = netdev_priv(dev);
7890
7891 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7892 if (value)
7893 return -EINVAL;
7894 return 0;
7895 }
7896 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) {
7897 if (value)
7898 dev->features |= NETIF_F_TSO6;
7899 else
7900 dev->features &= ~NETIF_F_TSO6;
7901 }
7902 return ethtool_op_set_tso(dev, value);
7903 }
7904 #endif
7905
7906 static int tg3_nway_reset(struct net_device *dev)
7907 {
7908 struct tg3 *tp = netdev_priv(dev);
7909 u32 bmcr;
7910 int r;
7911
7912 if (!netif_running(dev))
7913 return -EAGAIN;
7914
7915 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
7916 return -EINVAL;
7917
7918 spin_lock_bh(&tp->lock);
7919 r = -EINVAL;
7920 tg3_readphy(tp, MII_BMCR, &bmcr);
7921 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
7922 ((bmcr & BMCR_ANENABLE) ||
7923 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
7924 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
7925 BMCR_ANENABLE);
7926 r = 0;
7927 }
7928 spin_unlock_bh(&tp->lock);
7929
7930 return r;
7931 }
7932
7933 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7934 {
7935 struct tg3 *tp = netdev_priv(dev);
7936
7937 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
7938 ering->rx_mini_max_pending = 0;
7939 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
7940 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
7941 else
7942 ering->rx_jumbo_max_pending = 0;
7943
7944 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
7945
7946 ering->rx_pending = tp->rx_pending;
7947 ering->rx_mini_pending = 0;
7948 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
7949 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
7950 else
7951 ering->rx_jumbo_pending = 0;
7952
7953 ering->tx_pending = tp->tx_pending;
7954 }
7955
7956 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7957 {
7958 struct tg3 *tp = netdev_priv(dev);
7959 int irq_sync = 0, err = 0;
7960
7961 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
7962 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
7963 (ering->tx_pending > TG3_TX_RING_SIZE - 1))
7964 return -EINVAL;
7965
7966 if (netif_running(dev)) {
7967 tg3_netif_stop(tp);
7968 irq_sync = 1;
7969 }
7970
7971 tg3_full_lock(tp, irq_sync);
7972
7973 tp->rx_pending = ering->rx_pending;
7974
7975 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
7976 tp->rx_pending > 63)
7977 tp->rx_pending = 63;
7978 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
7979 tp->tx_pending = ering->tx_pending;
7980
7981 if (netif_running(dev)) {
7982 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7983 err = tg3_restart_hw(tp, 1);
7984 if (!err)
7985 tg3_netif_start(tp);
7986 }
7987
7988 tg3_full_unlock(tp);
7989
7990 return err;
7991 }
7992
7993 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7994 {
7995 struct tg3 *tp = netdev_priv(dev);
7996
7997 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
7998 epause->rx_pause = (tp->tg3_flags & TG3_FLAG_RX_PAUSE) != 0;
7999 epause->tx_pause = (tp->tg3_flags & TG3_FLAG_TX_PAUSE) != 0;
8000 }
8001
8002 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8003 {
8004 struct tg3 *tp = netdev_priv(dev);
8005 int irq_sync = 0, err = 0;
8006
8007 if (netif_running(dev)) {
8008 tg3_netif_stop(tp);
8009 irq_sync = 1;
8010 }
8011
8012 tg3_full_lock(tp, irq_sync);
8013
8014 if (epause->autoneg)
8015 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
8016 else
8017 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
8018 if (epause->rx_pause)
8019 tp->tg3_flags |= TG3_FLAG_RX_PAUSE;
8020 else
8021 tp->tg3_flags &= ~TG3_FLAG_RX_PAUSE;
8022 if (epause->tx_pause)
8023 tp->tg3_flags |= TG3_FLAG_TX_PAUSE;
8024 else
8025 tp->tg3_flags &= ~TG3_FLAG_TX_PAUSE;
8026
8027 if (netif_running(dev)) {
8028 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8029 err = tg3_restart_hw(tp, 1);
8030 if (!err)
8031 tg3_netif_start(tp);
8032 }
8033
8034 tg3_full_unlock(tp);
8035
8036 return err;
8037 }
8038
8039 static u32 tg3_get_rx_csum(struct net_device *dev)
8040 {
8041 struct tg3 *tp = netdev_priv(dev);
8042 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
8043 }
8044
8045 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
8046 {
8047 struct tg3 *tp = netdev_priv(dev);
8048
8049 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8050 if (data != 0)
8051 return -EINVAL;
8052 return 0;
8053 }
8054
8055 spin_lock_bh(&tp->lock);
8056 if (data)
8057 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
8058 else
8059 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
8060 spin_unlock_bh(&tp->lock);
8061
8062 return 0;
8063 }
8064
8065 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
8066 {
8067 struct tg3 *tp = netdev_priv(dev);
8068
8069 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8070 if (data != 0)
8071 return -EINVAL;
8072 return 0;
8073 }
8074
8075 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8076 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8077 ethtool_op_set_tx_hw_csum(dev, data);
8078 else
8079 ethtool_op_set_tx_csum(dev, data);
8080
8081 return 0;
8082 }
8083
8084 static int tg3_get_stats_count (struct net_device *dev)
8085 {
8086 return TG3_NUM_STATS;
8087 }
8088
8089 static int tg3_get_test_count (struct net_device *dev)
8090 {
8091 return TG3_NUM_TEST;
8092 }
8093
8094 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
8095 {
8096 switch (stringset) {
8097 case ETH_SS_STATS:
8098 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
8099 break;
8100 case ETH_SS_TEST:
8101 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
8102 break;
8103 default:
8104 WARN_ON(1); /* we need a WARN() */
8105 break;
8106 }
8107 }
8108
8109 static int tg3_phys_id(struct net_device *dev, u32 data)
8110 {
8111 struct tg3 *tp = netdev_priv(dev);
8112 int i;
8113
8114 if (!netif_running(tp->dev))
8115 return -EAGAIN;
8116
8117 if (data == 0)
8118 data = 2;
8119
8120 for (i = 0; i < (data * 2); i++) {
8121 if ((i % 2) == 0)
8122 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8123 LED_CTRL_1000MBPS_ON |
8124 LED_CTRL_100MBPS_ON |
8125 LED_CTRL_10MBPS_ON |
8126 LED_CTRL_TRAFFIC_OVERRIDE |
8127 LED_CTRL_TRAFFIC_BLINK |
8128 LED_CTRL_TRAFFIC_LED);
8129
8130 else
8131 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8132 LED_CTRL_TRAFFIC_OVERRIDE);
8133
8134 if (msleep_interruptible(500))
8135 break;
8136 }
8137 tw32(MAC_LED_CTRL, tp->led_ctrl);
8138 return 0;
8139 }
8140
8141 static void tg3_get_ethtool_stats (struct net_device *dev,
8142 struct ethtool_stats *estats, u64 *tmp_stats)
8143 {
8144 struct tg3 *tp = netdev_priv(dev);
8145 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
8146 }
8147
8148 #define NVRAM_TEST_SIZE 0x100
8149 #define NVRAM_SELFBOOT_FORMAT1_SIZE 0x14
8150
8151 static int tg3_test_nvram(struct tg3 *tp)
8152 {
8153 u32 *buf, csum, magic;
8154 int i, j, err = 0, size;
8155
8156 if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
8157 return -EIO;
8158
8159 if (magic == TG3_EEPROM_MAGIC)
8160 size = NVRAM_TEST_SIZE;
8161 else if ((magic & 0xff000000) == 0xa5000000) {
8162 if ((magic & 0xe00000) == 0x200000)
8163 size = NVRAM_SELFBOOT_FORMAT1_SIZE;
8164 else
8165 return 0;
8166 } else
8167 return -EIO;
8168
8169 buf = kmalloc(size, GFP_KERNEL);
8170 if (buf == NULL)
8171 return -ENOMEM;
8172
8173 err = -EIO;
8174 for (i = 0, j = 0; i < size; i += 4, j++) {
8175 u32 val;
8176
8177 if ((err = tg3_nvram_read(tp, i, &val)) != 0)
8178 break;
8179 buf[j] = cpu_to_le32(val);
8180 }
8181 if (i < size)
8182 goto out;
8183
8184 /* Selfboot format */
8185 if (cpu_to_be32(buf[0]) != TG3_EEPROM_MAGIC) {
8186 u8 *buf8 = (u8 *) buf, csum8 = 0;
8187
8188 for (i = 0; i < size; i++)
8189 csum8 += buf8[i];
8190
8191 if (csum8 == 0) {
8192 err = 0;
8193 goto out;
8194 }
8195
8196 err = -EIO;
8197 goto out;
8198 }
8199
8200 /* Bootstrap checksum at offset 0x10 */
8201 csum = calc_crc((unsigned char *) buf, 0x10);
8202 if(csum != cpu_to_le32(buf[0x10/4]))
8203 goto out;
8204
8205 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
8206 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
8207 if (csum != cpu_to_le32(buf[0xfc/4]))
8208 goto out;
8209
8210 err = 0;
8211
8212 out:
8213 kfree(buf);
8214 return err;
8215 }
8216
8217 #define TG3_SERDES_TIMEOUT_SEC 2
8218 #define TG3_COPPER_TIMEOUT_SEC 6
8219
8220 static int tg3_test_link(struct tg3 *tp)
8221 {
8222 int i, max;
8223
8224 if (!netif_running(tp->dev))
8225 return -ENODEV;
8226
8227 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
8228 max = TG3_SERDES_TIMEOUT_SEC;
8229 else
8230 max = TG3_COPPER_TIMEOUT_SEC;
8231
8232 for (i = 0; i < max; i++) {
8233 if (netif_carrier_ok(tp->dev))
8234 return 0;
8235
8236 if (msleep_interruptible(1000))
8237 break;
8238 }
8239
8240 return -EIO;
8241 }
8242
8243 /* Only test the commonly used registers */
8244 static int tg3_test_registers(struct tg3 *tp)
8245 {
8246 int i, is_5705;
8247 u32 offset, read_mask, write_mask, val, save_val, read_val;
8248 static struct {
8249 u16 offset;
8250 u16 flags;
8251 #define TG3_FL_5705 0x1
8252 #define TG3_FL_NOT_5705 0x2
8253 #define TG3_FL_NOT_5788 0x4
8254 u32 read_mask;
8255 u32 write_mask;
8256 } reg_tbl[] = {
8257 /* MAC Control Registers */
8258 { MAC_MODE, TG3_FL_NOT_5705,
8259 0x00000000, 0x00ef6f8c },
8260 { MAC_MODE, TG3_FL_5705,
8261 0x00000000, 0x01ef6b8c },
8262 { MAC_STATUS, TG3_FL_NOT_5705,
8263 0x03800107, 0x00000000 },
8264 { MAC_STATUS, TG3_FL_5705,
8265 0x03800100, 0x00000000 },
8266 { MAC_ADDR_0_HIGH, 0x0000,
8267 0x00000000, 0x0000ffff },
8268 { MAC_ADDR_0_LOW, 0x0000,
8269 0x00000000, 0xffffffff },
8270 { MAC_RX_MTU_SIZE, 0x0000,
8271 0x00000000, 0x0000ffff },
8272 { MAC_TX_MODE, 0x0000,
8273 0x00000000, 0x00000070 },
8274 { MAC_TX_LENGTHS, 0x0000,
8275 0x00000000, 0x00003fff },
8276 { MAC_RX_MODE, TG3_FL_NOT_5705,
8277 0x00000000, 0x000007fc },
8278 { MAC_RX_MODE, TG3_FL_5705,
8279 0x00000000, 0x000007dc },
8280 { MAC_HASH_REG_0, 0x0000,
8281 0x00000000, 0xffffffff },
8282 { MAC_HASH_REG_1, 0x0000,
8283 0x00000000, 0xffffffff },
8284 { MAC_HASH_REG_2, 0x0000,
8285 0x00000000, 0xffffffff },
8286 { MAC_HASH_REG_3, 0x0000,
8287 0x00000000, 0xffffffff },
8288
8289 /* Receive Data and Receive BD Initiator Control Registers. */
8290 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
8291 0x00000000, 0xffffffff },
8292 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
8293 0x00000000, 0xffffffff },
8294 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
8295 0x00000000, 0x00000003 },
8296 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
8297 0x00000000, 0xffffffff },
8298 { RCVDBDI_STD_BD+0, 0x0000,
8299 0x00000000, 0xffffffff },
8300 { RCVDBDI_STD_BD+4, 0x0000,
8301 0x00000000, 0xffffffff },
8302 { RCVDBDI_STD_BD+8, 0x0000,
8303 0x00000000, 0xffff0002 },
8304 { RCVDBDI_STD_BD+0xc, 0x0000,
8305 0x00000000, 0xffffffff },
8306
8307 /* Receive BD Initiator Control Registers. */
8308 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
8309 0x00000000, 0xffffffff },
8310 { RCVBDI_STD_THRESH, TG3_FL_5705,
8311 0x00000000, 0x000003ff },
8312 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
8313 0x00000000, 0xffffffff },
8314
8315 /* Host Coalescing Control Registers. */
8316 { HOSTCC_MODE, TG3_FL_NOT_5705,
8317 0x00000000, 0x00000004 },
8318 { HOSTCC_MODE, TG3_FL_5705,
8319 0x00000000, 0x000000f6 },
8320 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
8321 0x00000000, 0xffffffff },
8322 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
8323 0x00000000, 0x000003ff },
8324 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
8325 0x00000000, 0xffffffff },
8326 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
8327 0x00000000, 0x000003ff },
8328 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
8329 0x00000000, 0xffffffff },
8330 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8331 0x00000000, 0x000000ff },
8332 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
8333 0x00000000, 0xffffffff },
8334 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8335 0x00000000, 0x000000ff },
8336 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
8337 0x00000000, 0xffffffff },
8338 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
8339 0x00000000, 0xffffffff },
8340 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8341 0x00000000, 0xffffffff },
8342 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8343 0x00000000, 0x000000ff },
8344 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8345 0x00000000, 0xffffffff },
8346 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8347 0x00000000, 0x000000ff },
8348 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
8349 0x00000000, 0xffffffff },
8350 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
8351 0x00000000, 0xffffffff },
8352 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
8353 0x00000000, 0xffffffff },
8354 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
8355 0x00000000, 0xffffffff },
8356 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
8357 0x00000000, 0xffffffff },
8358 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
8359 0xffffffff, 0x00000000 },
8360 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
8361 0xffffffff, 0x00000000 },
8362
8363 /* Buffer Manager Control Registers. */
8364 { BUFMGR_MB_POOL_ADDR, 0x0000,
8365 0x00000000, 0x007fff80 },
8366 { BUFMGR_MB_POOL_SIZE, 0x0000,
8367 0x00000000, 0x007fffff },
8368 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
8369 0x00000000, 0x0000003f },
8370 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
8371 0x00000000, 0x000001ff },
8372 { BUFMGR_MB_HIGH_WATER, 0x0000,
8373 0x00000000, 0x000001ff },
8374 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
8375 0xffffffff, 0x00000000 },
8376 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
8377 0xffffffff, 0x00000000 },
8378
8379 /* Mailbox Registers */
8380 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
8381 0x00000000, 0x000001ff },
8382 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
8383 0x00000000, 0x000001ff },
8384 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
8385 0x00000000, 0x000007ff },
8386 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
8387 0x00000000, 0x000001ff },
8388
8389 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
8390 };
8391
8392 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8393 is_5705 = 1;
8394 else
8395 is_5705 = 0;
8396
8397 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
8398 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
8399 continue;
8400
8401 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
8402 continue;
8403
8404 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8405 (reg_tbl[i].flags & TG3_FL_NOT_5788))
8406 continue;
8407
8408 offset = (u32) reg_tbl[i].offset;
8409 read_mask = reg_tbl[i].read_mask;
8410 write_mask = reg_tbl[i].write_mask;
8411
8412 /* Save the original register content */
8413 save_val = tr32(offset);
8414
8415 /* Determine the read-only value. */
8416 read_val = save_val & read_mask;
8417
8418 /* Write zero to the register, then make sure the read-only bits
8419 * are not changed and the read/write bits are all zeros.
8420 */
8421 tw32(offset, 0);
8422
8423 val = tr32(offset);
8424
8425 /* Test the read-only and read/write bits. */
8426 if (((val & read_mask) != read_val) || (val & write_mask))
8427 goto out;
8428
8429 /* Write ones to all the bits defined by RdMask and WrMask, then
8430 * make sure the read-only bits are not changed and the
8431 * read/write bits are all ones.
8432 */
8433 tw32(offset, read_mask | write_mask);
8434
8435 val = tr32(offset);
8436
8437 /* Test the read-only bits. */
8438 if ((val & read_mask) != read_val)
8439 goto out;
8440
8441 /* Test the read/write bits. */
8442 if ((val & write_mask) != write_mask)
8443 goto out;
8444
8445 tw32(offset, save_val);
8446 }
8447
8448 return 0;
8449
8450 out:
8451 printk(KERN_ERR PFX "Register test failed at offset %x\n", offset);
8452 tw32(offset, save_val);
8453 return -EIO;
8454 }
8455
8456 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
8457 {
8458 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
8459 int i;
8460 u32 j;
8461
8462 for (i = 0; i < sizeof(test_pattern)/sizeof(u32); i++) {
8463 for (j = 0; j < len; j += 4) {
8464 u32 val;
8465
8466 tg3_write_mem(tp, offset + j, test_pattern[i]);
8467 tg3_read_mem(tp, offset + j, &val);
8468 if (val != test_pattern[i])
8469 return -EIO;
8470 }
8471 }
8472 return 0;
8473 }
8474
8475 static int tg3_test_memory(struct tg3 *tp)
8476 {
8477 static struct mem_entry {
8478 u32 offset;
8479 u32 len;
8480 } mem_tbl_570x[] = {
8481 { 0x00000000, 0x00b50},
8482 { 0x00002000, 0x1c000},
8483 { 0xffffffff, 0x00000}
8484 }, mem_tbl_5705[] = {
8485 { 0x00000100, 0x0000c},
8486 { 0x00000200, 0x00008},
8487 { 0x00004000, 0x00800},
8488 { 0x00006000, 0x01000},
8489 { 0x00008000, 0x02000},
8490 { 0x00010000, 0x0e000},
8491 { 0xffffffff, 0x00000}
8492 }, mem_tbl_5755[] = {
8493 { 0x00000200, 0x00008},
8494 { 0x00004000, 0x00800},
8495 { 0x00006000, 0x00800},
8496 { 0x00008000, 0x02000},
8497 { 0x00010000, 0x0c000},
8498 { 0xffffffff, 0x00000}
8499 };
8500 struct mem_entry *mem_tbl;
8501 int err = 0;
8502 int i;
8503
8504 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
8505 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8506 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8507 mem_tbl = mem_tbl_5755;
8508 else
8509 mem_tbl = mem_tbl_5705;
8510 } else
8511 mem_tbl = mem_tbl_570x;
8512
8513 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
8514 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
8515 mem_tbl[i].len)) != 0)
8516 break;
8517 }
8518
8519 return err;
8520 }
8521
8522 #define TG3_MAC_LOOPBACK 0
8523 #define TG3_PHY_LOOPBACK 1
8524
8525 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
8526 {
8527 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
8528 u32 desc_idx;
8529 struct sk_buff *skb, *rx_skb;
8530 u8 *tx_data;
8531 dma_addr_t map;
8532 int num_pkts, tx_len, rx_len, i, err;
8533 struct tg3_rx_buffer_desc *desc;
8534
8535 if (loopback_mode == TG3_MAC_LOOPBACK) {
8536 /* HW errata - mac loopback fails in some cases on 5780.
8537 * Normal traffic and PHY loopback are not affected by
8538 * errata.
8539 */
8540 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
8541 return 0;
8542
8543 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8544 MAC_MODE_PORT_INT_LPBACK | MAC_MODE_LINK_POLARITY |
8545 MAC_MODE_PORT_MODE_GMII;
8546 tw32(MAC_MODE, mac_mode);
8547 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
8548 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK | BMCR_FULLDPLX |
8549 BMCR_SPEED1000);
8550 udelay(40);
8551 /* reset to prevent losing 1st rx packet intermittently */
8552 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
8553 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8554 udelay(10);
8555 tw32_f(MAC_RX_MODE, tp->rx_mode);
8556 }
8557 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8558 MAC_MODE_LINK_POLARITY | MAC_MODE_PORT_MODE_GMII;
8559 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
8560 mac_mode &= ~MAC_MODE_LINK_POLARITY;
8561 tg3_writephy(tp, MII_TG3_EXT_CTRL,
8562 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
8563 }
8564 tw32(MAC_MODE, mac_mode);
8565 }
8566 else
8567 return -EINVAL;
8568
8569 err = -EIO;
8570
8571 tx_len = 1514;
8572 skb = netdev_alloc_skb(tp->dev, tx_len);
8573 if (!skb)
8574 return -ENOMEM;
8575
8576 tx_data = skb_put(skb, tx_len);
8577 memcpy(tx_data, tp->dev->dev_addr, 6);
8578 memset(tx_data + 6, 0x0, 8);
8579
8580 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
8581
8582 for (i = 14; i < tx_len; i++)
8583 tx_data[i] = (u8) (i & 0xff);
8584
8585 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
8586
8587 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8588 HOSTCC_MODE_NOW);
8589
8590 udelay(10);
8591
8592 rx_start_idx = tp->hw_status->idx[0].rx_producer;
8593
8594 num_pkts = 0;
8595
8596 tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
8597
8598 tp->tx_prod++;
8599 num_pkts++;
8600
8601 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
8602 tp->tx_prod);
8603 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
8604
8605 udelay(10);
8606
8607 for (i = 0; i < 10; i++) {
8608 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8609 HOSTCC_MODE_NOW);
8610
8611 udelay(10);
8612
8613 tx_idx = tp->hw_status->idx[0].tx_consumer;
8614 rx_idx = tp->hw_status->idx[0].rx_producer;
8615 if ((tx_idx == tp->tx_prod) &&
8616 (rx_idx == (rx_start_idx + num_pkts)))
8617 break;
8618 }
8619
8620 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
8621 dev_kfree_skb(skb);
8622
8623 if (tx_idx != tp->tx_prod)
8624 goto out;
8625
8626 if (rx_idx != rx_start_idx + num_pkts)
8627 goto out;
8628
8629 desc = &tp->rx_rcb[rx_start_idx];
8630 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
8631 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
8632 if (opaque_key != RXD_OPAQUE_RING_STD)
8633 goto out;
8634
8635 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
8636 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
8637 goto out;
8638
8639 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
8640 if (rx_len != tx_len)
8641 goto out;
8642
8643 rx_skb = tp->rx_std_buffers[desc_idx].skb;
8644
8645 map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
8646 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
8647
8648 for (i = 14; i < tx_len; i++) {
8649 if (*(rx_skb->data + i) != (u8) (i & 0xff))
8650 goto out;
8651 }
8652 err = 0;
8653
8654 /* tg3_free_rings will unmap and free the rx_skb */
8655 out:
8656 return err;
8657 }
8658
8659 #define TG3_MAC_LOOPBACK_FAILED 1
8660 #define TG3_PHY_LOOPBACK_FAILED 2
8661 #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
8662 TG3_PHY_LOOPBACK_FAILED)
8663
8664 static int tg3_test_loopback(struct tg3 *tp)
8665 {
8666 int err = 0;
8667
8668 if (!netif_running(tp->dev))
8669 return TG3_LOOPBACK_FAILED;
8670
8671 err = tg3_reset_hw(tp, 1);
8672 if (err)
8673 return TG3_LOOPBACK_FAILED;
8674
8675 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
8676 err |= TG3_MAC_LOOPBACK_FAILED;
8677 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8678 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
8679 err |= TG3_PHY_LOOPBACK_FAILED;
8680 }
8681
8682 return err;
8683 }
8684
8685 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
8686 u64 *data)
8687 {
8688 struct tg3 *tp = netdev_priv(dev);
8689
8690 if (tp->link_config.phy_is_low_power)
8691 tg3_set_power_state(tp, PCI_D0);
8692
8693 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
8694
8695 if (tg3_test_nvram(tp) != 0) {
8696 etest->flags |= ETH_TEST_FL_FAILED;
8697 data[0] = 1;
8698 }
8699 if (tg3_test_link(tp) != 0) {
8700 etest->flags |= ETH_TEST_FL_FAILED;
8701 data[1] = 1;
8702 }
8703 if (etest->flags & ETH_TEST_FL_OFFLINE) {
8704 int err, irq_sync = 0;
8705
8706 if (netif_running(dev)) {
8707 tg3_netif_stop(tp);
8708 irq_sync = 1;
8709 }
8710
8711 tg3_full_lock(tp, irq_sync);
8712
8713 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
8714 err = tg3_nvram_lock(tp);
8715 tg3_halt_cpu(tp, RX_CPU_BASE);
8716 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8717 tg3_halt_cpu(tp, TX_CPU_BASE);
8718 if (!err)
8719 tg3_nvram_unlock(tp);
8720
8721 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8722 tg3_phy_reset(tp);
8723
8724 if (tg3_test_registers(tp) != 0) {
8725 etest->flags |= ETH_TEST_FL_FAILED;
8726 data[2] = 1;
8727 }
8728 if (tg3_test_memory(tp) != 0) {
8729 etest->flags |= ETH_TEST_FL_FAILED;
8730 data[3] = 1;
8731 }
8732 if ((data[4] = tg3_test_loopback(tp)) != 0)
8733 etest->flags |= ETH_TEST_FL_FAILED;
8734
8735 tg3_full_unlock(tp);
8736
8737 if (tg3_test_interrupt(tp) != 0) {
8738 etest->flags |= ETH_TEST_FL_FAILED;
8739 data[5] = 1;
8740 }
8741
8742 tg3_full_lock(tp, 0);
8743
8744 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8745 if (netif_running(dev)) {
8746 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8747 if (!tg3_restart_hw(tp, 1))
8748 tg3_netif_start(tp);
8749 }
8750
8751 tg3_full_unlock(tp);
8752 }
8753 if (tp->link_config.phy_is_low_power)
8754 tg3_set_power_state(tp, PCI_D3hot);
8755
8756 }
8757
8758 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
8759 {
8760 struct mii_ioctl_data *data = if_mii(ifr);
8761 struct tg3 *tp = netdev_priv(dev);
8762 int err;
8763
8764 switch(cmd) {
8765 case SIOCGMIIPHY:
8766 data->phy_id = PHY_ADDR;
8767
8768 /* fallthru */
8769 case SIOCGMIIREG: {
8770 u32 mii_regval;
8771
8772 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8773 break; /* We have no PHY */
8774
8775 if (tp->link_config.phy_is_low_power)
8776 return -EAGAIN;
8777
8778 spin_lock_bh(&tp->lock);
8779 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
8780 spin_unlock_bh(&tp->lock);
8781
8782 data->val_out = mii_regval;
8783
8784 return err;
8785 }
8786
8787 case SIOCSMIIREG:
8788 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8789 break; /* We have no PHY */
8790
8791 if (!capable(CAP_NET_ADMIN))
8792 return -EPERM;
8793
8794 if (tp->link_config.phy_is_low_power)
8795 return -EAGAIN;
8796
8797 spin_lock_bh(&tp->lock);
8798 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
8799 spin_unlock_bh(&tp->lock);
8800
8801 return err;
8802
8803 default:
8804 /* do nothing */
8805 break;
8806 }
8807 return -EOPNOTSUPP;
8808 }
8809
8810 #if TG3_VLAN_TAG_USED
8811 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
8812 {
8813 struct tg3 *tp = netdev_priv(dev);
8814
8815 if (netif_running(dev))
8816 tg3_netif_stop(tp);
8817
8818 tg3_full_lock(tp, 0);
8819
8820 tp->vlgrp = grp;
8821
8822 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
8823 __tg3_set_rx_mode(dev);
8824
8825 tg3_full_unlock(tp);
8826
8827 if (netif_running(dev))
8828 tg3_netif_start(tp);
8829 }
8830
8831 static void tg3_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
8832 {
8833 struct tg3 *tp = netdev_priv(dev);
8834
8835 if (netif_running(dev))
8836 tg3_netif_stop(tp);
8837
8838 tg3_full_lock(tp, 0);
8839 if (tp->vlgrp)
8840 tp->vlgrp->vlan_devices[vid] = NULL;
8841 tg3_full_unlock(tp);
8842
8843 if (netif_running(dev))
8844 tg3_netif_start(tp);
8845 }
8846 #endif
8847
8848 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
8849 {
8850 struct tg3 *tp = netdev_priv(dev);
8851
8852 memcpy(ec, &tp->coal, sizeof(*ec));
8853 return 0;
8854 }
8855
8856 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
8857 {
8858 struct tg3 *tp = netdev_priv(dev);
8859 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
8860 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
8861
8862 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8863 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
8864 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
8865 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
8866 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
8867 }
8868
8869 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
8870 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
8871 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
8872 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
8873 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
8874 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
8875 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
8876 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
8877 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
8878 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
8879 return -EINVAL;
8880
8881 /* No rx interrupts will be generated if both are zero */
8882 if ((ec->rx_coalesce_usecs == 0) &&
8883 (ec->rx_max_coalesced_frames == 0))
8884 return -EINVAL;
8885
8886 /* No tx interrupts will be generated if both are zero */
8887 if ((ec->tx_coalesce_usecs == 0) &&
8888 (ec->tx_max_coalesced_frames == 0))
8889 return -EINVAL;
8890
8891 /* Only copy relevant parameters, ignore all others. */
8892 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
8893 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
8894 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
8895 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
8896 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
8897 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
8898 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
8899 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
8900 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
8901
8902 if (netif_running(dev)) {
8903 tg3_full_lock(tp, 0);
8904 __tg3_set_coalesce(tp, &tp->coal);
8905 tg3_full_unlock(tp);
8906 }
8907 return 0;
8908 }
8909
8910 static const struct ethtool_ops tg3_ethtool_ops = {
8911 .get_settings = tg3_get_settings,
8912 .set_settings = tg3_set_settings,
8913 .get_drvinfo = tg3_get_drvinfo,
8914 .get_regs_len = tg3_get_regs_len,
8915 .get_regs = tg3_get_regs,
8916 .get_wol = tg3_get_wol,
8917 .set_wol = tg3_set_wol,
8918 .get_msglevel = tg3_get_msglevel,
8919 .set_msglevel = tg3_set_msglevel,
8920 .nway_reset = tg3_nway_reset,
8921 .get_link = ethtool_op_get_link,
8922 .get_eeprom_len = tg3_get_eeprom_len,
8923 .get_eeprom = tg3_get_eeprom,
8924 .set_eeprom = tg3_set_eeprom,
8925 .get_ringparam = tg3_get_ringparam,
8926 .set_ringparam = tg3_set_ringparam,
8927 .get_pauseparam = tg3_get_pauseparam,
8928 .set_pauseparam = tg3_set_pauseparam,
8929 .get_rx_csum = tg3_get_rx_csum,
8930 .set_rx_csum = tg3_set_rx_csum,
8931 .get_tx_csum = ethtool_op_get_tx_csum,
8932 .set_tx_csum = tg3_set_tx_csum,
8933 .get_sg = ethtool_op_get_sg,
8934 .set_sg = ethtool_op_set_sg,
8935 #if TG3_TSO_SUPPORT != 0
8936 .get_tso = ethtool_op_get_tso,
8937 .set_tso = tg3_set_tso,
8938 #endif
8939 .self_test_count = tg3_get_test_count,
8940 .self_test = tg3_self_test,
8941 .get_strings = tg3_get_strings,
8942 .phys_id = tg3_phys_id,
8943 .get_stats_count = tg3_get_stats_count,
8944 .get_ethtool_stats = tg3_get_ethtool_stats,
8945 .get_coalesce = tg3_get_coalesce,
8946 .set_coalesce = tg3_set_coalesce,
8947 .get_perm_addr = ethtool_op_get_perm_addr,
8948 };
8949
8950 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
8951 {
8952 u32 cursize, val, magic;
8953
8954 tp->nvram_size = EEPROM_CHIP_SIZE;
8955
8956 if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
8957 return;
8958
8959 if ((magic != TG3_EEPROM_MAGIC) && ((magic & 0xff000000) != 0xa5000000))
8960 return;
8961
8962 /*
8963 * Size the chip by reading offsets at increasing powers of two.
8964 * When we encounter our validation signature, we know the addressing
8965 * has wrapped around, and thus have our chip size.
8966 */
8967 cursize = 0x10;
8968
8969 while (cursize < tp->nvram_size) {
8970 if (tg3_nvram_read_swab(tp, cursize, &val) != 0)
8971 return;
8972
8973 if (val == magic)
8974 break;
8975
8976 cursize <<= 1;
8977 }
8978
8979 tp->nvram_size = cursize;
8980 }
8981
8982 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
8983 {
8984 u32 val;
8985
8986 if (tg3_nvram_read_swab(tp, 0, &val) != 0)
8987 return;
8988
8989 /* Selfboot format */
8990 if (val != TG3_EEPROM_MAGIC) {
8991 tg3_get_eeprom_size(tp);
8992 return;
8993 }
8994
8995 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
8996 if (val != 0) {
8997 tp->nvram_size = (val >> 16) * 1024;
8998 return;
8999 }
9000 }
9001 tp->nvram_size = 0x20000;
9002 }
9003
9004 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
9005 {
9006 u32 nvcfg1;
9007
9008 nvcfg1 = tr32(NVRAM_CFG1);
9009 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
9010 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9011 }
9012 else {
9013 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9014 tw32(NVRAM_CFG1, nvcfg1);
9015 }
9016
9017 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
9018 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
9019 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
9020 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
9021 tp->nvram_jedecnum = JEDEC_ATMEL;
9022 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9023 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9024 break;
9025 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
9026 tp->nvram_jedecnum = JEDEC_ATMEL;
9027 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
9028 break;
9029 case FLASH_VENDOR_ATMEL_EEPROM:
9030 tp->nvram_jedecnum = JEDEC_ATMEL;
9031 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9032 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9033 break;
9034 case FLASH_VENDOR_ST:
9035 tp->nvram_jedecnum = JEDEC_ST;
9036 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
9037 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9038 break;
9039 case FLASH_VENDOR_SAIFUN:
9040 tp->nvram_jedecnum = JEDEC_SAIFUN;
9041 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
9042 break;
9043 case FLASH_VENDOR_SST_SMALL:
9044 case FLASH_VENDOR_SST_LARGE:
9045 tp->nvram_jedecnum = JEDEC_SST;
9046 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
9047 break;
9048 }
9049 }
9050 else {
9051 tp->nvram_jedecnum = JEDEC_ATMEL;
9052 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9053 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9054 }
9055 }
9056
9057 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
9058 {
9059 u32 nvcfg1;
9060
9061 nvcfg1 = tr32(NVRAM_CFG1);
9062
9063 /* NVRAM protection for TPM */
9064 if (nvcfg1 & (1 << 27))
9065 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
9066
9067 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9068 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
9069 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
9070 tp->nvram_jedecnum = JEDEC_ATMEL;
9071 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9072 break;
9073 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9074 tp->nvram_jedecnum = JEDEC_ATMEL;
9075 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9076 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9077 break;
9078 case FLASH_5752VENDOR_ST_M45PE10:
9079 case FLASH_5752VENDOR_ST_M45PE20:
9080 case FLASH_5752VENDOR_ST_M45PE40:
9081 tp->nvram_jedecnum = JEDEC_ST;
9082 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9083 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9084 break;
9085 }
9086
9087 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
9088 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
9089 case FLASH_5752PAGE_SIZE_256:
9090 tp->nvram_pagesize = 256;
9091 break;
9092 case FLASH_5752PAGE_SIZE_512:
9093 tp->nvram_pagesize = 512;
9094 break;
9095 case FLASH_5752PAGE_SIZE_1K:
9096 tp->nvram_pagesize = 1024;
9097 break;
9098 case FLASH_5752PAGE_SIZE_2K:
9099 tp->nvram_pagesize = 2048;
9100 break;
9101 case FLASH_5752PAGE_SIZE_4K:
9102 tp->nvram_pagesize = 4096;
9103 break;
9104 case FLASH_5752PAGE_SIZE_264:
9105 tp->nvram_pagesize = 264;
9106 break;
9107 }
9108 }
9109 else {
9110 /* For eeprom, set pagesize to maximum eeprom size */
9111 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9112
9113 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9114 tw32(NVRAM_CFG1, nvcfg1);
9115 }
9116 }
9117
9118 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
9119 {
9120 u32 nvcfg1;
9121
9122 nvcfg1 = tr32(NVRAM_CFG1);
9123
9124 /* NVRAM protection for TPM */
9125 if (nvcfg1 & (1 << 27))
9126 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
9127
9128 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9129 case FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ:
9130 case FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ:
9131 tp->nvram_jedecnum = JEDEC_ATMEL;
9132 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9133 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9134
9135 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9136 tw32(NVRAM_CFG1, nvcfg1);
9137 break;
9138 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9139 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9140 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9141 case FLASH_5755VENDOR_ATMEL_FLASH_3:
9142 case FLASH_5755VENDOR_ATMEL_FLASH_4:
9143 tp->nvram_jedecnum = JEDEC_ATMEL;
9144 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9145 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9146 tp->nvram_pagesize = 264;
9147 break;
9148 case FLASH_5752VENDOR_ST_M45PE10:
9149 case FLASH_5752VENDOR_ST_M45PE20:
9150 case FLASH_5752VENDOR_ST_M45PE40:
9151 tp->nvram_jedecnum = JEDEC_ST;
9152 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9153 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9154 tp->nvram_pagesize = 256;
9155 break;
9156 }
9157 }
9158
9159 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
9160 {
9161 u32 nvcfg1;
9162
9163 nvcfg1 = tr32(NVRAM_CFG1);
9164
9165 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9166 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
9167 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
9168 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
9169 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
9170 tp->nvram_jedecnum = JEDEC_ATMEL;
9171 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9172 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9173
9174 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9175 tw32(NVRAM_CFG1, nvcfg1);
9176 break;
9177 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9178 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9179 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9180 case FLASH_5755VENDOR_ATMEL_FLASH_3:
9181 tp->nvram_jedecnum = JEDEC_ATMEL;
9182 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9183 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9184 tp->nvram_pagesize = 264;
9185 break;
9186 case FLASH_5752VENDOR_ST_M45PE10:
9187 case FLASH_5752VENDOR_ST_M45PE20:
9188 case FLASH_5752VENDOR_ST_M45PE40:
9189 tp->nvram_jedecnum = JEDEC_ST;
9190 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9191 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9192 tp->nvram_pagesize = 256;
9193 break;
9194 }
9195 }
9196
9197 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
9198 static void __devinit tg3_nvram_init(struct tg3 *tp)
9199 {
9200 int j;
9201
9202 tw32_f(GRC_EEPROM_ADDR,
9203 (EEPROM_ADDR_FSM_RESET |
9204 (EEPROM_DEFAULT_CLOCK_PERIOD <<
9205 EEPROM_ADDR_CLKPERD_SHIFT)));
9206
9207 /* XXX schedule_timeout() ... */
9208 for (j = 0; j < 100; j++)
9209 udelay(10);
9210
9211 /* Enable seeprom accesses. */
9212 tw32_f(GRC_LOCAL_CTRL,
9213 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
9214 udelay(100);
9215
9216 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
9217 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
9218 tp->tg3_flags |= TG3_FLAG_NVRAM;
9219
9220 if (tg3_nvram_lock(tp)) {
9221 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
9222 "tg3_nvram_init failed.\n", tp->dev->name);
9223 return;
9224 }
9225 tg3_enable_nvram_access(tp);
9226
9227 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
9228 tg3_get_5752_nvram_info(tp);
9229 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
9230 tg3_get_5755_nvram_info(tp);
9231 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
9232 tg3_get_5787_nvram_info(tp);
9233 else
9234 tg3_get_nvram_info(tp);
9235
9236 tg3_get_nvram_size(tp);
9237
9238 tg3_disable_nvram_access(tp);
9239 tg3_nvram_unlock(tp);
9240
9241 } else {
9242 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
9243
9244 tg3_get_eeprom_size(tp);
9245 }
9246 }
9247
9248 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
9249 u32 offset, u32 *val)
9250 {
9251 u32 tmp;
9252 int i;
9253
9254 if (offset > EEPROM_ADDR_ADDR_MASK ||
9255 (offset % 4) != 0)
9256 return -EINVAL;
9257
9258 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
9259 EEPROM_ADDR_DEVID_MASK |
9260 EEPROM_ADDR_READ);
9261 tw32(GRC_EEPROM_ADDR,
9262 tmp |
9263 (0 << EEPROM_ADDR_DEVID_SHIFT) |
9264 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
9265 EEPROM_ADDR_ADDR_MASK) |
9266 EEPROM_ADDR_READ | EEPROM_ADDR_START);
9267
9268 for (i = 0; i < 10000; i++) {
9269 tmp = tr32(GRC_EEPROM_ADDR);
9270
9271 if (tmp & EEPROM_ADDR_COMPLETE)
9272 break;
9273 udelay(100);
9274 }
9275 if (!(tmp & EEPROM_ADDR_COMPLETE))
9276 return -EBUSY;
9277
9278 *val = tr32(GRC_EEPROM_DATA);
9279 return 0;
9280 }
9281
9282 #define NVRAM_CMD_TIMEOUT 10000
9283
9284 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
9285 {
9286 int i;
9287
9288 tw32(NVRAM_CMD, nvram_cmd);
9289 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
9290 udelay(10);
9291 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
9292 udelay(10);
9293 break;
9294 }
9295 }
9296 if (i == NVRAM_CMD_TIMEOUT) {
9297 return -EBUSY;
9298 }
9299 return 0;
9300 }
9301
9302 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
9303 {
9304 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9305 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9306 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9307 (tp->nvram_jedecnum == JEDEC_ATMEL))
9308
9309 addr = ((addr / tp->nvram_pagesize) <<
9310 ATMEL_AT45DB0X1B_PAGE_POS) +
9311 (addr % tp->nvram_pagesize);
9312
9313 return addr;
9314 }
9315
9316 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
9317 {
9318 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9319 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9320 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9321 (tp->nvram_jedecnum == JEDEC_ATMEL))
9322
9323 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
9324 tp->nvram_pagesize) +
9325 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
9326
9327 return addr;
9328 }
9329
9330 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
9331 {
9332 int ret;
9333
9334 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
9335 return tg3_nvram_read_using_eeprom(tp, offset, val);
9336
9337 offset = tg3_nvram_phys_addr(tp, offset);
9338
9339 if (offset > NVRAM_ADDR_MSK)
9340 return -EINVAL;
9341
9342 ret = tg3_nvram_lock(tp);
9343 if (ret)
9344 return ret;
9345
9346 tg3_enable_nvram_access(tp);
9347
9348 tw32(NVRAM_ADDR, offset);
9349 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
9350 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
9351
9352 if (ret == 0)
9353 *val = swab32(tr32(NVRAM_RDDATA));
9354
9355 tg3_disable_nvram_access(tp);
9356
9357 tg3_nvram_unlock(tp);
9358
9359 return ret;
9360 }
9361
9362 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val)
9363 {
9364 int err;
9365 u32 tmp;
9366
9367 err = tg3_nvram_read(tp, offset, &tmp);
9368 *val = swab32(tmp);
9369 return err;
9370 }
9371
9372 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
9373 u32 offset, u32 len, u8 *buf)
9374 {
9375 int i, j, rc = 0;
9376 u32 val;
9377
9378 for (i = 0; i < len; i += 4) {
9379 u32 addr, data;
9380
9381 addr = offset + i;
9382
9383 memcpy(&data, buf + i, 4);
9384
9385 tw32(GRC_EEPROM_DATA, cpu_to_le32(data));
9386
9387 val = tr32(GRC_EEPROM_ADDR);
9388 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
9389
9390 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
9391 EEPROM_ADDR_READ);
9392 tw32(GRC_EEPROM_ADDR, val |
9393 (0 << EEPROM_ADDR_DEVID_SHIFT) |
9394 (addr & EEPROM_ADDR_ADDR_MASK) |
9395 EEPROM_ADDR_START |
9396 EEPROM_ADDR_WRITE);
9397
9398 for (j = 0; j < 10000; j++) {
9399 val = tr32(GRC_EEPROM_ADDR);
9400
9401 if (val & EEPROM_ADDR_COMPLETE)
9402 break;
9403 udelay(100);
9404 }
9405 if (!(val & EEPROM_ADDR_COMPLETE)) {
9406 rc = -EBUSY;
9407 break;
9408 }
9409 }
9410
9411 return rc;
9412 }
9413
9414 /* offset and length are dword aligned */
9415 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
9416 u8 *buf)
9417 {
9418 int ret = 0;
9419 u32 pagesize = tp->nvram_pagesize;
9420 u32 pagemask = pagesize - 1;
9421 u32 nvram_cmd;
9422 u8 *tmp;
9423
9424 tmp = kmalloc(pagesize, GFP_KERNEL);
9425 if (tmp == NULL)
9426 return -ENOMEM;
9427
9428 while (len) {
9429 int j;
9430 u32 phy_addr, page_off, size;
9431
9432 phy_addr = offset & ~pagemask;
9433
9434 for (j = 0; j < pagesize; j += 4) {
9435 if ((ret = tg3_nvram_read(tp, phy_addr + j,
9436 (u32 *) (tmp + j))))
9437 break;
9438 }
9439 if (ret)
9440 break;
9441
9442 page_off = offset & pagemask;
9443 size = pagesize;
9444 if (len < size)
9445 size = len;
9446
9447 len -= size;
9448
9449 memcpy(tmp + page_off, buf, size);
9450
9451 offset = offset + (pagesize - page_off);
9452
9453 tg3_enable_nvram_access(tp);
9454
9455 /*
9456 * Before we can erase the flash page, we need
9457 * to issue a special "write enable" command.
9458 */
9459 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9460
9461 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9462 break;
9463
9464 /* Erase the target page */
9465 tw32(NVRAM_ADDR, phy_addr);
9466
9467 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
9468 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
9469
9470 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9471 break;
9472
9473 /* Issue another write enable to start the write. */
9474 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9475
9476 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9477 break;
9478
9479 for (j = 0; j < pagesize; j += 4) {
9480 u32 data;
9481
9482 data = *((u32 *) (tmp + j));
9483 tw32(NVRAM_WRDATA, cpu_to_be32(data));
9484
9485 tw32(NVRAM_ADDR, phy_addr + j);
9486
9487 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
9488 NVRAM_CMD_WR;
9489
9490 if (j == 0)
9491 nvram_cmd |= NVRAM_CMD_FIRST;
9492 else if (j == (pagesize - 4))
9493 nvram_cmd |= NVRAM_CMD_LAST;
9494
9495 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
9496 break;
9497 }
9498 if (ret)
9499 break;
9500 }
9501
9502 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9503 tg3_nvram_exec_cmd(tp, nvram_cmd);
9504
9505 kfree(tmp);
9506
9507 return ret;
9508 }
9509
9510 /* offset and length are dword aligned */
9511 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
9512 u8 *buf)
9513 {
9514 int i, ret = 0;
9515
9516 for (i = 0; i < len; i += 4, offset += 4) {
9517 u32 data, page_off, phy_addr, nvram_cmd;
9518
9519 memcpy(&data, buf + i, 4);
9520 tw32(NVRAM_WRDATA, cpu_to_be32(data));
9521
9522 page_off = offset % tp->nvram_pagesize;
9523
9524 phy_addr = tg3_nvram_phys_addr(tp, offset);
9525
9526 tw32(NVRAM_ADDR, phy_addr);
9527
9528 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
9529
9530 if ((page_off == 0) || (i == 0))
9531 nvram_cmd |= NVRAM_CMD_FIRST;
9532 if (page_off == (tp->nvram_pagesize - 4))
9533 nvram_cmd |= NVRAM_CMD_LAST;
9534
9535 if (i == (len - 4))
9536 nvram_cmd |= NVRAM_CMD_LAST;
9537
9538 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
9539 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) &&
9540 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) &&
9541 (tp->nvram_jedecnum == JEDEC_ST) &&
9542 (nvram_cmd & NVRAM_CMD_FIRST)) {
9543
9544 if ((ret = tg3_nvram_exec_cmd(tp,
9545 NVRAM_CMD_WREN | NVRAM_CMD_GO |
9546 NVRAM_CMD_DONE)))
9547
9548 break;
9549 }
9550 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
9551 /* We always do complete word writes to eeprom. */
9552 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
9553 }
9554
9555 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
9556 break;
9557 }
9558 return ret;
9559 }
9560
9561 /* offset and length are dword aligned */
9562 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
9563 {
9564 int ret;
9565
9566 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
9567 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
9568 ~GRC_LCLCTRL_GPIO_OUTPUT1);
9569 udelay(40);
9570 }
9571
9572 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
9573 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
9574 }
9575 else {
9576 u32 grc_mode;
9577
9578 ret = tg3_nvram_lock(tp);
9579 if (ret)
9580 return ret;
9581
9582 tg3_enable_nvram_access(tp);
9583 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
9584 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
9585 tw32(NVRAM_WRITE1, 0x406);
9586
9587 grc_mode = tr32(GRC_MODE);
9588 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
9589
9590 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
9591 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
9592
9593 ret = tg3_nvram_write_block_buffered(tp, offset, len,
9594 buf);
9595 }
9596 else {
9597 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
9598 buf);
9599 }
9600
9601 grc_mode = tr32(GRC_MODE);
9602 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
9603
9604 tg3_disable_nvram_access(tp);
9605 tg3_nvram_unlock(tp);
9606 }
9607
9608 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
9609 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
9610 udelay(40);
9611 }
9612
9613 return ret;
9614 }
9615
9616 struct subsys_tbl_ent {
9617 u16 subsys_vendor, subsys_devid;
9618 u32 phy_id;
9619 };
9620
9621 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
9622 /* Broadcom boards. */
9623 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
9624 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
9625 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
9626 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
9627 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
9628 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
9629 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
9630 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
9631 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
9632 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
9633 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
9634
9635 /* 3com boards. */
9636 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
9637 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
9638 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
9639 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
9640 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
9641
9642 /* DELL boards. */
9643 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
9644 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
9645 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
9646 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
9647
9648 /* Compaq boards. */
9649 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
9650 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
9651 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
9652 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
9653 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
9654
9655 /* IBM boards. */
9656 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
9657 };
9658
9659 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
9660 {
9661 int i;
9662
9663 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
9664 if ((subsys_id_to_phy_id[i].subsys_vendor ==
9665 tp->pdev->subsystem_vendor) &&
9666 (subsys_id_to_phy_id[i].subsys_devid ==
9667 tp->pdev->subsystem_device))
9668 return &subsys_id_to_phy_id[i];
9669 }
9670 return NULL;
9671 }
9672
9673 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
9674 {
9675 u32 val;
9676 u16 pmcsr;
9677
9678 /* On some early chips the SRAM cannot be accessed in D3hot state,
9679 * so need make sure we're in D0.
9680 */
9681 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
9682 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
9683 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
9684 msleep(1);
9685
9686 /* Make sure register accesses (indirect or otherwise)
9687 * will function correctly.
9688 */
9689 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
9690 tp->misc_host_ctrl);
9691
9692 /* The memory arbiter has to be enabled in order for SRAM accesses
9693 * to succeed. Normally on powerup the tg3 chip firmware will make
9694 * sure it is enabled, but other entities such as system netboot
9695 * code might disable it.
9696 */
9697 val = tr32(MEMARB_MODE);
9698 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
9699
9700 tp->phy_id = PHY_ID_INVALID;
9701 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
9702
9703 /* Assume an onboard device by default. */
9704 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9705
9706 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
9707 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
9708 u32 nic_cfg, led_cfg;
9709 u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
9710 int eeprom_phy_serdes = 0;
9711
9712 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
9713 tp->nic_sram_data_cfg = nic_cfg;
9714
9715 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
9716 ver >>= NIC_SRAM_DATA_VER_SHIFT;
9717 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
9718 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
9719 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
9720 (ver > 0) && (ver < 0x100))
9721 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
9722
9723 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
9724 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
9725 eeprom_phy_serdes = 1;
9726
9727 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
9728 if (nic_phy_id != 0) {
9729 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
9730 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
9731
9732 eeprom_phy_id = (id1 >> 16) << 10;
9733 eeprom_phy_id |= (id2 & 0xfc00) << 16;
9734 eeprom_phy_id |= (id2 & 0x03ff) << 0;
9735 } else
9736 eeprom_phy_id = 0;
9737
9738 tp->phy_id = eeprom_phy_id;
9739 if (eeprom_phy_serdes) {
9740 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
9741 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
9742 else
9743 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
9744 }
9745
9746 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9747 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
9748 SHASTA_EXT_LED_MODE_MASK);
9749 else
9750 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
9751
9752 switch (led_cfg) {
9753 default:
9754 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
9755 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
9756 break;
9757
9758 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
9759 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
9760 break;
9761
9762 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
9763 tp->led_ctrl = LED_CTRL_MODE_MAC;
9764
9765 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
9766 * read on some older 5700/5701 bootcode.
9767 */
9768 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
9769 ASIC_REV_5700 ||
9770 GET_ASIC_REV(tp->pci_chip_rev_id) ==
9771 ASIC_REV_5701)
9772 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
9773
9774 break;
9775
9776 case SHASTA_EXT_LED_SHARED:
9777 tp->led_ctrl = LED_CTRL_MODE_SHARED;
9778 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
9779 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
9780 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
9781 LED_CTRL_MODE_PHY_2);
9782 break;
9783
9784 case SHASTA_EXT_LED_MAC:
9785 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
9786 break;
9787
9788 case SHASTA_EXT_LED_COMBO:
9789 tp->led_ctrl = LED_CTRL_MODE_COMBO;
9790 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
9791 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
9792 LED_CTRL_MODE_PHY_2);
9793 break;
9794
9795 };
9796
9797 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9798 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
9799 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
9800 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
9801
9802 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP)
9803 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9804 else
9805 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9806
9807 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
9808 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
9809 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9810 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
9811 }
9812 if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)
9813 tp->tg3_flags |= TG3_FLAG_SERDES_WOL_CAP;
9814
9815 if (cfg2 & (1 << 17))
9816 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
9817
9818 /* serdes signal pre-emphasis in register 0x590 set by */
9819 /* bootcode if bit 18 is set */
9820 if (cfg2 & (1 << 18))
9821 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
9822 }
9823 }
9824
9825 static int __devinit tg3_phy_probe(struct tg3 *tp)
9826 {
9827 u32 hw_phy_id_1, hw_phy_id_2;
9828 u32 hw_phy_id, hw_phy_id_masked;
9829 int err;
9830
9831 /* Reading the PHY ID register can conflict with ASF
9832 * firwmare access to the PHY hardware.
9833 */
9834 err = 0;
9835 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
9836 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
9837 } else {
9838 /* Now read the physical PHY_ID from the chip and verify
9839 * that it is sane. If it doesn't look good, we fall back
9840 * to either the hard-coded table based PHY_ID and failing
9841 * that the value found in the eeprom area.
9842 */
9843 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
9844 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
9845
9846 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
9847 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
9848 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
9849
9850 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
9851 }
9852
9853 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
9854 tp->phy_id = hw_phy_id;
9855 if (hw_phy_id_masked == PHY_ID_BCM8002)
9856 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
9857 else
9858 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
9859 } else {
9860 if (tp->phy_id != PHY_ID_INVALID) {
9861 /* Do nothing, phy ID already set up in
9862 * tg3_get_eeprom_hw_cfg().
9863 */
9864 } else {
9865 struct subsys_tbl_ent *p;
9866
9867 /* No eeprom signature? Try the hardcoded
9868 * subsys device table.
9869 */
9870 p = lookup_by_subsys(tp);
9871 if (!p)
9872 return -ENODEV;
9873
9874 tp->phy_id = p->phy_id;
9875 if (!tp->phy_id ||
9876 tp->phy_id == PHY_ID_BCM8002)
9877 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
9878 }
9879 }
9880
9881 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
9882 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
9883 u32 bmsr, adv_reg, tg3_ctrl;
9884
9885 tg3_readphy(tp, MII_BMSR, &bmsr);
9886 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
9887 (bmsr & BMSR_LSTATUS))
9888 goto skip_phy_reset;
9889
9890 err = tg3_phy_reset(tp);
9891 if (err)
9892 return err;
9893
9894 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
9895 ADVERTISE_100HALF | ADVERTISE_100FULL |
9896 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
9897 tg3_ctrl = 0;
9898 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
9899 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
9900 MII_TG3_CTRL_ADV_1000_FULL);
9901 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
9902 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
9903 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
9904 MII_TG3_CTRL_ENABLE_AS_MASTER);
9905 }
9906
9907 if (!tg3_copper_is_advertising_all(tp)) {
9908 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
9909
9910 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9911 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
9912
9913 tg3_writephy(tp, MII_BMCR,
9914 BMCR_ANENABLE | BMCR_ANRESTART);
9915 }
9916 tg3_phy_set_wirespeed(tp);
9917
9918 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
9919 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9920 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
9921 }
9922
9923 skip_phy_reset:
9924 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
9925 err = tg3_init_5401phy_dsp(tp);
9926 if (err)
9927 return err;
9928 }
9929
9930 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
9931 err = tg3_init_5401phy_dsp(tp);
9932 }
9933
9934 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
9935 tp->link_config.advertising =
9936 (ADVERTISED_1000baseT_Half |
9937 ADVERTISED_1000baseT_Full |
9938 ADVERTISED_Autoneg |
9939 ADVERTISED_FIBRE);
9940 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
9941 tp->link_config.advertising &=
9942 ~(ADVERTISED_1000baseT_Half |
9943 ADVERTISED_1000baseT_Full);
9944
9945 return err;
9946 }
9947
9948 static void __devinit tg3_read_partno(struct tg3 *tp)
9949 {
9950 unsigned char vpd_data[256];
9951 int i;
9952 u32 magic;
9953
9954 if (tg3_nvram_read_swab(tp, 0x0, &magic))
9955 goto out_not_found;
9956
9957 if (magic == TG3_EEPROM_MAGIC) {
9958 for (i = 0; i < 256; i += 4) {
9959 u32 tmp;
9960
9961 if (tg3_nvram_read(tp, 0x100 + i, &tmp))
9962 goto out_not_found;
9963
9964 vpd_data[i + 0] = ((tmp >> 0) & 0xff);
9965 vpd_data[i + 1] = ((tmp >> 8) & 0xff);
9966 vpd_data[i + 2] = ((tmp >> 16) & 0xff);
9967 vpd_data[i + 3] = ((tmp >> 24) & 0xff);
9968 }
9969 } else {
9970 int vpd_cap;
9971
9972 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
9973 for (i = 0; i < 256; i += 4) {
9974 u32 tmp, j = 0;
9975 u16 tmp16;
9976
9977 pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
9978 i);
9979 while (j++ < 100) {
9980 pci_read_config_word(tp->pdev, vpd_cap +
9981 PCI_VPD_ADDR, &tmp16);
9982 if (tmp16 & 0x8000)
9983 break;
9984 msleep(1);
9985 }
9986 if (!(tmp16 & 0x8000))
9987 goto out_not_found;
9988
9989 pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
9990 &tmp);
9991 tmp = cpu_to_le32(tmp);
9992 memcpy(&vpd_data[i], &tmp, 4);
9993 }
9994 }
9995
9996 /* Now parse and find the part number. */
9997 for (i = 0; i < 256; ) {
9998 unsigned char val = vpd_data[i];
9999 int block_end;
10000
10001 if (val == 0x82 || val == 0x91) {
10002 i = (i + 3 +
10003 (vpd_data[i + 1] +
10004 (vpd_data[i + 2] << 8)));
10005 continue;
10006 }
10007
10008 if (val != 0x90)
10009 goto out_not_found;
10010
10011 block_end = (i + 3 +
10012 (vpd_data[i + 1] +
10013 (vpd_data[i + 2] << 8)));
10014 i += 3;
10015 while (i < block_end) {
10016 if (vpd_data[i + 0] == 'P' &&
10017 vpd_data[i + 1] == 'N') {
10018 int partno_len = vpd_data[i + 2];
10019
10020 if (partno_len > 24)
10021 goto out_not_found;
10022
10023 memcpy(tp->board_part_number,
10024 &vpd_data[i + 3],
10025 partno_len);
10026
10027 /* Success. */
10028 return;
10029 }
10030 }
10031
10032 /* Part number not found. */
10033 goto out_not_found;
10034 }
10035
10036 out_not_found:
10037 strcpy(tp->board_part_number, "none");
10038 }
10039
10040 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
10041 {
10042 u32 val, offset, start;
10043
10044 if (tg3_nvram_read_swab(tp, 0, &val))
10045 return;
10046
10047 if (val != TG3_EEPROM_MAGIC)
10048 return;
10049
10050 if (tg3_nvram_read_swab(tp, 0xc, &offset) ||
10051 tg3_nvram_read_swab(tp, 0x4, &start))
10052 return;
10053
10054 offset = tg3_nvram_logical_addr(tp, offset);
10055 if (tg3_nvram_read_swab(tp, offset, &val))
10056 return;
10057
10058 if ((val & 0xfc000000) == 0x0c000000) {
10059 u32 ver_offset, addr;
10060 int i;
10061
10062 if (tg3_nvram_read_swab(tp, offset + 4, &val) ||
10063 tg3_nvram_read_swab(tp, offset + 8, &ver_offset))
10064 return;
10065
10066 if (val != 0)
10067 return;
10068
10069 addr = offset + ver_offset - start;
10070 for (i = 0; i < 16; i += 4) {
10071 if (tg3_nvram_read(tp, addr + i, &val))
10072 return;
10073
10074 val = cpu_to_le32(val);
10075 memcpy(tp->fw_ver + i, &val, 4);
10076 }
10077 }
10078 }
10079
10080 static int __devinit tg3_get_invariants(struct tg3 *tp)
10081 {
10082 static struct pci_device_id write_reorder_chipsets[] = {
10083 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
10084 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
10085 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
10086 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
10087 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
10088 PCI_DEVICE_ID_VIA_8385_0) },
10089 { },
10090 };
10091 u32 misc_ctrl_reg;
10092 u32 cacheline_sz_reg;
10093 u32 pci_state_reg, grc_misc_cfg;
10094 u32 val;
10095 u16 pci_cmd;
10096 int err;
10097
10098 /* Force memory write invalidate off. If we leave it on,
10099 * then on 5700_BX chips we have to enable a workaround.
10100 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
10101 * to match the cacheline size. The Broadcom driver have this
10102 * workaround but turns MWI off all the times so never uses
10103 * it. This seems to suggest that the workaround is insufficient.
10104 */
10105 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10106 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
10107 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10108
10109 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
10110 * has the register indirect write enable bit set before
10111 * we try to access any of the MMIO registers. It is also
10112 * critical that the PCI-X hw workaround situation is decided
10113 * before that as well.
10114 */
10115 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10116 &misc_ctrl_reg);
10117
10118 tp->pci_chip_rev_id = (misc_ctrl_reg >>
10119 MISC_HOST_CTRL_CHIPREV_SHIFT);
10120
10121 /* Wrong chip ID in 5752 A0. This code can be removed later
10122 * as A0 is not in production.
10123 */
10124 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
10125 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
10126
10127 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
10128 * we need to disable memory and use config. cycles
10129 * only to access all registers. The 5702/03 chips
10130 * can mistakenly decode the special cycles from the
10131 * ICH chipsets as memory write cycles, causing corruption
10132 * of register and memory space. Only certain ICH bridges
10133 * will drive special cycles with non-zero data during the
10134 * address phase which can fall within the 5703's address
10135 * range. This is not an ICH bug as the PCI spec allows
10136 * non-zero address during special cycles. However, only
10137 * these ICH bridges are known to drive non-zero addresses
10138 * during special cycles.
10139 *
10140 * Since special cycles do not cross PCI bridges, we only
10141 * enable this workaround if the 5703 is on the secondary
10142 * bus of these ICH bridges.
10143 */
10144 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
10145 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
10146 static struct tg3_dev_id {
10147 u32 vendor;
10148 u32 device;
10149 u32 rev;
10150 } ich_chipsets[] = {
10151 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
10152 PCI_ANY_ID },
10153 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
10154 PCI_ANY_ID },
10155 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
10156 0xa },
10157 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
10158 PCI_ANY_ID },
10159 { },
10160 };
10161 struct tg3_dev_id *pci_id = &ich_chipsets[0];
10162 struct pci_dev *bridge = NULL;
10163
10164 while (pci_id->vendor != 0) {
10165 bridge = pci_get_device(pci_id->vendor, pci_id->device,
10166 bridge);
10167 if (!bridge) {
10168 pci_id++;
10169 continue;
10170 }
10171 if (pci_id->rev != PCI_ANY_ID) {
10172 u8 rev;
10173
10174 pci_read_config_byte(bridge, PCI_REVISION_ID,
10175 &rev);
10176 if (rev > pci_id->rev)
10177 continue;
10178 }
10179 if (bridge->subordinate &&
10180 (bridge->subordinate->number ==
10181 tp->pdev->bus->number)) {
10182
10183 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
10184 pci_dev_put(bridge);
10185 break;
10186 }
10187 }
10188 }
10189
10190 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
10191 * DMA addresses > 40-bit. This bridge may have other additional
10192 * 57xx devices behind it in some 4-port NIC designs for example.
10193 * Any tg3 device found behind the bridge will also need the 40-bit
10194 * DMA workaround.
10195 */
10196 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
10197 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
10198 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
10199 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
10200 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
10201 }
10202 else {
10203 struct pci_dev *bridge = NULL;
10204
10205 do {
10206 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
10207 PCI_DEVICE_ID_SERVERWORKS_EPB,
10208 bridge);
10209 if (bridge && bridge->subordinate &&
10210 (bridge->subordinate->number <=
10211 tp->pdev->bus->number) &&
10212 (bridge->subordinate->subordinate >=
10213 tp->pdev->bus->number)) {
10214 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
10215 pci_dev_put(bridge);
10216 break;
10217 }
10218 } while (bridge);
10219 }
10220
10221 /* Initialize misc host control in PCI block. */
10222 tp->misc_host_ctrl |= (misc_ctrl_reg &
10223 MISC_HOST_CTRL_CHIPREV);
10224 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10225 tp->misc_host_ctrl);
10226
10227 pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
10228 &cacheline_sz_reg);
10229
10230 tp->pci_cacheline_sz = (cacheline_sz_reg >> 0) & 0xff;
10231 tp->pci_lat_timer = (cacheline_sz_reg >> 8) & 0xff;
10232 tp->pci_hdr_type = (cacheline_sz_reg >> 16) & 0xff;
10233 tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff;
10234
10235 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
10236 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
10237 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10238 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10239 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
10240 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
10241
10242 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
10243 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
10244 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
10245
10246 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
10247 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10248 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) {
10249 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
10250 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
10251 } else {
10252 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 |
10253 TG3_FLG2_HW_TSO_1_BUG;
10254 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
10255 ASIC_REV_5750 &&
10256 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
10257 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_1_BUG;
10258 }
10259 }
10260
10261 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
10262 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
10263 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
10264 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755 &&
10265 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787)
10266 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
10267
10268 if (pci_find_capability(tp->pdev, PCI_CAP_ID_EXP) != 0)
10269 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
10270
10271 /* If we have an AMD 762 or VIA K8T800 chipset, write
10272 * reordering to the mailbox registers done by the host
10273 * controller can cause major troubles. We read back from
10274 * every mailbox register write to force the writes to be
10275 * posted to the chip in order.
10276 */
10277 if (pci_dev_present(write_reorder_chipsets) &&
10278 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
10279 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
10280
10281 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
10282 tp->pci_lat_timer < 64) {
10283 tp->pci_lat_timer = 64;
10284
10285 cacheline_sz_reg = ((tp->pci_cacheline_sz & 0xff) << 0);
10286 cacheline_sz_reg |= ((tp->pci_lat_timer & 0xff) << 8);
10287 cacheline_sz_reg |= ((tp->pci_hdr_type & 0xff) << 16);
10288 cacheline_sz_reg |= ((tp->pci_bist & 0xff) << 24);
10289
10290 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
10291 cacheline_sz_reg);
10292 }
10293
10294 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10295 &pci_state_reg);
10296
10297 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
10298 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
10299
10300 /* If this is a 5700 BX chipset, and we are in PCI-X
10301 * mode, enable register write workaround.
10302 *
10303 * The workaround is to use indirect register accesses
10304 * for all chip writes not to mailbox registers.
10305 */
10306 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
10307 u32 pm_reg;
10308 u16 pci_cmd;
10309
10310 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10311
10312 /* The chip can have it's power management PCI config
10313 * space registers clobbered due to this bug.
10314 * So explicitly force the chip into D0 here.
10315 */
10316 pci_read_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
10317 &pm_reg);
10318 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
10319 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
10320 pci_write_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
10321 pm_reg);
10322
10323 /* Also, force SERR#/PERR# in PCI command. */
10324 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10325 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
10326 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10327 }
10328 }
10329
10330 /* 5700 BX chips need to have their TX producer index mailboxes
10331 * written twice to workaround a bug.
10332 */
10333 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
10334 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
10335
10336 /* Back to back register writes can cause problems on this chip,
10337 * the workaround is to read back all reg writes except those to
10338 * mailbox regs. See tg3_write_indirect_reg32().
10339 *
10340 * PCI Express 5750_A0 rev chips need this workaround too.
10341 */
10342 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
10343 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
10344 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0))
10345 tp->tg3_flags |= TG3_FLAG_5701_REG_WRITE_BUG;
10346
10347 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
10348 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
10349 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
10350 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
10351
10352 /* Chip-specific fixup from Broadcom driver */
10353 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
10354 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
10355 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
10356 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
10357 }
10358
10359 /* Default fast path register access methods */
10360 tp->read32 = tg3_read32;
10361 tp->write32 = tg3_write32;
10362 tp->read32_mbox = tg3_read32;
10363 tp->write32_mbox = tg3_write32;
10364 tp->write32_tx_mbox = tg3_write32;
10365 tp->write32_rx_mbox = tg3_write32;
10366
10367 /* Various workaround register access methods */
10368 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
10369 tp->write32 = tg3_write_indirect_reg32;
10370 else if (tp->tg3_flags & TG3_FLAG_5701_REG_WRITE_BUG)
10371 tp->write32 = tg3_write_flush_reg32;
10372
10373 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
10374 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
10375 tp->write32_tx_mbox = tg3_write32_tx_mbox;
10376 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
10377 tp->write32_rx_mbox = tg3_write_flush_reg32;
10378 }
10379
10380 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
10381 tp->read32 = tg3_read_indirect_reg32;
10382 tp->write32 = tg3_write_indirect_reg32;
10383 tp->read32_mbox = tg3_read_indirect_mbox;
10384 tp->write32_mbox = tg3_write_indirect_mbox;
10385 tp->write32_tx_mbox = tg3_write_indirect_mbox;
10386 tp->write32_rx_mbox = tg3_write_indirect_mbox;
10387
10388 iounmap(tp->regs);
10389 tp->regs = NULL;
10390
10391 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10392 pci_cmd &= ~PCI_COMMAND_MEMORY;
10393 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10394 }
10395
10396 if (tp->write32 == tg3_write_indirect_reg32 ||
10397 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
10398 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10399 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
10400 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
10401
10402 /* Get eeprom hw config before calling tg3_set_power_state().
10403 * In particular, the TG3_FLAG_EEPROM_WRITE_PROT flag must be
10404 * determined before calling tg3_set_power_state() so that
10405 * we know whether or not to switch out of Vaux power.
10406 * When the flag is set, it means that GPIO1 is used for eeprom
10407 * write protect and also implies that it is a LOM where GPIOs
10408 * are not used to switch power.
10409 */
10410 tg3_get_eeprom_hw_cfg(tp);
10411
10412 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
10413 * GPIO1 driven high will bring 5700's external PHY out of reset.
10414 * It is also used as eeprom write protect on LOMs.
10415 */
10416 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
10417 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
10418 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
10419 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
10420 GRC_LCLCTRL_GPIO_OUTPUT1);
10421 /* Unused GPIO3 must be driven as output on 5752 because there
10422 * are no pull-up resistors on unused GPIO pins.
10423 */
10424 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10425 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
10426
10427 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10428 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
10429
10430 /* Force the chip into D0. */
10431 err = tg3_set_power_state(tp, PCI_D0);
10432 if (err) {
10433 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
10434 pci_name(tp->pdev));
10435 return err;
10436 }
10437
10438 /* 5700 B0 chips do not support checksumming correctly due
10439 * to hardware bugs.
10440 */
10441 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
10442 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
10443
10444 /* Derive initial jumbo mode from MTU assigned in
10445 * ether_setup() via the alloc_etherdev() call
10446 */
10447 if (tp->dev->mtu > ETH_DATA_LEN &&
10448 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
10449 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
10450
10451 /* Determine WakeOnLan speed to use. */
10452 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10453 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
10454 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
10455 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
10456 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
10457 } else {
10458 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
10459 }
10460
10461 /* A few boards don't want Ethernet@WireSpeed phy feature */
10462 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
10463 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
10464 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
10465 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
10466 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
10467 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
10468
10469 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
10470 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
10471 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
10472 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
10473 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
10474
10475 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10476 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10477 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
10478 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
10479 else
10480 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
10481 }
10482
10483 tp->coalesce_mode = 0;
10484 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
10485 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
10486 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
10487
10488 /* Initialize MAC MI mode, polling disabled. */
10489 tw32_f(MAC_MI_MODE, tp->mi_mode);
10490 udelay(80);
10491
10492 /* Initialize data/descriptor byte/word swapping. */
10493 val = tr32(GRC_MODE);
10494 val &= GRC_MODE_HOST_STACKUP;
10495 tw32(GRC_MODE, val | tp->grc_mode);
10496
10497 tg3_switch_clocks(tp);
10498
10499 /* Clear this out for sanity. */
10500 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
10501
10502 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10503 &pci_state_reg);
10504 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
10505 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
10506 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
10507
10508 if (chiprevid == CHIPREV_ID_5701_A0 ||
10509 chiprevid == CHIPREV_ID_5701_B0 ||
10510 chiprevid == CHIPREV_ID_5701_B2 ||
10511 chiprevid == CHIPREV_ID_5701_B5) {
10512 void __iomem *sram_base;
10513
10514 /* Write some dummy words into the SRAM status block
10515 * area, see if it reads back correctly. If the return
10516 * value is bad, force enable the PCIX workaround.
10517 */
10518 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
10519
10520 writel(0x00000000, sram_base);
10521 writel(0x00000000, sram_base + 4);
10522 writel(0xffffffff, sram_base + 4);
10523 if (readl(sram_base) != 0x00000000)
10524 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10525 }
10526 }
10527
10528 udelay(50);
10529 tg3_nvram_init(tp);
10530
10531 grc_misc_cfg = tr32(GRC_MISC_CFG);
10532 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
10533
10534 /* Broadcom's driver says that CIOBE multisplit has a bug */
10535 #if 0
10536 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
10537 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5704CIOBE) {
10538 tp->tg3_flags |= TG3_FLAG_SPLIT_MODE;
10539 tp->split_mode_max_reqs = SPLIT_MODE_5704_MAX_REQ;
10540 }
10541 #endif
10542 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
10543 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
10544 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
10545 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
10546
10547 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10548 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
10549 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
10550 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
10551 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
10552 HOSTCC_MODE_CLRTICK_TXBD);
10553
10554 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
10555 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10556 tp->misc_host_ctrl);
10557 }
10558
10559 /* these are limited to 10/100 only */
10560 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
10561 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
10562 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
10563 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
10564 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
10565 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
10566 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
10567 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
10568 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
10569 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F)))
10570 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
10571
10572 err = tg3_phy_probe(tp);
10573 if (err) {
10574 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
10575 pci_name(tp->pdev), err);
10576 /* ... but do not return immediately ... */
10577 }
10578
10579 tg3_read_partno(tp);
10580 tg3_read_fw_ver(tp);
10581
10582 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
10583 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
10584 } else {
10585 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
10586 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
10587 else
10588 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
10589 }
10590
10591 /* 5700 {AX,BX} chips have a broken status block link
10592 * change bit implementation, so we must use the
10593 * status register in those cases.
10594 */
10595 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
10596 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
10597 else
10598 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
10599
10600 /* The led_ctrl is set during tg3_phy_probe, here we might
10601 * have to force the link status polling mechanism based
10602 * upon subsystem IDs.
10603 */
10604 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
10605 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
10606 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
10607 TG3_FLAG_USE_LINKCHG_REG);
10608 }
10609
10610 /* For all SERDES we poll the MAC status register. */
10611 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10612 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
10613 else
10614 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
10615
10616 /* All chips before 5787 can get confused if TX buffers
10617 * straddle the 4GB address boundary in some cases.
10618 */
10619 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10620 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
10621 tp->dev->hard_start_xmit = tg3_start_xmit;
10622 else
10623 tp->dev->hard_start_xmit = tg3_start_xmit_dma_bug;
10624
10625 tp->rx_offset = 2;
10626 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
10627 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
10628 tp->rx_offset = 0;
10629
10630 tp->rx_std_max_post = TG3_RX_RING_SIZE;
10631
10632 /* Increment the rx prod index on the rx std ring by at most
10633 * 8 for these chips to workaround hw errata.
10634 */
10635 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
10636 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
10637 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10638 tp->rx_std_max_post = 8;
10639
10640 /* By default, disable wake-on-lan. User can change this
10641 * using ETHTOOL_SWOL.
10642 */
10643 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
10644
10645 return err;
10646 }
10647
10648 #ifdef CONFIG_SPARC64
10649 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
10650 {
10651 struct net_device *dev = tp->dev;
10652 struct pci_dev *pdev = tp->pdev;
10653 struct pcidev_cookie *pcp = pdev->sysdata;
10654
10655 if (pcp != NULL) {
10656 unsigned char *addr;
10657 int len;
10658
10659 addr = of_get_property(pcp->prom_node, "local-mac-address",
10660 &len);
10661 if (addr && len == 6) {
10662 memcpy(dev->dev_addr, addr, 6);
10663 memcpy(dev->perm_addr, dev->dev_addr, 6);
10664 return 0;
10665 }
10666 }
10667 return -ENODEV;
10668 }
10669
10670 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
10671 {
10672 struct net_device *dev = tp->dev;
10673
10674 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
10675 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
10676 return 0;
10677 }
10678 #endif
10679
10680 static int __devinit tg3_get_device_address(struct tg3 *tp)
10681 {
10682 struct net_device *dev = tp->dev;
10683 u32 hi, lo, mac_offset;
10684 int addr_ok = 0;
10685
10686 #ifdef CONFIG_SPARC64
10687 if (!tg3_get_macaddr_sparc(tp))
10688 return 0;
10689 #endif
10690
10691 mac_offset = 0x7c;
10692 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
10693 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
10694 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
10695 mac_offset = 0xcc;
10696 if (tg3_nvram_lock(tp))
10697 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
10698 else
10699 tg3_nvram_unlock(tp);
10700 }
10701
10702 /* First try to get it from MAC address mailbox. */
10703 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
10704 if ((hi >> 16) == 0x484b) {
10705 dev->dev_addr[0] = (hi >> 8) & 0xff;
10706 dev->dev_addr[1] = (hi >> 0) & 0xff;
10707
10708 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
10709 dev->dev_addr[2] = (lo >> 24) & 0xff;
10710 dev->dev_addr[3] = (lo >> 16) & 0xff;
10711 dev->dev_addr[4] = (lo >> 8) & 0xff;
10712 dev->dev_addr[5] = (lo >> 0) & 0xff;
10713
10714 /* Some old bootcode may report a 0 MAC address in SRAM */
10715 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
10716 }
10717 if (!addr_ok) {
10718 /* Next, try NVRAM. */
10719 if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
10720 !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
10721 dev->dev_addr[0] = ((hi >> 16) & 0xff);
10722 dev->dev_addr[1] = ((hi >> 24) & 0xff);
10723 dev->dev_addr[2] = ((lo >> 0) & 0xff);
10724 dev->dev_addr[3] = ((lo >> 8) & 0xff);
10725 dev->dev_addr[4] = ((lo >> 16) & 0xff);
10726 dev->dev_addr[5] = ((lo >> 24) & 0xff);
10727 }
10728 /* Finally just fetch it out of the MAC control regs. */
10729 else {
10730 hi = tr32(MAC_ADDR_0_HIGH);
10731 lo = tr32(MAC_ADDR_0_LOW);
10732
10733 dev->dev_addr[5] = lo & 0xff;
10734 dev->dev_addr[4] = (lo >> 8) & 0xff;
10735 dev->dev_addr[3] = (lo >> 16) & 0xff;
10736 dev->dev_addr[2] = (lo >> 24) & 0xff;
10737 dev->dev_addr[1] = hi & 0xff;
10738 dev->dev_addr[0] = (hi >> 8) & 0xff;
10739 }
10740 }
10741
10742 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
10743 #ifdef CONFIG_SPARC64
10744 if (!tg3_get_default_macaddr_sparc(tp))
10745 return 0;
10746 #endif
10747 return -EINVAL;
10748 }
10749 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
10750 return 0;
10751 }
10752
10753 #define BOUNDARY_SINGLE_CACHELINE 1
10754 #define BOUNDARY_MULTI_CACHELINE 2
10755
10756 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
10757 {
10758 int cacheline_size;
10759 u8 byte;
10760 int goal;
10761
10762 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
10763 if (byte == 0)
10764 cacheline_size = 1024;
10765 else
10766 cacheline_size = (int) byte * 4;
10767
10768 /* On 5703 and later chips, the boundary bits have no
10769 * effect.
10770 */
10771 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
10772 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
10773 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
10774 goto out;
10775
10776 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
10777 goal = BOUNDARY_MULTI_CACHELINE;
10778 #else
10779 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
10780 goal = BOUNDARY_SINGLE_CACHELINE;
10781 #else
10782 goal = 0;
10783 #endif
10784 #endif
10785
10786 if (!goal)
10787 goto out;
10788
10789 /* PCI controllers on most RISC systems tend to disconnect
10790 * when a device tries to burst across a cache-line boundary.
10791 * Therefore, letting tg3 do so just wastes PCI bandwidth.
10792 *
10793 * Unfortunately, for PCI-E there are only limited
10794 * write-side controls for this, and thus for reads
10795 * we will still get the disconnects. We'll also waste
10796 * these PCI cycles for both read and write for chips
10797 * other than 5700 and 5701 which do not implement the
10798 * boundary bits.
10799 */
10800 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
10801 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
10802 switch (cacheline_size) {
10803 case 16:
10804 case 32:
10805 case 64:
10806 case 128:
10807 if (goal == BOUNDARY_SINGLE_CACHELINE) {
10808 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
10809 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
10810 } else {
10811 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
10812 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
10813 }
10814 break;
10815
10816 case 256:
10817 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
10818 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
10819 break;
10820
10821 default:
10822 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
10823 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
10824 break;
10825 };
10826 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
10827 switch (cacheline_size) {
10828 case 16:
10829 case 32:
10830 case 64:
10831 if (goal == BOUNDARY_SINGLE_CACHELINE) {
10832 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
10833 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
10834 break;
10835 }
10836 /* fallthrough */
10837 case 128:
10838 default:
10839 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
10840 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
10841 break;
10842 };
10843 } else {
10844 switch (cacheline_size) {
10845 case 16:
10846 if (goal == BOUNDARY_SINGLE_CACHELINE) {
10847 val |= (DMA_RWCTRL_READ_BNDRY_16 |
10848 DMA_RWCTRL_WRITE_BNDRY_16);
10849 break;
10850 }
10851 /* fallthrough */
10852 case 32:
10853 if (goal == BOUNDARY_SINGLE_CACHELINE) {
10854 val |= (DMA_RWCTRL_READ_BNDRY_32 |
10855 DMA_RWCTRL_WRITE_BNDRY_32);
10856 break;
10857 }
10858 /* fallthrough */
10859 case 64:
10860 if (goal == BOUNDARY_SINGLE_CACHELINE) {
10861 val |= (DMA_RWCTRL_READ_BNDRY_64 |
10862 DMA_RWCTRL_WRITE_BNDRY_64);
10863 break;
10864 }
10865 /* fallthrough */
10866 case 128:
10867 if (goal == BOUNDARY_SINGLE_CACHELINE) {
10868 val |= (DMA_RWCTRL_READ_BNDRY_128 |
10869 DMA_RWCTRL_WRITE_BNDRY_128);
10870 break;
10871 }
10872 /* fallthrough */
10873 case 256:
10874 val |= (DMA_RWCTRL_READ_BNDRY_256 |
10875 DMA_RWCTRL_WRITE_BNDRY_256);
10876 break;
10877 case 512:
10878 val |= (DMA_RWCTRL_READ_BNDRY_512 |
10879 DMA_RWCTRL_WRITE_BNDRY_512);
10880 break;
10881 case 1024:
10882 default:
10883 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
10884 DMA_RWCTRL_WRITE_BNDRY_1024);
10885 break;
10886 };
10887 }
10888
10889 out:
10890 return val;
10891 }
10892
10893 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
10894 {
10895 struct tg3_internal_buffer_desc test_desc;
10896 u32 sram_dma_descs;
10897 int i, ret;
10898
10899 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
10900
10901 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
10902 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
10903 tw32(RDMAC_STATUS, 0);
10904 tw32(WDMAC_STATUS, 0);
10905
10906 tw32(BUFMGR_MODE, 0);
10907 tw32(FTQ_RESET, 0);
10908
10909 test_desc.addr_hi = ((u64) buf_dma) >> 32;
10910 test_desc.addr_lo = buf_dma & 0xffffffff;
10911 test_desc.nic_mbuf = 0x00002100;
10912 test_desc.len = size;
10913
10914 /*
10915 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
10916 * the *second* time the tg3 driver was getting loaded after an
10917 * initial scan.
10918 *
10919 * Broadcom tells me:
10920 * ...the DMA engine is connected to the GRC block and a DMA
10921 * reset may affect the GRC block in some unpredictable way...
10922 * The behavior of resets to individual blocks has not been tested.
10923 *
10924 * Broadcom noted the GRC reset will also reset all sub-components.
10925 */
10926 if (to_device) {
10927 test_desc.cqid_sqid = (13 << 8) | 2;
10928
10929 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
10930 udelay(40);
10931 } else {
10932 test_desc.cqid_sqid = (16 << 8) | 7;
10933
10934 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
10935 udelay(40);
10936 }
10937 test_desc.flags = 0x00000005;
10938
10939 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
10940 u32 val;
10941
10942 val = *(((u32 *)&test_desc) + i);
10943 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
10944 sram_dma_descs + (i * sizeof(u32)));
10945 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
10946 }
10947 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
10948
10949 if (to_device) {
10950 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
10951 } else {
10952 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
10953 }
10954
10955 ret = -ENODEV;
10956 for (i = 0; i < 40; i++) {
10957 u32 val;
10958
10959 if (to_device)
10960 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
10961 else
10962 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
10963 if ((val & 0xffff) == sram_dma_descs) {
10964 ret = 0;
10965 break;
10966 }
10967
10968 udelay(100);
10969 }
10970
10971 return ret;
10972 }
10973
10974 #define TEST_BUFFER_SIZE 0x2000
10975
10976 static int __devinit tg3_test_dma(struct tg3 *tp)
10977 {
10978 dma_addr_t buf_dma;
10979 u32 *buf, saved_dma_rwctrl;
10980 int ret;
10981
10982 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
10983 if (!buf) {
10984 ret = -ENOMEM;
10985 goto out_nofree;
10986 }
10987
10988 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
10989 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
10990
10991 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
10992
10993 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
10994 /* DMA read watermark not used on PCIE */
10995 tp->dma_rwctrl |= 0x00180000;
10996 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
10997 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
10998 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
10999 tp->dma_rwctrl |= 0x003f0000;
11000 else
11001 tp->dma_rwctrl |= 0x003f000f;
11002 } else {
11003 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
11004 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
11005 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
11006
11007 /* If the 5704 is behind the EPB bridge, we can
11008 * do the less restrictive ONE_DMA workaround for
11009 * better performance.
11010 */
11011 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
11012 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
11013 tp->dma_rwctrl |= 0x8000;
11014 else if (ccval == 0x6 || ccval == 0x7)
11015 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
11016
11017 /* Set bit 23 to enable PCIX hw bug fix */
11018 tp->dma_rwctrl |= 0x009f0000;
11019 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
11020 /* 5780 always in PCIX mode */
11021 tp->dma_rwctrl |= 0x00144000;
11022 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
11023 /* 5714 always in PCIX mode */
11024 tp->dma_rwctrl |= 0x00148000;
11025 } else {
11026 tp->dma_rwctrl |= 0x001b000f;
11027 }
11028 }
11029
11030 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
11031 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
11032 tp->dma_rwctrl &= 0xfffffff0;
11033
11034 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11035 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
11036 /* Remove this if it causes problems for some boards. */
11037 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
11038
11039 /* On 5700/5701 chips, we need to set this bit.
11040 * Otherwise the chip will issue cacheline transactions
11041 * to streamable DMA memory with not all the byte
11042 * enables turned on. This is an error on several
11043 * RISC PCI controllers, in particular sparc64.
11044 *
11045 * On 5703/5704 chips, this bit has been reassigned
11046 * a different meaning. In particular, it is used
11047 * on those chips to enable a PCI-X workaround.
11048 */
11049 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
11050 }
11051
11052 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11053
11054 #if 0
11055 /* Unneeded, already done by tg3_get_invariants. */
11056 tg3_switch_clocks(tp);
11057 #endif
11058
11059 ret = 0;
11060 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11061 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
11062 goto out;
11063
11064 /* It is best to perform DMA test with maximum write burst size
11065 * to expose the 5700/5701 write DMA bug.
11066 */
11067 saved_dma_rwctrl = tp->dma_rwctrl;
11068 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11069 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11070
11071 while (1) {
11072 u32 *p = buf, i;
11073
11074 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
11075 p[i] = i;
11076
11077 /* Send the buffer to the chip. */
11078 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
11079 if (ret) {
11080 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
11081 break;
11082 }
11083
11084 #if 0
11085 /* validate data reached card RAM correctly. */
11086 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
11087 u32 val;
11088 tg3_read_mem(tp, 0x2100 + (i*4), &val);
11089 if (le32_to_cpu(val) != p[i]) {
11090 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
11091 /* ret = -ENODEV here? */
11092 }
11093 p[i] = 0;
11094 }
11095 #endif
11096 /* Now read it back. */
11097 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
11098 if (ret) {
11099 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
11100
11101 break;
11102 }
11103
11104 /* Verify it. */
11105 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
11106 if (p[i] == i)
11107 continue;
11108
11109 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
11110 DMA_RWCTRL_WRITE_BNDRY_16) {
11111 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11112 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
11113 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11114 break;
11115 } else {
11116 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
11117 ret = -ENODEV;
11118 goto out;
11119 }
11120 }
11121
11122 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
11123 /* Success. */
11124 ret = 0;
11125 break;
11126 }
11127 }
11128 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
11129 DMA_RWCTRL_WRITE_BNDRY_16) {
11130 static struct pci_device_id dma_wait_state_chipsets[] = {
11131 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
11132 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
11133 { },
11134 };
11135
11136 /* DMA test passed without adjusting DMA boundary,
11137 * now look for chipsets that are known to expose the
11138 * DMA bug without failing the test.
11139 */
11140 if (pci_dev_present(dma_wait_state_chipsets)) {
11141 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11142 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
11143 }
11144 else
11145 /* Safe to use the calculated DMA boundary. */
11146 tp->dma_rwctrl = saved_dma_rwctrl;
11147
11148 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11149 }
11150
11151 out:
11152 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
11153 out_nofree:
11154 return ret;
11155 }
11156
11157 static void __devinit tg3_init_link_config(struct tg3 *tp)
11158 {
11159 tp->link_config.advertising =
11160 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11161 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11162 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
11163 ADVERTISED_Autoneg | ADVERTISED_MII);
11164 tp->link_config.speed = SPEED_INVALID;
11165 tp->link_config.duplex = DUPLEX_INVALID;
11166 tp->link_config.autoneg = AUTONEG_ENABLE;
11167 tp->link_config.active_speed = SPEED_INVALID;
11168 tp->link_config.active_duplex = DUPLEX_INVALID;
11169 tp->link_config.phy_is_low_power = 0;
11170 tp->link_config.orig_speed = SPEED_INVALID;
11171 tp->link_config.orig_duplex = DUPLEX_INVALID;
11172 tp->link_config.orig_autoneg = AUTONEG_INVALID;
11173 }
11174
11175 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
11176 {
11177 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11178 tp->bufmgr_config.mbuf_read_dma_low_water =
11179 DEFAULT_MB_RDMA_LOW_WATER_5705;
11180 tp->bufmgr_config.mbuf_mac_rx_low_water =
11181 DEFAULT_MB_MACRX_LOW_WATER_5705;
11182 tp->bufmgr_config.mbuf_high_water =
11183 DEFAULT_MB_HIGH_WATER_5705;
11184
11185 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11186 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
11187 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
11188 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
11189 tp->bufmgr_config.mbuf_high_water_jumbo =
11190 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
11191 } else {
11192 tp->bufmgr_config.mbuf_read_dma_low_water =
11193 DEFAULT_MB_RDMA_LOW_WATER;
11194 tp->bufmgr_config.mbuf_mac_rx_low_water =
11195 DEFAULT_MB_MACRX_LOW_WATER;
11196 tp->bufmgr_config.mbuf_high_water =
11197 DEFAULT_MB_HIGH_WATER;
11198
11199 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11200 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
11201 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
11202 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
11203 tp->bufmgr_config.mbuf_high_water_jumbo =
11204 DEFAULT_MB_HIGH_WATER_JUMBO;
11205 }
11206
11207 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
11208 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
11209 }
11210
11211 static char * __devinit tg3_phy_string(struct tg3 *tp)
11212 {
11213 switch (tp->phy_id & PHY_ID_MASK) {
11214 case PHY_ID_BCM5400: return "5400";
11215 case PHY_ID_BCM5401: return "5401";
11216 case PHY_ID_BCM5411: return "5411";
11217 case PHY_ID_BCM5701: return "5701";
11218 case PHY_ID_BCM5703: return "5703";
11219 case PHY_ID_BCM5704: return "5704";
11220 case PHY_ID_BCM5705: return "5705";
11221 case PHY_ID_BCM5750: return "5750";
11222 case PHY_ID_BCM5752: return "5752";
11223 case PHY_ID_BCM5714: return "5714";
11224 case PHY_ID_BCM5780: return "5780";
11225 case PHY_ID_BCM5755: return "5755";
11226 case PHY_ID_BCM5787: return "5787";
11227 case PHY_ID_BCM8002: return "8002/serdes";
11228 case 0: return "serdes";
11229 default: return "unknown";
11230 };
11231 }
11232
11233 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
11234 {
11235 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11236 strcpy(str, "PCI Express");
11237 return str;
11238 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
11239 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
11240
11241 strcpy(str, "PCIX:");
11242
11243 if ((clock_ctrl == 7) ||
11244 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
11245 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
11246 strcat(str, "133MHz");
11247 else if (clock_ctrl == 0)
11248 strcat(str, "33MHz");
11249 else if (clock_ctrl == 2)
11250 strcat(str, "50MHz");
11251 else if (clock_ctrl == 4)
11252 strcat(str, "66MHz");
11253 else if (clock_ctrl == 6)
11254 strcat(str, "100MHz");
11255 } else {
11256 strcpy(str, "PCI:");
11257 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
11258 strcat(str, "66MHz");
11259 else
11260 strcat(str, "33MHz");
11261 }
11262 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
11263 strcat(str, ":32-bit");
11264 else
11265 strcat(str, ":64-bit");
11266 return str;
11267 }
11268
11269 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
11270 {
11271 struct pci_dev *peer;
11272 unsigned int func, devnr = tp->pdev->devfn & ~7;
11273
11274 for (func = 0; func < 8; func++) {
11275 peer = pci_get_slot(tp->pdev->bus, devnr | func);
11276 if (peer && peer != tp->pdev)
11277 break;
11278 pci_dev_put(peer);
11279 }
11280 /* 5704 can be configured in single-port mode, set peer to
11281 * tp->pdev in that case.
11282 */
11283 if (!peer) {
11284 peer = tp->pdev;
11285 return peer;
11286 }
11287
11288 /*
11289 * We don't need to keep the refcount elevated; there's no way
11290 * to remove one half of this device without removing the other
11291 */
11292 pci_dev_put(peer);
11293
11294 return peer;
11295 }
11296
11297 static void __devinit tg3_init_coal(struct tg3 *tp)
11298 {
11299 struct ethtool_coalesce *ec = &tp->coal;
11300
11301 memset(ec, 0, sizeof(*ec));
11302 ec->cmd = ETHTOOL_GCOALESCE;
11303 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
11304 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
11305 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
11306 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
11307 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
11308 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
11309 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
11310 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
11311 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
11312
11313 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
11314 HOSTCC_MODE_CLRTICK_TXBD)) {
11315 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
11316 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
11317 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
11318 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
11319 }
11320
11321 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11322 ec->rx_coalesce_usecs_irq = 0;
11323 ec->tx_coalesce_usecs_irq = 0;
11324 ec->stats_block_coalesce_usecs = 0;
11325 }
11326 }
11327
11328 static int __devinit tg3_init_one(struct pci_dev *pdev,
11329 const struct pci_device_id *ent)
11330 {
11331 static int tg3_version_printed = 0;
11332 unsigned long tg3reg_base, tg3reg_len;
11333 struct net_device *dev;
11334 struct tg3 *tp;
11335 int i, err, pm_cap;
11336 char str[40];
11337 u64 dma_mask, persist_dma_mask;
11338
11339 if (tg3_version_printed++ == 0)
11340 printk(KERN_INFO "%s", version);
11341
11342 err = pci_enable_device(pdev);
11343 if (err) {
11344 printk(KERN_ERR PFX "Cannot enable PCI device, "
11345 "aborting.\n");
11346 return err;
11347 }
11348
11349 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
11350 printk(KERN_ERR PFX "Cannot find proper PCI device "
11351 "base address, aborting.\n");
11352 err = -ENODEV;
11353 goto err_out_disable_pdev;
11354 }
11355
11356 err = pci_request_regions(pdev, DRV_MODULE_NAME);
11357 if (err) {
11358 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
11359 "aborting.\n");
11360 goto err_out_disable_pdev;
11361 }
11362
11363 pci_set_master(pdev);
11364
11365 /* Find power-management capability. */
11366 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
11367 if (pm_cap == 0) {
11368 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
11369 "aborting.\n");
11370 err = -EIO;
11371 goto err_out_free_res;
11372 }
11373
11374 tg3reg_base = pci_resource_start(pdev, 0);
11375 tg3reg_len = pci_resource_len(pdev, 0);
11376
11377 dev = alloc_etherdev(sizeof(*tp));
11378 if (!dev) {
11379 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
11380 err = -ENOMEM;
11381 goto err_out_free_res;
11382 }
11383
11384 SET_MODULE_OWNER(dev);
11385 SET_NETDEV_DEV(dev, &pdev->dev);
11386
11387 #if TG3_VLAN_TAG_USED
11388 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
11389 dev->vlan_rx_register = tg3_vlan_rx_register;
11390 dev->vlan_rx_kill_vid = tg3_vlan_rx_kill_vid;
11391 #endif
11392
11393 tp = netdev_priv(dev);
11394 tp->pdev = pdev;
11395 tp->dev = dev;
11396 tp->pm_cap = pm_cap;
11397 tp->mac_mode = TG3_DEF_MAC_MODE;
11398 tp->rx_mode = TG3_DEF_RX_MODE;
11399 tp->tx_mode = TG3_DEF_TX_MODE;
11400 tp->mi_mode = MAC_MI_MODE_BASE;
11401 if (tg3_debug > 0)
11402 tp->msg_enable = tg3_debug;
11403 else
11404 tp->msg_enable = TG3_DEF_MSG_ENABLE;
11405
11406 /* The word/byte swap controls here control register access byte
11407 * swapping. DMA data byte swapping is controlled in the GRC_MODE
11408 * setting below.
11409 */
11410 tp->misc_host_ctrl =
11411 MISC_HOST_CTRL_MASK_PCI_INT |
11412 MISC_HOST_CTRL_WORD_SWAP |
11413 MISC_HOST_CTRL_INDIR_ACCESS |
11414 MISC_HOST_CTRL_PCISTATE_RW;
11415
11416 /* The NONFRM (non-frame) byte/word swap controls take effect
11417 * on descriptor entries, anything which isn't packet data.
11418 *
11419 * The StrongARM chips on the board (one for tx, one for rx)
11420 * are running in big-endian mode.
11421 */
11422 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
11423 GRC_MODE_WSWAP_NONFRM_DATA);
11424 #ifdef __BIG_ENDIAN
11425 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
11426 #endif
11427 spin_lock_init(&tp->lock);
11428 spin_lock_init(&tp->indirect_lock);
11429 INIT_WORK(&tp->reset_task, tg3_reset_task, tp);
11430
11431 tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
11432 if (tp->regs == 0UL) {
11433 printk(KERN_ERR PFX "Cannot map device registers, "
11434 "aborting.\n");
11435 err = -ENOMEM;
11436 goto err_out_free_dev;
11437 }
11438
11439 tg3_init_link_config(tp);
11440
11441 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
11442 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
11443 tp->tx_pending = TG3_DEF_TX_RING_PENDING;
11444
11445 dev->open = tg3_open;
11446 dev->stop = tg3_close;
11447 dev->get_stats = tg3_get_stats;
11448 dev->set_multicast_list = tg3_set_rx_mode;
11449 dev->set_mac_address = tg3_set_mac_addr;
11450 dev->do_ioctl = tg3_ioctl;
11451 dev->tx_timeout = tg3_tx_timeout;
11452 dev->poll = tg3_poll;
11453 dev->ethtool_ops = &tg3_ethtool_ops;
11454 dev->weight = 64;
11455 dev->watchdog_timeo = TG3_TX_TIMEOUT;
11456 dev->change_mtu = tg3_change_mtu;
11457 dev->irq = pdev->irq;
11458 #ifdef CONFIG_NET_POLL_CONTROLLER
11459 dev->poll_controller = tg3_poll_controller;
11460 #endif
11461
11462 err = tg3_get_invariants(tp);
11463 if (err) {
11464 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
11465 "aborting.\n");
11466 goto err_out_iounmap;
11467 }
11468
11469 /* The EPB bridge inside 5714, 5715, and 5780 and any
11470 * device behind the EPB cannot support DMA addresses > 40-bit.
11471 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
11472 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
11473 * do DMA address check in tg3_start_xmit().
11474 */
11475 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
11476 persist_dma_mask = dma_mask = DMA_32BIT_MASK;
11477 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
11478 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
11479 #ifdef CONFIG_HIGHMEM
11480 dma_mask = DMA_64BIT_MASK;
11481 #endif
11482 } else
11483 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
11484
11485 /* Configure DMA attributes. */
11486 if (dma_mask > DMA_32BIT_MASK) {
11487 err = pci_set_dma_mask(pdev, dma_mask);
11488 if (!err) {
11489 dev->features |= NETIF_F_HIGHDMA;
11490 err = pci_set_consistent_dma_mask(pdev,
11491 persist_dma_mask);
11492 if (err < 0) {
11493 printk(KERN_ERR PFX "Unable to obtain 64 bit "
11494 "DMA for consistent allocations\n");
11495 goto err_out_iounmap;
11496 }
11497 }
11498 }
11499 if (err || dma_mask == DMA_32BIT_MASK) {
11500 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
11501 if (err) {
11502 printk(KERN_ERR PFX "No usable DMA configuration, "
11503 "aborting.\n");
11504 goto err_out_iounmap;
11505 }
11506 }
11507
11508 tg3_init_bufmgr_config(tp);
11509
11510 #if TG3_TSO_SUPPORT != 0
11511 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
11512 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
11513 }
11514 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11515 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
11516 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
11517 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
11518 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
11519 } else {
11520 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
11521 }
11522
11523 /* TSO is on by default on chips that support hardware TSO.
11524 * Firmware TSO on older chips gives lower performance, so it
11525 * is off by default, but can be enabled using ethtool.
11526 */
11527 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
11528 dev->features |= NETIF_F_TSO;
11529 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
11530 dev->features |= NETIF_F_TSO6;
11531 }
11532
11533 #endif
11534
11535 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
11536 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
11537 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
11538 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
11539 tp->rx_pending = 63;
11540 }
11541
11542 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11543 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
11544 tp->pdev_peer = tg3_find_peer(tp);
11545
11546 err = tg3_get_device_address(tp);
11547 if (err) {
11548 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
11549 "aborting.\n");
11550 goto err_out_iounmap;
11551 }
11552
11553 /*
11554 * Reset chip in case UNDI or EFI driver did not shutdown
11555 * DMA self test will enable WDMAC and we'll see (spurious)
11556 * pending DMA on the PCI bus at that point.
11557 */
11558 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
11559 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
11560 pci_save_state(tp->pdev);
11561 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
11562 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11563 }
11564
11565 err = tg3_test_dma(tp);
11566 if (err) {
11567 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
11568 goto err_out_iounmap;
11569 }
11570
11571 /* Tigon3 can do ipv4 only... and some chips have buggy
11572 * checksumming.
11573 */
11574 if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
11575 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
11576 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
11577 dev->features |= NETIF_F_HW_CSUM;
11578 else
11579 dev->features |= NETIF_F_IP_CSUM;
11580 dev->features |= NETIF_F_SG;
11581 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
11582 } else
11583 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
11584
11585 /* flow control autonegotiation is default behavior */
11586 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
11587
11588 tg3_init_coal(tp);
11589
11590 /* Now that we have fully setup the chip, save away a snapshot
11591 * of the PCI config space. We need to restore this after
11592 * GRC_MISC_CFG core clock resets and some resume events.
11593 */
11594 pci_save_state(tp->pdev);
11595
11596 err = register_netdev(dev);
11597 if (err) {
11598 printk(KERN_ERR PFX "Cannot register net device, "
11599 "aborting.\n");
11600 goto err_out_iounmap;
11601 }
11602
11603 pci_set_drvdata(pdev, dev);
11604
11605 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (%s) %sBaseT Ethernet ",
11606 dev->name,
11607 tp->board_part_number,
11608 tp->pci_chip_rev_id,
11609 tg3_phy_string(tp),
11610 tg3_bus_string(tp, str),
11611 (tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100" : "10/100/1000");
11612
11613 for (i = 0; i < 6; i++)
11614 printk("%2.2x%c", dev->dev_addr[i],
11615 i == 5 ? '\n' : ':');
11616
11617 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
11618 "MIirq[%d] ASF[%d] Split[%d] WireSpeed[%d] "
11619 "TSOcap[%d] \n",
11620 dev->name,
11621 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
11622 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
11623 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
11624 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
11625 (tp->tg3_flags & TG3_FLAG_SPLIT_MODE) != 0,
11626 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
11627 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
11628 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
11629 dev->name, tp->dma_rwctrl,
11630 (pdev->dma_mask == DMA_32BIT_MASK) ? 32 :
11631 (((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64));
11632
11633 netif_carrier_off(tp->dev);
11634
11635 return 0;
11636
11637 err_out_iounmap:
11638 if (tp->regs) {
11639 iounmap(tp->regs);
11640 tp->regs = NULL;
11641 }
11642
11643 err_out_free_dev:
11644 free_netdev(dev);
11645
11646 err_out_free_res:
11647 pci_release_regions(pdev);
11648
11649 err_out_disable_pdev:
11650 pci_disable_device(pdev);
11651 pci_set_drvdata(pdev, NULL);
11652 return err;
11653 }
11654
11655 static void __devexit tg3_remove_one(struct pci_dev *pdev)
11656 {
11657 struct net_device *dev = pci_get_drvdata(pdev);
11658
11659 if (dev) {
11660 struct tg3 *tp = netdev_priv(dev);
11661
11662 flush_scheduled_work();
11663 unregister_netdev(dev);
11664 if (tp->regs) {
11665 iounmap(tp->regs);
11666 tp->regs = NULL;
11667 }
11668 free_netdev(dev);
11669 pci_release_regions(pdev);
11670 pci_disable_device(pdev);
11671 pci_set_drvdata(pdev, NULL);
11672 }
11673 }
11674
11675 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
11676 {
11677 struct net_device *dev = pci_get_drvdata(pdev);
11678 struct tg3 *tp = netdev_priv(dev);
11679 int err;
11680
11681 if (!netif_running(dev))
11682 return 0;
11683
11684 flush_scheduled_work();
11685 tg3_netif_stop(tp);
11686
11687 del_timer_sync(&tp->timer);
11688
11689 tg3_full_lock(tp, 1);
11690 tg3_disable_ints(tp);
11691 tg3_full_unlock(tp);
11692
11693 netif_device_detach(dev);
11694
11695 tg3_full_lock(tp, 0);
11696 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11697 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
11698 tg3_full_unlock(tp);
11699
11700 err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
11701 if (err) {
11702 tg3_full_lock(tp, 0);
11703
11704 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
11705 if (tg3_restart_hw(tp, 1))
11706 goto out;
11707
11708 tp->timer.expires = jiffies + tp->timer_offset;
11709 add_timer(&tp->timer);
11710
11711 netif_device_attach(dev);
11712 tg3_netif_start(tp);
11713
11714 out:
11715 tg3_full_unlock(tp);
11716 }
11717
11718 return err;
11719 }
11720
11721 static int tg3_resume(struct pci_dev *pdev)
11722 {
11723 struct net_device *dev = pci_get_drvdata(pdev);
11724 struct tg3 *tp = netdev_priv(dev);
11725 int err;
11726
11727 if (!netif_running(dev))
11728 return 0;
11729
11730 pci_restore_state(tp->pdev);
11731
11732 err = tg3_set_power_state(tp, PCI_D0);
11733 if (err)
11734 return err;
11735
11736 netif_device_attach(dev);
11737
11738 tg3_full_lock(tp, 0);
11739
11740 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
11741 err = tg3_restart_hw(tp, 1);
11742 if (err)
11743 goto out;
11744
11745 tp->timer.expires = jiffies + tp->timer_offset;
11746 add_timer(&tp->timer);
11747
11748 tg3_netif_start(tp);
11749
11750 out:
11751 tg3_full_unlock(tp);
11752
11753 return err;
11754 }
11755
11756 static struct pci_driver tg3_driver = {
11757 .name = DRV_MODULE_NAME,
11758 .id_table = tg3_pci_tbl,
11759 .probe = tg3_init_one,
11760 .remove = __devexit_p(tg3_remove_one),
11761 .suspend = tg3_suspend,
11762 .resume = tg3_resume
11763 };
11764
11765 static int __init tg3_init(void)
11766 {
11767 return pci_register_driver(&tg3_driver);
11768 }
11769
11770 static void __exit tg3_cleanup(void)
11771 {
11772 pci_unregister_driver(&tg3_driver);
11773 }
11774
11775 module_init(tg3_init);
11776 module_exit(tg3_cleanup);
Verdex Pro support