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[SUNLANCE]: Mark sparc_lance_probe_one as __devinit.
[linux-2.6/verdex.git] / drivers / serial / cpm_uart / cpm_uart_cpm2.c
blobef3bb476c4326ab5c46b98cc43530a48c3312b93
1 /*
2 * linux/drivers/serial/cpm_uart_cpm2.c
3 *
4 * Driver for CPM (SCC/SMC) serial ports; CPM2 definitions
5 *
6 * Maintainer: Kumar Gala (galak@kernel.crashing.org) (CPM2)
7 * Pantelis Antoniou (panto@intracom.gr) (CPM1)
8 *
9 * Copyright (C) 2004 Freescale Semiconductor, Inc.
10 * (C) 2004 Intracom, S.A.
11 * (C) 2006 MontaVista Software, Inc.
12 * Vitaly Bordug <vbordug@ru.mvista.com>
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27 *
28 */
29
30 #include <linux/module.h>
31 #include <linux/tty.h>
32 #include <linux/ioport.h>
33 #include <linux/init.h>
34 #include <linux/serial.h>
35 #include <linux/console.h>
36 #include <linux/sysrq.h>
37 #include <linux/device.h>
38 #include <linux/bootmem.h>
39 #include <linux/dma-mapping.h>
40
41 #include <asm/io.h>
42 #include <asm/irq.h>
43
44 #include <linux/serial_core.h>
45 #include <linux/kernel.h>
46
47 #include "cpm_uart.h"
48
49 /**************************************************************/
50
51 void cpm_line_cr_cmd(int line, int cmd)
52 {
53 volatile cpm_cpm2_t *cp = cpmp;
54 ulong val;
55
56 switch (line) {
57 case UART_SMC1:
58 val = mk_cr_cmd(CPM_CR_SMC1_PAGE, CPM_CR_SMC1_SBLOCK, 0,
59 cmd) | CPM_CR_FLG;
60 break;
61 case UART_SMC2:
62 val = mk_cr_cmd(CPM_CR_SMC2_PAGE, CPM_CR_SMC2_SBLOCK, 0,
63 cmd) | CPM_CR_FLG;
64 break;
65 case UART_SCC1:
66 val = mk_cr_cmd(CPM_CR_SCC1_PAGE, CPM_CR_SCC1_SBLOCK, 0,
67 cmd) | CPM_CR_FLG;
68 break;
69 case UART_SCC2:
70 val = mk_cr_cmd(CPM_CR_SCC2_PAGE, CPM_CR_SCC2_SBLOCK, 0,
71 cmd) | CPM_CR_FLG;
72 break;
73 case UART_SCC3:
74 val = mk_cr_cmd(CPM_CR_SCC3_PAGE, CPM_CR_SCC3_SBLOCK, 0,
75 cmd) | CPM_CR_FLG;
76 break;
77 case UART_SCC4:
78 val = mk_cr_cmd(CPM_CR_SCC4_PAGE, CPM_CR_SCC4_SBLOCK, 0,
79 cmd) | CPM_CR_FLG;
80 break;
81 default:
82 return;
83
84 }
85 cp->cp_cpcr = val;
86 while (cp->cp_cpcr & CPM_CR_FLG) ;
87 }
88
89 void smc1_lineif(struct uart_cpm_port *pinfo)
90 {
91 volatile iop_cpm2_t *io = &cpm2_immr->im_ioport;
92
93 /* SMC1 is only on port D */
94 io->iop_ppard |= 0x00c00000;
95 io->iop_pdird |= 0x00400000;
96 io->iop_pdird &= ~0x00800000;
97 io->iop_psord &= ~0x00c00000;
98
99 /* Wire BRG1 to SMC1 */
100 cpm2_immr->im_cpmux.cmx_smr &= 0x0f;
101 pinfo->brg = 1;
102 }
103
104 void smc2_lineif(struct uart_cpm_port *pinfo)
105 {
106 volatile iop_cpm2_t *io = &cpm2_immr->im_ioport;
107
108 /* SMC2 is only on port A */
109 io->iop_ppara |= 0x00c00000;
110 io->iop_pdira |= 0x00400000;
111 io->iop_pdira &= ~0x00800000;
112 io->iop_psora &= ~0x00c00000;
113
114 /* Wire BRG2 to SMC2 */
115 cpm2_immr->im_cpmux.cmx_smr &= 0xf0;
116 pinfo->brg = 2;
117 }
118
119 void scc1_lineif(struct uart_cpm_port *pinfo)
120 {
121 volatile iop_cpm2_t *io = &cpm2_immr->im_ioport;
122
123 /* Use Port D for SCC1 instead of other functions. */
124 io->iop_ppard |= 0x00000003;
125 io->iop_psord &= ~0x00000001; /* Rx */
126 io->iop_psord |= 0x00000002; /* Tx */
127 io->iop_pdird &= ~0x00000001; /* Rx */
128 io->iop_pdird |= 0x00000002; /* Tx */
129
130 /* Wire BRG1 to SCC1 */
131 cpm2_immr->im_cpmux.cmx_scr &= 0x00ffffff;
132 cpm2_immr->im_cpmux.cmx_scr |= 0x00000000;
133 pinfo->brg = 1;
134 }
135
136 void scc2_lineif(struct uart_cpm_port *pinfo)
137 {
138 /*
139 * STx GP3 uses the SCC2 secondary option pin assignment
140 * which this driver doesn't account for in the static
141 * pin assignments. This kind of board specific info
142 * really has to get out of the driver so boards can
143 * be supported in a sane fashion.
144 */
145 #ifndef CONFIG_STX_GP3
146 volatile iop_cpm2_t *io = &cpm2_immr->im_ioport;
147 io->iop_pparb |= 0x008b0000;
148 io->iop_pdirb |= 0x00880000;
149 io->iop_psorb |= 0x00880000;
150 io->iop_pdirb &= ~0x00030000;
151 io->iop_psorb &= ~0x00030000;
152 #endif
153 cpm2_immr->im_cpmux.cmx_scr &= 0xff00ffff;
154 cpm2_immr->im_cpmux.cmx_scr |= 0x00090000;
155 pinfo->brg = 2;
156 }
157
158 void scc3_lineif(struct uart_cpm_port *pinfo)
159 {
160 volatile iop_cpm2_t *io = &cpm2_immr->im_ioport;
161 io->iop_pparb |= 0x008b0000;
162 io->iop_pdirb |= 0x00880000;
163 io->iop_psorb |= 0x00880000;
164 io->iop_pdirb &= ~0x00030000;
165 io->iop_psorb &= ~0x00030000;
166 cpm2_immr->im_cpmux.cmx_scr &= 0xffff00ff;
167 cpm2_immr->im_cpmux.cmx_scr |= 0x00001200;
168 pinfo->brg = 3;
169 }
170
171 void scc4_lineif(struct uart_cpm_port *pinfo)
172 {
173 volatile iop_cpm2_t *io = &cpm2_immr->im_ioport;
174
175 io->iop_ppard |= 0x00000600;
176 io->iop_psord &= ~0x00000600; /* Tx/Rx */
177 io->iop_pdird &= ~0x00000200; /* Rx */
178 io->iop_pdird |= 0x00000400; /* Tx */
179
180 cpm2_immr->im_cpmux.cmx_scr &= 0xffffff00;
181 cpm2_immr->im_cpmux.cmx_scr |= 0x0000001b;
182 pinfo->brg = 4;
183 }
184
185 /*
186 * Allocate DP-Ram and memory buffers. We need to allocate a transmit and
187 * receive buffer descriptors from dual port ram, and a character
188 * buffer area from host mem. If we are allocating for the console we need
189 * to do it from bootmem
190 */
191 int cpm_uart_allocbuf(struct uart_cpm_port *pinfo, unsigned int is_con)
192 {
193 int dpmemsz, memsz;
194 u8 *dp_mem;
195 uint dp_offset;
196 u8 *mem_addr;
197 dma_addr_t dma_addr = 0;
198
199 pr_debug("CPM uart[%d]:allocbuf\n", pinfo->port.line);
200
201 dpmemsz = sizeof(cbd_t) * (pinfo->rx_nrfifos + pinfo->tx_nrfifos);
202 dp_offset = cpm_dpalloc(dpmemsz, 8);
203 if (IS_DPERR(dp_offset)) {
204 printk(KERN_ERR
205 "cpm_uart_cpm.c: could not allocate buffer descriptors\n");
206 return -ENOMEM;
207 }
208
209 dp_mem = cpm_dpram_addr(dp_offset);
210
211 memsz = L1_CACHE_ALIGN(pinfo->rx_nrfifos * pinfo->rx_fifosize) +
212 L1_CACHE_ALIGN(pinfo->tx_nrfifos * pinfo->tx_fifosize);
213 if (is_con) {
214 mem_addr = alloc_bootmem(memsz);
215 dma_addr = virt_to_bus(mem_addr);
216 }
217 else
218 mem_addr = dma_alloc_coherent(NULL, memsz, &dma_addr,
219 GFP_KERNEL);
220
221 if (mem_addr == NULL) {
222 cpm_dpfree(dp_offset);
223 printk(KERN_ERR
224 "cpm_uart_cpm.c: could not allocate coherent memory\n");
225 return -ENOMEM;
226 }
227
228 pinfo->dp_addr = dp_offset;
229 pinfo->mem_addr = mem_addr;
230 pinfo->dma_addr = dma_addr;
231 pinfo->mem_size = memsz;
232
233 pinfo->rx_buf = mem_addr;
234 pinfo->tx_buf = pinfo->rx_buf + L1_CACHE_ALIGN(pinfo->rx_nrfifos
235 * pinfo->rx_fifosize);
236
237 pinfo->rx_bd_base = (volatile cbd_t *)dp_mem;
238 pinfo->tx_bd_base = pinfo->rx_bd_base + pinfo->rx_nrfifos;
239
240 return 0;
241 }
242
243 void cpm_uart_freebuf(struct uart_cpm_port *pinfo)
244 {
245 dma_free_coherent(NULL, L1_CACHE_ALIGN(pinfo->rx_nrfifos *
246 pinfo->rx_fifosize) +
247 L1_CACHE_ALIGN(pinfo->tx_nrfifos *
248 pinfo->tx_fifosize), pinfo->mem_addr,
249 pinfo->dma_addr);
250
251 cpm_dpfree(pinfo->dp_addr);
252 }
253
254 /* Setup any dynamic params in the uart desc */
255 int cpm_uart_init_portdesc(void)
256 {
257 pr_debug("CPM uart[-]:init portdesc\n");
258
259 cpm_uart_nr = 0;
260 #ifdef CONFIG_SERIAL_CPM_SMC1
261 cpm_uart_ports[UART_SMC1].smcp = (smc_t *) & cpm2_immr->im_smc[0];
262 cpm_uart_ports[UART_SMC1].smcup =
263 (smc_uart_t *) & cpm2_immr->im_dprambase[PROFF_SMC1];
264 *(u16 *)(&cpm2_immr->im_dprambase[PROFF_SMC1_BASE]) = PROFF_SMC1;
265 cpm_uart_ports[UART_SMC1].port.mapbase =
266 (unsigned long)&cpm2_immr->im_smc[0];
267 cpm_uart_ports[UART_SMC1].smcp->smc_smcm |= (SMCM_RX | SMCM_TX);
268 cpm_uart_ports[UART_SMC1].smcp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
269 cpm_uart_ports[UART_SMC1].port.uartclk = (((bd_t *) __res)->bi_intfreq);
270 cpm_uart_port_map[cpm_uart_nr++] = UART_SMC1;
271 #endif
272
273 #ifdef CONFIG_SERIAL_CPM_SMC2
274 cpm_uart_ports[UART_SMC2].smcp = (smc_t *) & cpm2_immr->im_smc[1];
275 cpm_uart_ports[UART_SMC2].smcup =
276 (smc_uart_t *) & cpm2_immr->im_dprambase[PROFF_SMC2];
277 *(u16 *)(&cpm2_immr->im_dprambase[PROFF_SMC2_BASE]) = PROFF_SMC2;
278 cpm_uart_ports[UART_SMC2].port.mapbase =
279 (unsigned long)&cpm2_immr->im_smc[1];
280 cpm_uart_ports[UART_SMC2].smcp->smc_smcm |= (SMCM_RX | SMCM_TX);
281 cpm_uart_ports[UART_SMC2].smcp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
282 cpm_uart_ports[UART_SMC2].port.uartclk = (((bd_t *) __res)->bi_intfreq);
283 cpm_uart_port_map[cpm_uart_nr++] = UART_SMC2;
284 #endif
285
286 #ifdef CONFIG_SERIAL_CPM_SCC1
287 cpm_uart_ports[UART_SCC1].sccp = (scc_t *) & cpm2_immr->im_scc[0];
288 cpm_uart_ports[UART_SCC1].sccup =
289 (scc_uart_t *) & cpm2_immr->im_dprambase[PROFF_SCC1];
290 cpm_uart_ports[UART_SCC1].port.mapbase =
291 (unsigned long)&cpm2_immr->im_scc[0];
292 cpm_uart_ports[UART_SCC1].sccp->scc_sccm &=
293 ~(UART_SCCM_TX | UART_SCCM_RX);
294 cpm_uart_ports[UART_SCC1].sccp->scc_gsmrl &=
295 ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
296 cpm_uart_ports[UART_SCC1].port.uartclk = (((bd_t *) __res)->bi_intfreq);
297 cpm_uart_port_map[cpm_uart_nr++] = UART_SCC1;
298 #endif
299
300 #ifdef CONFIG_SERIAL_CPM_SCC2
301 cpm_uart_ports[UART_SCC2].sccp = (scc_t *) & cpm2_immr->im_scc[1];
302 cpm_uart_ports[UART_SCC2].sccup =
303 (scc_uart_t *) & cpm2_immr->im_dprambase[PROFF_SCC2];
304 cpm_uart_ports[UART_SCC2].port.mapbase =
305 (unsigned long)&cpm2_immr->im_scc[1];
306 cpm_uart_ports[UART_SCC2].sccp->scc_sccm &=
307 ~(UART_SCCM_TX | UART_SCCM_RX);
308 cpm_uart_ports[UART_SCC2].sccp->scc_gsmrl &=
309 ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
310 cpm_uart_ports[UART_SCC2].port.uartclk = (((bd_t *) __res)->bi_intfreq);
311 cpm_uart_port_map[cpm_uart_nr++] = UART_SCC2;
312 #endif
313
314 #ifdef CONFIG_SERIAL_CPM_SCC3
315 cpm_uart_ports[UART_SCC3].sccp = (scc_t *) & cpm2_immr->im_scc[2];
316 cpm_uart_ports[UART_SCC3].sccup =
317 (scc_uart_t *) & cpm2_immr->im_dprambase[PROFF_SCC3];
318 cpm_uart_ports[UART_SCC3].port.mapbase =
319 (unsigned long)&cpm2_immr->im_scc[2];
320 cpm_uart_ports[UART_SCC3].sccp->scc_sccm &=
321 ~(UART_SCCM_TX | UART_SCCM_RX);
322 cpm_uart_ports[UART_SCC3].sccp->scc_gsmrl &=
323 ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
324 cpm_uart_ports[UART_SCC3].port.uartclk = (((bd_t *) __res)->bi_intfreq);
325 cpm_uart_port_map[cpm_uart_nr++] = UART_SCC3;
326 #endif
327
328 #ifdef CONFIG_SERIAL_CPM_SCC4
329 cpm_uart_ports[UART_SCC4].sccp = (scc_t *) & cpm2_immr->im_scc[3];
330 cpm_uart_ports[UART_SCC4].sccup =
331 (scc_uart_t *) & cpm2_immr->im_dprambase[PROFF_SCC4];
332 cpm_uart_ports[UART_SCC4].port.mapbase =
333 (unsigned long)&cpm2_immr->im_scc[3];
334 cpm_uart_ports[UART_SCC4].sccp->scc_sccm &=
335 ~(UART_SCCM_TX | UART_SCCM_RX);
336 cpm_uart_ports[UART_SCC4].sccp->scc_gsmrl &=
337 ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
338 cpm_uart_ports[UART_SCC4].port.uartclk = (((bd_t *) __res)->bi_intfreq);
339 cpm_uart_port_map[cpm_uart_nr++] = UART_SCC4;
340 #endif
341
342 return 0;
343 }
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