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[SUNLANCE]: Mark sparc_lance_probe_one as __devinit.
[linux-2.6/verdex.git] / drivers / serial / pmac_zilog.c
bloba3b99caf80e64a2f379c437ae19c2f59f012eb97
1 /*
2 * linux/drivers/serial/pmac_zilog.c
3 *
4 * Driver for PowerMac Z85c30 based ESCC cell found in the
5 * "macio" ASICs of various PowerMac models
6 *
7 * Copyright (C) 2003 Ben. Herrenschmidt (benh@kernel.crashing.org)
8 *
9 * Derived from drivers/macintosh/macserial.c by Paul Mackerras
10 * and drivers/serial/sunzilog.c by David S. Miller
11 *
12 * Hrm... actually, I ripped most of sunzilog (Thanks David !) and
13 * adapted special tweaks needed for us. I don't think it's worth
14 * merging back those though. The DMA code still has to get in
15 * and once done, I expect that driver to remain fairly stable in
16 * the long term, unless we change the driver model again...
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 *
32 * 2004-08-06 Harald Welte <laforge@gnumonks.org>
33 * - Enable BREAK interrupt
34 * - Add support for sysreq
35 *
36 * TODO: - Add DMA support
37 * - Defer port shutdown to a few seconds after close
38 * - maybe put something right into uap->clk_divisor
39 */
40
41 #undef DEBUG
42 #undef DEBUG_HARD
43 #undef USE_CTRL_O_SYSRQ
44
45 #include <linux/module.h>
46 #include <linux/tty.h>
47
48 #include <linux/tty_flip.h>
49 #include <linux/major.h>
50 #include <linux/string.h>
51 #include <linux/fcntl.h>
52 #include <linux/mm.h>
53 #include <linux/kernel.h>
54 #include <linux/delay.h>
55 #include <linux/init.h>
56 #include <linux/console.h>
57 #include <linux/slab.h>
58 #include <linux/adb.h>
59 #include <linux/pmu.h>
60 #include <linux/bitops.h>
61 #include <linux/sysrq.h>
62 #include <linux/mutex.h>
63 #include <asm/sections.h>
64 #include <asm/io.h>
65 #include <asm/irq.h>
66 #include <asm/prom.h>
67 #include <asm/machdep.h>
68 #include <asm/pmac_feature.h>
69 #include <asm/dbdma.h>
70 #include <asm/macio.h>
71
72 #if defined (CONFIG_SERIAL_PMACZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
73 #define SUPPORT_SYSRQ
74 #endif
75
76 #include <linux/serial.h>
77 #include <linux/serial_core.h>
78
79 #include "pmac_zilog.h"
80
81 /* Not yet implemented */
82 #undef HAS_DBDMA
83
84 static char version[] __initdata = "pmac_zilog: 0.6 (Benjamin Herrenschmidt <benh@kernel.crashing.org>)";
85 MODULE_AUTHOR("Benjamin Herrenschmidt <benh@kernel.crashing.org>");
86 MODULE_DESCRIPTION("Driver for the PowerMac serial ports.");
87 MODULE_LICENSE("GPL");
88
89 #define PWRDBG(fmt, arg...) printk(KERN_DEBUG fmt , ## arg)
90
91
92 /*
93 * For the sake of early serial console, we can do a pre-probe
94 * (optional) of the ports at rather early boot time.
95 */
96 static struct uart_pmac_port pmz_ports[MAX_ZS_PORTS];
97 static int pmz_ports_count;
98 static DEFINE_MUTEX(pmz_irq_mutex);
99
100 static struct uart_driver pmz_uart_reg = {
101 .owner = THIS_MODULE,
102 .driver_name = "ttyS",
103 .dev_name = "ttyS",
104 .major = TTY_MAJOR,
105 };
106
107
108 /*
109 * Load all registers to reprogram the port
110 * This function must only be called when the TX is not busy. The UART
111 * port lock must be held and local interrupts disabled.
112 */
113 static void pmz_load_zsregs(struct uart_pmac_port *uap, u8 *regs)
114 {
115 int i;
116
117 if (ZS_IS_ASLEEP(uap))
118 return;
119
120 /* Let pending transmits finish. */
121 for (i = 0; i < 1000; i++) {
122 unsigned char stat = read_zsreg(uap, R1);
123 if (stat & ALL_SNT)
124 break;
125 udelay(100);
126 }
127
128 ZS_CLEARERR(uap);
129 zssync(uap);
130 ZS_CLEARFIFO(uap);
131 zssync(uap);
132 ZS_CLEARERR(uap);
133
134 /* Disable all interrupts. */
135 write_zsreg(uap, R1,
136 regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB));
137
138 /* Set parity, sync config, stop bits, and clock divisor. */
139 write_zsreg(uap, R4, regs[R4]);
140
141 /* Set misc. TX/RX control bits. */
142 write_zsreg(uap, R10, regs[R10]);
143
144 /* Set TX/RX controls sans the enable bits. */
145 write_zsreg(uap, R3, regs[R3] & ~RxENABLE);
146 write_zsreg(uap, R5, regs[R5] & ~TxENABLE);
147
148 /* now set R7 "prime" on ESCC */
149 write_zsreg(uap, R15, regs[R15] | EN85C30);
150 write_zsreg(uap, R7, regs[R7P]);
151
152 /* make sure we use R7 "non-prime" on ESCC */
153 write_zsreg(uap, R15, regs[R15] & ~EN85C30);
154
155 /* Synchronous mode config. */
156 write_zsreg(uap, R6, regs[R6]);
157 write_zsreg(uap, R7, regs[R7]);
158
159 /* Disable baud generator. */
160 write_zsreg(uap, R14, regs[R14] & ~BRENAB);
161
162 /* Clock mode control. */
163 write_zsreg(uap, R11, regs[R11]);
164
165 /* Lower and upper byte of baud rate generator divisor. */
166 write_zsreg(uap, R12, regs[R12]);
167 write_zsreg(uap, R13, regs[R13]);
168
169 /* Now rewrite R14, with BRENAB (if set). */
170 write_zsreg(uap, R14, regs[R14]);
171
172 /* Reset external status interrupts. */
173 write_zsreg(uap, R0, RES_EXT_INT);
174 write_zsreg(uap, R0, RES_EXT_INT);
175
176 /* Rewrite R3/R5, this time without enables masked. */
177 write_zsreg(uap, R3, regs[R3]);
178 write_zsreg(uap, R5, regs[R5]);
179
180 /* Rewrite R1, this time without IRQ enabled masked. */
181 write_zsreg(uap, R1, regs[R1]);
182
183 /* Enable interrupts */
184 write_zsreg(uap, R9, regs[R9]);
185 }
186
187 /*
188 * We do like sunzilog to avoid disrupting pending Tx
189 * Reprogram the Zilog channel HW registers with the copies found in the
190 * software state struct. If the transmitter is busy, we defer this update
191 * until the next TX complete interrupt. Else, we do it right now.
192 *
193 * The UART port lock must be held and local interrupts disabled.
194 */
195 static void pmz_maybe_update_regs(struct uart_pmac_port *uap)
196 {
197 if (!ZS_REGS_HELD(uap)) {
198 if (ZS_TX_ACTIVE(uap)) {
199 uap->flags |= PMACZILOG_FLAG_REGS_HELD;
200 } else {
201 pmz_debug("pmz: maybe_update_regs: updating\n");
202 pmz_load_zsregs(uap, uap->curregs);
203 }
204 }
205 }
206
207 static struct tty_struct *pmz_receive_chars(struct uart_pmac_port *uap,
208 struct pt_regs *regs)
209 {
210 struct tty_struct *tty = NULL;
211 unsigned char ch, r1, drop, error, flag;
212 int loops = 0;
213
214 /* The interrupt can be enabled when the port isn't open, typically
215 * that happens when using one port is open and the other closed (stale
216 * interrupt) or when one port is used as a console.
217 */
218 if (!ZS_IS_OPEN(uap)) {
219 pmz_debug("pmz: draining input\n");
220 /* Port is closed, drain input data */
221 for (;;) {
222 if ((++loops) > 1000)
223 goto flood;
224 (void)read_zsreg(uap, R1);
225 write_zsreg(uap, R0, ERR_RES);
226 (void)read_zsdata(uap);
227 ch = read_zsreg(uap, R0);
228 if (!(ch & Rx_CH_AV))
229 break;
230 }
231 return NULL;
232 }
233
234 /* Sanity check, make sure the old bug is no longer happening */
235 if (uap->port.info == NULL || uap->port.info->tty == NULL) {
236 WARN_ON(1);
237 (void)read_zsdata(uap);
238 return NULL;
239 }
240 tty = uap->port.info->tty;
241
242 while (1) {
243 error = 0;
244 drop = 0;
245
246 r1 = read_zsreg(uap, R1);
247 ch = read_zsdata(uap);
248
249 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
250 write_zsreg(uap, R0, ERR_RES);
251 zssync(uap);
252 }
253
254 ch &= uap->parity_mask;
255 if (ch == 0 && uap->flags & PMACZILOG_FLAG_BREAK) {
256 uap->flags &= ~PMACZILOG_FLAG_BREAK;
257 }
258
259 #if defined(CONFIG_MAGIC_SYSRQ) && defined(CONFIG_SERIAL_CORE_CONSOLE)
260 #ifdef USE_CTRL_O_SYSRQ
261 /* Handle the SysRq ^O Hack */
262 if (ch == '\x0f') {
263 uap->port.sysrq = jiffies + HZ*5;
264 goto next_char;
265 }
266 #endif /* USE_CTRL_O_SYSRQ */
267 if (uap->port.sysrq) {
268 int swallow;
269 spin_unlock(&uap->port.lock);
270 swallow = uart_handle_sysrq_char(&uap->port, ch, regs);
271 spin_lock(&uap->port.lock);
272 if (swallow)
273 goto next_char;
274 }
275 #endif /* CONFIG_MAGIC_SYSRQ && CONFIG_SERIAL_CORE_CONSOLE */
276
277 /* A real serial line, record the character and status. */
278 if (drop)
279 goto next_char;
280
281 flag = TTY_NORMAL;
282 uap->port.icount.rx++;
283
284 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR | BRK_ABRT)) {
285 error = 1;
286 if (r1 & BRK_ABRT) {
287 pmz_debug("pmz: got break !\n");
288 r1 &= ~(PAR_ERR | CRC_ERR);
289 uap->port.icount.brk++;
290 if (uart_handle_break(&uap->port))
291 goto next_char;
292 }
293 else if (r1 & PAR_ERR)
294 uap->port.icount.parity++;
295 else if (r1 & CRC_ERR)
296 uap->port.icount.frame++;
297 if (r1 & Rx_OVR)
298 uap->port.icount.overrun++;
299 r1 &= uap->port.read_status_mask;
300 if (r1 & BRK_ABRT)
301 flag = TTY_BREAK;
302 else if (r1 & PAR_ERR)
303 flag = TTY_PARITY;
304 else if (r1 & CRC_ERR)
305 flag = TTY_FRAME;
306 }
307
308 if (uap->port.ignore_status_mask == 0xff ||
309 (r1 & uap->port.ignore_status_mask) == 0) {
310 tty_insert_flip_char(tty, ch, flag);
311 }
312 if (r1 & Rx_OVR)
313 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
314 next_char:
315 /* We can get stuck in an infinite loop getting char 0 when the
316 * line is in a wrong HW state, we break that here.
317 * When that happens, I disable the receive side of the driver.
318 * Note that what I've been experiencing is a real irq loop where
319 * I'm getting flooded regardless of the actual port speed.
320 * Something stange is going on with the HW
321 */
322 if ((++loops) > 1000)
323 goto flood;
324 ch = read_zsreg(uap, R0);
325 if (!(ch & Rx_CH_AV))
326 break;
327 }
328
329 return tty;
330 flood:
331 uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
332 write_zsreg(uap, R1, uap->curregs[R1]);
333 zssync(uap);
334 dev_err(&uap->dev->ofdev.dev, "pmz: rx irq flood !\n");
335 return tty;
336 }
337
338 static void pmz_status_handle(struct uart_pmac_port *uap, struct pt_regs *regs)
339 {
340 unsigned char status;
341
342 status = read_zsreg(uap, R0);
343 write_zsreg(uap, R0, RES_EXT_INT);
344 zssync(uap);
345
346 if (ZS_IS_OPEN(uap) && ZS_WANTS_MODEM_STATUS(uap)) {
347 if (status & SYNC_HUNT)
348 uap->port.icount.dsr++;
349
350 /* The Zilog just gives us an interrupt when DCD/CTS/etc. change.
351 * But it does not tell us which bit has changed, we have to keep
352 * track of this ourselves.
353 * The CTS input is inverted for some reason. -- paulus
354 */
355 if ((status ^ uap->prev_status) & DCD)
356 uart_handle_dcd_change(&uap->port,
357 (status & DCD));
358 if ((status ^ uap->prev_status) & CTS)
359 uart_handle_cts_change(&uap->port,
360 !(status & CTS));
361
362 wake_up_interruptible(&uap->port.info->delta_msr_wait);
363 }
364
365 if (status & BRK_ABRT)
366 uap->flags |= PMACZILOG_FLAG_BREAK;
367
368 uap->prev_status = status;
369 }
370
371 static void pmz_transmit_chars(struct uart_pmac_port *uap)
372 {
373 struct circ_buf *xmit;
374
375 if (ZS_IS_ASLEEP(uap))
376 return;
377 if (ZS_IS_CONS(uap)) {
378 unsigned char status = read_zsreg(uap, R0);
379
380 /* TX still busy? Just wait for the next TX done interrupt.
381 *
382 * It can occur because of how we do serial console writes. It would
383 * be nice to transmit console writes just like we normally would for
384 * a TTY line. (ie. buffered and TX interrupt driven). That is not
385 * easy because console writes cannot sleep. One solution might be
386 * to poll on enough port->xmit space becomming free. -DaveM
387 */
388 if (!(status & Tx_BUF_EMP))
389 return;
390 }
391
392 uap->flags &= ~PMACZILOG_FLAG_TX_ACTIVE;
393
394 if (ZS_REGS_HELD(uap)) {
395 pmz_load_zsregs(uap, uap->curregs);
396 uap->flags &= ~PMACZILOG_FLAG_REGS_HELD;
397 }
398
399 if (ZS_TX_STOPPED(uap)) {
400 uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED;
401 goto ack_tx_int;
402 }
403
404 if (uap->port.x_char) {
405 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
406 write_zsdata(uap, uap->port.x_char);
407 zssync(uap);
408 uap->port.icount.tx++;
409 uap->port.x_char = 0;
410 return;
411 }
412
413 if (uap->port.info == NULL)
414 goto ack_tx_int;
415 xmit = &uap->port.info->xmit;
416 if (uart_circ_empty(xmit)) {
417 uart_write_wakeup(&uap->port);
418 goto ack_tx_int;
419 }
420 if (uart_tx_stopped(&uap->port))
421 goto ack_tx_int;
422
423 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
424 write_zsdata(uap, xmit->buf[xmit->tail]);
425 zssync(uap);
426
427 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
428 uap->port.icount.tx++;
429
430 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
431 uart_write_wakeup(&uap->port);
432
433 return;
434
435 ack_tx_int:
436 write_zsreg(uap, R0, RES_Tx_P);
437 zssync(uap);
438 }
439
440 /* Hrm... we register that twice, fixme later.... */
441 static irqreturn_t pmz_interrupt(int irq, void *dev_id, struct pt_regs *regs)
442 {
443 struct uart_pmac_port *uap = dev_id;
444 struct uart_pmac_port *uap_a;
445 struct uart_pmac_port *uap_b;
446 int rc = IRQ_NONE;
447 struct tty_struct *tty;
448 u8 r3;
449
450 uap_a = pmz_get_port_A(uap);
451 uap_b = uap_a->mate;
452
453 spin_lock(&uap_a->port.lock);
454 r3 = read_zsreg(uap_a, R3);
455
456 #ifdef DEBUG_HARD
457 pmz_debug("irq, r3: %x\n", r3);
458 #endif
459 /* Channel A */
460 tty = NULL;
461 if (r3 & (CHAEXT | CHATxIP | CHARxIP)) {
462 write_zsreg(uap_a, R0, RES_H_IUS);
463 zssync(uap_a);
464 if (r3 & CHAEXT)
465 pmz_status_handle(uap_a, regs);
466 if (r3 & CHARxIP)
467 tty = pmz_receive_chars(uap_a, regs);
468 if (r3 & CHATxIP)
469 pmz_transmit_chars(uap_a);
470 rc = IRQ_HANDLED;
471 }
472 spin_unlock(&uap_a->port.lock);
473 if (tty != NULL)
474 tty_flip_buffer_push(tty);
475
476 if (uap_b->node == NULL)
477 goto out;
478
479 spin_lock(&uap_b->port.lock);
480 tty = NULL;
481 if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) {
482 write_zsreg(uap_b, R0, RES_H_IUS);
483 zssync(uap_b);
484 if (r3 & CHBEXT)
485 pmz_status_handle(uap_b, regs);
486 if (r3 & CHBRxIP)
487 tty = pmz_receive_chars(uap_b, regs);
488 if (r3 & CHBTxIP)
489 pmz_transmit_chars(uap_b);
490 rc = IRQ_HANDLED;
491 }
492 spin_unlock(&uap_b->port.lock);
493 if (tty != NULL)
494 tty_flip_buffer_push(tty);
495
496 out:
497 #ifdef DEBUG_HARD
498 pmz_debug("irq done.\n");
499 #endif
500 return rc;
501 }
502
503 /*
504 * Peek the status register, lock not held by caller
505 */
506 static inline u8 pmz_peek_status(struct uart_pmac_port *uap)
507 {
508 unsigned long flags;
509 u8 status;
510
511 spin_lock_irqsave(&uap->port.lock, flags);
512 status = read_zsreg(uap, R0);
513 spin_unlock_irqrestore(&uap->port.lock, flags);
514
515 return status;
516 }
517
518 /*
519 * Check if transmitter is empty
520 * The port lock is not held.
521 */
522 static unsigned int pmz_tx_empty(struct uart_port *port)
523 {
524 struct uart_pmac_port *uap = to_pmz(port);
525 unsigned char status;
526
527 if (ZS_IS_ASLEEP(uap) || uap->node == NULL)
528 return TIOCSER_TEMT;
529
530 status = pmz_peek_status(to_pmz(port));
531 if (status & Tx_BUF_EMP)
532 return TIOCSER_TEMT;
533 return 0;
534 }
535
536 /*
537 * Set Modem Control (RTS & DTR) bits
538 * The port lock is held and interrupts are disabled.
539 * Note: Shall we really filter out RTS on external ports or
540 * should that be dealt at higher level only ?
541 */
542 static void pmz_set_mctrl(struct uart_port *port, unsigned int mctrl)
543 {
544 struct uart_pmac_port *uap = to_pmz(port);
545 unsigned char set_bits, clear_bits;
546
547 /* Do nothing for irda for now... */
548 if (ZS_IS_IRDA(uap))
549 return;
550 /* We get called during boot with a port not up yet */
551 if (ZS_IS_ASLEEP(uap) ||
552 !(ZS_IS_OPEN(uap) || ZS_IS_CONS(uap)))
553 return;
554
555 set_bits = clear_bits = 0;
556
557 if (ZS_IS_INTMODEM(uap)) {
558 if (mctrl & TIOCM_RTS)
559 set_bits |= RTS;
560 else
561 clear_bits |= RTS;
562 }
563 if (mctrl & TIOCM_DTR)
564 set_bits |= DTR;
565 else
566 clear_bits |= DTR;
567
568 /* NOTE: Not subject to 'transmitter active' rule. */
569 uap->curregs[R5] |= set_bits;
570 uap->curregs[R5] &= ~clear_bits;
571 if (ZS_IS_ASLEEP(uap))
572 return;
573 write_zsreg(uap, R5, uap->curregs[R5]);
574 pmz_debug("pmz_set_mctrl: set bits: %x, clear bits: %x -> %x\n",
575 set_bits, clear_bits, uap->curregs[R5]);
576 zssync(uap);
577 }
578
579 /*
580 * Get Modem Control bits (only the input ones, the core will
581 * or that with a cached value of the control ones)
582 * The port lock is held and interrupts are disabled.
583 */
584 static unsigned int pmz_get_mctrl(struct uart_port *port)
585 {
586 struct uart_pmac_port *uap = to_pmz(port);
587 unsigned char status;
588 unsigned int ret;
589
590 if (ZS_IS_ASLEEP(uap) || uap->node == NULL)
591 return 0;
592
593 status = read_zsreg(uap, R0);
594
595 ret = 0;
596 if (status & DCD)
597 ret |= TIOCM_CAR;
598 if (status & SYNC_HUNT)
599 ret |= TIOCM_DSR;
600 if (!(status & CTS))
601 ret |= TIOCM_CTS;
602
603 return ret;
604 }
605
606 /*
607 * Stop TX side. Dealt like sunzilog at next Tx interrupt,
608 * though for DMA, we will have to do a bit more.
609 * The port lock is held and interrupts are disabled.
610 */
611 static void pmz_stop_tx(struct uart_port *port)
612 {
613 to_pmz(port)->flags |= PMACZILOG_FLAG_TX_STOPPED;
614 }
615
616 /*
617 * Kick the Tx side.
618 * The port lock is held and interrupts are disabled.
619 */
620 static void pmz_start_tx(struct uart_port *port)
621 {
622 struct uart_pmac_port *uap = to_pmz(port);
623 unsigned char status;
624
625 pmz_debug("pmz: start_tx()\n");
626
627 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
628 uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED;
629
630 if (ZS_IS_ASLEEP(uap) || uap->node == NULL)
631 return;
632
633 status = read_zsreg(uap, R0);
634
635 /* TX busy? Just wait for the TX done interrupt. */
636 if (!(status & Tx_BUF_EMP))
637 return;
638
639 /* Send the first character to jump-start the TX done
640 * IRQ sending engine.
641 */
642 if (port->x_char) {
643 write_zsdata(uap, port->x_char);
644 zssync(uap);
645 port->icount.tx++;
646 port->x_char = 0;
647 } else {
648 struct circ_buf *xmit = &port->info->xmit;
649
650 write_zsdata(uap, xmit->buf[xmit->tail]);
651 zssync(uap);
652 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
653 port->icount.tx++;
654
655 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
656 uart_write_wakeup(&uap->port);
657 }
658 pmz_debug("pmz: start_tx() done.\n");
659 }
660
661 /*
662 * Stop Rx side, basically disable emitting of
663 * Rx interrupts on the port. We don't disable the rx
664 * side of the chip proper though
665 * The port lock is held.
666 */
667 static void pmz_stop_rx(struct uart_port *port)
668 {
669 struct uart_pmac_port *uap = to_pmz(port);
670
671 if (ZS_IS_ASLEEP(uap) || uap->node == NULL)
672 return;
673
674 pmz_debug("pmz: stop_rx()()\n");
675
676 /* Disable all RX interrupts. */
677 uap->curregs[R1] &= ~RxINT_MASK;
678 pmz_maybe_update_regs(uap);
679
680 pmz_debug("pmz: stop_rx() done.\n");
681 }
682
683 /*
684 * Enable modem status change interrupts
685 * The port lock is held.
686 */
687 static void pmz_enable_ms(struct uart_port *port)
688 {
689 struct uart_pmac_port *uap = to_pmz(port);
690 unsigned char new_reg;
691
692 if (ZS_IS_IRDA(uap) || uap->node == NULL)
693 return;
694 new_reg = uap->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
695 if (new_reg != uap->curregs[R15]) {
696 uap->curregs[R15] = new_reg;
697
698 if (ZS_IS_ASLEEP(uap))
699 return;
700 /* NOTE: Not subject to 'transmitter active' rule. */
701 write_zsreg(uap, R15, uap->curregs[R15]);
702 }
703 }
704
705 /*
706 * Control break state emission
707 * The port lock is not held.
708 */
709 static void pmz_break_ctl(struct uart_port *port, int break_state)
710 {
711 struct uart_pmac_port *uap = to_pmz(port);
712 unsigned char set_bits, clear_bits, new_reg;
713 unsigned long flags;
714
715 if (uap->node == NULL)
716 return;
717 set_bits = clear_bits = 0;
718
719 if (break_state)
720 set_bits |= SND_BRK;
721 else
722 clear_bits |= SND_BRK;
723
724 spin_lock_irqsave(&port->lock, flags);
725
726 new_reg = (uap->curregs[R5] | set_bits) & ~clear_bits;
727 if (new_reg != uap->curregs[R5]) {
728 uap->curregs[R5] = new_reg;
729
730 /* NOTE: Not subject to 'transmitter active' rule. */
731 if (ZS_IS_ASLEEP(uap))
732 return;
733 write_zsreg(uap, R5, uap->curregs[R5]);
734 }
735
736 spin_unlock_irqrestore(&port->lock, flags);
737 }
738
739 /*
740 * Turn power on or off to the SCC and associated stuff
741 * (port drivers, modem, IR port, etc.)
742 * Returns the number of milliseconds we should wait before
743 * trying to use the port.
744 */
745 static int pmz_set_scc_power(struct uart_pmac_port *uap, int state)
746 {
747 int delay = 0;
748 int rc;
749
750 if (state) {
751 rc = pmac_call_feature(
752 PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 1);
753 pmz_debug("port power on result: %d\n", rc);
754 if (ZS_IS_INTMODEM(uap)) {
755 rc = pmac_call_feature(
756 PMAC_FTR_MODEM_ENABLE, uap->node, 0, 1);
757 delay = 2500; /* wait for 2.5s before using */
758 pmz_debug("modem power result: %d\n", rc);
759 }
760 } else {
761 /* TODO: Make that depend on a timer, don't power down
762 * immediately
763 */
764 if (ZS_IS_INTMODEM(uap)) {
765 rc = pmac_call_feature(
766 PMAC_FTR_MODEM_ENABLE, uap->node, 0, 0);
767 pmz_debug("port power off result: %d\n", rc);
768 }
769 pmac_call_feature(PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 0);
770 }
771 return delay;
772 }
773
774 /*
775 * FixZeroBug....Works around a bug in the SCC receving channel.
776 * Inspired from Darwin code, 15 Sept. 2000 -DanM
777 *
778 * The following sequence prevents a problem that is seen with O'Hare ASICs
779 * (most versions -- also with some Heathrow and Hydra ASICs) where a zero
780 * at the input to the receiver becomes 'stuck' and locks up the receiver.
781 * This problem can occur as a result of a zero bit at the receiver input
782 * coincident with any of the following events:
783 *
784 * The SCC is initialized (hardware or software).
785 * A framing error is detected.
786 * The clocking option changes from synchronous or X1 asynchronous
787 * clocking to X16, X32, or X64 asynchronous clocking.
788 * The decoding mode is changed among NRZ, NRZI, FM0, or FM1.
789 *
790 * This workaround attempts to recover from the lockup condition by placing
791 * the SCC in synchronous loopback mode with a fast clock before programming
792 * any of the asynchronous modes.
793 */
794 static void pmz_fix_zero_bug_scc(struct uart_pmac_port *uap)
795 {
796 write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB);
797 zssync(uap);
798 udelay(10);
799 write_zsreg(uap, 9, (ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB) | NV);
800 zssync(uap);
801
802 write_zsreg(uap, 4, X1CLK | MONSYNC);
803 write_zsreg(uap, 3, Rx8);
804 write_zsreg(uap, 5, Tx8 | RTS);
805 write_zsreg(uap, 9, NV); /* Didn't we already do this? */
806 write_zsreg(uap, 11, RCBR | TCBR);
807 write_zsreg(uap, 12, 0);
808 write_zsreg(uap, 13, 0);
809 write_zsreg(uap, 14, (LOOPBAK | BRSRC));
810 write_zsreg(uap, 14, (LOOPBAK | BRSRC | BRENAB));
811 write_zsreg(uap, 3, Rx8 | RxENABLE);
812 write_zsreg(uap, 0, RES_EXT_INT);
813 write_zsreg(uap, 0, RES_EXT_INT);
814 write_zsreg(uap, 0, RES_EXT_INT); /* to kill some time */
815
816 /* The channel should be OK now, but it is probably receiving
817 * loopback garbage.
818 * Switch to asynchronous mode, disable the receiver,
819 * and discard everything in the receive buffer.
820 */
821 write_zsreg(uap, 9, NV);
822 write_zsreg(uap, 4, X16CLK | SB_MASK);
823 write_zsreg(uap, 3, Rx8);
824
825 while (read_zsreg(uap, 0) & Rx_CH_AV) {
826 (void)read_zsreg(uap, 8);
827 write_zsreg(uap, 0, RES_EXT_INT);
828 write_zsreg(uap, 0, ERR_RES);
829 }
830 }
831
832 /*
833 * Real startup routine, powers up the hardware and sets up
834 * the SCC. Returns a delay in ms where you need to wait before
835 * actually using the port, this is typically the internal modem
836 * powerup delay. This routine expect the lock to be taken.
837 */
838 static int __pmz_startup(struct uart_pmac_port *uap)
839 {
840 int pwr_delay = 0;
841
842 memset(&uap->curregs, 0, sizeof(uap->curregs));
843
844 /* Power up the SCC & underlying hardware (modem/irda) */
845 pwr_delay = pmz_set_scc_power(uap, 1);
846
847 /* Nice buggy HW ... */
848 pmz_fix_zero_bug_scc(uap);
849
850 /* Reset the channel */
851 uap->curregs[R9] = 0;
852 write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB);
853 zssync(uap);
854 udelay(10);
855 write_zsreg(uap, 9, 0);
856 zssync(uap);
857
858 /* Clear the interrupt registers */
859 write_zsreg(uap, R1, 0);
860 write_zsreg(uap, R0, ERR_RES);
861 write_zsreg(uap, R0, ERR_RES);
862 write_zsreg(uap, R0, RES_H_IUS);
863 write_zsreg(uap, R0, RES_H_IUS);
864
865 /* Setup some valid baud rate */
866 uap->curregs[R4] = X16CLK | SB1;
867 uap->curregs[R3] = Rx8;
868 uap->curregs[R5] = Tx8 | RTS;
869 if (!ZS_IS_IRDA(uap))
870 uap->curregs[R5] |= DTR;
871 uap->curregs[R12] = 0;
872 uap->curregs[R13] = 0;
873 uap->curregs[R14] = BRENAB;
874
875 /* Clear handshaking, enable BREAK interrupts */
876 uap->curregs[R15] = BRKIE;
877
878 /* Master interrupt enable */
879 uap->curregs[R9] |= NV | MIE;
880
881 pmz_load_zsregs(uap, uap->curregs);
882
883 /* Enable receiver and transmitter. */
884 write_zsreg(uap, R3, uap->curregs[R3] |= RxENABLE);
885 write_zsreg(uap, R5, uap->curregs[R5] |= TxENABLE);
886
887 /* Remember status for DCD/CTS changes */
888 uap->prev_status = read_zsreg(uap, R0);
889
890
891 return pwr_delay;
892 }
893
894 static void pmz_irda_reset(struct uart_pmac_port *uap)
895 {
896 uap->curregs[R5] |= DTR;
897 write_zsreg(uap, R5, uap->curregs[R5]);
898 zssync(uap);
899 mdelay(110);
900 uap->curregs[R5] &= ~DTR;
901 write_zsreg(uap, R5, uap->curregs[R5]);
902 zssync(uap);
903 mdelay(10);
904 }
905
906 /*
907 * This is the "normal" startup routine, using the above one
908 * wrapped with the lock and doing a schedule delay
909 */
910 static int pmz_startup(struct uart_port *port)
911 {
912 struct uart_pmac_port *uap = to_pmz(port);
913 unsigned long flags;
914 int pwr_delay = 0;
915
916 pmz_debug("pmz: startup()\n");
917
918 if (ZS_IS_ASLEEP(uap))
919 return -EAGAIN;
920 if (uap->node == NULL)
921 return -ENODEV;
922
923 mutex_lock(&pmz_irq_mutex);
924
925 uap->flags |= PMACZILOG_FLAG_IS_OPEN;
926
927 /* A console is never powered down. Else, power up and
928 * initialize the chip
929 */
930 if (!ZS_IS_CONS(uap)) {
931 spin_lock_irqsave(&port->lock, flags);
932 pwr_delay = __pmz_startup(uap);
933 spin_unlock_irqrestore(&port->lock, flags);
934 }
935
936 pmz_get_port_A(uap)->flags |= PMACZILOG_FLAG_IS_IRQ_ON;
937 if (request_irq(uap->port.irq, pmz_interrupt, IRQF_SHARED, "PowerMac Zilog", uap)) {
938 dev_err(&uap->dev->ofdev.dev,
939 "Unable to register zs interrupt handler.\n");
940 pmz_set_scc_power(uap, 0);
941 mutex_unlock(&pmz_irq_mutex);
942 return -ENXIO;
943 }
944
945 mutex_unlock(&pmz_irq_mutex);
946
947 /* Right now, we deal with delay by blocking here, I'll be
948 * smarter later on
949 */
950 if (pwr_delay != 0) {
951 pmz_debug("pmz: delaying %d ms\n", pwr_delay);
952 msleep(pwr_delay);
953 }
954
955 /* IrDA reset is done now */
956 if (ZS_IS_IRDA(uap))
957 pmz_irda_reset(uap);
958
959 /* Enable interrupts emission from the chip */
960 spin_lock_irqsave(&port->lock, flags);
961 uap->curregs[R1] |= INT_ALL_Rx | TxINT_ENAB;
962 if (!ZS_IS_EXTCLK(uap))
963 uap->curregs[R1] |= EXT_INT_ENAB;
964 write_zsreg(uap, R1, uap->curregs[R1]);
965 spin_unlock_irqrestore(&port->lock, flags);
966
967 pmz_debug("pmz: startup() done.\n");
968
969 return 0;
970 }
971
972 static void pmz_shutdown(struct uart_port *port)
973 {
974 struct uart_pmac_port *uap = to_pmz(port);
975 unsigned long flags;
976
977 pmz_debug("pmz: shutdown()\n");
978
979 if (uap->node == NULL)
980 return;
981
982 mutex_lock(&pmz_irq_mutex);
983
984 /* Release interrupt handler */
985 free_irq(uap->port.irq, uap);
986
987 spin_lock_irqsave(&port->lock, flags);
988
989 uap->flags &= ~PMACZILOG_FLAG_IS_OPEN;
990
991 if (!ZS_IS_OPEN(uap->mate))
992 pmz_get_port_A(uap)->flags &= ~PMACZILOG_FLAG_IS_IRQ_ON;
993
994 /* Disable interrupts */
995 if (!ZS_IS_ASLEEP(uap)) {
996 uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
997 write_zsreg(uap, R1, uap->curregs[R1]);
998 zssync(uap);
999 }
1000
1001 if (ZS_IS_CONS(uap) || ZS_IS_ASLEEP(uap)) {
1002 spin_unlock_irqrestore(&port->lock, flags);
1003 mutex_unlock(&pmz_irq_mutex);
1004 return;
1005 }
1006
1007 /* Disable receiver and transmitter. */
1008 uap->curregs[R3] &= ~RxENABLE;
1009 uap->curregs[R5] &= ~TxENABLE;
1010
1011 /* Disable all interrupts and BRK assertion. */
1012 uap->curregs[R5] &= ~SND_BRK;
1013 pmz_maybe_update_regs(uap);
1014
1015 /* Shut the chip down */
1016 pmz_set_scc_power(uap, 0);
1017
1018 spin_unlock_irqrestore(&port->lock, flags);
1019
1020 mutex_unlock(&pmz_irq_mutex);
1021
1022 pmz_debug("pmz: shutdown() done.\n");
1023 }
1024
1025 /* Shared by TTY driver and serial console setup. The port lock is held
1026 * and local interrupts are disabled.
1027 */
1028 static void pmz_convert_to_zs(struct uart_pmac_port *uap, unsigned int cflag,
1029 unsigned int iflag, unsigned long baud)
1030 {
1031 int brg;
1032
1033
1034 /* Switch to external clocking for IrDA high clock rates. That
1035 * code could be re-used for Midi interfaces with different
1036 * multipliers
1037 */
1038 if (baud >= 115200 && ZS_IS_IRDA(uap)) {
1039 uap->curregs[R4] = X1CLK;
1040 uap->curregs[R11] = RCTRxCP | TCTRxCP;
1041 uap->curregs[R14] = 0; /* BRG off */
1042 uap->curregs[R12] = 0;
1043 uap->curregs[R13] = 0;
1044 uap->flags |= PMACZILOG_FLAG_IS_EXTCLK;
1045 } else {
1046 switch (baud) {
1047 case ZS_CLOCK/16: /* 230400 */
1048 uap->curregs[R4] = X16CLK;
1049 uap->curregs[R11] = 0;
1050 uap->curregs[R14] = 0;
1051 break;
1052 case ZS_CLOCK/32: /* 115200 */
1053 uap->curregs[R4] = X32CLK;
1054 uap->curregs[R11] = 0;
1055 uap->curregs[R14] = 0;
1056 break;
1057 default:
1058 uap->curregs[R4] = X16CLK;
1059 uap->curregs[R11] = TCBR | RCBR;
1060 brg = BPS_TO_BRG(baud, ZS_CLOCK / 16);
1061 uap->curregs[R12] = (brg & 255);
1062 uap->curregs[R13] = ((brg >> 8) & 255);
1063 uap->curregs[R14] = BRENAB;
1064 }
1065 uap->flags &= ~PMACZILOG_FLAG_IS_EXTCLK;
1066 }
1067
1068 /* Character size, stop bits, and parity. */
1069 uap->curregs[3] &= ~RxN_MASK;
1070 uap->curregs[5] &= ~TxN_MASK;
1071
1072 switch (cflag & CSIZE) {
1073 case CS5:
1074 uap->curregs[3] |= Rx5;
1075 uap->curregs[5] |= Tx5;
1076 uap->parity_mask = 0x1f;
1077 break;
1078 case CS6:
1079 uap->curregs[3] |= Rx6;
1080 uap->curregs[5] |= Tx6;
1081 uap->parity_mask = 0x3f;
1082 break;
1083 case CS7:
1084 uap->curregs[3] |= Rx7;
1085 uap->curregs[5] |= Tx7;
1086 uap->parity_mask = 0x7f;
1087 break;
1088 case CS8:
1089 default:
1090 uap->curregs[3] |= Rx8;
1091 uap->curregs[5] |= Tx8;
1092 uap->parity_mask = 0xff;
1093 break;
1094 };
1095 uap->curregs[4] &= ~(SB_MASK);
1096 if (cflag & CSTOPB)
1097 uap->curregs[4] |= SB2;
1098 else
1099 uap->curregs[4] |= SB1;
1100 if (cflag & PARENB)
1101 uap->curregs[4] |= PAR_ENAB;
1102 else
1103 uap->curregs[4] &= ~PAR_ENAB;
1104 if (!(cflag & PARODD))
1105 uap->curregs[4] |= PAR_EVEN;
1106 else
1107 uap->curregs[4] &= ~PAR_EVEN;
1108
1109 uap->port.read_status_mask = Rx_OVR;
1110 if (iflag & INPCK)
1111 uap->port.read_status_mask |= CRC_ERR | PAR_ERR;
1112 if (iflag & (BRKINT | PARMRK))
1113 uap->port.read_status_mask |= BRK_ABRT;
1114
1115 uap->port.ignore_status_mask = 0;
1116 if (iflag & IGNPAR)
1117 uap->port.ignore_status_mask |= CRC_ERR | PAR_ERR;
1118 if (iflag & IGNBRK) {
1119 uap->port.ignore_status_mask |= BRK_ABRT;
1120 if (iflag & IGNPAR)
1121 uap->port.ignore_status_mask |= Rx_OVR;
1122 }
1123
1124 if ((cflag & CREAD) == 0)
1125 uap->port.ignore_status_mask = 0xff;
1126 }
1127
1128
1129 /*
1130 * Set the irda codec on the imac to the specified baud rate.
1131 */
1132 static void pmz_irda_setup(struct uart_pmac_port *uap, unsigned long *baud)
1133 {
1134 u8 cmdbyte;
1135 int t, version;
1136
1137 switch (*baud) {
1138 /* SIR modes */
1139 case 2400:
1140 cmdbyte = 0x53;
1141 break;
1142 case 4800:
1143 cmdbyte = 0x52;
1144 break;
1145 case 9600:
1146 cmdbyte = 0x51;
1147 break;
1148 case 19200:
1149 cmdbyte = 0x50;
1150 break;
1151 case 38400:
1152 cmdbyte = 0x4f;
1153 break;
1154 case 57600:
1155 cmdbyte = 0x4e;
1156 break;
1157 case 115200:
1158 cmdbyte = 0x4d;
1159 break;
1160 /* The FIR modes aren't really supported at this point, how
1161 * do we select the speed ? via the FCR on KeyLargo ?
1162 */
1163 case 1152000:
1164 cmdbyte = 0;
1165 break;
1166 case 4000000:
1167 cmdbyte = 0;
1168 break;
1169 default: /* 9600 */
1170 cmdbyte = 0x51;
1171 *baud = 9600;
1172 break;
1173 }
1174
1175 /* Wait for transmitter to drain */
1176 t = 10000;
1177 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0
1178 || (read_zsreg(uap, R1) & ALL_SNT) == 0) {
1179 if (--t <= 0) {
1180 dev_err(&uap->dev->ofdev.dev, "transmitter didn't drain\n");
1181 return;
1182 }
1183 udelay(10);
1184 }
1185
1186 /* Drain the receiver too */
1187 t = 100;
1188 (void)read_zsdata(uap);
1189 (void)read_zsdata(uap);
1190 (void)read_zsdata(uap);
1191 mdelay(10);
1192 while (read_zsreg(uap, R0) & Rx_CH_AV) {
1193 read_zsdata(uap);
1194 mdelay(10);
1195 if (--t <= 0) {
1196 dev_err(&uap->dev->ofdev.dev, "receiver didn't drain\n");
1197 return;
1198 }
1199 }
1200
1201 /* Switch to command mode */
1202 uap->curregs[R5] |= DTR;
1203 write_zsreg(uap, R5, uap->curregs[R5]);
1204 zssync(uap);
1205 mdelay(1);
1206
1207 /* Switch SCC to 19200 */
1208 pmz_convert_to_zs(uap, CS8, 0, 19200);
1209 pmz_load_zsregs(uap, uap->curregs);
1210 mdelay(1);
1211
1212 /* Write get_version command byte */
1213 write_zsdata(uap, 1);
1214 t = 5000;
1215 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) {
1216 if (--t <= 0) {
1217 dev_err(&uap->dev->ofdev.dev,
1218 "irda_setup timed out on get_version byte\n");
1219 goto out;
1220 }
1221 udelay(10);
1222 }
1223 version = read_zsdata(uap);
1224
1225 if (version < 4) {
1226 dev_info(&uap->dev->ofdev.dev, "IrDA: dongle version %d not supported\n",
1227 version);
1228 goto out;
1229 }
1230
1231 /* Send speed mode */
1232 write_zsdata(uap, cmdbyte);
1233 t = 5000;
1234 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) {
1235 if (--t <= 0) {
1236 dev_err(&uap->dev->ofdev.dev,
1237 "irda_setup timed out on speed mode byte\n");
1238 goto out;
1239 }
1240 udelay(10);
1241 }
1242 t = read_zsdata(uap);
1243 if (t != cmdbyte)
1244 dev_err(&uap->dev->ofdev.dev,
1245 "irda_setup speed mode byte = %x (%x)\n", t, cmdbyte);
1246
1247 dev_info(&uap->dev->ofdev.dev, "IrDA setup for %ld bps, dongle version: %d\n",
1248 *baud, version);
1249
1250 (void)read_zsdata(uap);
1251 (void)read_zsdata(uap);
1252 (void)read_zsdata(uap);
1253
1254 out:
1255 /* Switch back to data mode */
1256 uap->curregs[R5] &= ~DTR;
1257 write_zsreg(uap, R5, uap->curregs[R5]);
1258 zssync(uap);
1259
1260 (void)read_zsdata(uap);
1261 (void)read_zsdata(uap);
1262 (void)read_zsdata(uap);
1263 }
1264
1265
1266 static void __pmz_set_termios(struct uart_port *port, struct termios *termios,
1267 struct termios *old)
1268 {
1269 struct uart_pmac_port *uap = to_pmz(port);
1270 unsigned long baud;
1271
1272 pmz_debug("pmz: set_termios()\n");
1273
1274 if (ZS_IS_ASLEEP(uap))
1275 return;
1276
1277 memcpy(&uap->termios_cache, termios, sizeof(struct termios));
1278
1279 /* XXX Check which revs of machines actually allow 1 and 4Mb speeds
1280 * on the IR dongle. Note that the IRTTY driver currently doesn't know
1281 * about the FIR mode and high speed modes. So these are unused. For
1282 * implementing proper support for these, we should probably add some
1283 * DMA as well, at least on the Rx side, which isn't a simple thing
1284 * at this point.
1285 */
1286 if (ZS_IS_IRDA(uap)) {
1287 /* Calc baud rate */
1288 baud = uart_get_baud_rate(port, termios, old, 1200, 4000000);
1289 pmz_debug("pmz: switch IRDA to %ld bauds\n", baud);
1290 /* Cet the irda codec to the right rate */
1291 pmz_irda_setup(uap, &baud);
1292 /* Set final baud rate */
1293 pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud);
1294 pmz_load_zsregs(uap, uap->curregs);
1295 zssync(uap);
1296 } else {
1297 baud = uart_get_baud_rate(port, termios, old, 1200, 230400);
1298 pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud);
1299 /* Make sure modem status interrupts are correctly configured */
1300 if (UART_ENABLE_MS(&uap->port, termios->c_cflag)) {
1301 uap->curregs[R15] |= DCDIE | SYNCIE | CTSIE;
1302 uap->flags |= PMACZILOG_FLAG_MODEM_STATUS;
1303 } else {
1304 uap->curregs[R15] &= ~(DCDIE | SYNCIE | CTSIE);
1305 uap->flags &= ~PMACZILOG_FLAG_MODEM_STATUS;
1306 }
1307
1308 /* Load registers to the chip */
1309 pmz_maybe_update_regs(uap);
1310 }
1311 uart_update_timeout(port, termios->c_cflag, baud);
1312
1313 pmz_debug("pmz: set_termios() done.\n");
1314 }
1315
1316 /* The port lock is not held. */
1317 static void pmz_set_termios(struct uart_port *port, struct termios *termios,
1318 struct termios *old)
1319 {
1320 struct uart_pmac_port *uap = to_pmz(port);
1321 unsigned long flags;
1322
1323 spin_lock_irqsave(&port->lock, flags);
1324
1325 /* Disable IRQs on the port */
1326 uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
1327 write_zsreg(uap, R1, uap->curregs[R1]);
1328
1329 /* Setup new port configuration */
1330 __pmz_set_termios(port, termios, old);
1331
1332 /* Re-enable IRQs on the port */
1333 if (ZS_IS_OPEN(uap)) {
1334 uap->curregs[R1] |= INT_ALL_Rx | TxINT_ENAB;
1335 if (!ZS_IS_EXTCLK(uap))
1336 uap->curregs[R1] |= EXT_INT_ENAB;
1337 write_zsreg(uap, R1, uap->curregs[R1]);
1338 }
1339 spin_unlock_irqrestore(&port->lock, flags);
1340 }
1341
1342 static const char *pmz_type(struct uart_port *port)
1343 {
1344 struct uart_pmac_port *uap = to_pmz(port);
1345
1346 if (ZS_IS_IRDA(uap))
1347 return "Z85c30 ESCC - Infrared port";
1348 else if (ZS_IS_INTMODEM(uap))
1349 return "Z85c30 ESCC - Internal modem";
1350 return "Z85c30 ESCC - Serial port";
1351 }
1352
1353 /* We do not request/release mappings of the registers here, this
1354 * happens at early serial probe time.
1355 */
1356 static void pmz_release_port(struct uart_port *port)
1357 {
1358 }
1359
1360 static int pmz_request_port(struct uart_port *port)
1361 {
1362 return 0;
1363 }
1364
1365 /* These do not need to do anything interesting either. */
1366 static void pmz_config_port(struct uart_port *port, int flags)
1367 {
1368 }
1369
1370 /* We do not support letting the user mess with the divisor, IRQ, etc. */
1371 static int pmz_verify_port(struct uart_port *port, struct serial_struct *ser)
1372 {
1373 return -EINVAL;
1374 }
1375
1376 static struct uart_ops pmz_pops = {
1377 .tx_empty = pmz_tx_empty,
1378 .set_mctrl = pmz_set_mctrl,
1379 .get_mctrl = pmz_get_mctrl,
1380 .stop_tx = pmz_stop_tx,
1381 .start_tx = pmz_start_tx,
1382 .stop_rx = pmz_stop_rx,
1383 .enable_ms = pmz_enable_ms,
1384 .break_ctl = pmz_break_ctl,
1385 .startup = pmz_startup,
1386 .shutdown = pmz_shutdown,
1387 .set_termios = pmz_set_termios,
1388 .type = pmz_type,
1389 .release_port = pmz_release_port,
1390 .request_port = pmz_request_port,
1391 .config_port = pmz_config_port,
1392 .verify_port = pmz_verify_port,
1393 };
1394
1395 /*
1396 * Setup one port structure after probing, HW is down at this point,
1397 * Unlike sunzilog, we don't need to pre-init the spinlock as we don't
1398 * register our console before uart_add_one_port() is called
1399 */
1400 static int __init pmz_init_port(struct uart_pmac_port *uap)
1401 {
1402 struct device_node *np = uap->node;
1403 const char *conn;
1404 const struct slot_names_prop {
1405 int count;
1406 char name[1];
1407 } *slots;
1408 int len;
1409 struct resource r_ports, r_rxdma, r_txdma;
1410
1411 /*
1412 * Request & map chip registers
1413 */
1414 if (of_address_to_resource(np, 0, &r_ports))
1415 return -ENODEV;
1416 uap->port.mapbase = r_ports.start;
1417 uap->port.membase = ioremap(uap->port.mapbase, 0x1000);
1418
1419 uap->control_reg = uap->port.membase;
1420 uap->data_reg = uap->control_reg + 0x10;
1421
1422 /*
1423 * Request & map DBDMA registers
1424 */
1425 #ifdef HAS_DBDMA
1426 if (of_address_to_resource(np, 1, &r_txdma) == 0 &&
1427 of_address_to_resource(np, 2, &r_rxdma) == 0)
1428 uap->flags |= PMACZILOG_FLAG_HAS_DMA;
1429 #else
1430 memset(&r_txdma, 0, sizeof(struct resource));
1431 memset(&r_rxdma, 0, sizeof(struct resource));
1432 #endif
1433 if (ZS_HAS_DMA(uap)) {
1434 uap->tx_dma_regs = ioremap(r_txdma.start, 0x100);
1435 if (uap->tx_dma_regs == NULL) {
1436 uap->flags &= ~PMACZILOG_FLAG_HAS_DMA;
1437 goto no_dma;
1438 }
1439 uap->rx_dma_regs = ioremap(r_rxdma.start, 0x100);
1440 if (uap->rx_dma_regs == NULL) {
1441 iounmap(uap->tx_dma_regs);
1442 uap->tx_dma_regs = NULL;
1443 uap->flags &= ~PMACZILOG_FLAG_HAS_DMA;
1444 goto no_dma;
1445 }
1446 uap->tx_dma_irq = irq_of_parse_and_map(np, 1);
1447 uap->rx_dma_irq = irq_of_parse_and_map(np, 2);
1448 }
1449 no_dma:
1450
1451 /*
1452 * Detect port type
1453 */
1454 if (device_is_compatible(np, "cobalt"))
1455 uap->flags |= PMACZILOG_FLAG_IS_INTMODEM;
1456 conn = get_property(np, "AAPL,connector", &len);
1457 if (conn && (strcmp(conn, "infrared") == 0))
1458 uap->flags |= PMACZILOG_FLAG_IS_IRDA;
1459 uap->port_type = PMAC_SCC_ASYNC;
1460 /* 1999 Powerbook G3 has slot-names property instead */
1461 slots = get_property(np, "slot-names", &len);
1462 if (slots && slots->count > 0) {
1463 if (strcmp(slots->name, "IrDA") == 0)
1464 uap->flags |= PMACZILOG_FLAG_IS_IRDA;
1465 else if (strcmp(slots->name, "Modem") == 0)
1466 uap->flags |= PMACZILOG_FLAG_IS_INTMODEM;
1467 }
1468 if (ZS_IS_IRDA(uap))
1469 uap->port_type = PMAC_SCC_IRDA;
1470 if (ZS_IS_INTMODEM(uap)) {
1471 struct device_node* i2c_modem = find_devices("i2c-modem");
1472 if (i2c_modem) {
1473 const char* mid =
1474 get_property(i2c_modem, "modem-id", NULL);
1475 if (mid) switch(*mid) {
1476 case 0x04 :
1477 case 0x05 :
1478 case 0x07 :
1479 case 0x08 :
1480 case 0x0b :
1481 case 0x0c :
1482 uap->port_type = PMAC_SCC_I2S1;
1483 }
1484 printk(KERN_INFO "pmac_zilog: i2c-modem detected, id: %d\n",
1485 mid ? (*mid) : 0);
1486 } else {
1487 printk(KERN_INFO "pmac_zilog: serial modem detected\n");
1488 }
1489 }
1490
1491 /*
1492 * Init remaining bits of "port" structure
1493 */
1494 uap->port.iotype = UPIO_MEM;
1495 uap->port.irq = irq_of_parse_and_map(np, 0);
1496 uap->port.uartclk = ZS_CLOCK;
1497 uap->port.fifosize = 1;
1498 uap->port.ops = &pmz_pops;
1499 uap->port.type = PORT_PMAC_ZILOG;
1500 uap->port.flags = 0;
1501
1502 /* Setup some valid baud rate information in the register
1503 * shadows so we don't write crap there before baud rate is
1504 * first initialized.
1505 */
1506 pmz_convert_to_zs(uap, CS8, 0, 9600);
1507
1508 return 0;
1509 }
1510
1511 /*
1512 * Get rid of a port on module removal
1513 */
1514 static void pmz_dispose_port(struct uart_pmac_port *uap)
1515 {
1516 struct device_node *np;
1517
1518 np = uap->node;
1519 iounmap(uap->rx_dma_regs);
1520 iounmap(uap->tx_dma_regs);
1521 iounmap(uap->control_reg);
1522 uap->node = NULL;
1523 of_node_put(np);
1524 memset(uap, 0, sizeof(struct uart_pmac_port));
1525 }
1526
1527 /*
1528 * Called upon match with an escc node in the devive-tree.
1529 */
1530 static int pmz_attach(struct macio_dev *mdev, const struct of_device_id *match)
1531 {
1532 int i;
1533
1534 /* Iterate the pmz_ports array to find a matching entry
1535 */
1536 for (i = 0; i < MAX_ZS_PORTS; i++)
1537 if (pmz_ports[i].node == mdev->ofdev.node) {
1538 struct uart_pmac_port *uap = &pmz_ports[i];
1539
1540 uap->dev = mdev;
1541 dev_set_drvdata(&mdev->ofdev.dev, uap);
1542 if (macio_request_resources(uap->dev, "pmac_zilog"))
1543 printk(KERN_WARNING "%s: Failed to request resource"
1544 ", port still active\n",
1545 uap->node->name);
1546 else
1547 uap->flags |= PMACZILOG_FLAG_RSRC_REQUESTED;
1548 return 0;
1549 }
1550 return -ENODEV;
1551 }
1552
1553 /*
1554 * That one should not be called, macio isn't really a hotswap device,
1555 * we don't expect one of those serial ports to go away...
1556 */
1557 static int pmz_detach(struct macio_dev *mdev)
1558 {
1559 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1560
1561 if (!uap)
1562 return -ENODEV;
1563
1564 if (uap->flags & PMACZILOG_FLAG_RSRC_REQUESTED) {
1565 macio_release_resources(uap->dev);
1566 uap->flags &= ~PMACZILOG_FLAG_RSRC_REQUESTED;
1567 }
1568 dev_set_drvdata(&mdev->ofdev.dev, NULL);
1569 uap->dev = NULL;
1570
1571 return 0;
1572 }
1573
1574
1575 static int pmz_suspend(struct macio_dev *mdev, pm_message_t pm_state)
1576 {
1577 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1578 struct uart_state *state;
1579 unsigned long flags;
1580
1581 if (uap == NULL) {
1582 printk("HRM... pmz_suspend with NULL uap\n");
1583 return 0;
1584 }
1585
1586 if (pm_state.event == mdev->ofdev.dev.power.power_state.event)
1587 return 0;
1588
1589 pmz_debug("suspend, switching to state %d\n", pm_state);
1590
1591 state = pmz_uart_reg.state + uap->port.line;
1592
1593 mutex_lock(&pmz_irq_mutex);
1594 mutex_lock(&state->mutex);
1595
1596 spin_lock_irqsave(&uap->port.lock, flags);
1597
1598 if (ZS_IS_OPEN(uap) || ZS_IS_CONS(uap)) {
1599 /* Disable receiver and transmitter. */
1600 uap->curregs[R3] &= ~RxENABLE;
1601 uap->curregs[R5] &= ~TxENABLE;
1602
1603 /* Disable all interrupts and BRK assertion. */
1604 uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
1605 uap->curregs[R5] &= ~SND_BRK;
1606 pmz_load_zsregs(uap, uap->curregs);
1607 uap->flags |= PMACZILOG_FLAG_IS_ASLEEP;
1608 mb();
1609 }
1610
1611 spin_unlock_irqrestore(&uap->port.lock, flags);
1612
1613 if (ZS_IS_OPEN(uap) || ZS_IS_OPEN(uap->mate))
1614 if (ZS_IS_ASLEEP(uap->mate) && ZS_IS_IRQ_ON(pmz_get_port_A(uap))) {
1615 pmz_get_port_A(uap)->flags &= ~PMACZILOG_FLAG_IS_IRQ_ON;
1616 disable_irq(uap->port.irq);
1617 }
1618
1619 if (ZS_IS_CONS(uap))
1620 uap->port.cons->flags &= ~CON_ENABLED;
1621
1622 /* Shut the chip down */
1623 pmz_set_scc_power(uap, 0);
1624
1625 mutex_unlock(&state->mutex);
1626 mutex_unlock(&pmz_irq_mutex);
1627
1628 pmz_debug("suspend, switching complete\n");
1629
1630 mdev->ofdev.dev.power.power_state = pm_state;
1631
1632 return 0;
1633 }
1634
1635
1636 static int pmz_resume(struct macio_dev *mdev)
1637 {
1638 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1639 struct uart_state *state;
1640 unsigned long flags;
1641 int pwr_delay = 0;
1642
1643 if (uap == NULL)
1644 return 0;
1645
1646 if (mdev->ofdev.dev.power.power_state.event == PM_EVENT_ON)
1647 return 0;
1648
1649 pmz_debug("resume, switching to state 0\n");
1650
1651 state = pmz_uart_reg.state + uap->port.line;
1652
1653 mutex_lock(&pmz_irq_mutex);
1654 mutex_lock(&state->mutex);
1655
1656 spin_lock_irqsave(&uap->port.lock, flags);
1657 if (!ZS_IS_OPEN(uap) && !ZS_IS_CONS(uap)) {
1658 spin_unlock_irqrestore(&uap->port.lock, flags);
1659 goto bail;
1660 }
1661 pwr_delay = __pmz_startup(uap);
1662
1663 /* Take care of config that may have changed while asleep */
1664 __pmz_set_termios(&uap->port, &uap->termios_cache, NULL);
1665
1666 if (ZS_IS_OPEN(uap)) {
1667 /* Enable interrupts */
1668 uap->curregs[R1] |= INT_ALL_Rx | TxINT_ENAB;
1669 if (!ZS_IS_EXTCLK(uap))
1670 uap->curregs[R1] |= EXT_INT_ENAB;
1671 write_zsreg(uap, R1, uap->curregs[R1]);
1672 }
1673
1674 spin_unlock_irqrestore(&uap->port.lock, flags);
1675
1676 if (ZS_IS_CONS(uap))
1677 uap->port.cons->flags |= CON_ENABLED;
1678
1679 /* Re-enable IRQ on the controller */
1680 if (ZS_IS_OPEN(uap) && !ZS_IS_IRQ_ON(pmz_get_port_A(uap))) {
1681 pmz_get_port_A(uap)->flags |= PMACZILOG_FLAG_IS_IRQ_ON;
1682 enable_irq(uap->port.irq);
1683 }
1684
1685 bail:
1686 mutex_unlock(&state->mutex);
1687 mutex_unlock(&pmz_irq_mutex);
1688
1689 /* Right now, we deal with delay by blocking here, I'll be
1690 * smarter later on
1691 */
1692 if (pwr_delay != 0) {
1693 pmz_debug("pmz: delaying %d ms\n", pwr_delay);
1694 msleep(pwr_delay);
1695 }
1696
1697 pmz_debug("resume, switching complete\n");
1698
1699 mdev->ofdev.dev.power.power_state.event = PM_EVENT_ON;
1700
1701 return 0;
1702 }
1703
1704 /*
1705 * Probe all ports in the system and build the ports array, we register
1706 * with the serial layer at this point, the macio-type probing is only
1707 * used later to "attach" to the sysfs tree so we get power management
1708 * events
1709 */
1710 static int __init pmz_probe(void)
1711 {
1712 struct device_node *node_p, *node_a, *node_b, *np;
1713 int count = 0;
1714 int rc;
1715
1716 /*
1717 * Find all escc chips in the system
1718 */
1719 node_p = of_find_node_by_name(NULL, "escc");
1720 while (node_p) {
1721 /*
1722 * First get channel A/B node pointers
1723 *
1724 * TODO: Add routines with proper locking to do that...
1725 */
1726 node_a = node_b = NULL;
1727 for (np = NULL; (np = of_get_next_child(node_p, np)) != NULL;) {
1728 if (strncmp(np->name, "ch-a", 4) == 0)
1729 node_a = of_node_get(np);
1730 else if (strncmp(np->name, "ch-b", 4) == 0)
1731 node_b = of_node_get(np);
1732 }
1733 if (!node_a && !node_b) {
1734 of_node_put(node_a);
1735 of_node_put(node_b);
1736 printk(KERN_ERR "pmac_zilog: missing node %c for escc %s\n",
1737 (!node_a) ? 'a' : 'b', node_p->full_name);
1738 goto next;
1739 }
1740
1741 /*
1742 * Fill basic fields in the port structures
1743 */
1744 pmz_ports[count].mate = &pmz_ports[count+1];
1745 pmz_ports[count+1].mate = &pmz_ports[count];
1746 pmz_ports[count].flags = PMACZILOG_FLAG_IS_CHANNEL_A;
1747 pmz_ports[count].node = node_a;
1748 pmz_ports[count+1].node = node_b;
1749 pmz_ports[count].port.line = count;
1750 pmz_ports[count+1].port.line = count+1;
1751
1752 /*
1753 * Setup the ports for real
1754 */
1755 rc = pmz_init_port(&pmz_ports[count]);
1756 if (rc == 0 && node_b != NULL)
1757 rc = pmz_init_port(&pmz_ports[count+1]);
1758 if (rc != 0) {
1759 of_node_put(node_a);
1760 of_node_put(node_b);
1761 memset(&pmz_ports[count], 0, sizeof(struct uart_pmac_port));
1762 memset(&pmz_ports[count+1], 0, sizeof(struct uart_pmac_port));
1763 goto next;
1764 }
1765 count += 2;
1766 next:
1767 node_p = of_find_node_by_name(node_p, "escc");
1768 }
1769 pmz_ports_count = count;
1770
1771 return 0;
1772 }
1773
1774 #ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE
1775
1776 static void pmz_console_write(struct console *con, const char *s, unsigned int count);
1777 static int __init pmz_console_setup(struct console *co, char *options);
1778
1779 static struct console pmz_console = {
1780 .name = "ttyS",
1781 .write = pmz_console_write,
1782 .device = uart_console_device,
1783 .setup = pmz_console_setup,
1784 .flags = CON_PRINTBUFFER,
1785 .index = -1,
1786 .data = &pmz_uart_reg,
1787 };
1788
1789 #define PMACZILOG_CONSOLE &pmz_console
1790 #else /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
1791 #define PMACZILOG_CONSOLE (NULL)
1792 #endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
1793
1794 /*
1795 * Register the driver, console driver and ports with the serial
1796 * core
1797 */
1798 static int __init pmz_register(void)
1799 {
1800 int i, rc;
1801
1802 pmz_uart_reg.nr = pmz_ports_count;
1803 pmz_uart_reg.cons = PMACZILOG_CONSOLE;
1804 pmz_uart_reg.minor = 64;
1805
1806 /*
1807 * Register this driver with the serial core
1808 */
1809 rc = uart_register_driver(&pmz_uart_reg);
1810 if (rc)
1811 return rc;
1812
1813 /*
1814 * Register each port with the serial core
1815 */
1816 for (i = 0; i < pmz_ports_count; i++) {
1817 struct uart_pmac_port *uport = &pmz_ports[i];
1818 /* NULL node may happen on wallstreet */
1819 if (uport->node != NULL)
1820 rc = uart_add_one_port(&pmz_uart_reg, &uport->port);
1821 if (rc)
1822 goto err_out;
1823 }
1824
1825 return 0;
1826 err_out:
1827 while (i-- > 0) {
1828 struct uart_pmac_port *uport = &pmz_ports[i];
1829 uart_remove_one_port(&pmz_uart_reg, &uport->port);
1830 }
1831 uart_unregister_driver(&pmz_uart_reg);
1832 return rc;
1833 }
1834
1835 static struct of_device_id pmz_match[] =
1836 {
1837 {
1838 .name = "ch-a",
1839 },
1840 {
1841 .name = "ch-b",
1842 },
1843 {},
1844 };
1845 MODULE_DEVICE_TABLE (of, pmz_match);
1846
1847 static struct macio_driver pmz_driver =
1848 {
1849 .name = "pmac_zilog",
1850 .match_table = pmz_match,
1851 .probe = pmz_attach,
1852 .remove = pmz_detach,
1853 .suspend = pmz_suspend,
1854 .resume = pmz_resume,
1855 };
1856
1857 static int __init init_pmz(void)
1858 {
1859 int rc, i;
1860 printk(KERN_INFO "%s\n", version);
1861
1862 /*
1863 * First, we need to do a direct OF-based probe pass. We
1864 * do that because we want serial console up before the
1865 * macio stuffs calls us back, and since that makes it
1866 * easier to pass the proper number of channels to
1867 * uart_register_driver()
1868 */
1869 if (pmz_ports_count == 0)
1870 pmz_probe();
1871
1872 /*
1873 * Bail early if no port found
1874 */
1875 if (pmz_ports_count == 0)
1876 return -ENODEV;
1877
1878 /*
1879 * Now we register with the serial layer
1880 */
1881 rc = pmz_register();
1882 if (rc) {
1883 printk(KERN_ERR
1884 "pmac_zilog: Error registering serial device, disabling pmac_zilog.\n"
1885 "pmac_zilog: Did another serial driver already claim the minors?\n");
1886 /* effectively "pmz_unprobe()" */
1887 for (i=0; i < pmz_ports_count; i++)
1888 pmz_dispose_port(&pmz_ports[i]);
1889 return rc;
1890 }
1891
1892 /*
1893 * Then we register the macio driver itself
1894 */
1895 return macio_register_driver(&pmz_driver);
1896 }
1897
1898 static void __exit exit_pmz(void)
1899 {
1900 int i;
1901
1902 /* Get rid of macio-driver (detach from macio) */
1903 macio_unregister_driver(&pmz_driver);
1904
1905 for (i = 0; i < pmz_ports_count; i++) {
1906 struct uart_pmac_port *uport = &pmz_ports[i];
1907 if (uport->node != NULL) {
1908 uart_remove_one_port(&pmz_uart_reg, &uport->port);
1909 pmz_dispose_port(uport);
1910 }
1911 }
1912 /* Unregister UART driver */
1913 uart_unregister_driver(&pmz_uart_reg);
1914 }
1915
1916 #ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE
1917
1918 static void pmz_console_putchar(struct uart_port *port, int ch)
1919 {
1920 struct uart_pmac_port *uap = (struct uart_pmac_port *)port;
1921
1922 /* Wait for the transmit buffer to empty. */
1923 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0)
1924 udelay(5);
1925 write_zsdata(uap, ch);
1926 }
1927
1928 /*
1929 * Print a string to the serial port trying not to disturb
1930 * any possible real use of the port...
1931 */
1932 static void pmz_console_write(struct console *con, const char *s, unsigned int count)
1933 {
1934 struct uart_pmac_port *uap = &pmz_ports[con->index];
1935 unsigned long flags;
1936
1937 if (ZS_IS_ASLEEP(uap))
1938 return;
1939 spin_lock_irqsave(&uap->port.lock, flags);
1940
1941 /* Turn of interrupts and enable the transmitter. */
1942 write_zsreg(uap, R1, uap->curregs[1] & ~TxINT_ENAB);
1943 write_zsreg(uap, R5, uap->curregs[5] | TxENABLE | RTS | DTR);
1944
1945 uart_console_write(&uap->port, s, count, pmz_console_putchar);
1946
1947 /* Restore the values in the registers. */
1948 write_zsreg(uap, R1, uap->curregs[1]);
1949 /* Don't disable the transmitter. */
1950
1951 spin_unlock_irqrestore(&uap->port.lock, flags);
1952 }
1953
1954 /*
1955 * Setup the serial console
1956 */
1957 static int __init pmz_console_setup(struct console *co, char *options)
1958 {
1959 struct uart_pmac_port *uap;
1960 struct uart_port *port;
1961 int baud = 38400;
1962 int bits = 8;
1963 int parity = 'n';
1964 int flow = 'n';
1965 unsigned long pwr_delay;
1966
1967 /*
1968 * XServe's default to 57600 bps
1969 */
1970 if (machine_is_compatible("RackMac1,1")
1971 || machine_is_compatible("RackMac1,2")
1972 || machine_is_compatible("MacRISC4"))
1973 baud = 57600;
1974
1975 /*
1976 * Check whether an invalid uart number has been specified, and
1977 * if so, search for the first available port that does have
1978 * console support.
1979 */
1980 if (co->index >= pmz_ports_count)
1981 co->index = 0;
1982 uap = &pmz_ports[co->index];
1983 if (uap->node == NULL)
1984 return -ENODEV;
1985 port = &uap->port;
1986
1987 /*
1988 * Mark port as beeing a console
1989 */
1990 uap->flags |= PMACZILOG_FLAG_IS_CONS;
1991
1992 /*
1993 * Temporary fix for uart layer who didn't setup the spinlock yet
1994 */
1995 spin_lock_init(&port->lock);
1996
1997 /*
1998 * Enable the hardware
1999 */
2000 pwr_delay = __pmz_startup(uap);
2001 if (pwr_delay)
2002 mdelay(pwr_delay);
2003
2004 if (options)
2005 uart_parse_options(options, &baud, &parity, &bits, &flow);
2006
2007 return uart_set_options(port, co, baud, parity, bits, flow);
2008 }
2009
2010 static int __init pmz_console_init(void)
2011 {
2012 /* Probe ports */
2013 pmz_probe();
2014
2015 /* TODO: Autoprobe console based on OF */
2016 /* pmz_console.index = i; */
2017 register_console(&pmz_console);
2018
2019 return 0;
2020
2021 }
2022 console_initcall(pmz_console_init);
2023 #endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
2024
2025 module_init(init_pmz);
2026 module_exit(exit_pmz);
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