1 /* b44.c: Broadcom 4400 device driver.
3 * Copyright (C) 2002 David S. Miller (davem@redhat.com)
4 * Fixed by Pekka Pietikainen (pp@ee.oulu.fi)
6 * Distribute under GPL.
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/moduleparam.h>
12 #include <linux/types.h>
13 #include <linux/netdevice.h>
14 #include <linux/ethtool.h>
15 #include <linux/mii.h>
16 #include <linux/if_ether.h>
17 #include <linux/etherdevice.h>
18 #include <linux/pci.h>
19 #include <linux/delay.h>
20 #include <linux/init.h>
21 #include <linux/dma-mapping.h>
23 #include <asm/uaccess.h>
29 #define DRV_MODULE_NAME "b44"
30 #define PFX DRV_MODULE_NAME ": "
31 #define DRV_MODULE_VERSION "0.97"
32 #define DRV_MODULE_RELDATE "Nov 30, 2005"
34 #define B44_DEF_MSG_ENABLE \
44 /* length of time before we decide the hardware is borked,
45 * and dev->tx_timeout() should be called to fix the problem
47 #define B44_TX_TIMEOUT (5 * HZ)
49 /* hardware minimum and maximum for a single frame's data payload */
50 #define B44_MIN_MTU 60
51 #define B44_MAX_MTU 1500
53 #define B44_RX_RING_SIZE 512
54 #define B44_DEF_RX_RING_PENDING 200
55 #define B44_RX_RING_BYTES (sizeof(struct dma_desc) * \
57 #define B44_TX_RING_SIZE 512
58 #define B44_DEF_TX_RING_PENDING (B44_TX_RING_SIZE - 1)
59 #define B44_TX_RING_BYTES (sizeof(struct dma_desc) * \
61 #define B44_DMA_MASK 0x3fffffff
63 #define TX_RING_GAP(BP) \
64 (B44_TX_RING_SIZE - (BP)->tx_pending)
65 #define TX_BUFFS_AVAIL(BP) \
66 (((BP)->tx_cons <= (BP)->tx_prod) ? \
67 (BP)->tx_cons + (BP)->tx_pending - (BP)->tx_prod : \
68 (BP)->tx_cons - (BP)->tx_prod - TX_RING_GAP(BP))
69 #define NEXT_TX(N) (((N) + 1) & (B44_TX_RING_SIZE - 1))
71 #define RX_PKT_BUF_SZ (1536 + bp->rx_offset + 64)
72 #define TX_PKT_BUF_SZ (B44_MAX_MTU + ETH_HLEN + 8)
74 /* minimum number of free TX descriptors required to wake up TX process */
75 #define B44_TX_WAKEUP_THRESH (B44_TX_RING_SIZE / 4)
77 static char version
[] __devinitdata
=
78 DRV_MODULE_NAME
".c:v" DRV_MODULE_VERSION
" (" DRV_MODULE_RELDATE
")\n";
80 MODULE_AUTHOR("Florian Schirmer, Pekka Pietikainen, David S. Miller");
81 MODULE_DESCRIPTION("Broadcom 4400 10/100 PCI ethernet driver");
82 MODULE_LICENSE("GPL");
83 MODULE_VERSION(DRV_MODULE_VERSION
);
85 static int b44_debug
= -1; /* -1 == use B44_DEF_MSG_ENABLE as value */
86 module_param(b44_debug
, int, 0);
87 MODULE_PARM_DESC(b44_debug
, "B44 bitmapped debugging message enable value");
89 static struct pci_device_id b44_pci_tbl
[] = {
90 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_BCM4401
,
91 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
92 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_BCM4401B0
,
93 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
94 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_BCM4401B1
,
95 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
96 { } /* terminate list with empty entry */
99 MODULE_DEVICE_TABLE(pci
, b44_pci_tbl
);
101 static void b44_halt(struct b44
*);
102 static void b44_init_rings(struct b44
*);
103 static void b44_init_hw(struct b44
*);
105 static int dma_desc_align_mask
;
106 static int dma_desc_sync_size
;
108 static const char b44_gstrings
[][ETH_GSTRING_LEN
] = {
109 #define _B44(x...) # x,
114 static inline void b44_sync_dma_desc_for_device(struct pci_dev
*pdev
,
116 unsigned long offset
,
117 enum dma_data_direction dir
)
119 dma_sync_single_range_for_device(&pdev
->dev
, dma_base
,
120 offset
& dma_desc_align_mask
,
121 dma_desc_sync_size
, dir
);
124 static inline void b44_sync_dma_desc_for_cpu(struct pci_dev
*pdev
,
126 unsigned long offset
,
127 enum dma_data_direction dir
)
129 dma_sync_single_range_for_cpu(&pdev
->dev
, dma_base
,
130 offset
& dma_desc_align_mask
,
131 dma_desc_sync_size
, dir
);
134 static inline unsigned long br32(const struct b44
*bp
, unsigned long reg
)
136 return readl(bp
->regs
+ reg
);
139 static inline void bw32(const struct b44
*bp
,
140 unsigned long reg
, unsigned long val
)
142 writel(val
, bp
->regs
+ reg
);
145 static int b44_wait_bit(struct b44
*bp
, unsigned long reg
,
146 u32 bit
, unsigned long timeout
, const int clear
)
150 for (i
= 0; i
< timeout
; i
++) {
151 u32 val
= br32(bp
, reg
);
153 if (clear
&& !(val
& bit
))
155 if (!clear
&& (val
& bit
))
160 printk(KERN_ERR PFX
"%s: BUG! Timeout waiting for bit %08x of register "
164 (clear
? "clear" : "set"));
170 /* Sonics SiliconBackplane support routines. ROFL, you should see all the
171 * buzz words used on this company's website :-)
173 * All of these routines must be invoked with bp->lock held and
174 * interrupts disabled.
177 #define SB_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
178 #define BCM4400_PCI_CORE_ADDR 0x18002000 /* Address of PCI core on BCM4400 cards */
180 static u32
ssb_get_core_rev(struct b44
*bp
)
182 return (br32(bp
, B44_SBIDHIGH
) & SBIDHIGH_RC_MASK
);
185 static u32
ssb_pci_setup(struct b44
*bp
, u32 cores
)
187 u32 bar_orig
, pci_rev
, val
;
189 pci_read_config_dword(bp
->pdev
, SSB_BAR0_WIN
, &bar_orig
);
190 pci_write_config_dword(bp
->pdev
, SSB_BAR0_WIN
, BCM4400_PCI_CORE_ADDR
);
191 pci_rev
= ssb_get_core_rev(bp
);
193 val
= br32(bp
, B44_SBINTVEC
);
195 bw32(bp
, B44_SBINTVEC
, val
);
197 val
= br32(bp
, SSB_PCI_TRANS_2
);
198 val
|= SSB_PCI_PREF
| SSB_PCI_BURST
;
199 bw32(bp
, SSB_PCI_TRANS_2
, val
);
201 pci_write_config_dword(bp
->pdev
, SSB_BAR0_WIN
, bar_orig
);
206 static void ssb_core_disable(struct b44
*bp
)
208 if (br32(bp
, B44_SBTMSLOW
) & SBTMSLOW_RESET
)
211 bw32(bp
, B44_SBTMSLOW
, (SBTMSLOW_REJECT
| SBTMSLOW_CLOCK
));
212 b44_wait_bit(bp
, B44_SBTMSLOW
, SBTMSLOW_REJECT
, 100000, 0);
213 b44_wait_bit(bp
, B44_SBTMSHIGH
, SBTMSHIGH_BUSY
, 100000, 1);
214 bw32(bp
, B44_SBTMSLOW
, (SBTMSLOW_FGC
| SBTMSLOW_CLOCK
|
215 SBTMSLOW_REJECT
| SBTMSLOW_RESET
));
216 br32(bp
, B44_SBTMSLOW
);
218 bw32(bp
, B44_SBTMSLOW
, (SBTMSLOW_REJECT
| SBTMSLOW_RESET
));
219 br32(bp
, B44_SBTMSLOW
);
223 static void ssb_core_reset(struct b44
*bp
)
227 ssb_core_disable(bp
);
228 bw32(bp
, B44_SBTMSLOW
, (SBTMSLOW_RESET
| SBTMSLOW_CLOCK
| SBTMSLOW_FGC
));
229 br32(bp
, B44_SBTMSLOW
);
232 /* Clear SERR if set, this is a hw bug workaround. */
233 if (br32(bp
, B44_SBTMSHIGH
) & SBTMSHIGH_SERR
)
234 bw32(bp
, B44_SBTMSHIGH
, 0);
236 val
= br32(bp
, B44_SBIMSTATE
);
237 if (val
& (SBIMSTATE_IBE
| SBIMSTATE_TO
))
238 bw32(bp
, B44_SBIMSTATE
, val
& ~(SBIMSTATE_IBE
| SBIMSTATE_TO
));
240 bw32(bp
, B44_SBTMSLOW
, (SBTMSLOW_CLOCK
| SBTMSLOW_FGC
));
241 br32(bp
, B44_SBTMSLOW
);
244 bw32(bp
, B44_SBTMSLOW
, (SBTMSLOW_CLOCK
));
245 br32(bp
, B44_SBTMSLOW
);
249 static int ssb_core_unit(struct b44
*bp
)
252 u32 val
= br32(bp
, B44_SBADMATCH0
);
255 type
= val
& SBADMATCH0_TYPE_MASK
;
258 base
= val
& SBADMATCH0_BS0_MASK
;
262 base
= val
& SBADMATCH0_BS1_MASK
;
267 base
= val
& SBADMATCH0_BS2_MASK
;
274 static int ssb_is_core_up(struct b44
*bp
)
276 return ((br32(bp
, B44_SBTMSLOW
) & (SBTMSLOW_RESET
| SBTMSLOW_REJECT
| SBTMSLOW_CLOCK
))
280 static void __b44_cam_write(struct b44
*bp
, unsigned char *data
, int index
)
284 val
= ((u32
) data
[2]) << 24;
285 val
|= ((u32
) data
[3]) << 16;
286 val
|= ((u32
) data
[4]) << 8;
287 val
|= ((u32
) data
[5]) << 0;
288 bw32(bp
, B44_CAM_DATA_LO
, val
);
289 val
= (CAM_DATA_HI_VALID
|
290 (((u32
) data
[0]) << 8) |
291 (((u32
) data
[1]) << 0));
292 bw32(bp
, B44_CAM_DATA_HI
, val
);
293 bw32(bp
, B44_CAM_CTRL
, (CAM_CTRL_WRITE
|
294 (index
<< CAM_CTRL_INDEX_SHIFT
)));
295 b44_wait_bit(bp
, B44_CAM_CTRL
, CAM_CTRL_BUSY
, 100, 1);
298 static inline void __b44_disable_ints(struct b44
*bp
)
300 bw32(bp
, B44_IMASK
, 0);
303 static void b44_disable_ints(struct b44
*bp
)
305 __b44_disable_ints(bp
);
307 /* Flush posted writes. */
311 static void b44_enable_ints(struct b44
*bp
)
313 bw32(bp
, B44_IMASK
, bp
->imask
);
316 static int b44_readphy(struct b44
*bp
, int reg
, u32
*val
)
320 bw32(bp
, B44_EMAC_ISTAT
, EMAC_INT_MII
);
321 bw32(bp
, B44_MDIO_DATA
, (MDIO_DATA_SB_START
|
322 (MDIO_OP_READ
<< MDIO_DATA_OP_SHIFT
) |
323 (bp
->phy_addr
<< MDIO_DATA_PMD_SHIFT
) |
324 (reg
<< MDIO_DATA_RA_SHIFT
) |
325 (MDIO_TA_VALID
<< MDIO_DATA_TA_SHIFT
)));
326 err
= b44_wait_bit(bp
, B44_EMAC_ISTAT
, EMAC_INT_MII
, 100, 0);
327 *val
= br32(bp
, B44_MDIO_DATA
) & MDIO_DATA_DATA
;
332 static int b44_writephy(struct b44
*bp
, int reg
, u32 val
)
334 bw32(bp
, B44_EMAC_ISTAT
, EMAC_INT_MII
);
335 bw32(bp
, B44_MDIO_DATA
, (MDIO_DATA_SB_START
|
336 (MDIO_OP_WRITE
<< MDIO_DATA_OP_SHIFT
) |
337 (bp
->phy_addr
<< MDIO_DATA_PMD_SHIFT
) |
338 (reg
<< MDIO_DATA_RA_SHIFT
) |
339 (MDIO_TA_VALID
<< MDIO_DATA_TA_SHIFT
) |
340 (val
& MDIO_DATA_DATA
)));
341 return b44_wait_bit(bp
, B44_EMAC_ISTAT
, EMAC_INT_MII
, 100, 0);
344 /* miilib interface */
345 /* FIXME FIXME: phy_id is ignored, bp->phy_addr use is unconditional
346 * due to code existing before miilib use was added to this driver.
347 * Someone should remove this artificial driver limitation in
348 * b44_{read,write}phy. bp->phy_addr itself is fine (and needed).
350 static int b44_mii_read(struct net_device
*dev
, int phy_id
, int location
)
353 struct b44
*bp
= netdev_priv(dev
);
354 int rc
= b44_readphy(bp
, location
, &val
);
360 static void b44_mii_write(struct net_device
*dev
, int phy_id
, int location
,
363 struct b44
*bp
= netdev_priv(dev
);
364 b44_writephy(bp
, location
, val
);
367 static int b44_phy_reset(struct b44
*bp
)
372 err
= b44_writephy(bp
, MII_BMCR
, BMCR_RESET
);
376 err
= b44_readphy(bp
, MII_BMCR
, &val
);
378 if (val
& BMCR_RESET
) {
379 printk(KERN_ERR PFX
"%s: PHY Reset would not complete.\n",
388 static void __b44_set_flow_ctrl(struct b44
*bp
, u32 pause_flags
)
392 bp
->flags
&= ~(B44_FLAG_TX_PAUSE
| B44_FLAG_RX_PAUSE
);
393 bp
->flags
|= pause_flags
;
395 val
= br32(bp
, B44_RXCONFIG
);
396 if (pause_flags
& B44_FLAG_RX_PAUSE
)
397 val
|= RXCONFIG_FLOW
;
399 val
&= ~RXCONFIG_FLOW
;
400 bw32(bp
, B44_RXCONFIG
, val
);
402 val
= br32(bp
, B44_MAC_FLOW
);
403 if (pause_flags
& B44_FLAG_TX_PAUSE
)
404 val
|= (MAC_FLOW_PAUSE_ENAB
|
405 (0xc0 & MAC_FLOW_RX_HI_WATER
));
407 val
&= ~MAC_FLOW_PAUSE_ENAB
;
408 bw32(bp
, B44_MAC_FLOW
, val
);
411 static void b44_set_flow_ctrl(struct b44
*bp
, u32 local
, u32 remote
)
413 u32 pause_enab
= bp
->flags
& (B44_FLAG_TX_PAUSE
|
416 if (local
& ADVERTISE_PAUSE_CAP
) {
417 if (local
& ADVERTISE_PAUSE_ASYM
) {
418 if (remote
& LPA_PAUSE_CAP
)
419 pause_enab
|= (B44_FLAG_TX_PAUSE
|
421 else if (remote
& LPA_PAUSE_ASYM
)
422 pause_enab
|= B44_FLAG_RX_PAUSE
;
424 if (remote
& LPA_PAUSE_CAP
)
425 pause_enab
|= (B44_FLAG_TX_PAUSE
|
428 } else if (local
& ADVERTISE_PAUSE_ASYM
) {
429 if ((remote
& LPA_PAUSE_CAP
) &&
430 (remote
& LPA_PAUSE_ASYM
))
431 pause_enab
|= B44_FLAG_TX_PAUSE
;
434 __b44_set_flow_ctrl(bp
, pause_enab
);
437 static int b44_setup_phy(struct b44
*bp
)
442 if ((err
= b44_readphy(bp
, B44_MII_ALEDCTRL
, &val
)) != 0)
444 if ((err
= b44_writephy(bp
, B44_MII_ALEDCTRL
,
445 val
& MII_ALEDCTRL_ALLMSK
)) != 0)
447 if ((err
= b44_readphy(bp
, B44_MII_TLEDCTRL
, &val
)) != 0)
449 if ((err
= b44_writephy(bp
, B44_MII_TLEDCTRL
,
450 val
| MII_TLEDCTRL_ENABLE
)) != 0)
453 if (!(bp
->flags
& B44_FLAG_FORCE_LINK
)) {
454 u32 adv
= ADVERTISE_CSMA
;
456 if (bp
->flags
& B44_FLAG_ADV_10HALF
)
457 adv
|= ADVERTISE_10HALF
;
458 if (bp
->flags
& B44_FLAG_ADV_10FULL
)
459 adv
|= ADVERTISE_10FULL
;
460 if (bp
->flags
& B44_FLAG_ADV_100HALF
)
461 adv
|= ADVERTISE_100HALF
;
462 if (bp
->flags
& B44_FLAG_ADV_100FULL
)
463 adv
|= ADVERTISE_100FULL
;
465 if (bp
->flags
& B44_FLAG_PAUSE_AUTO
)
466 adv
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
468 if ((err
= b44_writephy(bp
, MII_ADVERTISE
, adv
)) != 0)
470 if ((err
= b44_writephy(bp
, MII_BMCR
, (BMCR_ANENABLE
|
471 BMCR_ANRESTART
))) != 0)
476 if ((err
= b44_readphy(bp
, MII_BMCR
, &bmcr
)) != 0)
478 bmcr
&= ~(BMCR_FULLDPLX
| BMCR_ANENABLE
| BMCR_SPEED100
);
479 if (bp
->flags
& B44_FLAG_100_BASE_T
)
480 bmcr
|= BMCR_SPEED100
;
481 if (bp
->flags
& B44_FLAG_FULL_DUPLEX
)
482 bmcr
|= BMCR_FULLDPLX
;
483 if ((err
= b44_writephy(bp
, MII_BMCR
, bmcr
)) != 0)
486 /* Since we will not be negotiating there is no safe way
487 * to determine if the link partner supports flow control
488 * or not. So just disable it completely in this case.
490 b44_set_flow_ctrl(bp
, 0, 0);
497 static void b44_stats_update(struct b44
*bp
)
502 val
= &bp
->hw_stats
.tx_good_octets
;
503 for (reg
= B44_TX_GOOD_O
; reg
<= B44_TX_PAUSE
; reg
+= 4UL) {
504 *val
++ += br32(bp
, reg
);
510 for (reg
= B44_RX_GOOD_O
; reg
<= B44_RX_NPAUSE
; reg
+= 4UL) {
511 *val
++ += br32(bp
, reg
);
515 static void b44_link_report(struct b44
*bp
)
517 if (!netif_carrier_ok(bp
->dev
)) {
518 printk(KERN_INFO PFX
"%s: Link is down.\n", bp
->dev
->name
);
520 printk(KERN_INFO PFX
"%s: Link is up at %d Mbps, %s duplex.\n",
522 (bp
->flags
& B44_FLAG_100_BASE_T
) ? 100 : 10,
523 (bp
->flags
& B44_FLAG_FULL_DUPLEX
) ? "full" : "half");
525 printk(KERN_INFO PFX
"%s: Flow control is %s for TX and "
528 (bp
->flags
& B44_FLAG_TX_PAUSE
) ? "on" : "off",
529 (bp
->flags
& B44_FLAG_RX_PAUSE
) ? "on" : "off");
533 static void b44_check_phy(struct b44
*bp
)
537 if (!b44_readphy(bp
, MII_BMSR
, &bmsr
) &&
538 !b44_readphy(bp
, B44_MII_AUXCTRL
, &aux
) &&
540 if (aux
& MII_AUXCTRL_SPEED
)
541 bp
->flags
|= B44_FLAG_100_BASE_T
;
543 bp
->flags
&= ~B44_FLAG_100_BASE_T
;
544 if (aux
& MII_AUXCTRL_DUPLEX
)
545 bp
->flags
|= B44_FLAG_FULL_DUPLEX
;
547 bp
->flags
&= ~B44_FLAG_FULL_DUPLEX
;
549 if (!netif_carrier_ok(bp
->dev
) &&
550 (bmsr
& BMSR_LSTATUS
)) {
551 u32 val
= br32(bp
, B44_TX_CTRL
);
552 u32 local_adv
, remote_adv
;
554 if (bp
->flags
& B44_FLAG_FULL_DUPLEX
)
555 val
|= TX_CTRL_DUPLEX
;
557 val
&= ~TX_CTRL_DUPLEX
;
558 bw32(bp
, B44_TX_CTRL
, val
);
560 if (!(bp
->flags
& B44_FLAG_FORCE_LINK
) &&
561 !b44_readphy(bp
, MII_ADVERTISE
, &local_adv
) &&
562 !b44_readphy(bp
, MII_LPA
, &remote_adv
))
563 b44_set_flow_ctrl(bp
, local_adv
, remote_adv
);
566 netif_carrier_on(bp
->dev
);
568 } else if (netif_carrier_ok(bp
->dev
) && !(bmsr
& BMSR_LSTATUS
)) {
570 netif_carrier_off(bp
->dev
);
574 if (bmsr
& BMSR_RFAULT
)
575 printk(KERN_WARNING PFX
"%s: Remote fault detected in PHY\n",
578 printk(KERN_WARNING PFX
"%s: Jabber detected in PHY\n",
583 static void b44_timer(unsigned long __opaque
)
585 struct b44
*bp
= (struct b44
*) __opaque
;
587 spin_lock_irq(&bp
->lock
);
591 b44_stats_update(bp
);
593 spin_unlock_irq(&bp
->lock
);
595 bp
->timer
.expires
= jiffies
+ HZ
;
596 add_timer(&bp
->timer
);
599 static void b44_tx(struct b44
*bp
)
603 cur
= br32(bp
, B44_DMATX_STAT
) & DMATX_STAT_CDMASK
;
604 cur
/= sizeof(struct dma_desc
);
606 /* XXX needs updating when NETIF_F_SG is supported */
607 for (cons
= bp
->tx_cons
; cons
!= cur
; cons
= NEXT_TX(cons
)) {
608 struct ring_info
*rp
= &bp
->tx_buffers
[cons
];
609 struct sk_buff
*skb
= rp
->skb
;
613 pci_unmap_single(bp
->pdev
,
614 pci_unmap_addr(rp
, mapping
),
618 dev_kfree_skb_irq(skb
);
622 if (netif_queue_stopped(bp
->dev
) &&
623 TX_BUFFS_AVAIL(bp
) > B44_TX_WAKEUP_THRESH
)
624 netif_wake_queue(bp
->dev
);
626 bw32(bp
, B44_GPTIMER
, 0);
629 /* Works like this. This chip writes a 'struct rx_header" 30 bytes
630 * before the DMA address you give it. So we allocate 30 more bytes
631 * for the RX buffer, DMA map all of it, skb_reserve the 30 bytes, then
632 * point the chip at 30 bytes past where the rx_header will go.
634 static int b44_alloc_rx_skb(struct b44
*bp
, int src_idx
, u32 dest_idx_unmasked
)
637 struct ring_info
*src_map
, *map
;
638 struct rx_header
*rh
;
646 src_map
= &bp
->rx_buffers
[src_idx
];
647 dest_idx
= dest_idx_unmasked
& (B44_RX_RING_SIZE
- 1);
648 map
= &bp
->rx_buffers
[dest_idx
];
649 skb
= dev_alloc_skb(RX_PKT_BUF_SZ
);
653 mapping
= pci_map_single(bp
->pdev
, skb
->data
,
657 /* Hardware bug work-around, the chip is unable to do PCI DMA
658 to/from anything above 1GB :-( */
659 if (mapping
+ RX_PKT_BUF_SZ
> B44_DMA_MASK
) {
661 pci_unmap_single(bp
->pdev
, mapping
, RX_PKT_BUF_SZ
,PCI_DMA_FROMDEVICE
);
662 dev_kfree_skb_any(skb
);
663 skb
= __dev_alloc_skb(RX_PKT_BUF_SZ
,GFP_DMA
);
666 mapping
= pci_map_single(bp
->pdev
, skb
->data
,
669 if (mapping
+ RX_PKT_BUF_SZ
> B44_DMA_MASK
) {
670 pci_unmap_single(bp
->pdev
, mapping
, RX_PKT_BUF_SZ
,PCI_DMA_FROMDEVICE
);
671 dev_kfree_skb_any(skb
);
677 skb_reserve(skb
, bp
->rx_offset
);
679 rh
= (struct rx_header
*)
680 (skb
->data
- bp
->rx_offset
);
685 pci_unmap_addr_set(map
, mapping
, mapping
);
690 ctrl
= (DESC_CTRL_LEN
& (RX_PKT_BUF_SZ
- bp
->rx_offset
));
691 if (dest_idx
== (B44_RX_RING_SIZE
- 1))
692 ctrl
|= DESC_CTRL_EOT
;
694 dp
= &bp
->rx_ring
[dest_idx
];
695 dp
->ctrl
= cpu_to_le32(ctrl
);
696 dp
->addr
= cpu_to_le32((u32
) mapping
+ bp
->rx_offset
+ bp
->dma_offset
);
698 if (bp
->flags
& B44_FLAG_RX_RING_HACK
)
699 b44_sync_dma_desc_for_device(bp
->pdev
, bp
->rx_ring_dma
,
700 dest_idx
* sizeof(dp
),
703 return RX_PKT_BUF_SZ
;
706 static void b44_recycle_rx(struct b44
*bp
, int src_idx
, u32 dest_idx_unmasked
)
708 struct dma_desc
*src_desc
, *dest_desc
;
709 struct ring_info
*src_map
, *dest_map
;
710 struct rx_header
*rh
;
714 dest_idx
= dest_idx_unmasked
& (B44_RX_RING_SIZE
- 1);
715 dest_desc
= &bp
->rx_ring
[dest_idx
];
716 dest_map
= &bp
->rx_buffers
[dest_idx
];
717 src_desc
= &bp
->rx_ring
[src_idx
];
718 src_map
= &bp
->rx_buffers
[src_idx
];
720 dest_map
->skb
= src_map
->skb
;
721 rh
= (struct rx_header
*) src_map
->skb
->data
;
724 pci_unmap_addr_set(dest_map
, mapping
,
725 pci_unmap_addr(src_map
, mapping
));
727 if (bp
->flags
& B44_FLAG_RX_RING_HACK
)
728 b44_sync_dma_desc_for_cpu(bp
->pdev
, bp
->rx_ring_dma
,
729 src_idx
* sizeof(src_desc
),
732 ctrl
= src_desc
->ctrl
;
733 if (dest_idx
== (B44_RX_RING_SIZE
- 1))
734 ctrl
|= cpu_to_le32(DESC_CTRL_EOT
);
736 ctrl
&= cpu_to_le32(~DESC_CTRL_EOT
);
738 dest_desc
->ctrl
= ctrl
;
739 dest_desc
->addr
= src_desc
->addr
;
743 if (bp
->flags
& B44_FLAG_RX_RING_HACK
)
744 b44_sync_dma_desc_for_device(bp
->pdev
, bp
->rx_ring_dma
,
745 dest_idx
* sizeof(dest_desc
),
748 pci_dma_sync_single_for_device(bp
->pdev
, src_desc
->addr
,
753 static int b44_rx(struct b44
*bp
, int budget
)
759 prod
= br32(bp
, B44_DMARX_STAT
) & DMARX_STAT_CDMASK
;
760 prod
/= sizeof(struct dma_desc
);
763 while (cons
!= prod
&& budget
> 0) {
764 struct ring_info
*rp
= &bp
->rx_buffers
[cons
];
765 struct sk_buff
*skb
= rp
->skb
;
766 dma_addr_t map
= pci_unmap_addr(rp
, mapping
);
767 struct rx_header
*rh
;
770 pci_dma_sync_single_for_cpu(bp
->pdev
, map
,
773 rh
= (struct rx_header
*) skb
->data
;
774 len
= cpu_to_le16(rh
->len
);
775 if ((len
> (RX_PKT_BUF_SZ
- bp
->rx_offset
)) ||
776 (rh
->flags
& cpu_to_le16(RX_FLAG_ERRORS
))) {
778 b44_recycle_rx(bp
, cons
, bp
->rx_prod
);
780 bp
->stats
.rx_dropped
++;
790 len
= cpu_to_le16(rh
->len
);
791 } while (len
== 0 && i
++ < 5);
799 if (len
> RX_COPY_THRESHOLD
) {
801 skb_size
= b44_alloc_rx_skb(bp
, cons
, bp
->rx_prod
);
804 pci_unmap_single(bp
->pdev
, map
,
805 skb_size
, PCI_DMA_FROMDEVICE
);
806 /* Leave out rx_header */
807 skb_put(skb
, len
+bp
->rx_offset
);
808 skb_pull(skb
,bp
->rx_offset
);
810 struct sk_buff
*copy_skb
;
812 b44_recycle_rx(bp
, cons
, bp
->rx_prod
);
813 copy_skb
= dev_alloc_skb(len
+ 2);
814 if (copy_skb
== NULL
)
815 goto drop_it_no_recycle
;
817 copy_skb
->dev
= bp
->dev
;
818 skb_reserve(copy_skb
, 2);
819 skb_put(copy_skb
, len
);
820 /* DMA sync done above, copy just the actual packet */
821 memcpy(copy_skb
->data
, skb
->data
+bp
->rx_offset
, len
);
825 skb
->ip_summed
= CHECKSUM_NONE
;
826 skb
->protocol
= eth_type_trans(skb
, bp
->dev
);
827 netif_receive_skb(skb
);
828 bp
->dev
->last_rx
= jiffies
;
832 bp
->rx_prod
= (bp
->rx_prod
+ 1) &
833 (B44_RX_RING_SIZE
- 1);
834 cons
= (cons
+ 1) & (B44_RX_RING_SIZE
- 1);
838 bw32(bp
, B44_DMARX_PTR
, cons
* sizeof(struct dma_desc
));
843 static int b44_poll(struct net_device
*netdev
, int *budget
)
845 struct b44
*bp
= netdev_priv(netdev
);
848 spin_lock_irq(&bp
->lock
);
850 if (bp
->istat
& (ISTAT_TX
| ISTAT_TO
)) {
851 /* spin_lock(&bp->tx_lock); */
853 /* spin_unlock(&bp->tx_lock); */
855 spin_unlock_irq(&bp
->lock
);
858 if (bp
->istat
& ISTAT_RX
) {
859 int orig_budget
= *budget
;
862 if (orig_budget
> netdev
->quota
)
863 orig_budget
= netdev
->quota
;
865 work_done
= b44_rx(bp
, orig_budget
);
867 *budget
-= work_done
;
868 netdev
->quota
-= work_done
;
870 if (work_done
>= orig_budget
)
874 if (bp
->istat
& ISTAT_ERRORS
) {
875 spin_lock_irq(&bp
->lock
);
879 netif_wake_queue(bp
->dev
);
880 spin_unlock_irq(&bp
->lock
);
885 netif_rx_complete(netdev
);
889 return (done
? 0 : 1);
892 static irqreturn_t
b44_interrupt(int irq
, void *dev_id
, struct pt_regs
*regs
)
894 struct net_device
*dev
= dev_id
;
895 struct b44
*bp
= netdev_priv(dev
);
899 spin_lock(&bp
->lock
);
901 istat
= br32(bp
, B44_ISTAT
);
902 imask
= br32(bp
, B44_IMASK
);
904 /* ??? What the fuck is the purpose of the interrupt mask
905 * ??? register if we have to mask it out by hand anyways?
911 if (unlikely(!netif_running(dev
))) {
912 printk(KERN_INFO
"%s: late interrupt.\n", dev
->name
);
916 if (netif_rx_schedule_prep(dev
)) {
917 /* NOTE: These writes are posted by the readback of
918 * the ISTAT register below.
921 __b44_disable_ints(bp
);
922 __netif_rx_schedule(dev
);
924 printk(KERN_ERR PFX
"%s: Error, poll already scheduled\n",
929 bw32(bp
, B44_ISTAT
, istat
);
932 spin_unlock(&bp
->lock
);
933 return IRQ_RETVAL(handled
);
936 static void b44_tx_timeout(struct net_device
*dev
)
938 struct b44
*bp
= netdev_priv(dev
);
940 printk(KERN_ERR PFX
"%s: transmit timed out, resetting\n",
943 spin_lock_irq(&bp
->lock
);
949 spin_unlock_irq(&bp
->lock
);
953 netif_wake_queue(dev
);
956 static int b44_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
958 struct b44
*bp
= netdev_priv(dev
);
959 struct sk_buff
*bounce_skb
;
960 int rc
= NETDEV_TX_OK
;
962 u32 len
, entry
, ctrl
;
965 spin_lock_irq(&bp
->lock
);
967 /* This is a hard error, log it. */
968 if (unlikely(TX_BUFFS_AVAIL(bp
) < 1)) {
969 netif_stop_queue(dev
);
970 printk(KERN_ERR PFX
"%s: BUG! Tx Ring full when queue awake!\n",
975 mapping
= pci_map_single(bp
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
976 if (mapping
+ len
> B44_DMA_MASK
) {
977 /* Chip can't handle DMA to/from >1GB, use bounce buffer */
978 pci_unmap_single(bp
->pdev
, mapping
, len
, PCI_DMA_TODEVICE
);
980 bounce_skb
= __dev_alloc_skb(TX_PKT_BUF_SZ
,
985 mapping
= pci_map_single(bp
->pdev
, bounce_skb
->data
,
986 len
, PCI_DMA_TODEVICE
);
987 if (mapping
+ len
> B44_DMA_MASK
) {
988 pci_unmap_single(bp
->pdev
, mapping
,
989 len
, PCI_DMA_TODEVICE
);
990 dev_kfree_skb_any(bounce_skb
);
994 memcpy(skb_put(bounce_skb
, len
), skb
->data
, skb
->len
);
995 dev_kfree_skb_any(skb
);
1000 bp
->tx_buffers
[entry
].skb
= skb
;
1001 pci_unmap_addr_set(&bp
->tx_buffers
[entry
], mapping
, mapping
);
1003 ctrl
= (len
& DESC_CTRL_LEN
);
1004 ctrl
|= DESC_CTRL_IOC
| DESC_CTRL_SOF
| DESC_CTRL_EOF
;
1005 if (entry
== (B44_TX_RING_SIZE
- 1))
1006 ctrl
|= DESC_CTRL_EOT
;
1008 bp
->tx_ring
[entry
].ctrl
= cpu_to_le32(ctrl
);
1009 bp
->tx_ring
[entry
].addr
= cpu_to_le32((u32
) mapping
+bp
->dma_offset
);
1011 if (bp
->flags
& B44_FLAG_TX_RING_HACK
)
1012 b44_sync_dma_desc_for_device(bp
->pdev
, bp
->tx_ring_dma
,
1013 entry
* sizeof(bp
->tx_ring
[0]),
1016 entry
= NEXT_TX(entry
);
1018 bp
->tx_prod
= entry
;
1022 bw32(bp
, B44_DMATX_PTR
, entry
* sizeof(struct dma_desc
));
1023 if (bp
->flags
& B44_FLAG_BUGGY_TXPTR
)
1024 bw32(bp
, B44_DMATX_PTR
, entry
* sizeof(struct dma_desc
));
1025 if (bp
->flags
& B44_FLAG_REORDER_BUG
)
1026 br32(bp
, B44_DMATX_PTR
);
1028 if (TX_BUFFS_AVAIL(bp
) < 1)
1029 netif_stop_queue(dev
);
1031 dev
->trans_start
= jiffies
;
1034 spin_unlock_irq(&bp
->lock
);
1039 rc
= NETDEV_TX_BUSY
;
1043 static int b44_change_mtu(struct net_device
*dev
, int new_mtu
)
1045 struct b44
*bp
= netdev_priv(dev
);
1047 if (new_mtu
< B44_MIN_MTU
|| new_mtu
> B44_MAX_MTU
)
1050 if (!netif_running(dev
)) {
1051 /* We'll just catch it later when the
1058 spin_lock_irq(&bp
->lock
);
1063 spin_unlock_irq(&bp
->lock
);
1065 b44_enable_ints(bp
);
1070 /* Free up pending packets in all rx/tx rings.
1072 * The chip has been shut down and the driver detached from
1073 * the networking, so no interrupts or new tx packets will
1074 * end up in the driver. bp->lock is not held and we are not
1075 * in an interrupt context and thus may sleep.
1077 static void b44_free_rings(struct b44
*bp
)
1079 struct ring_info
*rp
;
1082 for (i
= 0; i
< B44_RX_RING_SIZE
; i
++) {
1083 rp
= &bp
->rx_buffers
[i
];
1085 if (rp
->skb
== NULL
)
1087 pci_unmap_single(bp
->pdev
,
1088 pci_unmap_addr(rp
, mapping
),
1090 PCI_DMA_FROMDEVICE
);
1091 dev_kfree_skb_any(rp
->skb
);
1095 /* XXX needs changes once NETIF_F_SG is set... */
1096 for (i
= 0; i
< B44_TX_RING_SIZE
; i
++) {
1097 rp
= &bp
->tx_buffers
[i
];
1099 if (rp
->skb
== NULL
)
1101 pci_unmap_single(bp
->pdev
,
1102 pci_unmap_addr(rp
, mapping
),
1105 dev_kfree_skb_any(rp
->skb
);
1110 /* Initialize tx/rx rings for packet processing.
1112 * The chip has been shut down and the driver detached from
1113 * the networking, so no interrupts or new tx packets will
1114 * end up in the driver.
1116 static void b44_init_rings(struct b44
*bp
)
1122 memset(bp
->rx_ring
, 0, B44_RX_RING_BYTES
);
1123 memset(bp
->tx_ring
, 0, B44_TX_RING_BYTES
);
1125 if (bp
->flags
& B44_FLAG_RX_RING_HACK
)
1126 dma_sync_single_for_device(&bp
->pdev
->dev
, bp
->rx_ring_dma
,
1128 PCI_DMA_BIDIRECTIONAL
);
1130 if (bp
->flags
& B44_FLAG_TX_RING_HACK
)
1131 dma_sync_single_for_device(&bp
->pdev
->dev
, bp
->tx_ring_dma
,
1135 for (i
= 0; i
< bp
->rx_pending
; i
++) {
1136 if (b44_alloc_rx_skb(bp
, -1, i
) < 0)
1142 * Must not be invoked with interrupt sources disabled and
1143 * the hardware shutdown down.
1145 static void b44_free_consistent(struct b44
*bp
)
1147 kfree(bp
->rx_buffers
);
1148 bp
->rx_buffers
= NULL
;
1149 kfree(bp
->tx_buffers
);
1150 bp
->tx_buffers
= NULL
;
1152 if (bp
->flags
& B44_FLAG_RX_RING_HACK
) {
1153 dma_unmap_single(&bp
->pdev
->dev
, bp
->rx_ring_dma
,
1158 pci_free_consistent(bp
->pdev
, DMA_TABLE_BYTES
,
1159 bp
->rx_ring
, bp
->rx_ring_dma
);
1161 bp
->flags
&= ~B44_FLAG_RX_RING_HACK
;
1164 if (bp
->flags
& B44_FLAG_TX_RING_HACK
) {
1165 dma_unmap_single(&bp
->pdev
->dev
, bp
->tx_ring_dma
,
1170 pci_free_consistent(bp
->pdev
, DMA_TABLE_BYTES
,
1171 bp
->tx_ring
, bp
->tx_ring_dma
);
1173 bp
->flags
&= ~B44_FLAG_TX_RING_HACK
;
1178 * Must not be invoked with interrupt sources disabled and
1179 * the hardware shutdown down. Can sleep.
1181 static int b44_alloc_consistent(struct b44
*bp
)
1185 size
= B44_RX_RING_SIZE
* sizeof(struct ring_info
);
1186 bp
->rx_buffers
= kzalloc(size
, GFP_KERNEL
);
1187 if (!bp
->rx_buffers
)
1190 size
= B44_TX_RING_SIZE
* sizeof(struct ring_info
);
1191 bp
->tx_buffers
= kzalloc(size
, GFP_KERNEL
);
1192 if (!bp
->tx_buffers
)
1195 size
= DMA_TABLE_BYTES
;
1196 bp
->rx_ring
= pci_alloc_consistent(bp
->pdev
, size
, &bp
->rx_ring_dma
);
1198 /* Allocation may have failed due to pci_alloc_consistent
1199 insisting on use of GFP_DMA, which is more restrictive
1200 than necessary... */
1201 struct dma_desc
*rx_ring
;
1202 dma_addr_t rx_ring_dma
;
1204 rx_ring
= kzalloc(size
, GFP_KERNEL
);
1208 rx_ring_dma
= dma_map_single(&bp
->pdev
->dev
, rx_ring
,
1212 if (rx_ring_dma
+ size
> B44_DMA_MASK
) {
1217 bp
->rx_ring
= rx_ring
;
1218 bp
->rx_ring_dma
= rx_ring_dma
;
1219 bp
->flags
|= B44_FLAG_RX_RING_HACK
;
1222 bp
->tx_ring
= pci_alloc_consistent(bp
->pdev
, size
, &bp
->tx_ring_dma
);
1224 /* Allocation may have failed due to pci_alloc_consistent
1225 insisting on use of GFP_DMA, which is more restrictive
1226 than necessary... */
1227 struct dma_desc
*tx_ring
;
1228 dma_addr_t tx_ring_dma
;
1230 tx_ring
= kzalloc(size
, GFP_KERNEL
);
1234 tx_ring_dma
= dma_map_single(&bp
->pdev
->dev
, tx_ring
,
1238 if (tx_ring_dma
+ size
> B44_DMA_MASK
) {
1243 bp
->tx_ring
= tx_ring
;
1244 bp
->tx_ring_dma
= tx_ring_dma
;
1245 bp
->flags
|= B44_FLAG_TX_RING_HACK
;
1251 b44_free_consistent(bp
);
1255 /* bp->lock is held. */
1256 static void b44_clear_stats(struct b44
*bp
)
1260 bw32(bp
, B44_MIB_CTRL
, MIB_CTRL_CLR_ON_READ
);
1261 for (reg
= B44_TX_GOOD_O
; reg
<= B44_TX_PAUSE
; reg
+= 4UL)
1263 for (reg
= B44_RX_GOOD_O
; reg
<= B44_RX_NPAUSE
; reg
+= 4UL)
1267 /* bp->lock is held. */
1268 static void b44_chip_reset(struct b44
*bp
)
1270 if (ssb_is_core_up(bp
)) {
1271 bw32(bp
, B44_RCV_LAZY
, 0);
1272 bw32(bp
, B44_ENET_CTRL
, ENET_CTRL_DISABLE
);
1273 b44_wait_bit(bp
, B44_ENET_CTRL
, ENET_CTRL_DISABLE
, 100, 1);
1274 bw32(bp
, B44_DMATX_CTRL
, 0);
1275 bp
->tx_prod
= bp
->tx_cons
= 0;
1276 if (br32(bp
, B44_DMARX_STAT
) & DMARX_STAT_EMASK
) {
1277 b44_wait_bit(bp
, B44_DMARX_STAT
, DMARX_STAT_SIDLE
,
1280 bw32(bp
, B44_DMARX_CTRL
, 0);
1281 bp
->rx_prod
= bp
->rx_cons
= 0;
1283 ssb_pci_setup(bp
, (bp
->core_unit
== 0 ?
1290 b44_clear_stats(bp
);
1292 /* Make PHY accessible. */
1293 bw32(bp
, B44_MDIO_CTRL
, (MDIO_CTRL_PREAMBLE
|
1294 (0x0d & MDIO_CTRL_MAXF_MASK
)));
1295 br32(bp
, B44_MDIO_CTRL
);
1297 if (!(br32(bp
, B44_DEVCTRL
) & DEVCTRL_IPP
)) {
1298 bw32(bp
, B44_ENET_CTRL
, ENET_CTRL_EPSEL
);
1299 br32(bp
, B44_ENET_CTRL
);
1300 bp
->flags
&= ~B44_FLAG_INTERNAL_PHY
;
1302 u32 val
= br32(bp
, B44_DEVCTRL
);
1304 if (val
& DEVCTRL_EPR
) {
1305 bw32(bp
, B44_DEVCTRL
, (val
& ~DEVCTRL_EPR
));
1306 br32(bp
, B44_DEVCTRL
);
1309 bp
->flags
|= B44_FLAG_INTERNAL_PHY
;
1313 /* bp->lock is held. */
1314 static void b44_halt(struct b44
*bp
)
1316 b44_disable_ints(bp
);
1320 /* bp->lock is held. */
1321 static void __b44_set_mac_addr(struct b44
*bp
)
1323 bw32(bp
, B44_CAM_CTRL
, 0);
1324 if (!(bp
->dev
->flags
& IFF_PROMISC
)) {
1327 __b44_cam_write(bp
, bp
->dev
->dev_addr
, 0);
1328 val
= br32(bp
, B44_CAM_CTRL
);
1329 bw32(bp
, B44_CAM_CTRL
, val
| CAM_CTRL_ENABLE
);
1333 static int b44_set_mac_addr(struct net_device
*dev
, void *p
)
1335 struct b44
*bp
= netdev_priv(dev
);
1336 struct sockaddr
*addr
= p
;
1338 if (netif_running(dev
))
1341 if (!is_valid_ether_addr(addr
->sa_data
))
1344 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
1346 spin_lock_irq(&bp
->lock
);
1347 __b44_set_mac_addr(bp
);
1348 spin_unlock_irq(&bp
->lock
);
1353 /* Called at device open time to get the chip ready for
1354 * packet processing. Invoked with bp->lock held.
1356 static void __b44_set_rx_mode(struct net_device
*);
1357 static void b44_init_hw(struct b44
*bp
)
1365 /* Enable CRC32, set proper LED modes and power on PHY */
1366 bw32(bp
, B44_MAC_CTRL
, MAC_CTRL_CRC32_ENAB
| MAC_CTRL_PHY_LEDCTRL
);
1367 bw32(bp
, B44_RCV_LAZY
, (1 << RCV_LAZY_FC_SHIFT
));
1369 /* This sets the MAC address too. */
1370 __b44_set_rx_mode(bp
->dev
);
1372 /* MTU + eth header + possible VLAN tag + struct rx_header */
1373 bw32(bp
, B44_RXMAXLEN
, bp
->dev
->mtu
+ ETH_HLEN
+ 8 + RX_HEADER_LEN
);
1374 bw32(bp
, B44_TXMAXLEN
, bp
->dev
->mtu
+ ETH_HLEN
+ 8 + RX_HEADER_LEN
);
1376 bw32(bp
, B44_TX_WMARK
, 56); /* XXX magic */
1377 bw32(bp
, B44_DMATX_CTRL
, DMATX_CTRL_ENABLE
);
1378 bw32(bp
, B44_DMATX_ADDR
, bp
->tx_ring_dma
+ bp
->dma_offset
);
1379 bw32(bp
, B44_DMARX_CTRL
, (DMARX_CTRL_ENABLE
|
1380 (bp
->rx_offset
<< DMARX_CTRL_ROSHIFT
)));
1381 bw32(bp
, B44_DMARX_ADDR
, bp
->rx_ring_dma
+ bp
->dma_offset
);
1383 bw32(bp
, B44_DMARX_PTR
, bp
->rx_pending
);
1384 bp
->rx_prod
= bp
->rx_pending
;
1386 bw32(bp
, B44_MIB_CTRL
, MIB_CTRL_CLR_ON_READ
);
1388 val
= br32(bp
, B44_ENET_CTRL
);
1389 bw32(bp
, B44_ENET_CTRL
, (val
| ENET_CTRL_ENABLE
));
1392 static int b44_open(struct net_device
*dev
)
1394 struct b44
*bp
= netdev_priv(dev
);
1397 err
= b44_alloc_consistent(bp
);
1406 err
= request_irq(dev
->irq
, b44_interrupt
, SA_SHIRQ
, dev
->name
, dev
);
1407 if (unlikely(err
< 0)) {
1410 b44_free_consistent(bp
);
1414 init_timer(&bp
->timer
);
1415 bp
->timer
.expires
= jiffies
+ HZ
;
1416 bp
->timer
.data
= (unsigned long) bp
;
1417 bp
->timer
.function
= b44_timer
;
1418 add_timer(&bp
->timer
);
1420 b44_enable_ints(bp
);
1421 netif_start_queue(dev
);
1427 /*static*/ void b44_dump_state(struct b44
*bp
)
1429 u32 val32
, val32_2
, val32_3
, val32_4
, val32_5
;
1432 pci_read_config_word(bp
->pdev
, PCI_STATUS
, &val16
);
1433 printk("DEBUG: PCI status [%04x] \n", val16
);
1438 #ifdef CONFIG_NET_POLL_CONTROLLER
1440 * Polling receive - used by netconsole and other diagnostic tools
1441 * to allow network i/o with interrupts disabled.
1443 static void b44_poll_controller(struct net_device
*dev
)
1445 disable_irq(dev
->irq
);
1446 b44_interrupt(dev
->irq
, dev
, NULL
);
1447 enable_irq(dev
->irq
);
1451 static int b44_close(struct net_device
*dev
)
1453 struct b44
*bp
= netdev_priv(dev
);
1455 netif_stop_queue(dev
);
1457 netif_poll_disable(dev
);
1459 del_timer_sync(&bp
->timer
);
1461 spin_lock_irq(&bp
->lock
);
1468 netif_carrier_off(dev
);
1470 spin_unlock_irq(&bp
->lock
);
1472 free_irq(dev
->irq
, dev
);
1474 netif_poll_enable(dev
);
1476 b44_free_consistent(bp
);
1481 static struct net_device_stats
*b44_get_stats(struct net_device
*dev
)
1483 struct b44
*bp
= netdev_priv(dev
);
1484 struct net_device_stats
*nstat
= &bp
->stats
;
1485 struct b44_hw_stats
*hwstat
= &bp
->hw_stats
;
1487 /* Convert HW stats into netdevice stats. */
1488 nstat
->rx_packets
= hwstat
->rx_pkts
;
1489 nstat
->tx_packets
= hwstat
->tx_pkts
;
1490 nstat
->rx_bytes
= hwstat
->rx_octets
;
1491 nstat
->tx_bytes
= hwstat
->tx_octets
;
1492 nstat
->tx_errors
= (hwstat
->tx_jabber_pkts
+
1493 hwstat
->tx_oversize_pkts
+
1494 hwstat
->tx_underruns
+
1495 hwstat
->tx_excessive_cols
+
1496 hwstat
->tx_late_cols
);
1497 nstat
->multicast
= hwstat
->tx_multicast_pkts
;
1498 nstat
->collisions
= hwstat
->tx_total_cols
;
1500 nstat
->rx_length_errors
= (hwstat
->rx_oversize_pkts
+
1501 hwstat
->rx_undersize
);
1502 nstat
->rx_over_errors
= hwstat
->rx_missed_pkts
;
1503 nstat
->rx_frame_errors
= hwstat
->rx_align_errs
;
1504 nstat
->rx_crc_errors
= hwstat
->rx_crc_errs
;
1505 nstat
->rx_errors
= (hwstat
->rx_jabber_pkts
+
1506 hwstat
->rx_oversize_pkts
+
1507 hwstat
->rx_missed_pkts
+
1508 hwstat
->rx_crc_align_errs
+
1509 hwstat
->rx_undersize
+
1510 hwstat
->rx_crc_errs
+
1511 hwstat
->rx_align_errs
+
1512 hwstat
->rx_symbol_errs
);
1514 nstat
->tx_aborted_errors
= hwstat
->tx_underruns
;
1516 /* Carrier lost counter seems to be broken for some devices */
1517 nstat
->tx_carrier_errors
= hwstat
->tx_carrier_lost
;
1523 static int __b44_load_mcast(struct b44
*bp
, struct net_device
*dev
)
1525 struct dev_mc_list
*mclist
;
1528 num_ents
= min_t(int, dev
->mc_count
, B44_MCAST_TABLE_SIZE
);
1529 mclist
= dev
->mc_list
;
1530 for (i
= 0; mclist
&& i
< num_ents
; i
++, mclist
= mclist
->next
) {
1531 __b44_cam_write(bp
, mclist
->dmi_addr
, i
+ 1);
1536 static void __b44_set_rx_mode(struct net_device
*dev
)
1538 struct b44
*bp
= netdev_priv(dev
);
1541 val
= br32(bp
, B44_RXCONFIG
);
1542 val
&= ~(RXCONFIG_PROMISC
| RXCONFIG_ALLMULTI
);
1543 if (dev
->flags
& IFF_PROMISC
) {
1544 val
|= RXCONFIG_PROMISC
;
1545 bw32(bp
, B44_RXCONFIG
, val
);
1547 unsigned char zero
[6] = {0, 0, 0, 0, 0, 0};
1550 __b44_set_mac_addr(bp
);
1552 if (dev
->flags
& IFF_ALLMULTI
)
1553 val
|= RXCONFIG_ALLMULTI
;
1555 i
= __b44_load_mcast(bp
, dev
);
1557 for (; i
< 64; i
++) {
1558 __b44_cam_write(bp
, zero
, i
);
1560 bw32(bp
, B44_RXCONFIG
, val
);
1561 val
= br32(bp
, B44_CAM_CTRL
);
1562 bw32(bp
, B44_CAM_CTRL
, val
| CAM_CTRL_ENABLE
);
1566 static void b44_set_rx_mode(struct net_device
*dev
)
1568 struct b44
*bp
= netdev_priv(dev
);
1570 spin_lock_irq(&bp
->lock
);
1571 __b44_set_rx_mode(dev
);
1572 spin_unlock_irq(&bp
->lock
);
1575 static u32
b44_get_msglevel(struct net_device
*dev
)
1577 struct b44
*bp
= netdev_priv(dev
);
1578 return bp
->msg_enable
;
1581 static void b44_set_msglevel(struct net_device
*dev
, u32 value
)
1583 struct b44
*bp
= netdev_priv(dev
);
1584 bp
->msg_enable
= value
;
1587 static void b44_get_drvinfo (struct net_device
*dev
, struct ethtool_drvinfo
*info
)
1589 struct b44
*bp
= netdev_priv(dev
);
1590 struct pci_dev
*pci_dev
= bp
->pdev
;
1592 strcpy (info
->driver
, DRV_MODULE_NAME
);
1593 strcpy (info
->version
, DRV_MODULE_VERSION
);
1594 strcpy (info
->bus_info
, pci_name(pci_dev
));
1597 static int b44_nway_reset(struct net_device
*dev
)
1599 struct b44
*bp
= netdev_priv(dev
);
1603 spin_lock_irq(&bp
->lock
);
1604 b44_readphy(bp
, MII_BMCR
, &bmcr
);
1605 b44_readphy(bp
, MII_BMCR
, &bmcr
);
1607 if (bmcr
& BMCR_ANENABLE
) {
1608 b44_writephy(bp
, MII_BMCR
,
1609 bmcr
| BMCR_ANRESTART
);
1612 spin_unlock_irq(&bp
->lock
);
1617 static int b44_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1619 struct b44
*bp
= netdev_priv(dev
);
1621 if (!netif_running(dev
))
1623 cmd
->supported
= (SUPPORTED_Autoneg
);
1624 cmd
->supported
|= (SUPPORTED_100baseT_Half
|
1625 SUPPORTED_100baseT_Full
|
1626 SUPPORTED_10baseT_Half
|
1627 SUPPORTED_10baseT_Full
|
1630 cmd
->advertising
= 0;
1631 if (bp
->flags
& B44_FLAG_ADV_10HALF
)
1632 cmd
->advertising
|= ADVERTISED_10baseT_Half
;
1633 if (bp
->flags
& B44_FLAG_ADV_10FULL
)
1634 cmd
->advertising
|= ADVERTISED_10baseT_Full
;
1635 if (bp
->flags
& B44_FLAG_ADV_100HALF
)
1636 cmd
->advertising
|= ADVERTISED_100baseT_Half
;
1637 if (bp
->flags
& B44_FLAG_ADV_100FULL
)
1638 cmd
->advertising
|= ADVERTISED_100baseT_Full
;
1639 cmd
->advertising
|= ADVERTISED_Pause
| ADVERTISED_Asym_Pause
;
1640 cmd
->speed
= (bp
->flags
& B44_FLAG_100_BASE_T
) ?
1641 SPEED_100
: SPEED_10
;
1642 cmd
->duplex
= (bp
->flags
& B44_FLAG_FULL_DUPLEX
) ?
1643 DUPLEX_FULL
: DUPLEX_HALF
;
1645 cmd
->phy_address
= bp
->phy_addr
;
1646 cmd
->transceiver
= (bp
->flags
& B44_FLAG_INTERNAL_PHY
) ?
1647 XCVR_INTERNAL
: XCVR_EXTERNAL
;
1648 cmd
->autoneg
= (bp
->flags
& B44_FLAG_FORCE_LINK
) ?
1649 AUTONEG_DISABLE
: AUTONEG_ENABLE
;
1655 static int b44_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1657 struct b44
*bp
= netdev_priv(dev
);
1659 if (!netif_running(dev
))
1662 /* We do not support gigabit. */
1663 if (cmd
->autoneg
== AUTONEG_ENABLE
) {
1664 if (cmd
->advertising
&
1665 (ADVERTISED_1000baseT_Half
|
1666 ADVERTISED_1000baseT_Full
))
1668 } else if ((cmd
->speed
!= SPEED_100
&&
1669 cmd
->speed
!= SPEED_10
) ||
1670 (cmd
->duplex
!= DUPLEX_HALF
&&
1671 cmd
->duplex
!= DUPLEX_FULL
)) {
1675 spin_lock_irq(&bp
->lock
);
1677 if (cmd
->autoneg
== AUTONEG_ENABLE
) {
1678 bp
->flags
&= ~B44_FLAG_FORCE_LINK
;
1679 bp
->flags
&= ~(B44_FLAG_ADV_10HALF
|
1680 B44_FLAG_ADV_10FULL
|
1681 B44_FLAG_ADV_100HALF
|
1682 B44_FLAG_ADV_100FULL
);
1683 if (cmd
->advertising
& ADVERTISE_10HALF
)
1684 bp
->flags
|= B44_FLAG_ADV_10HALF
;
1685 if (cmd
->advertising
& ADVERTISE_10FULL
)
1686 bp
->flags
|= B44_FLAG_ADV_10FULL
;
1687 if (cmd
->advertising
& ADVERTISE_100HALF
)
1688 bp
->flags
|= B44_FLAG_ADV_100HALF
;
1689 if (cmd
->advertising
& ADVERTISE_100FULL
)
1690 bp
->flags
|= B44_FLAG_ADV_100FULL
;
1692 bp
->flags
|= B44_FLAG_FORCE_LINK
;
1693 if (cmd
->speed
== SPEED_100
)
1694 bp
->flags
|= B44_FLAG_100_BASE_T
;
1695 if (cmd
->duplex
== DUPLEX_FULL
)
1696 bp
->flags
|= B44_FLAG_FULL_DUPLEX
;
1701 spin_unlock_irq(&bp
->lock
);
1706 static void b44_get_ringparam(struct net_device
*dev
,
1707 struct ethtool_ringparam
*ering
)
1709 struct b44
*bp
= netdev_priv(dev
);
1711 ering
->rx_max_pending
= B44_RX_RING_SIZE
- 1;
1712 ering
->rx_pending
= bp
->rx_pending
;
1714 /* XXX ethtool lacks a tx_max_pending, oops... */
1717 static int b44_set_ringparam(struct net_device
*dev
,
1718 struct ethtool_ringparam
*ering
)
1720 struct b44
*bp
= netdev_priv(dev
);
1722 if ((ering
->rx_pending
> B44_RX_RING_SIZE
- 1) ||
1723 (ering
->rx_mini_pending
!= 0) ||
1724 (ering
->rx_jumbo_pending
!= 0) ||
1725 (ering
->tx_pending
> B44_TX_RING_SIZE
- 1))
1728 spin_lock_irq(&bp
->lock
);
1730 bp
->rx_pending
= ering
->rx_pending
;
1731 bp
->tx_pending
= ering
->tx_pending
;
1736 netif_wake_queue(bp
->dev
);
1737 spin_unlock_irq(&bp
->lock
);
1739 b44_enable_ints(bp
);
1744 static void b44_get_pauseparam(struct net_device
*dev
,
1745 struct ethtool_pauseparam
*epause
)
1747 struct b44
*bp
= netdev_priv(dev
);
1750 (bp
->flags
& B44_FLAG_PAUSE_AUTO
) != 0;
1752 (bp
->flags
& B44_FLAG_RX_PAUSE
) != 0;
1754 (bp
->flags
& B44_FLAG_TX_PAUSE
) != 0;
1757 static int b44_set_pauseparam(struct net_device
*dev
,
1758 struct ethtool_pauseparam
*epause
)
1760 struct b44
*bp
= netdev_priv(dev
);
1762 spin_lock_irq(&bp
->lock
);
1763 if (epause
->autoneg
)
1764 bp
->flags
|= B44_FLAG_PAUSE_AUTO
;
1766 bp
->flags
&= ~B44_FLAG_PAUSE_AUTO
;
1767 if (epause
->rx_pause
)
1768 bp
->flags
|= B44_FLAG_RX_PAUSE
;
1770 bp
->flags
&= ~B44_FLAG_RX_PAUSE
;
1771 if (epause
->tx_pause
)
1772 bp
->flags
|= B44_FLAG_TX_PAUSE
;
1774 bp
->flags
&= ~B44_FLAG_TX_PAUSE
;
1775 if (bp
->flags
& B44_FLAG_PAUSE_AUTO
) {
1780 __b44_set_flow_ctrl(bp
, bp
->flags
);
1782 spin_unlock_irq(&bp
->lock
);
1784 b44_enable_ints(bp
);
1789 static void b44_get_strings(struct net_device
*dev
, u32 stringset
, u8
*data
)
1793 memcpy(data
, *b44_gstrings
, sizeof(b44_gstrings
));
1798 static int b44_get_stats_count(struct net_device
*dev
)
1800 return ARRAY_SIZE(b44_gstrings
);
1803 static void b44_get_ethtool_stats(struct net_device
*dev
,
1804 struct ethtool_stats
*stats
, u64
*data
)
1806 struct b44
*bp
= netdev_priv(dev
);
1807 u32
*val
= &bp
->hw_stats
.tx_good_octets
;
1810 spin_lock_irq(&bp
->lock
);
1812 b44_stats_update(bp
);
1814 for (i
= 0; i
< ARRAY_SIZE(b44_gstrings
); i
++)
1817 spin_unlock_irq(&bp
->lock
);
1820 static struct ethtool_ops b44_ethtool_ops
= {
1821 .get_drvinfo
= b44_get_drvinfo
,
1822 .get_settings
= b44_get_settings
,
1823 .set_settings
= b44_set_settings
,
1824 .nway_reset
= b44_nway_reset
,
1825 .get_link
= ethtool_op_get_link
,
1826 .get_ringparam
= b44_get_ringparam
,
1827 .set_ringparam
= b44_set_ringparam
,
1828 .get_pauseparam
= b44_get_pauseparam
,
1829 .set_pauseparam
= b44_set_pauseparam
,
1830 .get_msglevel
= b44_get_msglevel
,
1831 .set_msglevel
= b44_set_msglevel
,
1832 .get_strings
= b44_get_strings
,
1833 .get_stats_count
= b44_get_stats_count
,
1834 .get_ethtool_stats
= b44_get_ethtool_stats
,
1835 .get_perm_addr
= ethtool_op_get_perm_addr
,
1838 static int b44_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
1840 struct mii_ioctl_data
*data
= if_mii(ifr
);
1841 struct b44
*bp
= netdev_priv(dev
);
1844 if (!netif_running(dev
))
1847 spin_lock_irq(&bp
->lock
);
1848 err
= generic_mii_ioctl(&bp
->mii_if
, data
, cmd
, NULL
);
1849 spin_unlock_irq(&bp
->lock
);
1854 /* Read 128-bytes of EEPROM. */
1855 static int b44_read_eeprom(struct b44
*bp
, u8
*data
)
1858 u16
*ptr
= (u16
*) data
;
1860 for (i
= 0; i
< 128; i
+= 2)
1861 ptr
[i
/ 2] = readw(bp
->regs
+ 4096 + i
);
1866 static int __devinit
b44_get_invariants(struct b44
*bp
)
1871 err
= b44_read_eeprom(bp
, &eeprom
[0]);
1875 bp
->dev
->dev_addr
[0] = eeprom
[79];
1876 bp
->dev
->dev_addr
[1] = eeprom
[78];
1877 bp
->dev
->dev_addr
[2] = eeprom
[81];
1878 bp
->dev
->dev_addr
[3] = eeprom
[80];
1879 bp
->dev
->dev_addr
[4] = eeprom
[83];
1880 bp
->dev
->dev_addr
[5] = eeprom
[82];
1882 if (!is_valid_ether_addr(&bp
->dev
->dev_addr
[0])){
1883 printk(KERN_ERR PFX
"Invalid MAC address found in EEPROM\n");
1887 memcpy(bp
->dev
->perm_addr
, bp
->dev
->dev_addr
, bp
->dev
->addr_len
);
1889 bp
->phy_addr
= eeprom
[90] & 0x1f;
1891 /* With this, plus the rx_header prepended to the data by the
1892 * hardware, we'll land the ethernet header on a 2-byte boundary.
1896 bp
->imask
= IMASK_DEF
;
1898 bp
->core_unit
= ssb_core_unit(bp
);
1899 bp
->dma_offset
= SB_PCI_DMA
;
1901 /* XXX - really required?
1902 bp->flags |= B44_FLAG_BUGGY_TXPTR;
1908 static int __devinit
b44_init_one(struct pci_dev
*pdev
,
1909 const struct pci_device_id
*ent
)
1911 static int b44_version_printed
= 0;
1912 unsigned long b44reg_base
, b44reg_len
;
1913 struct net_device
*dev
;
1917 if (b44_version_printed
++ == 0)
1918 printk(KERN_INFO
"%s", version
);
1920 err
= pci_enable_device(pdev
);
1922 printk(KERN_ERR PFX
"Cannot enable PCI device, "
1927 if (!(pci_resource_flags(pdev
, 0) & IORESOURCE_MEM
)) {
1928 printk(KERN_ERR PFX
"Cannot find proper PCI device "
1929 "base address, aborting.\n");
1931 goto err_out_disable_pdev
;
1934 err
= pci_request_regions(pdev
, DRV_MODULE_NAME
);
1936 printk(KERN_ERR PFX
"Cannot obtain PCI resources, "
1938 goto err_out_disable_pdev
;
1941 pci_set_master(pdev
);
1943 err
= pci_set_dma_mask(pdev
, (u64
) B44_DMA_MASK
);
1945 printk(KERN_ERR PFX
"No usable DMA configuration, "
1947 goto err_out_free_res
;
1950 err
= pci_set_consistent_dma_mask(pdev
, (u64
) B44_DMA_MASK
);
1952 printk(KERN_ERR PFX
"No usable DMA configuration, "
1954 goto err_out_free_res
;
1957 b44reg_base
= pci_resource_start(pdev
, 0);
1958 b44reg_len
= pci_resource_len(pdev
, 0);
1960 dev
= alloc_etherdev(sizeof(*bp
));
1962 printk(KERN_ERR PFX
"Etherdev alloc failed, aborting.\n");
1964 goto err_out_free_res
;
1967 SET_MODULE_OWNER(dev
);
1968 SET_NETDEV_DEV(dev
,&pdev
->dev
);
1970 /* No interesting netdevice features in this card... */
1973 bp
= netdev_priv(dev
);
1977 bp
->msg_enable
= netif_msg_init(b44_debug
, B44_DEF_MSG_ENABLE
);
1979 spin_lock_init(&bp
->lock
);
1981 bp
->regs
= ioremap(b44reg_base
, b44reg_len
);
1982 if (bp
->regs
== 0UL) {
1983 printk(KERN_ERR PFX
"Cannot map device registers, "
1986 goto err_out_free_dev
;
1989 bp
->rx_pending
= B44_DEF_RX_RING_PENDING
;
1990 bp
->tx_pending
= B44_DEF_TX_RING_PENDING
;
1992 dev
->open
= b44_open
;
1993 dev
->stop
= b44_close
;
1994 dev
->hard_start_xmit
= b44_start_xmit
;
1995 dev
->get_stats
= b44_get_stats
;
1996 dev
->set_multicast_list
= b44_set_rx_mode
;
1997 dev
->set_mac_address
= b44_set_mac_addr
;
1998 dev
->do_ioctl
= b44_ioctl
;
1999 dev
->tx_timeout
= b44_tx_timeout
;
2000 dev
->poll
= b44_poll
;
2002 dev
->watchdog_timeo
= B44_TX_TIMEOUT
;
2003 #ifdef CONFIG_NET_POLL_CONTROLLER
2004 dev
->poll_controller
= b44_poll_controller
;
2006 dev
->change_mtu
= b44_change_mtu
;
2007 dev
->irq
= pdev
->irq
;
2008 SET_ETHTOOL_OPS(dev
, &b44_ethtool_ops
);
2010 netif_carrier_off(dev
);
2012 err
= b44_get_invariants(bp
);
2014 printk(KERN_ERR PFX
"Problem fetching invariants of chip, "
2016 goto err_out_iounmap
;
2019 bp
->mii_if
.dev
= dev
;
2020 bp
->mii_if
.mdio_read
= b44_mii_read
;
2021 bp
->mii_if
.mdio_write
= b44_mii_write
;
2022 bp
->mii_if
.phy_id
= bp
->phy_addr
;
2023 bp
->mii_if
.phy_id_mask
= 0x1f;
2024 bp
->mii_if
.reg_num_mask
= 0x1f;
2026 /* By default, advertise all speed/duplex settings. */
2027 bp
->flags
|= (B44_FLAG_ADV_10HALF
| B44_FLAG_ADV_10FULL
|
2028 B44_FLAG_ADV_100HALF
| B44_FLAG_ADV_100FULL
);
2030 /* By default, auto-negotiate PAUSE. */
2031 bp
->flags
|= B44_FLAG_PAUSE_AUTO
;
2033 err
= register_netdev(dev
);
2035 printk(KERN_ERR PFX
"Cannot register net device, "
2037 goto err_out_iounmap
;
2040 pci_set_drvdata(pdev
, dev
);
2042 pci_save_state(bp
->pdev
);
2044 /* Chip reset provides power to the b44 MAC & PCI cores, which
2045 * is necessary for MAC register access.
2049 printk(KERN_INFO
"%s: Broadcom 4400 10/100BaseT Ethernet ", dev
->name
);
2050 for (i
= 0; i
< 6; i
++)
2051 printk("%2.2x%c", dev
->dev_addr
[i
],
2052 i
== 5 ? '\n' : ':');
2063 pci_release_regions(pdev
);
2065 err_out_disable_pdev
:
2066 pci_disable_device(pdev
);
2067 pci_set_drvdata(pdev
, NULL
);
2071 static void __devexit
b44_remove_one(struct pci_dev
*pdev
)
2073 struct net_device
*dev
= pci_get_drvdata(pdev
);
2074 struct b44
*bp
= netdev_priv(dev
);
2076 unregister_netdev(dev
);
2079 pci_release_regions(pdev
);
2080 pci_disable_device(pdev
);
2081 pci_set_drvdata(pdev
, NULL
);
2084 static int b44_suspend(struct pci_dev
*pdev
, pm_message_t state
)
2086 struct net_device
*dev
= pci_get_drvdata(pdev
);
2087 struct b44
*bp
= netdev_priv(dev
);
2089 if (!netif_running(dev
))
2092 del_timer_sync(&bp
->timer
);
2094 spin_lock_irq(&bp
->lock
);
2097 netif_carrier_off(bp
->dev
);
2098 netif_device_detach(bp
->dev
);
2101 spin_unlock_irq(&bp
->lock
);
2103 free_irq(dev
->irq
, dev
);
2104 pci_disable_device(pdev
);
2108 static int b44_resume(struct pci_dev
*pdev
)
2110 struct net_device
*dev
= pci_get_drvdata(pdev
);
2111 struct b44
*bp
= netdev_priv(dev
);
2113 pci_restore_state(pdev
);
2114 pci_enable_device(pdev
);
2115 pci_set_master(pdev
);
2117 if (!netif_running(dev
))
2120 if (request_irq(dev
->irq
, b44_interrupt
, SA_SHIRQ
, dev
->name
, dev
))
2121 printk(KERN_ERR PFX
"%s: request_irq failed\n", dev
->name
);
2123 spin_lock_irq(&bp
->lock
);
2127 netif_device_attach(bp
->dev
);
2128 spin_unlock_irq(&bp
->lock
);
2130 bp
->timer
.expires
= jiffies
+ HZ
;
2131 add_timer(&bp
->timer
);
2133 b44_enable_ints(bp
);
2134 netif_wake_queue(dev
);
2138 static struct pci_driver b44_driver
= {
2139 .name
= DRV_MODULE_NAME
,
2140 .id_table
= b44_pci_tbl
,
2141 .probe
= b44_init_one
,
2142 .remove
= __devexit_p(b44_remove_one
),
2143 .suspend
= b44_suspend
,
2144 .resume
= b44_resume
,
2147 static int __init
b44_init(void)
2149 unsigned int dma_desc_align_size
= dma_get_cache_alignment();
2151 /* Setup paramaters for syncing RX/TX DMA descriptors */
2152 dma_desc_align_mask
= ~(dma_desc_align_size
- 1);
2153 dma_desc_sync_size
= max_t(unsigned int, dma_desc_align_size
, sizeof(struct dma_desc
));
2155 return pci_module_init(&b44_driver
);
2158 static void __exit
b44_cleanup(void)
2160 pci_unregister_driver(&b44_driver
);
2163 module_init(b44_init
);
2164 module_exit(b44_cleanup
);