drivers/char/rio/board.h

   1 /*
   2 ** -----------------------------------------------------------------------------
   3 **
   4 **  Perle Specialix driver for Linux
   5 **  Ported from existing RIO Driver for SCO sources.
   6  *
   7  *  (C) 1990 - 2000 Specialix International Ltd., Byfleet, Surrey, UK.
   8  *
   9  *      This program is free software; you can redistribute it and/or modify
  10  *      it under the terms of the GNU General Public License as published by
  11  *      the Free Software Foundation; either version 2 of the License, or
  12  *      (at your option) any later version.
  13  *
  14  *      This program is distributed in the hope that it will be useful,
  15  *      but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *      GNU General Public License for more details.
  18  *
  19  *      You should have received a copy of the GNU General Public License
  20  *      along with this program; if not, write to the Free Software
  21  *      Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22 **
  23 **      Module          : board.h
  24 **      SID             : 1.2
  25 **      Last Modified   : 11/6/98 11:34:07
  26 **      Retrieved       : 11/6/98 11:34:20
  27 **
  28 **  ident @(#)board.h   1.2
  29 **
  30 ** -----------------------------------------------------------------------------
  31 */
  32
  33 #ifndef __rio_board_h__
  34 #define __rio_board_h__
  35
  36 #ifdef SCCS_LABELS
  37 static char *_board_h_sccs_ = "@(#)board.h      1.2";
  38 #endif
  39
  40 /*
  41 ** board.h contains the definitions for the *hardware* of the host cards.
  42 ** It describes the memory overlay for the dual port RAM area.
  43 */
  44
  45 #define DP_SRAM1_SIZE   0x7C00
  46 #define DP_SRAM2_SIZE   0x0200
  47 #define DP_SRAM3_SIZE   0x7000
  48 #define DP_SCRATCH_SIZE 0x1000
  49 #define DP_PARMMAP_ADDR 0x01FE  /* offset into SRAM2 */
  50 #define DP_STARTUP_ADDR 0x01F8  /* offset into SRAM2 */
  51
  52 /*
  53 **      The shape of the Host Control area, at offset 0x7C00, Write Only
  54 */
  55 struct s_Ctrl {
  56         BYTE DpCtl;             /* 7C00 */
  57         BYTE Dp_Unused2_[127];
  58         BYTE DpIntSet;          /* 7C80 */
  59         BYTE Dp_Unused3_[127];
  60         BYTE DpTpuReset;        /* 7D00 */
  61         BYTE Dp_Unused4_[127];
  62         BYTE DpIntReset;        /* 7D80 */
  63         BYTE Dp_Unused5_[127];
  64 };
  65
  66 /*
  67 ** The PROM data area on the host (0x7C00), Read Only
  68 */
  69 struct s_Prom {
  70         WORD DpSlxCode[2];
  71         WORD DpRev;
  72         WORD Dp_Unused6_;
  73         WORD DpUniq[4];
  74         WORD DpJahre;
  75         WORD DpWoche;
  76         WORD DpHwFeature[5];
  77         WORD DpOemId;
  78         WORD DpSiggy[16];
  79 };
  80
  81 /*
  82 ** Union of the Ctrl and Prom areas
  83 */
  84 union u_CtrlProm {              /* This is the control/PROM area (0x7C00) */
  85         struct s_Ctrl DpCtrl;
  86         struct s_Prom DpProm;
  87 };
  88
  89 /*
  90 ** The top end of memory!
  91 */
  92 struct s_ParmMapS {             /* Area containing Parm Map Pointer */
  93         BYTE Dp_Unused8_[DP_PARMMAP_ADDR];
  94         WORD DpParmMapAd;
  95 };
  96
  97 struct s_StartUpS {
  98         BYTE Dp_Unused9_[DP_STARTUP_ADDR];
  99         BYTE Dp_LongJump[0x4];
 100         BYTE Dp_Unused10_[2];
 101         BYTE Dp_ShortJump[0x2];
 102 };
 103
 104 union u_Sram2ParmMap {          /* This is the top of memory (0x7E00-0x7FFF) */
 105         BYTE DpSramMem[DP_SRAM2_SIZE];
 106         struct s_ParmMapS DpParmMapS;
 107         struct s_StartUpS DpStartUpS;
 108 };
 109
 110 /*
 111 **      This is the DP RAM overlay.
 112 */
 113 struct DpRam {
 114         BYTE DpSram1[DP_SRAM1_SIZE];    /* 0000 - 7BFF */
 115         union u_CtrlProm DpCtrlProm;    /* 7C00 - 7DFF */
 116         union u_Sram2ParmMap DpSram2ParmMap;    /* 7E00 - 7FFF */
 117         BYTE DpScratch[DP_SCRATCH_SIZE];        /* 8000 - 8FFF */
 118         BYTE DpSram3[DP_SRAM3_SIZE];    /* 9000 - FFFF */
 119 };
 120
 121 #define DpControl       DpCtrlProm.DpCtrl.DpCtl
 122 #define DpSetInt        DpCtrlProm.DpCtrl.DpIntSet
 123 #define DpResetTpu      DpCtrlProm.DpCtrl.DpTpuReset
 124 #define DpResetInt      DpCtrlProm.DpCtrl.DpIntReset
 125
 126 #define DpSlx           DpCtrlProm.DpProm.DpSlxCode
 127 #define DpRevision      DpCtrlProm.DpProm.DpRev
 128 #define DpUnique        DpCtrlProm.DpProm.DpUniq
 129 #define DpYear          DpCtrlProm.DpProm.DpJahre
 130 #define DpWeek          DpCtrlProm.DpProm.DpWoche
 131 #define DpSignature     DpCtrlProm.DpProm.DpSiggy
 132
 133 #define DpParmMapR      DpSram2ParmMap.DpParmMapS.DpParmMapAd
 134 #define DpSram2         DpSram2ParmMap.DpSramMem
 135
 136 #endif