drivers/char/rio/cirrus.h

   1 /****************************************************************************
   2  *******                                                              *******
   3  *******                CIRRUS.H                                      *******
   4  *******                                                              *******
   5  ****************************************************************************
   6
   7  Author  : Jeremy Rolls
   8  Date    : 3 Aug 1990
   9
  10  *
  11  *  (C) 1990 - 2000 Specialix International Ltd., Byfleet, Surrey, UK.
  12  *
  13  *      This program is free software; you can redistribute it and/or modify
  14  *      it under the terms of the GNU General Public License as published by
  15  *      the Free Software Foundation; either version 2 of the License, or
  16  *      (at your option) any later version.
  17  *
  18  *      This program is distributed in the hope that it will be useful,
  19  *      but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  *      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  *      GNU General Public License for more details.
  22  *
  23  *      You should have received a copy of the GNU General Public License
  24  *      along with this program; if not, write to the Free Software
  25  *      Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  26
  27  Version : 0.01
  28
  29
  30                             Mods
  31  ----------------------------------------------------------------------------
  32   Date     By                Description
  33  ----------------------------------------------------------------------------
  34
  35  ***************************************************************************/
  36
  37 #ifndef _cirrus_h
  38 #ifndef lint
  39 /* static char* _cirrus_h_sccs = "@(#)cirrus.h  1.16"; */
  40 #endif
  41 #define _cirrus_h 1
  42
  43
  44
  45 /* Bit fields for particular registers */
  46
  47 /* GCR */
  48 #define GCR_SERIAL      0x00    /* Configure as serial channel */
  49 #define GCR_PARALLEL    0x80    /* Configure as parallel channel */
  50
  51 /* RDSR - when status read from FIFO */
  52 #define RDSR_BREAK              0x08    /* Break received */
  53 #define RDSR_TIMEOUT            0x80    /* No new data timeout */
  54 #define RDSR_SC1                0x10    /* Special char 1 (tx XON) matched */
  55 #define RDSR_SC2                0x20    /* Special char 2 (tx XOFF) matched */
  56 #define RDSR_SC12_MASK          0x30    /* Mask for special chars 1 and 2 */
  57
  58 /* PPR */
  59 #define PPR_DEFAULT     0x31    /* Default value - for a 25Mhz clock gives
  60                                    a timeout period of 1ms */
  61
  62 /* LIVR */
  63 #define LIVR_EXCEPTION  0x07    /* Receive exception interrupt */
  64
  65 /* CCR */
  66 #define CCR_RESET       0x80    /* Reset channel */
  67 #define CCR_CHANGE      0x4e    /* COR's have changed - NB always change all
  68                                    COR's */
  69 #define CCR_WFLUSH      0x82    /* Flush transmit FIFO and TSR / THR */
  70
  71 #define CCR_SENDSC1     0x21    /* Send special character one */
  72 #define CCR_SENDSC2     0x22    /* Send special character two */
  73 #define CCR_SENDSC3     0x23    /* Send special character three */
  74 #define CCR_SENDSC4     0x24    /* Send special character four */
  75
  76 #define CCR_TENABLE     0x18    /* Enable transmitter */
  77 #define CCR_TDISABLE    0x14    /* Disable transmitter */
  78 #define CCR_RENABLE     0x12    /* Enable receiver */
  79 #define CCR_RDISABLE    0x11    /* Disable receiver */
  80
  81 #define CCR_READY       0x00    /* CCR is ready for another command */
  82
  83 /* CCSR */
  84 #define CCSR_TXENABLE   0x08    /* Transmitter enable */
  85 #define CCSR_RXENABLE   0x80    /* Receiver enable */
  86 #define CCSR_TXFLOWOFF  0x04    /* Transmit flow off */
  87 #define CCSR_TXFLOWON   0x02    /* Transmit flow on */
  88
  89 /* SVRR */
  90 #define SVRR_RECEIVE    0x01    /* Receive interrupt pending */
  91 #define SVRR_TRANSMIT   0x02    /* Transmit interrupt pending */
  92 #define SVRR_MODEM      0x04    /* Modem interrupt pending */
  93
  94 /* CAR */
  95 #define CAR_PORTS       0x03    /* Bit fields for ports */
  96
  97 /* IER */
  98 #define IER_MODEM       0x80    /* Change in modem status */
  99 #define IER_RECEIVE     0x10    /* Good data / data exception */
 100 #define IER_TRANSMITR   0x04    /* Transmit ready (FIFO empty) */
 101 #define IER_TRANSMITE   0x02    /* Transmit empty */
 102 #define IER_TIMEOUT     0x01    /* Timeout on no data */
 103
 104 #define IER_DEFAULT     0x94    /* Default values */
 105 #define IER_PARALLEL    0x84    /* Default for Parallel */
 106 #define IER_EMPTY       0x92    /* Transmitter empty rather than ready */
 107
 108 /* COR1 - Driver only */
 109 #define COR1_INPCK      0x10    /* Check parity of received characters */
 110
 111 /* COR1 - driver and RTA */
 112 #define COR1_ODD        0x80    /* Odd parity */
 113 #define COR1_EVEN       0x00    /* Even parity */
 114 #define COR1_NOP        0x00    /* No parity */
 115 #define COR1_FORCE      0x20    /* Force parity */
 116 #define COR1_NORMAL     0x40    /* With parity */
 117 #define COR1_1STOP      0x00    /* 1 stop bit */
 118 #define COR1_15STOP     0x04    /* 1.5 stop bits */
 119 #define COR1_2STOP      0x08    /* 2 stop bits */
 120 #define COR1_5BITS      0x00    /* 5 data bits */
 121 #define COR1_6BITS      0x01    /* 6 data bits */
 122 #define COR1_7BITS      0x02    /* 7 data bits */
 123 #define COR1_8BITS      0x03    /* 8 data bits */
 124
 125 #define COR1_HOST       0xef    /* Safe host bits */
 126
 127 /* RTA only */
 128 #define COR1_CINPCK     0x00    /* Check parity of received characters */
 129 #define COR1_CNINPCK    0x10    /* Don't check parity */
 130
 131 /* COR2 bits for both RTA and driver use */
 132 #define COR2_IXANY      0x80    /* IXANY - any character is XON */
 133 #define COR2_IXON       0x40    /* IXON - enable tx soft flowcontrol */
 134 #define COR2_RTSFLOW    0x02    /* Enable tx hardware flow control */
 135
 136 /* Additional driver bits */
 137 #define COR2_HUPCL      0x20    /* Hang up on close */
 138 #define COR2_CTSFLOW    0x04    /* Enable rx hardware flow control */
 139 #define COR2_IXOFF      0x01    /* Enable rx software flow control */
 140 #define COR2_DTRFLOW    0x08    /* Enable tx hardware flow control */
 141
 142 /* RTA use only */
 143 #define COR2_ETC        0x20    /* Embedded transmit options */
 144 #define COR2_LOCAL      0x10    /* Local loopback mode */
 145 #define COR2_REMOTE     0x08    /* Remote loopback mode */
 146 #define COR2_HOST       0xc2    /* Safe host bits */
 147
 148 /* COR3 - RTA use only */
 149 #define COR3_SCDRNG     0x80    /* Enable special char detect for range */
 150 #define COR3_SCD34      0x40    /* Special character detect for SCHR's 3 + 4 */
 151 #define COR3_FCT        0x20    /* Flow control transparency */
 152 #define COR3_SCD12      0x10    /* Special character detect for SCHR's 1 + 2 */
 153 #define COR3_FIFO12     0x0c    /* 12 chars for receive FIFO threshold */
 154 #define COR3_FIFO10     0x0a    /* 10 chars for receive FIFO threshold */
 155 #define COR3_FIFO8      0x08    /* 8 chars for receive FIFO threshold */
 156 #define COR3_FIFO6      0x06    /* 6 chars for receive FIFO threshold */
 157
 158 #define COR3_THRESHOLD  COR3_FIFO8      /* MUST BE LESS THAN MCOR_THRESHOLD */
 159
 160 #define COR3_DEFAULT    (COR3_FCT | COR3_THRESHOLD)
 161                                 /* Default bits for COR3 */
 162
 163 /* COR4 driver and RTA use */
 164 #define COR4_IGNCR      0x80    /* Throw away CR's on input */
 165 #define COR4_ICRNL      0x40    /* Map CR -> NL on input */
 166 #define COR4_INLCR      0x20    /* Map NL -> CR on input */
 167 #define COR4_IGNBRK     0x10    /* Ignore Break */
 168 #define COR4_NBRKINT    0x08    /* No interrupt on break (-BRKINT) */
 169 #define COR4_RAISEMOD   0x01    /* Raise modem output lines on non-zero baud */
 170
 171
 172 /* COR4 driver only */
 173 #define COR4_IGNPAR     0x04    /* IGNPAR (ignore characters with errors) */
 174 #define COR4_PARMRK     0x02    /* PARMRK */
 175
 176 #define COR4_HOST       0xf8    /* Safe host bits */
 177
 178 /* COR4 RTA only */
 179 #define COR4_CIGNPAR    0x02    /* Thrown away bad characters */
 180 #define COR4_CPARMRK    0x04    /* PARMRK characters */
 181 #define COR4_CNPARMRK   0x03    /* Don't PARMRK */
 182
 183 /* COR5 driver and RTA use */
 184 #define COR5_ISTRIP     0x80    /* Strip input chars to 7 bits */
 185 #define COR5_LNE        0x40    /* Enable LNEXT processing */
 186 #define COR5_CMOE       0x20    /* Match good and errored characters */
 187 #define COR5_ONLCR      0x02    /* NL -> CR NL on output */
 188 #define COR5_OCRNL      0x01    /* CR -> NL on output */
 189
 190 /*
 191 ** Spare bits - these are not used in the CIRRUS registers, so we use
 192 ** them to set various other features.
 193 */
 194 /*
 195 ** tstop and tbusy indication
 196 */
 197 #define COR5_TSTATE_ON  0x08    /* Turn on monitoring of tbusy and tstop */
 198 #define COR5_TSTATE_OFF 0x04    /* Turn off monitoring of tbusy and tstop */
 199 /*
 200 ** TAB3
 201 */
 202 #define COR5_TAB3       0x10    /* TAB3 mode */
 203
 204 #define COR5_HOST       0xc3    /* Safe host bits */
 205
 206 /* CCSR */
 207 #define CCSR_TXFLOFF    0x04    /* Tx is xoffed */
 208
 209 /* MSVR1 */
 210 /* NB. DTR / CD swapped from Cirrus spec as the pins are also reversed on the
 211    RTA. This is because otherwise DCD would get lost on the 1 parallel / 3
 212    serial option.
 213 */
 214 #define MSVR1_CD        0x80    /* CD (DSR on Cirrus) */
 215 #define MSVR1_RTS       0x40    /* RTS (CTS on Cirrus) */
 216 #define MSVR1_RI        0x20    /* RI */
 217 #define MSVR1_DTR       0x10    /* DTR (CD on Cirrus) */
 218 #define MSVR1_CTS       0x01    /* CTS output pin (RTS on Cirrus) */
 219 /* Next two used to indicate state of tbusy and tstop to driver */
 220 #define MSVR1_TSTOP     0x08    /* Set if port flow controlled */
 221 #define MSVR1_TEMPTY    0x04    /* Set if port tx buffer empty */
 222
 223 #define MSVR1_HOST      0xf3    /* The bits the host wants */
 224
 225 /* MSVR2 */
 226 #define MSVR2_DSR       0x02    /* DSR output pin (DTR on Cirrus) */
 227
 228 /* MCOR */
 229 #define MCOR_CD         0x80    /* CD (DSR on Cirrus) */
 230 #define MCOR_RTS        0x40    /* RTS (CTS on Cirrus) */
 231 #define MCOR_RI         0x20    /* RI */
 232 #define MCOR_DTR        0x10    /* DTR (CD on Cirrus) */
 233
 234 #define MCOR_DEFAULT    (MCOR_CD | MCOR_RTS | MCOR_RI | MCOR_DTR)
 235 #define MCOR_FULLMODEM  MCOR_DEFAULT
 236 #define MCOR_RJ45       (MCOR_CD | MCOR_RTS | MCOR_DTR)
 237 #define MCOR_RESTRICTED (MCOR_CD | MCOR_RTS)
 238
 239 /* More MCOR - H/W Handshake (flowcontrol) stuff */
 240 #define MCOR_THRESH8    0x08    /* eight characters then we stop */
 241 #define MCOR_THRESH9    0x09    /* nine characters then we stop */
 242 #define MCOR_THRESH10   0x0A    /* ten characters then we stop */
 243 #define MCOR_THRESH11   0x0B    /* eleven characters then we stop */
 244
 245 #define MCOR_THRESHBITS 0x0F    /* mask for ANDing out the above */
 246
 247 #define MCOR_THRESHOLD  MCOR_THRESH9    /* MUST BE GREATER THAN COR3_THRESHOLD */
 248
 249
 250 /* RTPR */
 251 #define RTPR_DEFAULT    0x02    /* Default */
 252
 253
 254 /* Defines for the subscripts of a CONFIG packet */
 255 #define CONFIG_COR1     1       /* Option register 1 */
 256 #define CONFIG_COR2     2       /* Option register 2 */
 257 #define CONFIG_COR4     3       /* Option register 4 */
 258 #define CONFIG_COR5     4       /* Option register 5 */
 259 #define CONFIG_TXXON    5       /* Tx XON character */
 260 #define CONFIG_TXXOFF   6       /* Tx XOFF character */
 261 #define CONFIG_RXXON    7       /* Rx XON character */
 262 #define CONFIG_RXXOFF   8       /* Rx XOFF character */
 263 #define CONFIG_LNEXT    9       /* LNEXT character */
 264 #define CONFIG_TXBAUD   10      /* Tx baud rate */
 265 #define CONFIG_RXBAUD   11      /* Rx baud rate */
 266
 267 /* Port status stuff */
 268 #define IDLE_CLOSED     0       /* Closed */
 269 #define IDLE_OPEN       1       /* Idle open */
 270 #define IDLE_BREAK      2       /* Idle on break */
 271
 272 /* Subscript of MODEM STATUS packet */
 273 #define MODEM_VALUE     3       /* Current values of handshake pins */
 274 /* Subscript of SBREAK packet */
 275 #define BREAK_LENGTH    1       /* Length of a break in slices of 0.01 seconds
 276                                    0 = stay on break until an EBREAK command
 277                                    is sent */
 278
 279
 280 #define PRE_EMPTIVE     0x80    /* Pre-emptive bit in command field */
 281
 282 /* Packet types going from Host to remote - with the exception of OPEN, MOPEN,
 283    CONFIG, SBREAK and MEMDUMP the remaining bytes of the data array will not
 284    be used
 285 */
 286 #define OPEN            0x00    /* Open a port */
 287 #define CONFIG          0x01    /* Configure a port */
 288 #define MOPEN           0x02    /* Modem open (block for DCD) */
 289 #define CLOSE           0x03    /* Close a port */
 290 #define WFLUSH          (0x04 | PRE_EMPTIVE)    /* Write flush */
 291 #define RFLUSH          (0x05 | PRE_EMPTIVE)    /* Read flush */
 292 #define RESUME          (0x06 | PRE_EMPTIVE)    /* Resume if xoffed */
 293 #define SBREAK          0x07    /* Start break */
 294 #define EBREAK          0x08    /* End break */
 295 #define SUSPEND         (0x09 | PRE_EMPTIVE)    /* Susp op (behave as tho xoffed) */
 296 #define FCLOSE          (0x0a | PRE_EMPTIVE)    /* Force close */
 297 #define XPRINT          0x0b    /* Xprint packet */
 298 #define MBIS            (0x0c | PRE_EMPTIVE)    /* Set modem lines */
 299 #define MBIC            (0x0d | PRE_EMPTIVE)    /* Clear modem lines */
 300 #define MSET            (0x0e | PRE_EMPTIVE)    /* Set modem lines */
 301 #define PCLOSE          0x0f    /* Pseudo close - Leaves rx/tx enabled */
 302 #define MGET            (0x10 | PRE_EMPTIVE)    /* Force update of modem status */
 303 #define MEMDUMP         (0x11 | PRE_EMPTIVE)    /* Send back mem from addr supplied */
 304 #define READ_REGISTER   (0x12 | PRE_EMPTIVE)    /* Read CD1400 register (debug) */
 305
 306 /* "Command" packets going from remote to host COMPLETE and MODEM_STATUS
 307    use data[4] / data[3] to indicate current state and modem status respectively
 308 */
 309
 310 #define COMPLETE        (0x20 | PRE_EMPTIVE)
 311                                 /* Command complete */
 312 #define BREAK_RECEIVED  (0x21 | PRE_EMPTIVE)
 313                                 /* Break received */
 314 #define MODEM_STATUS    (0x22 | PRE_EMPTIVE)
 315                                 /* Change in modem status */
 316
 317 /* "Command" packet that could go either way - handshake wake-up */
 318 #define HANDSHAKE       (0x23 | PRE_EMPTIVE)
 319                                 /* Wake-up to HOST / RTA */
 320
 321 #endif