[NETFILTER]: Move ip6_masked_addrcmp to include/net/ipv6.h
[linux-2.6/verdex.git] / drivers / i2c / busses / i2c-amd756.c
blob1750dedaf4b5620a553455778efd62d3bf9ca2fd
1 /*
2 amd756.c - Part of lm_sensors, Linux kernel modules for hardware
3 monitoring
5 Copyright (c) 1999-2002 Merlin Hughes <merlin@merlin.org>
7 Shamelessly ripped from i2c-piix4.c:
9 Copyright (c) 1998, 1999 Frodo Looijaard <frodol@dds.nl> and
10 Philip Edelbrock <phil@netroedge.com>
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software
24 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
28 2002-04-08: Added nForce support. (Csaba Halasz)
29 2002-10-03: Fixed nForce PnP I/O port. (Michael Steil)
30 2002-12-28: Rewritten into something that resembles a Linux driver (hch)
31 2003-11-29: Added back AMD8111 removed by the previous rewrite.
32 (Philip Pokorny)
36 Supports AMD756, AMD766, AMD768, AMD8111 and nVidia nForce
37 Note: we assume there can only be one device, with one SMBus interface.
40 #include <linux/module.h>
41 #include <linux/pci.h>
42 #include <linux/kernel.h>
43 #include <linux/delay.h>
44 #include <linux/stddef.h>
45 #include <linux/sched.h>
46 #include <linux/ioport.h>
47 #include <linux/i2c.h>
48 #include <linux/init.h>
49 #include <asm/io.h>
51 /* AMD756 SMBus address offsets */
52 #define SMB_ADDR_OFFSET 0xE0
53 #define SMB_IOSIZE 16
54 #define SMB_GLOBAL_STATUS (0x0 + amd756_ioport)
55 #define SMB_GLOBAL_ENABLE (0x2 + amd756_ioport)
56 #define SMB_HOST_ADDRESS (0x4 + amd756_ioport)
57 #define SMB_HOST_DATA (0x6 + amd756_ioport)
58 #define SMB_HOST_COMMAND (0x8 + amd756_ioport)
59 #define SMB_HOST_BLOCK_DATA (0x9 + amd756_ioport)
60 #define SMB_HAS_DATA (0xA + amd756_ioport)
61 #define SMB_HAS_DEVICE_ADDRESS (0xC + amd756_ioport)
62 #define SMB_HAS_HOST_ADDRESS (0xE + amd756_ioport)
63 #define SMB_SNOOP_ADDRESS (0xF + amd756_ioport)
65 /* PCI Address Constants */
67 /* address of I/O space */
68 #define SMBBA 0x058 /* mh */
69 #define SMBBANFORCE 0x014
71 /* general configuration */
72 #define SMBGCFG 0x041 /* mh */
74 /* silicon revision code */
75 #define SMBREV 0x008
77 /* Other settings */
78 #define MAX_TIMEOUT 500
80 /* AMD756 constants */
81 #define AMD756_QUICK 0x00
82 #define AMD756_BYTE 0x01
83 #define AMD756_BYTE_DATA 0x02
84 #define AMD756_WORD_DATA 0x03
85 #define AMD756_PROCESS_CALL 0x04
86 #define AMD756_BLOCK_DATA 0x05
88 static struct pci_driver amd756_driver;
89 static unsigned short amd756_ioport;
91 /*
92 SMBUS event = I/O 28-29 bit 11
93 see E0 for the status bits and enabled in E2
96 #define GS_ABRT_STS (1 << 0)
97 #define GS_COL_STS (1 << 1)
98 #define GS_PRERR_STS (1 << 2)
99 #define GS_HST_STS (1 << 3)
100 #define GS_HCYC_STS (1 << 4)
101 #define GS_TO_STS (1 << 5)
102 #define GS_SMB_STS (1 << 11)
104 #define GS_CLEAR_STS (GS_ABRT_STS | GS_COL_STS | GS_PRERR_STS | \
105 GS_HCYC_STS | GS_TO_STS )
107 #define GE_CYC_TYPE_MASK (7)
108 #define GE_HOST_STC (1 << 3)
109 #define GE_ABORT (1 << 5)
112 static int amd756_transaction(struct i2c_adapter *adap)
114 int temp;
115 int result = 0;
116 int timeout = 0;
118 dev_dbg(&adap->dev, "Transaction (pre): GS=%04x, GE=%04x, ADD=%04x, "
119 "DAT=%04x\n", inw_p(SMB_GLOBAL_STATUS),
120 inw_p(SMB_GLOBAL_ENABLE), inw_p(SMB_HOST_ADDRESS),
121 inb_p(SMB_HOST_DATA));
123 /* Make sure the SMBus host is ready to start transmitting */
124 if ((temp = inw_p(SMB_GLOBAL_STATUS)) & (GS_HST_STS | GS_SMB_STS)) {
125 dev_dbg(&adap->dev, "SMBus busy (%04x). Waiting...\n", temp);
126 do {
127 msleep(1);
128 temp = inw_p(SMB_GLOBAL_STATUS);
129 } while ((temp & (GS_HST_STS | GS_SMB_STS)) &&
130 (timeout++ < MAX_TIMEOUT));
131 /* If the SMBus is still busy, we give up */
132 if (timeout >= MAX_TIMEOUT) {
133 dev_dbg(&adap->dev, "Busy wait timeout (%04x)\n", temp);
134 goto abort;
136 timeout = 0;
139 /* start the transaction by setting the start bit */
140 outw_p(inw(SMB_GLOBAL_ENABLE) | GE_HOST_STC, SMB_GLOBAL_ENABLE);
142 /* We will always wait for a fraction of a second! */
143 do {
144 msleep(1);
145 temp = inw_p(SMB_GLOBAL_STATUS);
146 } while ((temp & GS_HST_STS) && (timeout++ < MAX_TIMEOUT));
148 /* If the SMBus is still busy, we give up */
149 if (timeout >= MAX_TIMEOUT) {
150 dev_dbg(&adap->dev, "Completion timeout!\n");
151 goto abort;
154 if (temp & GS_PRERR_STS) {
155 result = -1;
156 dev_dbg(&adap->dev, "SMBus Protocol error (no response)!\n");
159 if (temp & GS_COL_STS) {
160 result = -1;
161 dev_warn(&adap->dev, "SMBus collision!\n");
164 if (temp & GS_TO_STS) {
165 result = -1;
166 dev_dbg(&adap->dev, "SMBus protocol timeout!\n");
169 if (temp & GS_HCYC_STS)
170 dev_dbg(&adap->dev, "SMBus protocol success!\n");
172 outw_p(GS_CLEAR_STS, SMB_GLOBAL_STATUS);
174 #ifdef DEBUG
175 if (((temp = inw_p(SMB_GLOBAL_STATUS)) & GS_CLEAR_STS) != 0x00) {
176 dev_dbg(&adap->dev,
177 "Failed reset at end of transaction (%04x)\n", temp);
179 #endif
181 dev_dbg(&adap->dev,
182 "Transaction (post): GS=%04x, GE=%04x, ADD=%04x, DAT=%04x\n",
183 inw_p(SMB_GLOBAL_STATUS), inw_p(SMB_GLOBAL_ENABLE),
184 inw_p(SMB_HOST_ADDRESS), inb_p(SMB_HOST_DATA));
186 return result;
188 abort:
189 dev_warn(&adap->dev, "Sending abort\n");
190 outw_p(inw(SMB_GLOBAL_ENABLE) | GE_ABORT, SMB_GLOBAL_ENABLE);
191 msleep(100);
192 outw_p(GS_CLEAR_STS, SMB_GLOBAL_STATUS);
193 return -1;
196 /* Return -1 on error. */
197 static s32 amd756_access(struct i2c_adapter * adap, u16 addr,
198 unsigned short flags, char read_write,
199 u8 command, int size, union i2c_smbus_data * data)
201 int i, len;
203 /** TODO: Should I supporte the 10-bit transfers? */
204 switch (size) {
205 case I2C_SMBUS_PROC_CALL:
206 dev_dbg(&adap->dev, "I2C_SMBUS_PROC_CALL not supported!\n");
207 /* TODO: Well... It is supported, I'm just not sure what to do here... */
208 return -1;
209 case I2C_SMBUS_QUICK:
210 outw_p(((addr & 0x7f) << 1) | (read_write & 0x01),
211 SMB_HOST_ADDRESS);
212 size = AMD756_QUICK;
213 break;
214 case I2C_SMBUS_BYTE:
215 outw_p(((addr & 0x7f) << 1) | (read_write & 0x01),
216 SMB_HOST_ADDRESS);
217 if (read_write == I2C_SMBUS_WRITE)
218 outb_p(command, SMB_HOST_DATA);
219 size = AMD756_BYTE;
220 break;
221 case I2C_SMBUS_BYTE_DATA:
222 outw_p(((addr & 0x7f) << 1) | (read_write & 0x01),
223 SMB_HOST_ADDRESS);
224 outb_p(command, SMB_HOST_COMMAND);
225 if (read_write == I2C_SMBUS_WRITE)
226 outw_p(data->byte, SMB_HOST_DATA);
227 size = AMD756_BYTE_DATA;
228 break;
229 case I2C_SMBUS_WORD_DATA:
230 outw_p(((addr & 0x7f) << 1) | (read_write & 0x01),
231 SMB_HOST_ADDRESS);
232 outb_p(command, SMB_HOST_COMMAND);
233 if (read_write == I2C_SMBUS_WRITE)
234 outw_p(data->word, SMB_HOST_DATA); /* TODO: endian???? */
235 size = AMD756_WORD_DATA;
236 break;
237 case I2C_SMBUS_BLOCK_DATA:
238 outw_p(((addr & 0x7f) << 1) | (read_write & 0x01),
239 SMB_HOST_ADDRESS);
240 outb_p(command, SMB_HOST_COMMAND);
241 if (read_write == I2C_SMBUS_WRITE) {
242 len = data->block[0];
243 if (len < 0)
244 len = 0;
245 if (len > 32)
246 len = 32;
247 outw_p(len, SMB_HOST_DATA);
248 /* i = inw_p(SMBHSTCNT); Reset SMBBLKDAT */
249 for (i = 1; i <= len; i++)
250 outb_p(data->block[i],
251 SMB_HOST_BLOCK_DATA);
253 size = AMD756_BLOCK_DATA;
254 break;
257 /* How about enabling interrupts... */
258 outw_p(size & GE_CYC_TYPE_MASK, SMB_GLOBAL_ENABLE);
260 if (amd756_transaction(adap)) /* Error in transaction */
261 return -1;
263 if ((read_write == I2C_SMBUS_WRITE) || (size == AMD756_QUICK))
264 return 0;
267 switch (size) {
268 case AMD756_BYTE:
269 data->byte = inw_p(SMB_HOST_DATA);
270 break;
271 case AMD756_BYTE_DATA:
272 data->byte = inw_p(SMB_HOST_DATA);
273 break;
274 case AMD756_WORD_DATA:
275 data->word = inw_p(SMB_HOST_DATA); /* TODO: endian???? */
276 break;
277 case AMD756_BLOCK_DATA:
278 data->block[0] = inw_p(SMB_HOST_DATA) & 0x3f;
279 if(data->block[0] > 32)
280 data->block[0] = 32;
281 /* i = inw_p(SMBHSTCNT); Reset SMBBLKDAT */
282 for (i = 1; i <= data->block[0]; i++)
283 data->block[i] = inb_p(SMB_HOST_BLOCK_DATA);
284 break;
287 return 0;
290 static u32 amd756_func(struct i2c_adapter *adapter)
292 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
293 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
294 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_PROC_CALL;
297 static struct i2c_algorithm smbus_algorithm = {
298 .smbus_xfer = amd756_access,
299 .functionality = amd756_func,
302 struct i2c_adapter amd756_smbus = {
303 .owner = THIS_MODULE,
304 .class = I2C_CLASS_HWMON,
305 .algo = &smbus_algorithm,
308 enum chiptype { AMD756, AMD766, AMD768, NFORCE, AMD8111 };
309 static const char* chipname[] = {
310 "AMD756", "AMD766", "AMD768",
311 "nVidia nForce", "AMD8111",
314 static struct pci_device_id amd756_ids[] = {
315 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_740B),
316 .driver_data = AMD756 },
317 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7413),
318 .driver_data = AMD766 },
319 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_OPUS_7443),
320 .driver_data = AMD768 },
321 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS),
322 .driver_data = AMD8111 },
323 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_SMBUS),
324 .driver_data = NFORCE },
325 { 0, }
328 MODULE_DEVICE_TABLE (pci, amd756_ids);
330 static int __devinit amd756_probe(struct pci_dev *pdev,
331 const struct pci_device_id *id)
333 int nforce = (id->driver_data == NFORCE);
334 int error;
335 u8 temp;
337 if (amd756_ioport) {
338 dev_err(&pdev->dev, "Only one device supported "
339 "(you have a strange motherboard, btw)\n");
340 return -ENODEV;
343 if (nforce) {
344 if (PCI_FUNC(pdev->devfn) != 1)
345 return -ENODEV;
347 pci_read_config_word(pdev, SMBBANFORCE, &amd756_ioport);
348 amd756_ioport &= 0xfffc;
349 } else { /* amd */
350 if (PCI_FUNC(pdev->devfn) != 3)
351 return -ENODEV;
353 pci_read_config_byte(pdev, SMBGCFG, &temp);
354 if ((temp & 128) == 0) {
355 dev_err(&pdev->dev,
356 "Error: SMBus controller I/O not enabled!\n");
357 return -ENODEV;
360 /* Determine the address of the SMBus areas */
361 /* Technically it is a dword but... */
362 pci_read_config_word(pdev, SMBBA, &amd756_ioport);
363 amd756_ioport &= 0xff00;
364 amd756_ioport += SMB_ADDR_OFFSET;
367 if (!request_region(amd756_ioport, SMB_IOSIZE, amd756_driver.name)) {
368 dev_err(&pdev->dev, "SMB region 0x%x already in use!\n",
369 amd756_ioport);
370 return -ENODEV;
373 pci_read_config_byte(pdev, SMBREV, &temp);
374 dev_dbg(&pdev->dev, "SMBREV = 0x%X\n", temp);
375 dev_dbg(&pdev->dev, "AMD756_smba = 0x%X\n", amd756_ioport);
377 /* set up the driverfs linkage to our parent device */
378 amd756_smbus.dev.parent = &pdev->dev;
380 sprintf(amd756_smbus.name, "SMBus %s adapter at %04x",
381 chipname[id->driver_data], amd756_ioport);
383 error = i2c_add_adapter(&amd756_smbus);
384 if (error) {
385 dev_err(&pdev->dev,
386 "Adapter registration failed, module not inserted\n");
387 goto out_err;
390 return 0;
392 out_err:
393 release_region(amd756_ioport, SMB_IOSIZE);
394 return error;
397 static void __devexit amd756_remove(struct pci_dev *dev)
399 i2c_del_adapter(&amd756_smbus);
400 release_region(amd756_ioport, SMB_IOSIZE);
403 static struct pci_driver amd756_driver = {
404 .name = "amd756_smbus",
405 .id_table = amd756_ids,
406 .probe = amd756_probe,
407 .remove = __devexit_p(amd756_remove),
410 static int __init amd756_init(void)
412 return pci_register_driver(&amd756_driver);
415 static void __exit amd756_exit(void)
417 pci_unregister_driver(&amd756_driver);
420 MODULE_AUTHOR("Merlin Hughes <merlin@merlin.org>");
421 MODULE_DESCRIPTION("AMD756/766/768/8111 and nVidia nForce SMBus driver");
422 MODULE_LICENSE("GPL");
424 EXPORT_SYMBOL(amd756_smbus);
426 module_init(amd756_init)
427 module_exit(amd756_exit)