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[PATCH] w1: Added default generic read/write operations.
[linux-2.6/verdex.git] / sound / pci / cmipci.c
blobe5ce2dabd081f28fb3f40e2ef64bc393a5d7a19c
1 /*
2 * Driver for C-Media CMI8338 and 8738 PCI soundcards.
3 * Copyright (c) 2000 by Takashi Iwai <tiwai@suse.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 /* Does not work. Warning may block system in capture mode */
21 /* #define USE_VAR48KRATE */
22
23 #include <sound/driver.h>
24 #include <asm/io.h>
25 #include <linux/delay.h>
26 #include <linux/interrupt.h>
27 #include <linux/init.h>
28 #include <linux/pci.h>
29 #include <linux/slab.h>
30 #include <linux/gameport.h>
31 #include <linux/moduleparam.h>
32 #include <linux/mutex.h>
33 #include <sound/core.h>
34 #include <sound/info.h>
35 #include <sound/control.h>
36 #include <sound/pcm.h>
37 #include <sound/rawmidi.h>
38 #include <sound/mpu401.h>
39 #include <sound/opl3.h>
40 #include <sound/sb.h>
41 #include <sound/asoundef.h>
42 #include <sound/initval.h>
43
44 MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
45 MODULE_DESCRIPTION("C-Media CMI8x38 PCI");
46 MODULE_LICENSE("GPL");
47 MODULE_SUPPORTED_DEVICE("{{C-Media,CMI8738},"
48 "{C-Media,CMI8738B},"
49 "{C-Media,CMI8338A},"
50 "{C-Media,CMI8338B}}");
51
52 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
53 #define SUPPORT_JOYSTICK 1
54 #endif
55
56 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
57 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
58 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */
59 static long mpu_port[SNDRV_CARDS];
60 static long fm_port[SNDRV_CARDS];
61 static int soft_ac3[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
62 #ifdef SUPPORT_JOYSTICK
63 static int joystick_port[SNDRV_CARDS];
64 #endif
65
66 module_param_array(index, int, NULL, 0444);
67 MODULE_PARM_DESC(index, "Index value for C-Media PCI soundcard.");
68 module_param_array(id, charp, NULL, 0444);
69 MODULE_PARM_DESC(id, "ID string for C-Media PCI soundcard.");
70 module_param_array(enable, bool, NULL, 0444);
71 MODULE_PARM_DESC(enable, "Enable C-Media PCI soundcard.");
72 module_param_array(mpu_port, long, NULL, 0444);
73 MODULE_PARM_DESC(mpu_port, "MPU-401 port.");
74 module_param_array(fm_port, long, NULL, 0444);
75 MODULE_PARM_DESC(fm_port, "FM port.");
76 module_param_array(soft_ac3, bool, NULL, 0444);
77 MODULE_PARM_DESC(soft_ac3, "Sofware-conversion of raw SPDIF packets (model 033 only).");
78 #ifdef SUPPORT_JOYSTICK
79 module_param_array(joystick_port, int, NULL, 0444);
80 MODULE_PARM_DESC(joystick_port, "Joystick port address.");
81 #endif
82
83 /*
84 * CM8x38 registers definition
85 */
86
87 #define CM_REG_FUNCTRL0 0x00
88 #define CM_RST_CH1 0x00080000
89 #define CM_RST_CH0 0x00040000
90 #define CM_CHEN1 0x00020000 /* ch1: enable */
91 #define CM_CHEN0 0x00010000 /* ch0: enable */
92 #define CM_PAUSE1 0x00000008 /* ch1: pause */
93 #define CM_PAUSE0 0x00000004 /* ch0: pause */
94 #define CM_CHADC1 0x00000002 /* ch1, 0:playback, 1:record */
95 #define CM_CHADC0 0x00000001 /* ch0, 0:playback, 1:record */
96
97 #define CM_REG_FUNCTRL1 0x04
98 #define CM_ASFC_MASK 0x0000E000 /* ADC sampling frequency */
99 #define CM_ASFC_SHIFT 13
100 #define CM_DSFC_MASK 0x00001C00 /* DAC sampling frequency */
101 #define CM_DSFC_SHIFT 10
102 #define CM_SPDF_1 0x00000200 /* SPDIF IN/OUT at channel B */
103 #define CM_SPDF_0 0x00000100 /* SPDIF OUT only channel A */
104 #define CM_SPDFLOOP 0x00000080 /* ext. SPDIIF/OUT -> IN loopback */
105 #define CM_SPDO2DAC 0x00000040 /* SPDIF/OUT can be heard from internal DAC */
106 #define CM_INTRM 0x00000020 /* master control block (MCB) interrupt enabled */
107 #define CM_BREQ 0x00000010 /* bus master enabled */
108 #define CM_VOICE_EN 0x00000008 /* legacy voice (SB16,FM) */
109 #define CM_UART_EN 0x00000004 /* UART */
110 #define CM_JYSTK_EN 0x00000002 /* joy stick */
111
112 #define CM_REG_CHFORMAT 0x08
113
114 #define CM_CHB3D5C 0x80000000 /* 5,6 channels */
115 #define CM_CHB3D 0x20000000 /* 4 channels */
116
117 #define CM_CHIP_MASK1 0x1f000000
118 #define CM_CHIP_037 0x01000000
119
120 #define CM_SPDIF_SELECT1 0x00080000 /* for model <= 037 ? */
121 #define CM_AC3EN1 0x00100000 /* enable AC3: model 037 */
122 #define CM_SPD24SEL 0x00020000 /* 24bit spdif: model 037 */
123 /* #define CM_SPDIF_INVERSE 0x00010000 */ /* ??? */
124
125 #define CM_ADCBITLEN_MASK 0x0000C000
126 #define CM_ADCBITLEN_16 0x00000000
127 #define CM_ADCBITLEN_15 0x00004000
128 #define CM_ADCBITLEN_14 0x00008000
129 #define CM_ADCBITLEN_13 0x0000C000
130
131 #define CM_ADCDACLEN_MASK 0x00003000
132 #define CM_ADCDACLEN_060 0x00000000
133 #define CM_ADCDACLEN_066 0x00001000
134 #define CM_ADCDACLEN_130 0x00002000
135 #define CM_ADCDACLEN_280 0x00003000
136
137 #define CM_CH1_SRATE_176K 0x00000800
138 #define CM_CH1_SRATE_88K 0x00000400
139 #define CM_CH0_SRATE_176K 0x00000200
140 #define CM_CH0_SRATE_88K 0x00000100
141
142 #define CM_SPDIF_INVERSE2 0x00000080 /* model 055? */
143
144 #define CM_CH1FMT_MASK 0x0000000C
145 #define CM_CH1FMT_SHIFT 2
146 #define CM_CH0FMT_MASK 0x00000003
147 #define CM_CH0FMT_SHIFT 0
148
149 #define CM_REG_INT_HLDCLR 0x0C
150 #define CM_CHIP_MASK2 0xff000000
151 #define CM_CHIP_039 0x04000000
152 #define CM_CHIP_039_6CH 0x01000000
153 #define CM_CHIP_055 0x08000000
154 #define CM_CHIP_8768 0x20000000
155 #define CM_TDMA_INT_EN 0x00040000
156 #define CM_CH1_INT_EN 0x00020000
157 #define CM_CH0_INT_EN 0x00010000
158 #define CM_INT_HOLD 0x00000002
159 #define CM_INT_CLEAR 0x00000001
160
161 #define CM_REG_INT_STATUS 0x10
162 #define CM_INTR 0x80000000
163 #define CM_VCO 0x08000000 /* Voice Control? CMI8738 */
164 #define CM_MCBINT 0x04000000 /* Master Control Block abort cond.? */
165 #define CM_UARTINT 0x00010000
166 #define CM_LTDMAINT 0x00008000
167 #define CM_HTDMAINT 0x00004000
168 #define CM_XDO46 0x00000080 /* Modell 033? Direct programming EEPROM (read data register) */
169 #define CM_LHBTOG 0x00000040 /* High/Low status from DMA ctrl register */
170 #define CM_LEG_HDMA 0x00000020 /* Legacy is in High DMA channel */
171 #define CM_LEG_STEREO 0x00000010 /* Legacy is in Stereo mode */
172 #define CM_CH1BUSY 0x00000008
173 #define CM_CH0BUSY 0x00000004
174 #define CM_CHINT1 0x00000002
175 #define CM_CHINT0 0x00000001
176
177 #define CM_REG_LEGACY_CTRL 0x14
178 #define CM_NXCHG 0x80000000 /* h/w multi channels? */
179 #define CM_VMPU_MASK 0x60000000 /* MPU401 i/o port address */
180 #define CM_VMPU_330 0x00000000
181 #define CM_VMPU_320 0x20000000
182 #define CM_VMPU_310 0x40000000
183 #define CM_VMPU_300 0x60000000
184 #define CM_VSBSEL_MASK 0x0C000000 /* SB16 base address */
185 #define CM_VSBSEL_220 0x00000000
186 #define CM_VSBSEL_240 0x04000000
187 #define CM_VSBSEL_260 0x08000000
188 #define CM_VSBSEL_280 0x0C000000
189 #define CM_FMSEL_MASK 0x03000000 /* FM OPL3 base address */
190 #define CM_FMSEL_388 0x00000000
191 #define CM_FMSEL_3C8 0x01000000
192 #define CM_FMSEL_3E0 0x02000000
193 #define CM_FMSEL_3E8 0x03000000
194 #define CM_ENSPDOUT 0x00800000 /* enable XPDIF/OUT to I/O interface */
195 #define CM_SPDCOPYRHT 0x00400000 /* set copyright spdif in/out */
196 #define CM_DAC2SPDO 0x00200000 /* enable wave+fm_midi -> SPDIF/OUT */
197 #define CM_SETRETRY 0x00010000 /* 0: legacy i/o wait (default), 1: legacy i/o bus retry */
198 #define CM_CHB3D6C 0x00008000 /* 5.1 channels support */
199 #define CM_LINE_AS_BASS 0x00006000 /* use line-in as bass */
200
201 #define CM_REG_MISC_CTRL 0x18
202 #define CM_PWD 0x80000000
203 #define CM_RESET 0x40000000
204 #define CM_SFIL_MASK 0x30000000
205 #define CM_TXVX 0x08000000
206 #define CM_N4SPK3D 0x04000000 /* 4ch output */
207 #define CM_SPDO5V 0x02000000 /* 5V spdif output (1 = 0.5v (coax)) */
208 #define CM_SPDIF48K 0x01000000 /* write */
209 #define CM_SPATUS48K 0x01000000 /* read */
210 #define CM_ENDBDAC 0x00800000 /* enable dual dac */
211 #define CM_XCHGDAC 0x00400000 /* 0: front=ch0, 1: front=ch1 */
212 #define CM_SPD32SEL 0x00200000 /* 0: 16bit SPDIF, 1: 32bit */
213 #define CM_SPDFLOOPI 0x00100000 /* int. SPDIF-IN -> int. OUT */
214 #define CM_FM_EN 0x00080000 /* enalbe FM */
215 #define CM_AC3EN2 0x00040000 /* enable AC3: model 039 */
216 #define CM_VIDWPDSB 0x00010000
217 #define CM_SPDF_AC97 0x00008000 /* 0: SPDIF/OUT 44.1K, 1: 48K */
218 #define CM_MASK_EN 0x00004000
219 #define CM_VIDWPPRT 0x00002000
220 #define CM_SFILENB 0x00001000
221 #define CM_MMODE_MASK 0x00000E00
222 #define CM_SPDIF_SELECT2 0x00000100 /* for model > 039 ? */
223 #define CM_ENCENTER 0x00000080
224 #define CM_FLINKON 0x00000040
225 #define CM_FLINKOFF 0x00000020
226 #define CM_MIDSMP 0x00000010
227 #define CM_UPDDMA_MASK 0x0000000C
228 #define CM_TWAIT_MASK 0x00000003
229
230 /* byte */
231 #define CM_REG_MIXER0 0x20
232
233 #define CM_REG_SB16_DATA 0x22
234 #define CM_REG_SB16_ADDR 0x23
235
236 #define CM_REFFREQ_XIN (315*1000*1000)/22 /* 14.31818 Mhz reference clock frequency pin XIN */
237 #define CM_ADCMULT_XIN 512 /* Guessed (487 best for 44.1kHz, not for 88/176kHz) */
238 #define CM_TOLERANCE_RATE 0.001 /* Tolerance sample rate pitch (1000ppm) */
239 #define CM_MAXIMUM_RATE 80000000 /* Note more than 80MHz */
240
241 #define CM_REG_MIXER1 0x24
242 #define CM_FMMUTE 0x80 /* mute FM */
243 #define CM_FMMUTE_SHIFT 7
244 #define CM_WSMUTE 0x40 /* mute PCM */
245 #define CM_WSMUTE_SHIFT 6
246 #define CM_SPK4 0x20 /* lin-in -> rear line out */
247 #define CM_SPK4_SHIFT 5
248 #define CM_REAR2FRONT 0x10 /* exchange rear/front */
249 #define CM_REAR2FRONT_SHIFT 4
250 #define CM_WAVEINL 0x08 /* digital wave rec. left chan */
251 #define CM_WAVEINL_SHIFT 3
252 #define CM_WAVEINR 0x04 /* digical wave rec. right */
253 #define CM_WAVEINR_SHIFT 2
254 #define CM_X3DEN 0x02 /* 3D surround enable */
255 #define CM_X3DEN_SHIFT 1
256 #define CM_CDPLAY 0x01 /* enable SPDIF/IN PCM -> DAC */
257 #define CM_CDPLAY_SHIFT 0
258
259 #define CM_REG_MIXER2 0x25
260 #define CM_RAUXREN 0x80 /* AUX right capture */
261 #define CM_RAUXREN_SHIFT 7
262 #define CM_RAUXLEN 0x40 /* AUX left capture */
263 #define CM_RAUXLEN_SHIFT 6
264 #define CM_VAUXRM 0x20 /* AUX right mute */
265 #define CM_VAUXRM_SHIFT 5
266 #define CM_VAUXLM 0x10 /* AUX left mute */
267 #define CM_VAUXLM_SHIFT 4
268 #define CM_VADMIC_MASK 0x0e /* mic gain level (0-3) << 1 */
269 #define CM_VADMIC_SHIFT 1
270 #define CM_MICGAINZ 0x01 /* mic boost */
271 #define CM_MICGAINZ_SHIFT 0
272
273 #define CM_REG_MIXER3 0x24
274 #define CM_REG_AUX_VOL 0x26
275 #define CM_VAUXL_MASK 0xf0
276 #define CM_VAUXR_MASK 0x0f
277
278 #define CM_REG_MISC 0x27
279 #define CM_XGPO1 0x20
280 // #define CM_XGPBIO 0x04
281 #define CM_MIC_CENTER_LFE 0x04 /* mic as center/lfe out? (model 039 or later?) */
282 #define CM_SPDIF_INVERSE 0x04 /* spdif input phase inverse (model 037) */
283 #define CM_SPDVALID 0x02 /* spdif input valid check */
284 #define CM_DMAUTO 0x01
285
286 #define CM_REG_AC97 0x28 /* hmmm.. do we have ac97 link? */
287 /*
288 * For CMI-8338 (0x28 - 0x2b) .. is this valid for CMI-8738
289 * or identical with AC97 codec?
290 */
291 #define CM_REG_EXTERN_CODEC CM_REG_AC97
292
293 /*
294 * MPU401 pci port index address 0x40 - 0x4f (CMI-8738 spec ver. 0.6)
295 */
296 #define CM_REG_MPU_PCI 0x40
297
298 /*
299 * FM pci port index address 0x50 - 0x5f (CMI-8738 spec ver. 0.6)
300 */
301 #define CM_REG_FM_PCI 0x50
302
303 /*
304 * access from SB-mixer port
305 */
306 #define CM_REG_EXTENT_IND 0xf0
307 #define CM_VPHONE_MASK 0xe0 /* Phone volume control (0-3) << 5 */
308 #define CM_VPHONE_SHIFT 5
309 #define CM_VPHOM 0x10 /* Phone mute control */
310 #define CM_VSPKM 0x08 /* Speaker mute control, default high */
311 #define CM_RLOOPREN 0x04 /* Rec. R-channel enable */
312 #define CM_RLOOPLEN 0x02 /* Rec. L-channel enable */
313 #define CM_VADMIC3 0x01 /* Mic record boost */
314
315 /*
316 * CMI-8338 spec ver 0.5 (this is not valid for CMI-8738):
317 * the 8 registers 0xf8 - 0xff are used for programming m/n counter by the PLL
318 * unit (readonly?).
319 */
320 #define CM_REG_PLL 0xf8
321
322 /*
323 * extended registers
324 */
325 #define CM_REG_CH0_FRAME1 0x80 /* base address */
326 #define CM_REG_CH0_FRAME2 0x84
327 #define CM_REG_CH1_FRAME1 0x88 /* 0-15: count of samples at bus master; buffer size */
328 #define CM_REG_CH1_FRAME2 0x8C /* 16-31: count of samples at codec; fragment size */
329 #define CM_REG_EXT_MISC 0x90
330 #define CM_REG_MISC_CTRL_8768 0x92 /* reg. name the same as 0x18 */
331 #define CM_CHB3D8C 0x20 /* 7.1 channels support */
332 #define CM_SPD32FMT 0x10 /* SPDIF/IN 32k */
333 #define CM_ADC2SPDIF 0x08 /* ADC output to SPDIF/OUT */
334 #define CM_SHAREADC 0x04 /* DAC in ADC as Center/LFE */
335 #define CM_REALTCMP 0x02 /* monitor the CMPL/CMPR of ADC */
336 #define CM_INVLRCK 0x01 /* invert ZVPORT's LRCK */
337
338 /*
339 * size of i/o region
340 */
341 #define CM_EXTENT_CODEC 0x100
342 #define CM_EXTENT_MIDI 0x2
343 #define CM_EXTENT_SYNTH 0x4
344
345
346 /*
347 * channels for playback / capture
348 */
349 #define CM_CH_PLAY 0
350 #define CM_CH_CAPT 1
351
352 /*
353 * flags to check device open/close
354 */
355 #define CM_OPEN_NONE 0
356 #define CM_OPEN_CH_MASK 0x01
357 #define CM_OPEN_DAC 0x10
358 #define CM_OPEN_ADC 0x20
359 #define CM_OPEN_SPDIF 0x40
360 #define CM_OPEN_MCHAN 0x80
361 #define CM_OPEN_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC)
362 #define CM_OPEN_PLAYBACK2 (CM_CH_CAPT | CM_OPEN_DAC)
363 #define CM_OPEN_PLAYBACK_MULTI (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_MCHAN)
364 #define CM_OPEN_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC)
365 #define CM_OPEN_SPDIF_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_SPDIF)
366 #define CM_OPEN_SPDIF_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC | CM_OPEN_SPDIF)
367
368
369 #if CM_CH_PLAY == 1
370 #define CM_PLAYBACK_SRATE_176K CM_CH1_SRATE_176K
371 #define CM_PLAYBACK_SPDF CM_SPDF_1
372 #define CM_CAPTURE_SPDF CM_SPDF_0
373 #else
374 #define CM_PLAYBACK_SRATE_176K CM_CH0_SRATE_176K
375 #define CM_PLAYBACK_SPDF CM_SPDF_0
376 #define CM_CAPTURE_SPDF CM_SPDF_1
377 #endif
378
379
380 /*
381 * driver data
382 */
383
384 struct cmipci_pcm {
385 struct snd_pcm_substream *substream;
386 int running; /* dac/adc running? */
387 unsigned int dma_size; /* in frames */
388 unsigned int period_size; /* in frames */
389 unsigned int offset; /* physical address of the buffer */
390 unsigned int fmt; /* format bits */
391 int ch; /* channel (0/1) */
392 unsigned int is_dac; /* is dac? */
393 int bytes_per_frame;
394 int shift;
395 };
396
397 /* mixer elements toggled/resumed during ac3 playback */
398 struct cmipci_mixer_auto_switches {
399 const char *name; /* switch to toggle */
400 int toggle_on; /* value to change when ac3 mode */
401 };
402 static const struct cmipci_mixer_auto_switches cm_saved_mixer[] = {
403 {"PCM Playback Switch", 0},
404 {"IEC958 Output Switch", 1},
405 {"IEC958 Mix Analog", 0},
406 // {"IEC958 Out To DAC", 1}, // no longer used
407 {"IEC958 Loop", 0},
408 };
409 #define CM_SAVED_MIXERS ARRAY_SIZE(cm_saved_mixer)
410
411 struct cmipci {
412 struct snd_card *card;
413
414 struct pci_dev *pci;
415 unsigned int device; /* device ID */
416 int irq;
417
418 unsigned long iobase;
419 unsigned int ctrl; /* FUNCTRL0 current value */
420
421 struct snd_pcm *pcm; /* DAC/ADC PCM */
422 struct snd_pcm *pcm2; /* 2nd DAC */
423 struct snd_pcm *pcm_spdif; /* SPDIF */
424
425 int chip_version;
426 int max_channels;
427 unsigned int has_dual_dac: 1;
428 unsigned int can_ac3_sw: 1;
429 unsigned int can_ac3_hw: 1;
430 unsigned int can_multi_ch: 1;
431 unsigned int do_soft_ac3: 1;
432
433 unsigned int spdif_playback_avail: 1; /* spdif ready? */
434 unsigned int spdif_playback_enabled: 1; /* spdif switch enabled? */
435 int spdif_counter; /* for software AC3 */
436
437 unsigned int dig_status;
438 unsigned int dig_pcm_status;
439
440 struct snd_pcm_hardware *hw_info[3]; /* for playbacks */
441
442 int opened[2]; /* open mode */
443 struct mutex open_mutex;
444
445 unsigned int mixer_insensitive: 1;
446 struct snd_kcontrol *mixer_res_ctl[CM_SAVED_MIXERS];
447 int mixer_res_status[CM_SAVED_MIXERS];
448
449 struct cmipci_pcm channel[2]; /* ch0 - DAC, ch1 - ADC or 2nd DAC */
450
451 /* external MIDI */
452 struct snd_rawmidi *rmidi;
453
454 #ifdef SUPPORT_JOYSTICK
455 struct gameport *gameport;
456 #endif
457
458 spinlock_t reg_lock;
459
460 #ifdef CONFIG_PM
461 unsigned int saved_regs[0x20];
462 unsigned char saved_mixers[0x20];
463 #endif
464 };
465
466
467 /* read/write operations for dword register */
468 static inline void snd_cmipci_write(struct cmipci *cm, unsigned int cmd, unsigned int data)
469 {
470 outl(data, cm->iobase + cmd);
471 }
472
473 static inline unsigned int snd_cmipci_read(struct cmipci *cm, unsigned int cmd)
474 {
475 return inl(cm->iobase + cmd);
476 }
477
478 /* read/write operations for word register */
479 static inline void snd_cmipci_write_w(struct cmipci *cm, unsigned int cmd, unsigned short data)
480 {
481 outw(data, cm->iobase + cmd);
482 }
483
484 static inline unsigned short snd_cmipci_read_w(struct cmipci *cm, unsigned int cmd)
485 {
486 return inw(cm->iobase + cmd);
487 }
488
489 /* read/write operations for byte register */
490 static inline void snd_cmipci_write_b(struct cmipci *cm, unsigned int cmd, unsigned char data)
491 {
492 outb(data, cm->iobase + cmd);
493 }
494
495 static inline unsigned char snd_cmipci_read_b(struct cmipci *cm, unsigned int cmd)
496 {
497 return inb(cm->iobase + cmd);
498 }
499
500 /* bit operations for dword register */
501 static int snd_cmipci_set_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
502 {
503 unsigned int val, oval;
504 val = oval = inl(cm->iobase + cmd);
505 val |= flag;
506 if (val == oval)
507 return 0;
508 outl(val, cm->iobase + cmd);
509 return 1;
510 }
511
512 static int snd_cmipci_clear_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
513 {
514 unsigned int val, oval;
515 val = oval = inl(cm->iobase + cmd);
516 val &= ~flag;
517 if (val == oval)
518 return 0;
519 outl(val, cm->iobase + cmd);
520 return 1;
521 }
522
523 /* bit operations for byte register */
524 static int snd_cmipci_set_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
525 {
526 unsigned char val, oval;
527 val = oval = inb(cm->iobase + cmd);
528 val |= flag;
529 if (val == oval)
530 return 0;
531 outb(val, cm->iobase + cmd);
532 return 1;
533 }
534
535 static int snd_cmipci_clear_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
536 {
537 unsigned char val, oval;
538 val = oval = inb(cm->iobase + cmd);
539 val &= ~flag;
540 if (val == oval)
541 return 0;
542 outb(val, cm->iobase + cmd);
543 return 1;
544 }
545
546
547 /*
548 * PCM interface
549 */
550
551 /*
552 * calculate frequency
553 */
554
555 static unsigned int rates[] = { 5512, 11025, 22050, 44100, 8000, 16000, 32000, 48000 };
556
557 static unsigned int snd_cmipci_rate_freq(unsigned int rate)
558 {
559 unsigned int i;
560 for (i = 0; i < ARRAY_SIZE(rates); i++) {
561 if (rates[i] == rate)
562 return i;
563 }
564 snd_BUG();
565 return 0;
566 }
567
568 #ifdef USE_VAR48KRATE
569 /*
570 * Determine PLL values for frequency setup, maybe the CMI8338 (CMI8738???)
571 * does it this way .. maybe not. Never get any information from C-Media about
572 * that <werner@suse.de>.
573 */
574 static int snd_cmipci_pll_rmn(unsigned int rate, unsigned int adcmult, int *r, int *m, int *n)
575 {
576 unsigned int delta, tolerance;
577 int xm, xn, xr;
578
579 for (*r = 0; rate < CM_MAXIMUM_RATE/adcmult; *r += (1<<5))
580 rate <<= 1;
581 *n = -1;
582 if (*r > 0xff)
583 goto out;
584 tolerance = rate*CM_TOLERANCE_RATE;
585
586 for (xn = (1+2); xn < (0x1f+2); xn++) {
587 for (xm = (1+2); xm < (0xff+2); xm++) {
588 xr = ((CM_REFFREQ_XIN/adcmult) * xm) / xn;
589
590 if (xr < rate)
591 delta = rate - xr;
592 else
593 delta = xr - rate;
594
595 /*
596 * If we found one, remember this,
597 * and try to find a closer one
598 */
599 if (delta < tolerance) {
600 tolerance = delta;
601 *m = xm - 2;
602 *n = xn - 2;
603 }
604 }
605 }
606 out:
607 return (*n > -1);
608 }
609
610 /*
611 * Program pll register bits, I assume that the 8 registers 0xf8 upto 0xff
612 * are mapped onto the 8 ADC/DAC sampling frequency which can be choosen
613 * at the register CM_REG_FUNCTRL1 (0x04).
614 * Problem: other ways are also possible (any information about that?)
615 */
616 static void snd_cmipci_set_pll(struct cmipci *cm, unsigned int rate, unsigned int slot)
617 {
618 unsigned int reg = CM_REG_PLL + slot;
619 /*
620 * Guess that this programs at reg. 0x04 the pos 15:13/12:10
621 * for DSFC/ASFC (000 upto 111).
622 */
623
624 /* FIXME: Init (Do we've to set an other register first before programming?) */
625
626 /* FIXME: Is this correct? Or shouldn't the m/n/r values be used for that? */
627 snd_cmipci_write_b(cm, reg, rate>>8);
628 snd_cmipci_write_b(cm, reg, rate&0xff);
629
630 /* FIXME: Setup (Do we've to set an other register first to enable this?) */
631 }
632 #endif /* USE_VAR48KRATE */
633
634 static int snd_cmipci_hw_params(struct snd_pcm_substream *substream,
635 struct snd_pcm_hw_params *hw_params)
636 {
637 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
638 }
639
640 static int snd_cmipci_playback2_hw_params(struct snd_pcm_substream *substream,
641 struct snd_pcm_hw_params *hw_params)
642 {
643 struct cmipci *cm = snd_pcm_substream_chip(substream);
644 if (params_channels(hw_params) > 2) {
645 mutex_lock(&cm->open_mutex);
646 if (cm->opened[CM_CH_PLAY]) {
647 mutex_unlock(&cm->open_mutex);
648 return -EBUSY;
649 }
650 /* reserve the channel A */
651 cm->opened[CM_CH_PLAY] = CM_OPEN_PLAYBACK_MULTI;
652 mutex_unlock(&cm->open_mutex);
653 }
654 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
655 }
656
657 static void snd_cmipci_ch_reset(struct cmipci *cm, int ch)
658 {
659 int reset = CM_RST_CH0 << (cm->channel[ch].ch);
660 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
661 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
662 udelay(10);
663 }
664
665 static int snd_cmipci_hw_free(struct snd_pcm_substream *substream)
666 {
667 return snd_pcm_lib_free_pages(substream);
668 }
669
670
671 /*
672 */
673
674 static unsigned int hw_channels[] = {1, 2, 4, 5, 6, 8};
675 static struct snd_pcm_hw_constraint_list hw_constraints_channels_4 = {
676 .count = 3,
677 .list = hw_channels,
678 .mask = 0,
679 };
680 static struct snd_pcm_hw_constraint_list hw_constraints_channels_6 = {
681 .count = 5,
682 .list = hw_channels,
683 .mask = 0,
684 };
685 static struct snd_pcm_hw_constraint_list hw_constraints_channels_8 = {
686 .count = 6,
687 .list = hw_channels,
688 .mask = 0,
689 };
690
691 static int set_dac_channels(struct cmipci *cm, struct cmipci_pcm *rec, int channels)
692 {
693 if (channels > 2) {
694 if (! cm->can_multi_ch)
695 return -EINVAL;
696 if (rec->fmt != 0x03) /* stereo 16bit only */
697 return -EINVAL;
698
699 spin_lock_irq(&cm->reg_lock);
700 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
701 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
702 if (channels > 4) {
703 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
704 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
705 } else {
706 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
707 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
708 }
709 if (channels >= 6) {
710 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
711 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER);
712 } else {
713 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
714 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER);
715 }
716 if (cm->chip_version == 68) {
717 if (channels == 8) {
718 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL_8768, CM_CHB3D8C);
719 } else {
720 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL_8768, CM_CHB3D8C);
721 }
722 }
723 spin_unlock_irq(&cm->reg_lock);
724
725 } else {
726 if (cm->can_multi_ch) {
727 spin_lock_irq(&cm->reg_lock);
728 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
729 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
730 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
731 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
732 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER);
733 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
734 spin_unlock_irq(&cm->reg_lock);
735 }
736 }
737 return 0;
738 }
739
740
741 /*
742 * prepare playback/capture channel
743 * channel to be used must have been set in rec->ch.
744 */
745 static int snd_cmipci_pcm_prepare(struct cmipci *cm, struct cmipci_pcm *rec,
746 struct snd_pcm_substream *substream)
747 {
748 unsigned int reg, freq, val;
749 struct snd_pcm_runtime *runtime = substream->runtime;
750
751 rec->fmt = 0;
752 rec->shift = 0;
753 if (snd_pcm_format_width(runtime->format) >= 16) {
754 rec->fmt |= 0x02;
755 if (snd_pcm_format_width(runtime->format) > 16)
756 rec->shift++; /* 24/32bit */
757 }
758 if (runtime->channels > 1)
759 rec->fmt |= 0x01;
760 if (rec->is_dac && set_dac_channels(cm, rec, runtime->channels) < 0) {
761 snd_printd("cannot set dac channels\n");
762 return -EINVAL;
763 }
764
765 rec->offset = runtime->dma_addr;
766 /* buffer and period sizes in frame */
767 rec->dma_size = runtime->buffer_size << rec->shift;
768 rec->period_size = runtime->period_size << rec->shift;
769 if (runtime->channels > 2) {
770 /* multi-channels */
771 rec->dma_size = (rec->dma_size * runtime->channels) / 2;
772 rec->period_size = (rec->period_size * runtime->channels) / 2;
773 }
774
775 spin_lock_irq(&cm->reg_lock);
776
777 /* set buffer address */
778 reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
779 snd_cmipci_write(cm, reg, rec->offset);
780 /* program sample counts */
781 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
782 snd_cmipci_write_w(cm, reg, rec->dma_size - 1);
783 snd_cmipci_write_w(cm, reg + 2, rec->period_size - 1);
784
785 /* set adc/dac flag */
786 val = rec->ch ? CM_CHADC1 : CM_CHADC0;
787 if (rec->is_dac)
788 cm->ctrl &= ~val;
789 else
790 cm->ctrl |= val;
791 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
792 //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl);
793
794 /* set sample rate */
795 freq = snd_cmipci_rate_freq(runtime->rate);
796 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
797 if (rec->ch) {
798 val &= ~CM_ASFC_MASK;
799 val |= (freq << CM_ASFC_SHIFT) & CM_ASFC_MASK;
800 } else {
801 val &= ~CM_DSFC_MASK;
802 val |= (freq << CM_DSFC_SHIFT) & CM_DSFC_MASK;
803 }
804 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
805 //snd_printd("cmipci: functrl1 = %08x\n", val);
806
807 /* set format */
808 val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
809 if (rec->ch) {
810 val &= ~CM_CH1FMT_MASK;
811 val |= rec->fmt << CM_CH1FMT_SHIFT;
812 } else {
813 val &= ~CM_CH0FMT_MASK;
814 val |= rec->fmt << CM_CH0FMT_SHIFT;
815 }
816 snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
817 //snd_printd("cmipci: chformat = %08x\n", val);
818
819 rec->running = 0;
820 spin_unlock_irq(&cm->reg_lock);
821
822 return 0;
823 }
824
825 /*
826 * PCM trigger/stop
827 */
828 static int snd_cmipci_pcm_trigger(struct cmipci *cm, struct cmipci_pcm *rec,
829 struct snd_pcm_substream *substream, int cmd)
830 {
831 unsigned int inthld, chen, reset, pause;
832 int result = 0;
833
834 inthld = CM_CH0_INT_EN << rec->ch;
835 chen = CM_CHEN0 << rec->ch;
836 reset = CM_RST_CH0 << rec->ch;
837 pause = CM_PAUSE0 << rec->ch;
838
839 spin_lock(&cm->reg_lock);
840 switch (cmd) {
841 case SNDRV_PCM_TRIGGER_START:
842 rec->running = 1;
843 /* set interrupt */
844 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, inthld);
845 cm->ctrl |= chen;
846 /* enable channel */
847 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
848 //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl);
849 break;
850 case SNDRV_PCM_TRIGGER_STOP:
851 rec->running = 0;
852 /* disable interrupt */
853 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, inthld);
854 /* reset */
855 cm->ctrl &= ~chen;
856 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
857 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
858 break;
859 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
860 case SNDRV_PCM_TRIGGER_SUSPEND:
861 cm->ctrl |= pause;
862 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
863 break;
864 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
865 case SNDRV_PCM_TRIGGER_RESUME:
866 cm->ctrl &= ~pause;
867 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
868 break;
869 default:
870 result = -EINVAL;
871 break;
872 }
873 spin_unlock(&cm->reg_lock);
874 return result;
875 }
876
877 /*
878 * return the current pointer
879 */
880 static snd_pcm_uframes_t snd_cmipci_pcm_pointer(struct cmipci *cm, struct cmipci_pcm *rec,
881 struct snd_pcm_substream *substream)
882 {
883 size_t ptr;
884 unsigned int reg;
885 if (!rec->running)
886 return 0;
887 #if 1 // this seems better..
888 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
889 ptr = rec->dma_size - (snd_cmipci_read_w(cm, reg) + 1);
890 ptr >>= rec->shift;
891 #else
892 reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
893 ptr = snd_cmipci_read(cm, reg) - rec->offset;
894 ptr = bytes_to_frames(substream->runtime, ptr);
895 #endif
896 if (substream->runtime->channels > 2)
897 ptr = (ptr * 2) / substream->runtime->channels;
898 return ptr;
899 }
900
901 /*
902 * playback
903 */
904
905 static int snd_cmipci_playback_trigger(struct snd_pcm_substream *substream,
906 int cmd)
907 {
908 struct cmipci *cm = snd_pcm_substream_chip(substream);
909 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_PLAY], substream, cmd);
910 }
911
912 static snd_pcm_uframes_t snd_cmipci_playback_pointer(struct snd_pcm_substream *substream)
913 {
914 struct cmipci *cm = snd_pcm_substream_chip(substream);
915 return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_PLAY], substream);
916 }
917
918
919
920 /*
921 * capture
922 */
923
924 static int snd_cmipci_capture_trigger(struct snd_pcm_substream *substream,
925 int cmd)
926 {
927 struct cmipci *cm = snd_pcm_substream_chip(substream);
928 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_CAPT], substream, cmd);
929 }
930
931 static snd_pcm_uframes_t snd_cmipci_capture_pointer(struct snd_pcm_substream *substream)
932 {
933 struct cmipci *cm = snd_pcm_substream_chip(substream);
934 return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_CAPT], substream);
935 }
936
937
938 /*
939 * hw preparation for spdif
940 */
941
942 static int snd_cmipci_spdif_default_info(struct snd_kcontrol *kcontrol,
943 struct snd_ctl_elem_info *uinfo)
944 {
945 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
946 uinfo->count = 1;
947 return 0;
948 }
949
950 static int snd_cmipci_spdif_default_get(struct snd_kcontrol *kcontrol,
951 struct snd_ctl_elem_value *ucontrol)
952 {
953 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
954 int i;
955
956 spin_lock_irq(&chip->reg_lock);
957 for (i = 0; i < 4; i++)
958 ucontrol->value.iec958.status[i] = (chip->dig_status >> (i * 8)) & 0xff;
959 spin_unlock_irq(&chip->reg_lock);
960 return 0;
961 }
962
963 static int snd_cmipci_spdif_default_put(struct snd_kcontrol *kcontrol,
964 struct snd_ctl_elem_value *ucontrol)
965 {
966 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
967 int i, change;
968 unsigned int val;
969
970 val = 0;
971 spin_lock_irq(&chip->reg_lock);
972 for (i = 0; i < 4; i++)
973 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
974 change = val != chip->dig_status;
975 chip->dig_status = val;
976 spin_unlock_irq(&chip->reg_lock);
977 return change;
978 }
979
980 static struct snd_kcontrol_new snd_cmipci_spdif_default __devinitdata =
981 {
982 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
983 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
984 .info = snd_cmipci_spdif_default_info,
985 .get = snd_cmipci_spdif_default_get,
986 .put = snd_cmipci_spdif_default_put
987 };
988
989 static int snd_cmipci_spdif_mask_info(struct snd_kcontrol *kcontrol,
990 struct snd_ctl_elem_info *uinfo)
991 {
992 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
993 uinfo->count = 1;
994 return 0;
995 }
996
997 static int snd_cmipci_spdif_mask_get(struct snd_kcontrol *kcontrol,
998 struct snd_ctl_elem_value *ucontrol)
999 {
1000 ucontrol->value.iec958.status[0] = 0xff;
1001 ucontrol->value.iec958.status[1] = 0xff;
1002 ucontrol->value.iec958.status[2] = 0xff;
1003 ucontrol->value.iec958.status[3] = 0xff;
1004 return 0;
1005 }
1006
1007 static struct snd_kcontrol_new snd_cmipci_spdif_mask __devinitdata =
1008 {
1009 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1010 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1011 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
1012 .info = snd_cmipci_spdif_mask_info,
1013 .get = snd_cmipci_spdif_mask_get,
1014 };
1015
1016 static int snd_cmipci_spdif_stream_info(struct snd_kcontrol *kcontrol,
1017 struct snd_ctl_elem_info *uinfo)
1018 {
1019 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1020 uinfo->count = 1;
1021 return 0;
1022 }
1023
1024 static int snd_cmipci_spdif_stream_get(struct snd_kcontrol *kcontrol,
1025 struct snd_ctl_elem_value *ucontrol)
1026 {
1027 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1028 int i;
1029
1030 spin_lock_irq(&chip->reg_lock);
1031 for (i = 0; i < 4; i++)
1032 ucontrol->value.iec958.status[i] = (chip->dig_pcm_status >> (i * 8)) & 0xff;
1033 spin_unlock_irq(&chip->reg_lock);
1034 return 0;
1035 }
1036
1037 static int snd_cmipci_spdif_stream_put(struct snd_kcontrol *kcontrol,
1038 struct snd_ctl_elem_value *ucontrol)
1039 {
1040 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1041 int i, change;
1042 unsigned int val;
1043
1044 val = 0;
1045 spin_lock_irq(&chip->reg_lock);
1046 for (i = 0; i < 4; i++)
1047 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
1048 change = val != chip->dig_pcm_status;
1049 chip->dig_pcm_status = val;
1050 spin_unlock_irq(&chip->reg_lock);
1051 return change;
1052 }
1053
1054 static struct snd_kcontrol_new snd_cmipci_spdif_stream __devinitdata =
1055 {
1056 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
1057 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1058 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1059 .info = snd_cmipci_spdif_stream_info,
1060 .get = snd_cmipci_spdif_stream_get,
1061 .put = snd_cmipci_spdif_stream_put
1062 };
1063
1064 /*
1065 */
1066
1067 /* save mixer setting and mute for AC3 playback */
1068 static int save_mixer_state(struct cmipci *cm)
1069 {
1070 if (! cm->mixer_insensitive) {
1071 struct snd_ctl_elem_value *val;
1072 unsigned int i;
1073
1074 val = kmalloc(sizeof(*val), GFP_ATOMIC);
1075 if (!val)
1076 return -ENOMEM;
1077 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1078 struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1079 if (ctl) {
1080 int event;
1081 memset(val, 0, sizeof(*val));
1082 ctl->get(ctl, val);
1083 cm->mixer_res_status[i] = val->value.integer.value[0];
1084 val->value.integer.value[0] = cm_saved_mixer[i].toggle_on;
1085 event = SNDRV_CTL_EVENT_MASK_INFO;
1086 if (cm->mixer_res_status[i] != val->value.integer.value[0]) {
1087 ctl->put(ctl, val); /* toggle */
1088 event |= SNDRV_CTL_EVENT_MASK_VALUE;
1089 }
1090 ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1091 snd_ctl_notify(cm->card, event, &ctl->id);
1092 }
1093 }
1094 kfree(val);
1095 cm->mixer_insensitive = 1;
1096 }
1097 return 0;
1098 }
1099
1100
1101 /* restore the previously saved mixer status */
1102 static void restore_mixer_state(struct cmipci *cm)
1103 {
1104 if (cm->mixer_insensitive) {
1105 struct snd_ctl_elem_value *val;
1106 unsigned int i;
1107
1108 val = kmalloc(sizeof(*val), GFP_KERNEL);
1109 if (!val)
1110 return;
1111 cm->mixer_insensitive = 0; /* at first clear this;
1112 otherwise the changes will be ignored */
1113 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1114 struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1115 if (ctl) {
1116 int event;
1117
1118 memset(val, 0, sizeof(*val));
1119 ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1120 ctl->get(ctl, val);
1121 event = SNDRV_CTL_EVENT_MASK_INFO;
1122 if (val->value.integer.value[0] != cm->mixer_res_status[i]) {
1123 val->value.integer.value[0] = cm->mixer_res_status[i];
1124 ctl->put(ctl, val);
1125 event |= SNDRV_CTL_EVENT_MASK_VALUE;
1126 }
1127 snd_ctl_notify(cm->card, event, &ctl->id);
1128 }
1129 }
1130 kfree(val);
1131 }
1132 }
1133
1134 /* spinlock held! */
1135 static void setup_ac3(struct cmipci *cm, struct snd_pcm_substream *subs, int do_ac3, int rate)
1136 {
1137 if (do_ac3) {
1138 /* AC3EN for 037 */
1139 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1140 /* AC3EN for 039 */
1141 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1142
1143 if (cm->can_ac3_hw) {
1144 /* SPD24SEL for 037, 0x02 */
1145 /* SPD24SEL for 039, 0x20, but cannot be set */
1146 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1147 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1148 } else { /* can_ac3_sw */
1149 /* SPD32SEL for 037 & 039, 0x20 */
1150 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1151 /* set 176K sample rate to fix 033 HW bug */
1152 if (cm->chip_version == 33) {
1153 if (rate >= 48000) {
1154 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1155 } else {
1156 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1157 }
1158 }
1159 }
1160
1161 } else {
1162 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1163 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1164
1165 if (cm->can_ac3_hw) {
1166 /* chip model >= 37 */
1167 if (snd_pcm_format_width(subs->runtime->format) > 16) {
1168 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1169 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1170 } else {
1171 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1172 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1173 }
1174 } else {
1175 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1176 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1177 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1178 }
1179 }
1180 }
1181
1182 static int setup_spdif_playback(struct cmipci *cm, struct snd_pcm_substream *subs, int up, int do_ac3)
1183 {
1184 int rate, err;
1185
1186 rate = subs->runtime->rate;
1187
1188 if (up && do_ac3)
1189 if ((err = save_mixer_state(cm)) < 0)
1190 return err;
1191
1192 spin_lock_irq(&cm->reg_lock);
1193 cm->spdif_playback_avail = up;
1194 if (up) {
1195 /* they are controlled via "IEC958 Output Switch" */
1196 /* snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1197 /* snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1198 if (cm->spdif_playback_enabled)
1199 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1200 setup_ac3(cm, subs, do_ac3, rate);
1201
1202 if (rate == 48000)
1203 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1204 else
1205 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1206
1207 } else {
1208 /* they are controlled via "IEC958 Output Switch" */
1209 /* snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1210 /* snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1211 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1212 setup_ac3(cm, subs, 0, 0);
1213 }
1214 spin_unlock_irq(&cm->reg_lock);
1215 return 0;
1216 }
1217
1218
1219 /*
1220 * preparation
1221 */
1222
1223 /* playback - enable spdif only on the certain condition */
1224 static int snd_cmipci_playback_prepare(struct snd_pcm_substream *substream)
1225 {
1226 struct cmipci *cm = snd_pcm_substream_chip(substream);
1227 int rate = substream->runtime->rate;
1228 int err, do_spdif, do_ac3 = 0;
1229
1230 do_spdif = ((rate == 44100 || rate == 48000) &&
1231 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE &&
1232 substream->runtime->channels == 2);
1233 if (do_spdif && cm->can_ac3_hw)
1234 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1235 if ((err = setup_spdif_playback(cm, substream, do_spdif, do_ac3)) < 0)
1236 return err;
1237 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1238 }
1239
1240 /* playback (via device #2) - enable spdif always */
1241 static int snd_cmipci_playback_spdif_prepare(struct snd_pcm_substream *substream)
1242 {
1243 struct cmipci *cm = snd_pcm_substream_chip(substream);
1244 int err, do_ac3;
1245
1246 if (cm->can_ac3_hw)
1247 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1248 else
1249 do_ac3 = 1; /* doesn't matter */
1250 if ((err = setup_spdif_playback(cm, substream, 1, do_ac3)) < 0)
1251 return err;
1252 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1253 }
1254
1255 static int snd_cmipci_playback_hw_free(struct snd_pcm_substream *substream)
1256 {
1257 struct cmipci *cm = snd_pcm_substream_chip(substream);
1258 setup_spdif_playback(cm, substream, 0, 0);
1259 restore_mixer_state(cm);
1260 return snd_cmipci_hw_free(substream);
1261 }
1262
1263 /* capture */
1264 static int snd_cmipci_capture_prepare(struct snd_pcm_substream *substream)
1265 {
1266 struct cmipci *cm = snd_pcm_substream_chip(substream);
1267 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1268 }
1269
1270 /* capture with spdif (via device #2) */
1271 static int snd_cmipci_capture_spdif_prepare(struct snd_pcm_substream *substream)
1272 {
1273 struct cmipci *cm = snd_pcm_substream_chip(substream);
1274
1275 spin_lock_irq(&cm->reg_lock);
1276 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1277 spin_unlock_irq(&cm->reg_lock);
1278
1279 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1280 }
1281
1282 static int snd_cmipci_capture_spdif_hw_free(struct snd_pcm_substream *subs)
1283 {
1284 struct cmipci *cm = snd_pcm_substream_chip(subs);
1285
1286 spin_lock_irq(&cm->reg_lock);
1287 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1288 spin_unlock_irq(&cm->reg_lock);
1289
1290 return snd_cmipci_hw_free(subs);
1291 }
1292
1293
1294 /*
1295 * interrupt handler
1296 */
1297 static irqreturn_t snd_cmipci_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1298 {
1299 struct cmipci *cm = dev_id;
1300 unsigned int status, mask = 0;
1301
1302 /* fastpath out, to ease interrupt sharing */
1303 status = snd_cmipci_read(cm, CM_REG_INT_STATUS);
1304 if (!(status & CM_INTR))
1305 return IRQ_NONE;
1306
1307 /* acknowledge interrupt */
1308 spin_lock(&cm->reg_lock);
1309 if (status & CM_CHINT0)
1310 mask |= CM_CH0_INT_EN;
1311 if (status & CM_CHINT1)
1312 mask |= CM_CH1_INT_EN;
1313 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, mask);
1314 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, mask);
1315 spin_unlock(&cm->reg_lock);
1316
1317 if (cm->rmidi && (status & CM_UARTINT))
1318 snd_mpu401_uart_interrupt(irq, cm->rmidi->private_data, regs);
1319
1320 if (cm->pcm) {
1321 if ((status & CM_CHINT0) && cm->channel[0].running)
1322 snd_pcm_period_elapsed(cm->channel[0].substream);
1323 if ((status & CM_CHINT1) && cm->channel[1].running)
1324 snd_pcm_period_elapsed(cm->channel[1].substream);
1325 }
1326 return IRQ_HANDLED;
1327 }
1328
1329 /*
1330 * h/w infos
1331 */
1332
1333 /* playback on channel A */
1334 static struct snd_pcm_hardware snd_cmipci_playback =
1335 {
1336 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1337 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1338 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1339 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1340 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1341 .rate_min = 5512,
1342 .rate_max = 48000,
1343 .channels_min = 1,
1344 .channels_max = 2,
1345 .buffer_bytes_max = (128*1024),
1346 .period_bytes_min = 64,
1347 .period_bytes_max = (128*1024),
1348 .periods_min = 2,
1349 .periods_max = 1024,
1350 .fifo_size = 0,
1351 };
1352
1353 /* capture on channel B */
1354 static struct snd_pcm_hardware snd_cmipci_capture =
1355 {
1356 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1357 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1358 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1359 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1360 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1361 .rate_min = 5512,
1362 .rate_max = 48000,
1363 .channels_min = 1,
1364 .channels_max = 2,
1365 .buffer_bytes_max = (128*1024),
1366 .period_bytes_min = 64,
1367 .period_bytes_max = (128*1024),
1368 .periods_min = 2,
1369 .periods_max = 1024,
1370 .fifo_size = 0,
1371 };
1372
1373 /* playback on channel B - stereo 16bit only? */
1374 static struct snd_pcm_hardware snd_cmipci_playback2 =
1375 {
1376 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1377 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1378 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1379 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1380 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1381 .rate_min = 5512,
1382 .rate_max = 48000,
1383 .channels_min = 2,
1384 .channels_max = 2,
1385 .buffer_bytes_max = (128*1024),
1386 .period_bytes_min = 64,
1387 .period_bytes_max = (128*1024),
1388 .periods_min = 2,
1389 .periods_max = 1024,
1390 .fifo_size = 0,
1391 };
1392
1393 /* spdif playback on channel A */
1394 static struct snd_pcm_hardware snd_cmipci_playback_spdif =
1395 {
1396 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1397 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1398 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1399 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1400 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1401 .rate_min = 44100,
1402 .rate_max = 48000,
1403 .channels_min = 2,
1404 .channels_max = 2,
1405 .buffer_bytes_max = (128*1024),
1406 .period_bytes_min = 64,
1407 .period_bytes_max = (128*1024),
1408 .periods_min = 2,
1409 .periods_max = 1024,
1410 .fifo_size = 0,
1411 };
1412
1413 /* spdif playback on channel A (32bit, IEC958 subframes) */
1414 static struct snd_pcm_hardware snd_cmipci_playback_iec958_subframe =
1415 {
1416 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1417 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1418 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1419 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1420 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1421 .rate_min = 44100,
1422 .rate_max = 48000,
1423 .channels_min = 2,
1424 .channels_max = 2,
1425 .buffer_bytes_max = (128*1024),
1426 .period_bytes_min = 64,
1427 .period_bytes_max = (128*1024),
1428 .periods_min = 2,
1429 .periods_max = 1024,
1430 .fifo_size = 0,
1431 };
1432
1433 /* spdif capture on channel B */
1434 static struct snd_pcm_hardware snd_cmipci_capture_spdif =
1435 {
1436 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1437 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1438 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1439 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1440 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1441 .rate_min = 44100,
1442 .rate_max = 48000,
1443 .channels_min = 2,
1444 .channels_max = 2,
1445 .buffer_bytes_max = (128*1024),
1446 .period_bytes_min = 64,
1447 .period_bytes_max = (128*1024),
1448 .periods_min = 2,
1449 .periods_max = 1024,
1450 .fifo_size = 0,
1451 };
1452
1453 /*
1454 * check device open/close
1455 */
1456 static int open_device_check(struct cmipci *cm, int mode, struct snd_pcm_substream *subs)
1457 {
1458 int ch = mode & CM_OPEN_CH_MASK;
1459
1460 /* FIXME: a file should wait until the device becomes free
1461 * when it's opened on blocking mode. however, since the current
1462 * pcm framework doesn't pass file pointer before actually opened,
1463 * we can't know whether blocking mode or not in open callback..
1464 */
1465 mutex_lock(&cm->open_mutex);
1466 if (cm->opened[ch]) {
1467 mutex_unlock(&cm->open_mutex);
1468 return -EBUSY;
1469 }
1470 cm->opened[ch] = mode;
1471 cm->channel[ch].substream = subs;
1472 if (! (mode & CM_OPEN_DAC)) {
1473 /* disable dual DAC mode */
1474 cm->channel[ch].is_dac = 0;
1475 spin_lock_irq(&cm->reg_lock);
1476 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1477 spin_unlock_irq(&cm->reg_lock);
1478 }
1479 mutex_unlock(&cm->open_mutex);
1480 return 0;
1481 }
1482
1483 static void close_device_check(struct cmipci *cm, int mode)
1484 {
1485 int ch = mode & CM_OPEN_CH_MASK;
1486
1487 mutex_lock(&cm->open_mutex);
1488 if (cm->opened[ch] == mode) {
1489 if (cm->channel[ch].substream) {
1490 snd_cmipci_ch_reset(cm, ch);
1491 cm->channel[ch].running = 0;
1492 cm->channel[ch].substream = NULL;
1493 }
1494 cm->opened[ch] = 0;
1495 if (! cm->channel[ch].is_dac) {
1496 /* enable dual DAC mode again */
1497 cm->channel[ch].is_dac = 1;
1498 spin_lock_irq(&cm->reg_lock);
1499 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1500 spin_unlock_irq(&cm->reg_lock);
1501 }
1502 }
1503 mutex_unlock(&cm->open_mutex);
1504 }
1505
1506 /*
1507 */
1508
1509 static int snd_cmipci_playback_open(struct snd_pcm_substream *substream)
1510 {
1511 struct cmipci *cm = snd_pcm_substream_chip(substream);
1512 struct snd_pcm_runtime *runtime = substream->runtime;
1513 int err;
1514
1515 if ((err = open_device_check(cm, CM_OPEN_PLAYBACK, substream)) < 0)
1516 return err;
1517 runtime->hw = snd_cmipci_playback;
1518 runtime->hw.channels_max = cm->max_channels;
1519 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1520 cm->dig_pcm_status = cm->dig_status;
1521 return 0;
1522 }
1523
1524 static int snd_cmipci_capture_open(struct snd_pcm_substream *substream)
1525 {
1526 struct cmipci *cm = snd_pcm_substream_chip(substream);
1527 struct snd_pcm_runtime *runtime = substream->runtime;
1528 int err;
1529
1530 if ((err = open_device_check(cm, CM_OPEN_CAPTURE, substream)) < 0)
1531 return err;
1532 runtime->hw = snd_cmipci_capture;
1533 if (cm->chip_version == 68) { // 8768 only supports 44k/48k recording
1534 runtime->hw.rate_min = 41000;
1535 runtime->hw.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000;
1536 }
1537 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1538 return 0;
1539 }
1540
1541 static int snd_cmipci_playback2_open(struct snd_pcm_substream *substream)
1542 {
1543 struct cmipci *cm = snd_pcm_substream_chip(substream);
1544 struct snd_pcm_runtime *runtime = substream->runtime;
1545 int err;
1546
1547 if ((err = open_device_check(cm, CM_OPEN_PLAYBACK2, substream)) < 0) /* use channel B */
1548 return err;
1549 runtime->hw = snd_cmipci_playback2;
1550 mutex_lock(&cm->open_mutex);
1551 if (! cm->opened[CM_CH_PLAY]) {
1552 if (cm->can_multi_ch) {
1553 runtime->hw.channels_max = cm->max_channels;
1554 if (cm->max_channels == 4)
1555 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_4);
1556 else if (cm->max_channels == 6)
1557 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_6);
1558 else if (cm->max_channels == 8)
1559 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_8);
1560 }
1561 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1562 }
1563 mutex_unlock(&cm->open_mutex);
1564 return 0;
1565 }
1566
1567 static int snd_cmipci_playback_spdif_open(struct snd_pcm_substream *substream)
1568 {
1569 struct cmipci *cm = snd_pcm_substream_chip(substream);
1570 struct snd_pcm_runtime *runtime = substream->runtime;
1571 int err;
1572
1573 if ((err = open_device_check(cm, CM_OPEN_SPDIF_PLAYBACK, substream)) < 0) /* use channel A */
1574 return err;
1575 if (cm->can_ac3_hw) {
1576 runtime->hw = snd_cmipci_playback_spdif;
1577 if (cm->chip_version >= 37)
1578 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1579 } else {
1580 runtime->hw = snd_cmipci_playback_iec958_subframe;
1581 }
1582 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1583 cm->dig_pcm_status = cm->dig_status;
1584 return 0;
1585 }
1586
1587 static int snd_cmipci_capture_spdif_open(struct snd_pcm_substream *substream)
1588 {
1589 struct cmipci *cm = snd_pcm_substream_chip(substream);
1590 struct snd_pcm_runtime *runtime = substream->runtime;
1591 int err;
1592
1593 if ((err = open_device_check(cm, CM_OPEN_SPDIF_CAPTURE, substream)) < 0) /* use channel B */
1594 return err;
1595 runtime->hw = snd_cmipci_capture_spdif;
1596 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1597 return 0;
1598 }
1599
1600
1601 /*
1602 */
1603
1604 static int snd_cmipci_playback_close(struct snd_pcm_substream *substream)
1605 {
1606 struct cmipci *cm = snd_pcm_substream_chip(substream);
1607 close_device_check(cm, CM_OPEN_PLAYBACK);
1608 return 0;
1609 }
1610
1611 static int snd_cmipci_capture_close(struct snd_pcm_substream *substream)
1612 {
1613 struct cmipci *cm = snd_pcm_substream_chip(substream);
1614 close_device_check(cm, CM_OPEN_CAPTURE);
1615 return 0;
1616 }
1617
1618 static int snd_cmipci_playback2_close(struct snd_pcm_substream *substream)
1619 {
1620 struct cmipci *cm = snd_pcm_substream_chip(substream);
1621 close_device_check(cm, CM_OPEN_PLAYBACK2);
1622 close_device_check(cm, CM_OPEN_PLAYBACK_MULTI);
1623 return 0;
1624 }
1625
1626 static int snd_cmipci_playback_spdif_close(struct snd_pcm_substream *substream)
1627 {
1628 struct cmipci *cm = snd_pcm_substream_chip(substream);
1629 close_device_check(cm, CM_OPEN_SPDIF_PLAYBACK);
1630 return 0;
1631 }
1632
1633 static int snd_cmipci_capture_spdif_close(struct snd_pcm_substream *substream)
1634 {
1635 struct cmipci *cm = snd_pcm_substream_chip(substream);
1636 close_device_check(cm, CM_OPEN_SPDIF_CAPTURE);
1637 return 0;
1638 }
1639
1640
1641 /*
1642 */
1643
1644 static struct snd_pcm_ops snd_cmipci_playback_ops = {
1645 .open = snd_cmipci_playback_open,
1646 .close = snd_cmipci_playback_close,
1647 .ioctl = snd_pcm_lib_ioctl,
1648 .hw_params = snd_cmipci_hw_params,
1649 .hw_free = snd_cmipci_playback_hw_free,
1650 .prepare = snd_cmipci_playback_prepare,
1651 .trigger = snd_cmipci_playback_trigger,
1652 .pointer = snd_cmipci_playback_pointer,
1653 };
1654
1655 static struct snd_pcm_ops snd_cmipci_capture_ops = {
1656 .open = snd_cmipci_capture_open,
1657 .close = snd_cmipci_capture_close,
1658 .ioctl = snd_pcm_lib_ioctl,
1659 .hw_params = snd_cmipci_hw_params,
1660 .hw_free = snd_cmipci_hw_free,
1661 .prepare = snd_cmipci_capture_prepare,
1662 .trigger = snd_cmipci_capture_trigger,
1663 .pointer = snd_cmipci_capture_pointer,
1664 };
1665
1666 static struct snd_pcm_ops snd_cmipci_playback2_ops = {
1667 .open = snd_cmipci_playback2_open,
1668 .close = snd_cmipci_playback2_close,
1669 .ioctl = snd_pcm_lib_ioctl,
1670 .hw_params = snd_cmipci_playback2_hw_params,
1671 .hw_free = snd_cmipci_hw_free,
1672 .prepare = snd_cmipci_capture_prepare, /* channel B */
1673 .trigger = snd_cmipci_capture_trigger, /* channel B */
1674 .pointer = snd_cmipci_capture_pointer, /* channel B */
1675 };
1676
1677 static struct snd_pcm_ops snd_cmipci_playback_spdif_ops = {
1678 .open = snd_cmipci_playback_spdif_open,
1679 .close = snd_cmipci_playback_spdif_close,
1680 .ioctl = snd_pcm_lib_ioctl,
1681 .hw_params = snd_cmipci_hw_params,
1682 .hw_free = snd_cmipci_playback_hw_free,
1683 .prepare = snd_cmipci_playback_spdif_prepare, /* set up rate */
1684 .trigger = snd_cmipci_playback_trigger,
1685 .pointer = snd_cmipci_playback_pointer,
1686 };
1687
1688 static struct snd_pcm_ops snd_cmipci_capture_spdif_ops = {
1689 .open = snd_cmipci_capture_spdif_open,
1690 .close = snd_cmipci_capture_spdif_close,
1691 .ioctl = snd_pcm_lib_ioctl,
1692 .hw_params = snd_cmipci_hw_params,
1693 .hw_free = snd_cmipci_capture_spdif_hw_free,
1694 .prepare = snd_cmipci_capture_spdif_prepare,
1695 .trigger = snd_cmipci_capture_trigger,
1696 .pointer = snd_cmipci_capture_pointer,
1697 };
1698
1699
1700 /*
1701 */
1702
1703 static int __devinit snd_cmipci_pcm_new(struct cmipci *cm, int device)
1704 {
1705 struct snd_pcm *pcm;
1706 int err;
1707
1708 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1709 if (err < 0)
1710 return err;
1711
1712 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_ops);
1713 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_ops);
1714
1715 pcm->private_data = cm;
1716 pcm->info_flags = 0;
1717 strcpy(pcm->name, "C-Media PCI DAC/ADC");
1718 cm->pcm = pcm;
1719
1720 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1721 snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1722
1723 return 0;
1724 }
1725
1726 static int __devinit snd_cmipci_pcm2_new(struct cmipci *cm, int device)
1727 {
1728 struct snd_pcm *pcm;
1729 int err;
1730
1731 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 0, &pcm);
1732 if (err < 0)
1733 return err;
1734
1735 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback2_ops);
1736
1737 pcm->private_data = cm;
1738 pcm->info_flags = 0;
1739 strcpy(pcm->name, "C-Media PCI 2nd DAC");
1740 cm->pcm2 = pcm;
1741
1742 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1743 snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1744
1745 return 0;
1746 }
1747
1748 static int __devinit snd_cmipci_pcm_spdif_new(struct cmipci *cm, int device)
1749 {
1750 struct snd_pcm *pcm;
1751 int err;
1752
1753 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1754 if (err < 0)
1755 return err;
1756
1757 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_spdif_ops);
1758 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_spdif_ops);
1759
1760 pcm->private_data = cm;
1761 pcm->info_flags = 0;
1762 strcpy(pcm->name, "C-Media PCI IEC958");
1763 cm->pcm_spdif = pcm;
1764
1765 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1766 snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1767
1768 return 0;
1769 }
1770
1771 /*
1772 * mixer interface:
1773 * - CM8338/8738 has a compatible mixer interface with SB16, but
1774 * lack of some elements like tone control, i/o gain and AGC.
1775 * - Access to native registers:
1776 * - A 3D switch
1777 * - Output mute switches
1778 */
1779
1780 static void snd_cmipci_mixer_write(struct cmipci *s, unsigned char idx, unsigned char data)
1781 {
1782 outb(idx, s->iobase + CM_REG_SB16_ADDR);
1783 outb(data, s->iobase + CM_REG_SB16_DATA);
1784 }
1785
1786 static unsigned char snd_cmipci_mixer_read(struct cmipci *s, unsigned char idx)
1787 {
1788 unsigned char v;
1789
1790 outb(idx, s->iobase + CM_REG_SB16_ADDR);
1791 v = inb(s->iobase + CM_REG_SB16_DATA);
1792 return v;
1793 }
1794
1795 /*
1796 * general mixer element
1797 */
1798 struct cmipci_sb_reg {
1799 unsigned int left_reg, right_reg;
1800 unsigned int left_shift, right_shift;
1801 unsigned int mask;
1802 unsigned int invert: 1;
1803 unsigned int stereo: 1;
1804 };
1805
1806 #define COMPOSE_SB_REG(lreg,rreg,lshift,rshift,mask,invert,stereo) \
1807 ((lreg) | ((rreg) << 8) | (lshift << 16) | (rshift << 19) | (mask << 24) | (invert << 22) | (stereo << 23))
1808
1809 #define CMIPCI_DOUBLE(xname, left_reg, right_reg, left_shift, right_shift, mask, invert, stereo) \
1810 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1811 .info = snd_cmipci_info_volume, \
1812 .get = snd_cmipci_get_volume, .put = snd_cmipci_put_volume, \
1813 .private_value = COMPOSE_SB_REG(left_reg, right_reg, left_shift, right_shift, mask, invert, stereo), \
1814 }
1815
1816 #define CMIPCI_SB_VOL_STEREO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg+1, shift, shift, mask, 0, 1)
1817 #define CMIPCI_SB_VOL_MONO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg, shift, shift, mask, 0, 0)
1818 #define CMIPCI_SB_SW_STEREO(xname,lshift,rshift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, lshift, rshift, 1, 0, 1)
1819 #define CMIPCI_SB_SW_MONO(xname,shift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, shift, shift, 1, 0, 0)
1820
1821 static void cmipci_sb_reg_decode(struct cmipci_sb_reg *r, unsigned long val)
1822 {
1823 r->left_reg = val & 0xff;
1824 r->right_reg = (val >> 8) & 0xff;
1825 r->left_shift = (val >> 16) & 0x07;
1826 r->right_shift = (val >> 19) & 0x07;
1827 r->invert = (val >> 22) & 1;
1828 r->stereo = (val >> 23) & 1;
1829 r->mask = (val >> 24) & 0xff;
1830 }
1831
1832 static int snd_cmipci_info_volume(struct snd_kcontrol *kcontrol,
1833 struct snd_ctl_elem_info *uinfo)
1834 {
1835 struct cmipci_sb_reg reg;
1836
1837 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1838 uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
1839 uinfo->count = reg.stereo + 1;
1840 uinfo->value.integer.min = 0;
1841 uinfo->value.integer.max = reg.mask;
1842 return 0;
1843 }
1844
1845 static int snd_cmipci_get_volume(struct snd_kcontrol *kcontrol,
1846 struct snd_ctl_elem_value *ucontrol)
1847 {
1848 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
1849 struct cmipci_sb_reg reg;
1850 int val;
1851
1852 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1853 spin_lock_irq(&cm->reg_lock);
1854 val = (snd_cmipci_mixer_read(cm, reg.left_reg) >> reg.left_shift) & reg.mask;
1855 if (reg.invert)
1856 val = reg.mask - val;
1857 ucontrol->value.integer.value[0] = val;
1858 if (reg.stereo) {
1859 val = (snd_cmipci_mixer_read(cm, reg.right_reg) >> reg.right_shift) & reg.mask;
1860 if (reg.invert)
1861 val = reg.mask - val;
1862 ucontrol->value.integer.value[1] = val;
1863 }
1864 spin_unlock_irq(&cm->reg_lock);
1865 return 0;
1866 }
1867
1868 static int snd_cmipci_put_volume(struct snd_kcontrol *kcontrol,
1869 struct snd_ctl_elem_value *ucontrol)
1870 {
1871 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
1872 struct cmipci_sb_reg reg;
1873 int change;
1874 int left, right, oleft, oright;
1875
1876 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1877 left = ucontrol->value.integer.value[0] & reg.mask;
1878 if (reg.invert)
1879 left = reg.mask - left;
1880 left <<= reg.left_shift;
1881 if (reg.stereo) {
1882 right = ucontrol->value.integer.value[1] & reg.mask;
1883 if (reg.invert)
1884 right = reg.mask - right;
1885 right <<= reg.right_shift;
1886 } else
1887 right = 0;
1888 spin_lock_irq(&cm->reg_lock);
1889 oleft = snd_cmipci_mixer_read(cm, reg.left_reg);
1890 left |= oleft & ~(reg.mask << reg.left_shift);
1891 change = left != oleft;
1892 if (reg.stereo) {
1893 if (reg.left_reg != reg.right_reg) {
1894 snd_cmipci_mixer_write(cm, reg.left_reg, left);
1895 oright = snd_cmipci_mixer_read(cm, reg.right_reg);
1896 } else
1897 oright = left;
1898 right |= oright & ~(reg.mask << reg.right_shift);
1899 change |= right != oright;
1900 snd_cmipci_mixer_write(cm, reg.right_reg, right);
1901 } else
1902 snd_cmipci_mixer_write(cm, reg.left_reg, left);
1903 spin_unlock_irq(&cm->reg_lock);
1904 return change;
1905 }
1906
1907 /*
1908 * input route (left,right) -> (left,right)
1909 */
1910 #define CMIPCI_SB_INPUT_SW(xname, left_shift, right_shift) \
1911 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1912 .info = snd_cmipci_info_input_sw, \
1913 .get = snd_cmipci_get_input_sw, .put = snd_cmipci_put_input_sw, \
1914 .private_value = COMPOSE_SB_REG(SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, left_shift, right_shift, 1, 0, 1), \
1915 }
1916
1917 static int snd_cmipci_info_input_sw(struct snd_kcontrol *kcontrol,
1918 struct snd_ctl_elem_info *uinfo)
1919 {
1920 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1921 uinfo->count = 4;
1922 uinfo->value.integer.min = 0;
1923 uinfo->value.integer.max = 1;
1924 return 0;
1925 }
1926
1927 static int snd_cmipci_get_input_sw(struct snd_kcontrol *kcontrol,
1928 struct snd_ctl_elem_value *ucontrol)
1929 {
1930 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
1931 struct cmipci_sb_reg reg;
1932 int val1, val2;
1933
1934 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1935 spin_lock_irq(&cm->reg_lock);
1936 val1 = snd_cmipci_mixer_read(cm, reg.left_reg);
1937 val2 = snd_cmipci_mixer_read(cm, reg.right_reg);
1938 spin_unlock_irq(&cm->reg_lock);
1939 ucontrol->value.integer.value[0] = (val1 >> reg.left_shift) & 1;
1940 ucontrol->value.integer.value[1] = (val2 >> reg.left_shift) & 1;
1941 ucontrol->value.integer.value[2] = (val1 >> reg.right_shift) & 1;
1942 ucontrol->value.integer.value[3] = (val2 >> reg.right_shift) & 1;
1943 return 0;
1944 }
1945
1946 static int snd_cmipci_put_input_sw(struct snd_kcontrol *kcontrol,
1947 struct snd_ctl_elem_value *ucontrol)
1948 {
1949 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
1950 struct cmipci_sb_reg reg;
1951 int change;
1952 int val1, val2, oval1, oval2;
1953
1954 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1955 spin_lock_irq(&cm->reg_lock);
1956 oval1 = snd_cmipci_mixer_read(cm, reg.left_reg);
1957 oval2 = snd_cmipci_mixer_read(cm, reg.right_reg);
1958 val1 = oval1 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
1959 val2 = oval2 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
1960 val1 |= (ucontrol->value.integer.value[0] & 1) << reg.left_shift;
1961 val2 |= (ucontrol->value.integer.value[1] & 1) << reg.left_shift;
1962 val1 |= (ucontrol->value.integer.value[2] & 1) << reg.right_shift;
1963 val2 |= (ucontrol->value.integer.value[3] & 1) << reg.right_shift;
1964 change = val1 != oval1 || val2 != oval2;
1965 snd_cmipci_mixer_write(cm, reg.left_reg, val1);
1966 snd_cmipci_mixer_write(cm, reg.right_reg, val2);
1967 spin_unlock_irq(&cm->reg_lock);
1968 return change;
1969 }
1970
1971 /*
1972 * native mixer switches/volumes
1973 */
1974
1975 #define CMIPCI_MIXER_SW_STEREO(xname, reg, lshift, rshift, invert) \
1976 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1977 .info = snd_cmipci_info_native_mixer, \
1978 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
1979 .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, 1, invert, 1), \
1980 }
1981
1982 #define CMIPCI_MIXER_SW_MONO(xname, reg, shift, invert) \
1983 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1984 .info = snd_cmipci_info_native_mixer, \
1985 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
1986 .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, 1, invert, 0), \
1987 }
1988
1989 #define CMIPCI_MIXER_VOL_STEREO(xname, reg, lshift, rshift, mask) \
1990 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1991 .info = snd_cmipci_info_native_mixer, \
1992 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
1993 .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, mask, 0, 1), \
1994 }
1995
1996 #define CMIPCI_MIXER_VOL_MONO(xname, reg, shift, mask) \
1997 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1998 .info = snd_cmipci_info_native_mixer, \
1999 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2000 .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, mask, 0, 0), \
2001 }
2002
2003 static int snd_cmipci_info_native_mixer(struct snd_kcontrol *kcontrol,
2004 struct snd_ctl_elem_info *uinfo)
2005 {
2006 struct cmipci_sb_reg reg;
2007
2008 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2009 uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2010 uinfo->count = reg.stereo + 1;
2011 uinfo->value.integer.min = 0;
2012 uinfo->value.integer.max = reg.mask;
2013 return 0;
2014
2015 }
2016
2017 static int snd_cmipci_get_native_mixer(struct snd_kcontrol *kcontrol,
2018 struct snd_ctl_elem_value *ucontrol)
2019 {
2020 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2021 struct cmipci_sb_reg reg;
2022 unsigned char oreg, val;
2023
2024 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2025 spin_lock_irq(&cm->reg_lock);
2026 oreg = inb(cm->iobase + reg.left_reg);
2027 val = (oreg >> reg.left_shift) & reg.mask;
2028 if (reg.invert)
2029 val = reg.mask - val;
2030 ucontrol->value.integer.value[0] = val;
2031 if (reg.stereo) {
2032 val = (oreg >> reg.right_shift) & reg.mask;
2033 if (reg.invert)
2034 val = reg.mask - val;
2035 ucontrol->value.integer.value[1] = val;
2036 }
2037 spin_unlock_irq(&cm->reg_lock);
2038 return 0;
2039 }
2040
2041 static int snd_cmipci_put_native_mixer(struct snd_kcontrol *kcontrol,
2042 struct snd_ctl_elem_value *ucontrol)
2043 {
2044 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2045 struct cmipci_sb_reg reg;
2046 unsigned char oreg, nreg, val;
2047
2048 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2049 spin_lock_irq(&cm->reg_lock);
2050 oreg = inb(cm->iobase + reg.left_reg);
2051 val = ucontrol->value.integer.value[0] & reg.mask;
2052 if (reg.invert)
2053 val = reg.mask - val;
2054 nreg = oreg & ~(reg.mask << reg.left_shift);
2055 nreg |= (val << reg.left_shift);
2056 if (reg.stereo) {
2057 val = ucontrol->value.integer.value[1] & reg.mask;
2058 if (reg.invert)
2059 val = reg.mask - val;
2060 nreg &= ~(reg.mask << reg.right_shift);
2061 nreg |= (val << reg.right_shift);
2062 }
2063 outb(nreg, cm->iobase + reg.left_reg);
2064 spin_unlock_irq(&cm->reg_lock);
2065 return (nreg != oreg);
2066 }
2067
2068 /*
2069 * special case - check mixer sensitivity
2070 */
2071 static int snd_cmipci_get_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
2072 struct snd_ctl_elem_value *ucontrol)
2073 {
2074 //struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2075 return snd_cmipci_get_native_mixer(kcontrol, ucontrol);
2076 }
2077
2078 static int snd_cmipci_put_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
2079 struct snd_ctl_elem_value *ucontrol)
2080 {
2081 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2082 if (cm->mixer_insensitive) {
2083 /* ignored */
2084 return 0;
2085 }
2086 return snd_cmipci_put_native_mixer(kcontrol, ucontrol);
2087 }
2088
2089
2090 static struct snd_kcontrol_new snd_cmipci_mixers[] __devinitdata = {
2091 CMIPCI_SB_VOL_STEREO("Master Playback Volume", SB_DSP4_MASTER_DEV, 3, 31),
2092 CMIPCI_MIXER_SW_MONO("3D Control - Switch", CM_REG_MIXER1, CM_X3DEN_SHIFT, 0),
2093 CMIPCI_SB_VOL_STEREO("PCM Playback Volume", SB_DSP4_PCM_DEV, 3, 31),
2094 //CMIPCI_MIXER_SW_MONO("PCM Playback Switch", CM_REG_MIXER1, CM_WSMUTE_SHIFT, 1),
2095 { /* switch with sensitivity */
2096 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2097 .name = "PCM Playback Switch",
2098 .info = snd_cmipci_info_native_mixer,
2099 .get = snd_cmipci_get_native_mixer_sensitive,
2100 .put = snd_cmipci_put_native_mixer_sensitive,
2101 .private_value = COMPOSE_SB_REG(CM_REG_MIXER1, CM_REG_MIXER1, CM_WSMUTE_SHIFT, CM_WSMUTE_SHIFT, 1, 1, 0),
2102 },
2103 CMIPCI_MIXER_SW_STEREO("PCM Capture Switch", CM_REG_MIXER1, CM_WAVEINL_SHIFT, CM_WAVEINR_SHIFT, 0),
2104 CMIPCI_SB_VOL_STEREO("Synth Playback Volume", SB_DSP4_SYNTH_DEV, 3, 31),
2105 CMIPCI_MIXER_SW_MONO("Synth Playback Switch", CM_REG_MIXER1, CM_FMMUTE_SHIFT, 1),
2106 CMIPCI_SB_INPUT_SW("Synth Capture Route", 6, 5),
2107 CMIPCI_SB_VOL_STEREO("CD Playback Volume", SB_DSP4_CD_DEV, 3, 31),
2108 CMIPCI_SB_SW_STEREO("CD Playback Switch", 2, 1),
2109 CMIPCI_SB_INPUT_SW("CD Capture Route", 2, 1),
2110 CMIPCI_SB_VOL_STEREO("Line Playback Volume", SB_DSP4_LINE_DEV, 3, 31),
2111 CMIPCI_SB_SW_STEREO("Line Playback Switch", 4, 3),
2112 CMIPCI_SB_INPUT_SW("Line Capture Route", 4, 3),
2113 CMIPCI_SB_VOL_MONO("Mic Playback Volume", SB_DSP4_MIC_DEV, 3, 31),
2114 CMIPCI_SB_SW_MONO("Mic Playback Switch", 0),
2115 CMIPCI_DOUBLE("Mic Capture Switch", SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, 0, 0, 1, 0, 0),
2116 CMIPCI_SB_VOL_MONO("PC Speaker Playback Volume", SB_DSP4_SPEAKER_DEV, 6, 3),
2117 CMIPCI_MIXER_VOL_STEREO("Aux Playback Volume", CM_REG_AUX_VOL, 4, 0, 15),
2118 CMIPCI_MIXER_SW_STEREO("Aux Playback Switch", CM_REG_MIXER2, CM_VAUXLM_SHIFT, CM_VAUXRM_SHIFT, 0),
2119 CMIPCI_MIXER_SW_STEREO("Aux Capture Switch", CM_REG_MIXER2, CM_RAUXLEN_SHIFT, CM_RAUXREN_SHIFT, 0),
2120 CMIPCI_MIXER_SW_MONO("Mic Boost Playback Switch", CM_REG_MIXER2, CM_MICGAINZ_SHIFT, 1),
2121 CMIPCI_MIXER_VOL_MONO("Mic Capture Volume", CM_REG_MIXER2, CM_VADMIC_SHIFT, 7),
2122 CMIPCI_SB_VOL_MONO("Phone Playback Volume", CM_REG_EXTENT_IND, 5, 7),
2123 CMIPCI_DOUBLE("Phone Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 4, 4, 1, 0, 0),
2124 CMIPCI_DOUBLE("PC Speaker Playnack Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 3, 3, 1, 0, 0),
2125 CMIPCI_DOUBLE("Mic Boost Capture Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 0, 0, 1, 0, 0),
2126 };
2127
2128 /*
2129 * other switches
2130 */
2131
2132 struct cmipci_switch_args {
2133 int reg; /* register index */
2134 unsigned int mask; /* mask bits */
2135 unsigned int mask_on; /* mask bits to turn on */
2136 unsigned int is_byte: 1; /* byte access? */
2137 unsigned int ac3_sensitive: 1; /* access forbidden during
2138 * non-audio operation?
2139 */
2140 };
2141
2142 static int snd_cmipci_uswitch_info(struct snd_kcontrol *kcontrol,
2143 struct snd_ctl_elem_info *uinfo)
2144 {
2145 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2146 uinfo->count = 1;
2147 uinfo->value.integer.min = 0;
2148 uinfo->value.integer.max = 1;
2149 return 0;
2150 }
2151
2152 static int _snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
2153 struct snd_ctl_elem_value *ucontrol,
2154 struct cmipci_switch_args *args)
2155 {
2156 unsigned int val;
2157 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2158
2159 spin_lock_irq(&cm->reg_lock);
2160 if (args->ac3_sensitive && cm->mixer_insensitive) {
2161 ucontrol->value.integer.value[0] = 0;
2162 spin_unlock_irq(&cm->reg_lock);
2163 return 0;
2164 }
2165 if (args->is_byte)
2166 val = inb(cm->iobase + args->reg);
2167 else
2168 val = snd_cmipci_read(cm, args->reg);
2169 ucontrol->value.integer.value[0] = ((val & args->mask) == args->mask_on) ? 1 : 0;
2170 spin_unlock_irq(&cm->reg_lock);
2171 return 0;
2172 }
2173
2174 static int snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
2175 struct snd_ctl_elem_value *ucontrol)
2176 {
2177 struct cmipci_switch_args *args;
2178 args = (struct cmipci_switch_args *)kcontrol->private_value;
2179 snd_assert(args != NULL, return -EINVAL);
2180 return _snd_cmipci_uswitch_get(kcontrol, ucontrol, args);
2181 }
2182
2183 static int _snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
2184 struct snd_ctl_elem_value *ucontrol,
2185 struct cmipci_switch_args *args)
2186 {
2187 unsigned int val;
2188 int change;
2189 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2190
2191 spin_lock_irq(&cm->reg_lock);
2192 if (args->ac3_sensitive && cm->mixer_insensitive) {
2193 /* ignored */
2194 spin_unlock_irq(&cm->reg_lock);
2195 return 0;
2196 }
2197 if (args->is_byte)
2198 val = inb(cm->iobase + args->reg);
2199 else
2200 val = snd_cmipci_read(cm, args->reg);
2201 change = (val & args->mask) != (ucontrol->value.integer.value[0] ? args->mask : 0);
2202 if (change) {
2203 val &= ~args->mask;
2204 if (ucontrol->value.integer.value[0])
2205 val |= args->mask_on;
2206 else
2207 val |= (args->mask & ~args->mask_on);
2208 if (args->is_byte)
2209 outb((unsigned char)val, cm->iobase + args->reg);
2210 else
2211 snd_cmipci_write(cm, args->reg, val);
2212 }
2213 spin_unlock_irq(&cm->reg_lock);
2214 return change;
2215 }
2216
2217 static int snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
2218 struct snd_ctl_elem_value *ucontrol)
2219 {
2220 struct cmipci_switch_args *args;
2221 args = (struct cmipci_switch_args *)kcontrol->private_value;
2222 snd_assert(args != NULL, return -EINVAL);
2223 return _snd_cmipci_uswitch_put(kcontrol, ucontrol, args);
2224 }
2225
2226 #define DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask_on, xis_byte, xac3) \
2227 static struct cmipci_switch_args cmipci_switch_arg_##sname = { \
2228 .reg = xreg, \
2229 .mask = xmask, \
2230 .mask_on = xmask_on, \
2231 .is_byte = xis_byte, \
2232 .ac3_sensitive = xac3, \
2233 }
2234
2235 #define DEFINE_BIT_SWITCH_ARG(sname, xreg, xmask, xis_byte, xac3) \
2236 DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask, xis_byte, xac3)
2237
2238 #if 0 /* these will be controlled in pcm device */
2239 DEFINE_BIT_SWITCH_ARG(spdif_in, CM_REG_FUNCTRL1, CM_SPDF_1, 0, 0);
2240 DEFINE_BIT_SWITCH_ARG(spdif_out, CM_REG_FUNCTRL1, CM_SPDF_0, 0, 0);
2241 #endif
2242 DEFINE_BIT_SWITCH_ARG(spdif_in_sel1, CM_REG_CHFORMAT, CM_SPDIF_SELECT1, 0, 0);
2243 DEFINE_BIT_SWITCH_ARG(spdif_in_sel2, CM_REG_MISC_CTRL, CM_SPDIF_SELECT2, 0, 0);
2244 DEFINE_BIT_SWITCH_ARG(spdif_enable, CM_REG_LEGACY_CTRL, CM_ENSPDOUT, 0, 0);
2245 DEFINE_BIT_SWITCH_ARG(spdo2dac, CM_REG_FUNCTRL1, CM_SPDO2DAC, 0, 1);
2246 DEFINE_BIT_SWITCH_ARG(spdi_valid, CM_REG_MISC, CM_SPDVALID, 1, 0);
2247 DEFINE_BIT_SWITCH_ARG(spdif_copyright, CM_REG_LEGACY_CTRL, CM_SPDCOPYRHT, 0, 0);
2248 DEFINE_BIT_SWITCH_ARG(spdif_dac_out, CM_REG_LEGACY_CTRL, CM_DAC2SPDO, 0, 1);
2249 DEFINE_SWITCH_ARG(spdo_5v, CM_REG_MISC_CTRL, CM_SPDO5V, 0, 0, 0); /* inverse: 0 = 5V */
2250 // DEFINE_BIT_SWITCH_ARG(spdo_48k, CM_REG_MISC_CTRL, CM_SPDF_AC97|CM_SPDIF48K, 0, 1);
2251 DEFINE_BIT_SWITCH_ARG(spdif_loop, CM_REG_FUNCTRL1, CM_SPDFLOOP, 0, 1);
2252 DEFINE_BIT_SWITCH_ARG(spdi_monitor, CM_REG_MIXER1, CM_CDPLAY, 1, 0);
2253 /* DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_CHFORMAT, CM_SPDIF_INVERSE, 0, 0); */
2254 DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_MISC, CM_SPDIF_INVERSE, 1, 0);
2255 DEFINE_BIT_SWITCH_ARG(spdi_phase2, CM_REG_CHFORMAT, CM_SPDIF_INVERSE2, 0, 0);
2256 #if CM_CH_PLAY == 1
2257 DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, 0, 0, 0); /* reversed */
2258 #else
2259 DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, CM_XCHGDAC, 0, 0);
2260 #endif
2261 DEFINE_BIT_SWITCH_ARG(fourch, CM_REG_MISC_CTRL, CM_N4SPK3D, 0, 0);
2262 // DEFINE_BIT_SWITCH_ARG(line_rear, CM_REG_MIXER1, CM_SPK4, 1, 0);
2263 // DEFINE_BIT_SWITCH_ARG(line_bass, CM_REG_LEGACY_CTRL, CM_LINE_AS_BASS, 0, 0);
2264 // DEFINE_BIT_SWITCH_ARG(joystick, CM_REG_FUNCTRL1, CM_JYSTK_EN, 0, 0); /* now module option */
2265 DEFINE_SWITCH_ARG(modem, CM_REG_MISC_CTRL, CM_FLINKON|CM_FLINKOFF, CM_FLINKON, 0, 0);
2266
2267 #define DEFINE_SWITCH(sname, stype, sarg) \
2268 { .name = sname, \
2269 .iface = stype, \
2270 .info = snd_cmipci_uswitch_info, \
2271 .get = snd_cmipci_uswitch_get, \
2272 .put = snd_cmipci_uswitch_put, \
2273 .private_value = (unsigned long)&cmipci_switch_arg_##sarg,\
2274 }
2275
2276 #define DEFINE_CARD_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_CARD, sarg)
2277 #define DEFINE_MIXER_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_MIXER, sarg)
2278
2279
2280 /*
2281 * callbacks for spdif output switch
2282 * needs toggle two registers..
2283 */
2284 static int snd_cmipci_spdout_enable_get(struct snd_kcontrol *kcontrol,
2285 struct snd_ctl_elem_value *ucontrol)
2286 {
2287 int changed;
2288 changed = _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2289 changed |= _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2290 return changed;
2291 }
2292
2293 static int snd_cmipci_spdout_enable_put(struct snd_kcontrol *kcontrol,
2294 struct snd_ctl_elem_value *ucontrol)
2295 {
2296 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
2297 int changed;
2298 changed = _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2299 changed |= _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2300 if (changed) {
2301 if (ucontrol->value.integer.value[0]) {
2302 if (chip->spdif_playback_avail)
2303 snd_cmipci_set_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2304 } else {
2305 if (chip->spdif_playback_avail)
2306 snd_cmipci_clear_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2307 }
2308 }
2309 chip->spdif_playback_enabled = ucontrol->value.integer.value[0];
2310 return changed;
2311 }
2312
2313
2314 static int snd_cmipci_line_in_mode_info(struct snd_kcontrol *kcontrol,
2315 struct snd_ctl_elem_info *uinfo)
2316 {
2317 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2318 static char *texts[3] = { "Line-In", "Rear Output", "Bass Output" };
2319 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2320 uinfo->count = 1;
2321 uinfo->value.enumerated.items = cm->chip_version >= 39 ? 3 : 2;
2322 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2323 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2324 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2325 return 0;
2326 }
2327
2328 static inline unsigned int get_line_in_mode(struct cmipci *cm)
2329 {
2330 unsigned int val;
2331 if (cm->chip_version >= 39) {
2332 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL);
2333 if (val & CM_LINE_AS_BASS)
2334 return 2;
2335 }
2336 val = snd_cmipci_read_b(cm, CM_REG_MIXER1);
2337 if (val & CM_SPK4)
2338 return 1;
2339 return 0;
2340 }
2341
2342 static int snd_cmipci_line_in_mode_get(struct snd_kcontrol *kcontrol,
2343 struct snd_ctl_elem_value *ucontrol)
2344 {
2345 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2346
2347 spin_lock_irq(&cm->reg_lock);
2348 ucontrol->value.enumerated.item[0] = get_line_in_mode(cm);
2349 spin_unlock_irq(&cm->reg_lock);
2350 return 0;
2351 }
2352
2353 static int snd_cmipci_line_in_mode_put(struct snd_kcontrol *kcontrol,
2354 struct snd_ctl_elem_value *ucontrol)
2355 {
2356 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2357 int change;
2358
2359 spin_lock_irq(&cm->reg_lock);
2360 if (ucontrol->value.enumerated.item[0] == 2)
2361 change = snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_LINE_AS_BASS);
2362 else
2363 change = snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_LINE_AS_BASS);
2364 if (ucontrol->value.enumerated.item[0] == 1)
2365 change |= snd_cmipci_set_bit_b(cm, CM_REG_MIXER1, CM_SPK4);
2366 else
2367 change |= snd_cmipci_clear_bit_b(cm, CM_REG_MIXER1, CM_SPK4);
2368 spin_unlock_irq(&cm->reg_lock);
2369 return change;
2370 }
2371
2372 static int snd_cmipci_mic_in_mode_info(struct snd_kcontrol *kcontrol,
2373 struct snd_ctl_elem_info *uinfo)
2374 {
2375 static char *texts[2] = { "Mic-In", "Center/LFE Output" };
2376 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2377 uinfo->count = 1;
2378 uinfo->value.enumerated.items = 2;
2379 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2380 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2381 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2382 return 0;
2383 }
2384
2385 static int snd_cmipci_mic_in_mode_get(struct snd_kcontrol *kcontrol,
2386 struct snd_ctl_elem_value *ucontrol)
2387 {
2388 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2389 /* same bit as spdi_phase */
2390 spin_lock_irq(&cm->reg_lock);
2391 ucontrol->value.enumerated.item[0] =
2392 (snd_cmipci_read_b(cm, CM_REG_MISC) & CM_SPDIF_INVERSE) ? 1 : 0;
2393 spin_unlock_irq(&cm->reg_lock);
2394 return 0;
2395 }
2396
2397 static int snd_cmipci_mic_in_mode_put(struct snd_kcontrol *kcontrol,
2398 struct snd_ctl_elem_value *ucontrol)
2399 {
2400 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2401 int change;
2402
2403 spin_lock_irq(&cm->reg_lock);
2404 if (ucontrol->value.enumerated.item[0])
2405 change = snd_cmipci_set_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2406 else
2407 change = snd_cmipci_clear_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2408 spin_unlock_irq(&cm->reg_lock);
2409 return change;
2410 }
2411
2412 /* both for CM8338/8738 */
2413 static struct snd_kcontrol_new snd_cmipci_mixer_switches[] __devinitdata = {
2414 DEFINE_MIXER_SWITCH("Four Channel Mode", fourch),
2415 {
2416 .name = "Line-In Mode",
2417 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2418 .info = snd_cmipci_line_in_mode_info,
2419 .get = snd_cmipci_line_in_mode_get,
2420 .put = snd_cmipci_line_in_mode_put,
2421 },
2422 };
2423
2424 /* for non-multichannel chips */
2425 static struct snd_kcontrol_new snd_cmipci_nomulti_switch __devinitdata =
2426 DEFINE_MIXER_SWITCH("Exchange DAC", exchange_dac);
2427
2428 /* only for CM8738 */
2429 static struct snd_kcontrol_new snd_cmipci_8738_mixer_switches[] __devinitdata = {
2430 #if 0 /* controlled in pcm device */
2431 DEFINE_MIXER_SWITCH("IEC958 In Record", spdif_in),
2432 DEFINE_MIXER_SWITCH("IEC958 Out", spdif_out),
2433 DEFINE_MIXER_SWITCH("IEC958 Out To DAC", spdo2dac),
2434 #endif
2435 // DEFINE_MIXER_SWITCH("IEC958 Output Switch", spdif_enable),
2436 { .name = "IEC958 Output Switch",
2437 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2438 .info = snd_cmipci_uswitch_info,
2439 .get = snd_cmipci_spdout_enable_get,
2440 .put = snd_cmipci_spdout_enable_put,
2441 },
2442 DEFINE_MIXER_SWITCH("IEC958 In Valid", spdi_valid),
2443 DEFINE_MIXER_SWITCH("IEC958 Copyright", spdif_copyright),
2444 DEFINE_MIXER_SWITCH("IEC958 5V", spdo_5v),
2445 // DEFINE_MIXER_SWITCH("IEC958 In/Out 48KHz", spdo_48k),
2446 DEFINE_MIXER_SWITCH("IEC958 Loop", spdif_loop),
2447 DEFINE_MIXER_SWITCH("IEC958 In Monitor", spdi_monitor),
2448 };
2449
2450 /* only for model 033/037 */
2451 static struct snd_kcontrol_new snd_cmipci_old_mixer_switches[] __devinitdata = {
2452 DEFINE_MIXER_SWITCH("IEC958 Mix Analog", spdif_dac_out),
2453 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase),
2454 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel1),
2455 };
2456
2457 /* only for model 039 or later */
2458 static struct snd_kcontrol_new snd_cmipci_extra_mixer_switches[] __devinitdata = {
2459 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel2),
2460 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase2),
2461 {
2462 .name = "Mic-In Mode",
2463 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2464 .info = snd_cmipci_mic_in_mode_info,
2465 .get = snd_cmipci_mic_in_mode_get,
2466 .put = snd_cmipci_mic_in_mode_put,
2467 }
2468 };
2469
2470 /* card control switches */
2471 static struct snd_kcontrol_new snd_cmipci_control_switches[] __devinitdata = {
2472 // DEFINE_CARD_SWITCH("Joystick", joystick), /* now module option */
2473 DEFINE_CARD_SWITCH("Modem", modem),
2474 };
2475
2476
2477 static int __devinit snd_cmipci_mixer_new(struct cmipci *cm, int pcm_spdif_device)
2478 {
2479 struct snd_card *card;
2480 struct snd_kcontrol_new *sw;
2481 struct snd_kcontrol *kctl;
2482 unsigned int idx;
2483 int err;
2484
2485 snd_assert(cm != NULL && cm->card != NULL, return -EINVAL);
2486
2487 card = cm->card;
2488
2489 strcpy(card->mixername, "CMedia PCI");
2490
2491 spin_lock_irq(&cm->reg_lock);
2492 snd_cmipci_mixer_write(cm, 0x00, 0x00); /* mixer reset */
2493 spin_unlock_irq(&cm->reg_lock);
2494
2495 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixers); idx++) {
2496 if (cm->chip_version == 68) { // 8768 has no PCM volume
2497 if (!strcmp(snd_cmipci_mixers[idx].name,
2498 "PCM Playback Volume"))
2499 continue;
2500 }
2501 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cmipci_mixers[idx], cm))) < 0)
2502 return err;
2503 }
2504
2505 /* mixer switches */
2506 sw = snd_cmipci_mixer_switches;
2507 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixer_switches); idx++, sw++) {
2508 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2509 if (err < 0)
2510 return err;
2511 }
2512 if (! cm->can_multi_ch) {
2513 err = snd_ctl_add(cm->card, snd_ctl_new1(&snd_cmipci_nomulti_switch, cm));
2514 if (err < 0)
2515 return err;
2516 }
2517 if (cm->device == PCI_DEVICE_ID_CMEDIA_CM8738 ||
2518 cm->device == PCI_DEVICE_ID_CMEDIA_CM8738B) {
2519 sw = snd_cmipci_8738_mixer_switches;
2520 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_8738_mixer_switches); idx++, sw++) {
2521 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2522 if (err < 0)
2523 return err;
2524 }
2525 if (cm->can_ac3_hw) {
2526 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_default, cm))) < 0)
2527 return err;
2528 kctl->id.device = pcm_spdif_device;
2529 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_mask, cm))) < 0)
2530 return err;
2531 kctl->id.device = pcm_spdif_device;
2532 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_stream, cm))) < 0)
2533 return err;
2534 kctl->id.device = pcm_spdif_device;
2535 }
2536 if (cm->chip_version <= 37) {
2537 sw = snd_cmipci_old_mixer_switches;
2538 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_old_mixer_switches); idx++, sw++) {
2539 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2540 if (err < 0)
2541 return err;
2542 }
2543 }
2544 }
2545 if (cm->chip_version >= 39) {
2546 sw = snd_cmipci_extra_mixer_switches;
2547 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_extra_mixer_switches); idx++, sw++) {
2548 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2549 if (err < 0)
2550 return err;
2551 }
2552 }
2553
2554 /* card switches */
2555 sw = snd_cmipci_control_switches;
2556 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_control_switches); idx++, sw++) {
2557 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2558 if (err < 0)
2559 return err;
2560 }
2561
2562 for (idx = 0; idx < CM_SAVED_MIXERS; idx++) {
2563 struct snd_ctl_elem_id id;
2564 struct snd_kcontrol *ctl;
2565 memset(&id, 0, sizeof(id));
2566 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2567 strcpy(id.name, cm_saved_mixer[idx].name);
2568 if ((ctl = snd_ctl_find_id(cm->card, &id)) != NULL)
2569 cm->mixer_res_ctl[idx] = ctl;
2570 }
2571
2572 return 0;
2573 }
2574
2575
2576 /*
2577 * proc interface
2578 */
2579
2580 #ifdef CONFIG_PROC_FS
2581 static void snd_cmipci_proc_read(struct snd_info_entry *entry,
2582 struct snd_info_buffer *buffer)
2583 {
2584 struct cmipci *cm = entry->private_data;
2585 int i;
2586
2587 snd_iprintf(buffer, "%s\n\n", cm->card->longname);
2588 for (i = 0; i < 0x40; i++) {
2589 int v = inb(cm->iobase + i);
2590 if (i % 4 == 0)
2591 snd_iprintf(buffer, "%02x: ", i);
2592 snd_iprintf(buffer, "%02x", v);
2593 if (i % 4 == 3)
2594 snd_iprintf(buffer, "\n");
2595 else
2596 snd_iprintf(buffer, " ");
2597 }
2598 }
2599
2600 static void __devinit snd_cmipci_proc_init(struct cmipci *cm)
2601 {
2602 struct snd_info_entry *entry;
2603
2604 if (! snd_card_proc_new(cm->card, "cmipci", &entry))
2605 snd_info_set_text_ops(entry, cm, 1024, snd_cmipci_proc_read);
2606 }
2607 #else /* !CONFIG_PROC_FS */
2608 static inline void snd_cmipci_proc_init(struct cmipci *cm) {}
2609 #endif
2610
2611
2612 static struct pci_device_id snd_cmipci_ids[] __devinitdata = {
2613 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2614 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2615 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2616 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2617 {PCI_VENDOR_ID_AL, PCI_DEVICE_ID_CMEDIA_CM8738, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2618 {0,},
2619 };
2620
2621
2622 /*
2623 * check chip version and capabilities
2624 * driver name is modified according to the chip model
2625 */
2626 static void __devinit query_chip(struct cmipci *cm)
2627 {
2628 unsigned int detect;
2629
2630 /* check reg 0Ch, bit 24-31 */
2631 detect = snd_cmipci_read(cm, CM_REG_INT_HLDCLR) & CM_CHIP_MASK2;
2632 if (! detect) {
2633 /* check reg 08h, bit 24-28 */
2634 detect = snd_cmipci_read(cm, CM_REG_CHFORMAT) & CM_CHIP_MASK1;
2635 if (! detect) {
2636 cm->chip_version = 33;
2637 cm->max_channels = 2;
2638 if (cm->do_soft_ac3)
2639 cm->can_ac3_sw = 1;
2640 else
2641 cm->can_ac3_hw = 1;
2642 cm->has_dual_dac = 1;
2643 } else {
2644 cm->chip_version = 37;
2645 cm->max_channels = 2;
2646 cm->can_ac3_hw = 1;
2647 cm->has_dual_dac = 1;
2648 }
2649 } else {
2650 /* check reg 0Ch, bit 26 */
2651 if (detect & CM_CHIP_8768) {
2652 cm->chip_version = 68;
2653 cm->max_channels = 8;
2654 cm->can_ac3_hw = 1;
2655 cm->has_dual_dac = 1;
2656 cm->can_multi_ch = 1;
2657 } else if (detect & CM_CHIP_055) {
2658 cm->chip_version = 55;
2659 cm->max_channels = 6;
2660 cm->can_ac3_hw = 1;
2661 cm->has_dual_dac = 1;
2662 cm->can_multi_ch = 1;
2663 } else if (detect & CM_CHIP_039) {
2664 cm->chip_version = 39;
2665 if (detect & CM_CHIP_039_6CH) /* 4 or 6 channels */
2666 cm->max_channels = 6;
2667 else
2668 cm->max_channels = 4;
2669 cm->can_ac3_hw = 1;
2670 cm->has_dual_dac = 1;
2671 cm->can_multi_ch = 1;
2672 } else {
2673 printk(KERN_ERR "chip %x version not supported\n", detect);
2674 }
2675 }
2676 }
2677
2678 #ifdef SUPPORT_JOYSTICK
2679 static int __devinit snd_cmipci_create_gameport(struct cmipci *cm, int dev)
2680 {
2681 static int ports[] = { 0x201, 0x200, 0 }; /* FIXME: majority is 0x201? */
2682 struct gameport *gp;
2683 struct resource *r = NULL;
2684 int i, io_port = 0;
2685
2686 if (joystick_port[dev] == 0)
2687 return -ENODEV;
2688
2689 if (joystick_port[dev] == 1) { /* auto-detect */
2690 for (i = 0; ports[i]; i++) {
2691 io_port = ports[i];
2692 r = request_region(io_port, 1, "CMIPCI gameport");
2693 if (r)
2694 break;
2695 }
2696 } else {
2697 io_port = joystick_port[dev];
2698 r = request_region(io_port, 1, "CMIPCI gameport");
2699 }
2700
2701 if (!r) {
2702 printk(KERN_WARNING "cmipci: cannot reserve joystick ports\n");
2703 return -EBUSY;
2704 }
2705
2706 cm->gameport = gp = gameport_allocate_port();
2707 if (!gp) {
2708 printk(KERN_ERR "cmipci: cannot allocate memory for gameport\n");
2709 release_and_free_resource(r);
2710 return -ENOMEM;
2711 }
2712 gameport_set_name(gp, "C-Media Gameport");
2713 gameport_set_phys(gp, "pci%s/gameport0", pci_name(cm->pci));
2714 gameport_set_dev_parent(gp, &cm->pci->dev);
2715 gp->io = io_port;
2716 gameport_set_port_data(gp, r);
2717
2718 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2719
2720 gameport_register_port(cm->gameport);
2721
2722 return 0;
2723 }
2724
2725 static void snd_cmipci_free_gameport(struct cmipci *cm)
2726 {
2727 if (cm->gameport) {
2728 struct resource *r = gameport_get_port_data(cm->gameport);
2729
2730 gameport_unregister_port(cm->gameport);
2731 cm->gameport = NULL;
2732
2733 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2734 release_and_free_resource(r);
2735 }
2736 }
2737 #else
2738 static inline int snd_cmipci_create_gameport(struct cmipci *cm, int dev) { return -ENOSYS; }
2739 static inline void snd_cmipci_free_gameport(struct cmipci *cm) { }
2740 #endif
2741
2742 static int snd_cmipci_free(struct cmipci *cm)
2743 {
2744 if (cm->irq >= 0) {
2745 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2746 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT);
2747 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */
2748 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
2749 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
2750 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
2751 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
2752
2753 /* reset mixer */
2754 snd_cmipci_mixer_write(cm, 0, 0);
2755
2756 synchronize_irq(cm->irq);
2757
2758 free_irq(cm->irq, cm);
2759 }
2760
2761 snd_cmipci_free_gameport(cm);
2762 pci_release_regions(cm->pci);
2763 pci_disable_device(cm->pci);
2764 kfree(cm);
2765 return 0;
2766 }
2767
2768 static int snd_cmipci_dev_free(struct snd_device *device)
2769 {
2770 struct cmipci *cm = device->device_data;
2771 return snd_cmipci_free(cm);
2772 }
2773
2774 static int __devinit snd_cmipci_create_fm(struct cmipci *cm, long fm_port)
2775 {
2776 long iosynth;
2777 unsigned int val;
2778 struct snd_opl3 *opl3;
2779 int err;
2780
2781 /* first try FM regs in PCI port range */
2782 iosynth = cm->iobase + CM_REG_FM_PCI;
2783 err = snd_opl3_create(cm->card, iosynth, iosynth + 2,
2784 OPL3_HW_OPL3, 1, &opl3);
2785 if (err < 0) {
2786 /* then try legacy ports */
2787 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL) & ~CM_FMSEL_MASK;
2788 iosynth = fm_port;
2789 switch (iosynth) {
2790 case 0x3E8: val |= CM_FMSEL_3E8; break;
2791 case 0x3E0: val |= CM_FMSEL_3E0; break;
2792 case 0x3C8: val |= CM_FMSEL_3C8; break;
2793 case 0x388: val |= CM_FMSEL_388; break;
2794 default:
2795 return 0;
2796 }
2797 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
2798 /* enable FM */
2799 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2800
2801 if (snd_opl3_create(cm->card, iosynth, iosynth + 2,
2802 OPL3_HW_OPL3, 0, &opl3) < 0) {
2803 printk(KERN_ERR "cmipci: no OPL device at %#lx, "
2804 "skipping...\n", iosynth);
2805 /* disable FM */
2806 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL,
2807 val & ~CM_FMSEL_MASK);
2808 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2809 return 0;
2810 }
2811 }
2812 if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
2813 printk(KERN_ERR "cmipci: cannot create OPL3 hwdep\n");
2814 return err;
2815 }
2816 return 0;
2817 }
2818
2819 static int __devinit snd_cmipci_create(struct snd_card *card, struct pci_dev *pci,
2820 int dev, struct cmipci **rcmipci)
2821 {
2822 struct cmipci *cm;
2823 int err;
2824 static struct snd_device_ops ops = {
2825 .dev_free = snd_cmipci_dev_free,
2826 };
2827 unsigned int val = 0;
2828 long iomidi;
2829 int integrated_midi;
2830 int pcm_index, pcm_spdif_index;
2831 static struct pci_device_id intel_82437vx[] = {
2832 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX) },
2833 { },
2834 };
2835
2836 *rcmipci = NULL;
2837
2838 if ((err = pci_enable_device(pci)) < 0)
2839 return err;
2840
2841 cm = kzalloc(sizeof(*cm), GFP_KERNEL);
2842 if (cm == NULL) {
2843 pci_disable_device(pci);
2844 return -ENOMEM;
2845 }
2846
2847 spin_lock_init(&cm->reg_lock);
2848 mutex_init(&cm->open_mutex);
2849 cm->device = pci->device;
2850 cm->card = card;
2851 cm->pci = pci;
2852 cm->irq = -1;
2853 cm->channel[0].ch = 0;
2854 cm->channel[1].ch = 1;
2855 cm->channel[0].is_dac = cm->channel[1].is_dac = 1; /* dual DAC mode */
2856
2857 if ((err = pci_request_regions(pci, card->driver)) < 0) {
2858 kfree(cm);
2859 pci_disable_device(pci);
2860 return err;
2861 }
2862 cm->iobase = pci_resource_start(pci, 0);
2863
2864 if (request_irq(pci->irq, snd_cmipci_interrupt,
2865 SA_INTERRUPT|SA_SHIRQ, card->driver, cm)) {
2866 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
2867 snd_cmipci_free(cm);
2868 return -EBUSY;
2869 }
2870 cm->irq = pci->irq;
2871
2872 pci_set_master(cm->pci);
2873
2874 /*
2875 * check chip version, max channels and capabilities
2876 */
2877
2878 cm->chip_version = 0;
2879 cm->max_channels = 2;
2880 cm->do_soft_ac3 = soft_ac3[dev];
2881
2882 if (pci->device != PCI_DEVICE_ID_CMEDIA_CM8338A &&
2883 pci->device != PCI_DEVICE_ID_CMEDIA_CM8338B)
2884 query_chip(cm);
2885 /* added -MCx suffix for chip supporting multi-channels */
2886 if (cm->can_multi_ch)
2887 sprintf(cm->card->driver + strlen(cm->card->driver),
2888 "-MC%d", cm->max_channels);
2889 else if (cm->can_ac3_sw)
2890 strcpy(cm->card->driver + strlen(cm->card->driver), "-SWIEC");
2891
2892 cm->dig_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
2893 cm->dig_pcm_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
2894
2895 #if CM_CH_PLAY == 1
2896 cm->ctrl = CM_CHADC0; /* default FUNCNTRL0 */
2897 #else
2898 cm->ctrl = CM_CHADC1; /* default FUNCNTRL0 */
2899 #endif
2900
2901 /* initialize codec registers */
2902 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */
2903 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
2904 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
2905 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
2906 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
2907
2908 snd_cmipci_write(cm, CM_REG_CHFORMAT, 0);
2909 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC|CM_N4SPK3D);
2910 #if CM_CH_PLAY == 1
2911 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
2912 #else
2913 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
2914 #endif
2915 /* Set Bus Master Request */
2916 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_BREQ);
2917
2918 /* Assume TX and compatible chip set (Autodetection required for VX chip sets) */
2919 switch (pci->device) {
2920 case PCI_DEVICE_ID_CMEDIA_CM8738:
2921 case PCI_DEVICE_ID_CMEDIA_CM8738B:
2922 if (!pci_dev_present(intel_82437vx))
2923 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_TXVX);
2924 break;
2925 default:
2926 break;
2927 }
2928
2929 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, cm, &ops)) < 0) {
2930 snd_cmipci_free(cm);
2931 return err;
2932 }
2933
2934 integrated_midi = snd_cmipci_read_b(cm, CM_REG_MPU_PCI) != 0xff;
2935 if (integrated_midi)
2936 iomidi = cm->iobase + CM_REG_MPU_PCI;
2937 else {
2938 iomidi = mpu_port[dev];
2939 switch (iomidi) {
2940 case 0x320: val = CM_VMPU_320; break;
2941 case 0x310: val = CM_VMPU_310; break;
2942 case 0x300: val = CM_VMPU_300; break;
2943 case 0x330: val = CM_VMPU_330; break;
2944 default:
2945 iomidi = 0; break;
2946 }
2947 if (iomidi > 0) {
2948 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
2949 /* enable UART */
2950 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_UART_EN);
2951 }
2952 }
2953
2954 if ((err = snd_cmipci_create_fm(cm, fm_port[dev])) < 0)
2955 return err;
2956
2957 /* reset mixer */
2958 snd_cmipci_mixer_write(cm, 0, 0);
2959
2960 snd_cmipci_proc_init(cm);
2961
2962 /* create pcm devices */
2963 pcm_index = pcm_spdif_index = 0;
2964 if ((err = snd_cmipci_pcm_new(cm, pcm_index)) < 0)
2965 return err;
2966 pcm_index++;
2967 if (cm->has_dual_dac) {
2968 if ((err = snd_cmipci_pcm2_new(cm, pcm_index)) < 0)
2969 return err;
2970 pcm_index++;
2971 }
2972 if (cm->can_ac3_hw || cm->can_ac3_sw) {
2973 pcm_spdif_index = pcm_index;
2974 if ((err = snd_cmipci_pcm_spdif_new(cm, pcm_index)) < 0)
2975 return err;
2976 }
2977
2978 /* create mixer interface & switches */
2979 if ((err = snd_cmipci_mixer_new(cm, pcm_spdif_index)) < 0)
2980 return err;
2981
2982 if (iomidi > 0) {
2983 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
2984 iomidi, integrated_midi,
2985 cm->irq, 0, &cm->rmidi)) < 0) {
2986 printk(KERN_ERR "cmipci: no UART401 device at 0x%lx\n", iomidi);
2987 }
2988 }
2989
2990 #ifdef USE_VAR48KRATE
2991 for (val = 0; val < ARRAY_SIZE(rates); val++)
2992 snd_cmipci_set_pll(cm, rates[val], val);
2993
2994 /*
2995 * (Re-)Enable external switch spdo_48k
2996 */
2997 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K|CM_SPDF_AC97);
2998 #endif /* USE_VAR48KRATE */
2999
3000 if (snd_cmipci_create_gameport(cm, dev) < 0)
3001 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
3002
3003 snd_card_set_dev(card, &pci->dev);
3004
3005 *rcmipci = cm;
3006 return 0;
3007 }
3008
3009 /*
3010 */
3011
3012 MODULE_DEVICE_TABLE(pci, snd_cmipci_ids);
3013
3014 static int __devinit snd_cmipci_probe(struct pci_dev *pci,
3015 const struct pci_device_id *pci_id)
3016 {
3017 static int dev;
3018 struct snd_card *card;
3019 struct cmipci *cm;
3020 int err;
3021
3022 if (dev >= SNDRV_CARDS)
3023 return -ENODEV;
3024 if (! enable[dev]) {
3025 dev++;
3026 return -ENOENT;
3027 }
3028
3029 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
3030 if (card == NULL)
3031 return -ENOMEM;
3032
3033 switch (pci->device) {
3034 case PCI_DEVICE_ID_CMEDIA_CM8738:
3035 case PCI_DEVICE_ID_CMEDIA_CM8738B:
3036 strcpy(card->driver, "CMI8738");
3037 break;
3038 case PCI_DEVICE_ID_CMEDIA_CM8338A:
3039 case PCI_DEVICE_ID_CMEDIA_CM8338B:
3040 strcpy(card->driver, "CMI8338");
3041 break;
3042 default:
3043 strcpy(card->driver, "CMIPCI");
3044 break;
3045 }
3046
3047 if ((err = snd_cmipci_create(card, pci, dev, &cm)) < 0) {
3048 snd_card_free(card);
3049 return err;
3050 }
3051 card->private_data = cm;
3052
3053 sprintf(card->shortname, "C-Media PCI %s", card->driver);
3054 sprintf(card->longname, "%s (model %d) at 0x%lx, irq %i",
3055 card->shortname,
3056 cm->chip_version,
3057 cm->iobase,
3058 cm->irq);
3059
3060 //snd_printd("%s is detected\n", card->longname);
3061
3062 if ((err = snd_card_register(card)) < 0) {
3063 snd_card_free(card);
3064 return err;
3065 }
3066 pci_set_drvdata(pci, card);
3067 dev++;
3068 return 0;
3069
3070 }
3071
3072 static void __devexit snd_cmipci_remove(struct pci_dev *pci)
3073 {
3074 snd_card_free(pci_get_drvdata(pci));
3075 pci_set_drvdata(pci, NULL);
3076 }
3077
3078
3079 #ifdef CONFIG_PM
3080 /*
3081 * power management
3082 */
3083 static unsigned char saved_regs[] = {
3084 CM_REG_FUNCTRL1, CM_REG_CHFORMAT, CM_REG_LEGACY_CTRL, CM_REG_MISC_CTRL,
3085 CM_REG_MIXER0, CM_REG_MIXER1, CM_REG_MIXER2, CM_REG_MIXER3, CM_REG_PLL,
3086 CM_REG_CH0_FRAME1, CM_REG_CH0_FRAME2,
3087 CM_REG_CH1_FRAME1, CM_REG_CH1_FRAME2, CM_REG_EXT_MISC,
3088 CM_REG_INT_STATUS, CM_REG_INT_HLDCLR, CM_REG_FUNCTRL0,
3089 };
3090
3091 static unsigned char saved_mixers[] = {
3092 SB_DSP4_MASTER_DEV, SB_DSP4_MASTER_DEV + 1,
3093 SB_DSP4_PCM_DEV, SB_DSP4_PCM_DEV + 1,
3094 SB_DSP4_SYNTH_DEV, SB_DSP4_SYNTH_DEV + 1,
3095 SB_DSP4_CD_DEV, SB_DSP4_CD_DEV + 1,
3096 SB_DSP4_LINE_DEV, SB_DSP4_LINE_DEV + 1,
3097 SB_DSP4_MIC_DEV, SB_DSP4_SPEAKER_DEV,
3098 CM_REG_EXTENT_IND, SB_DSP4_OUTPUT_SW,
3099 SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT,
3100 };
3101
3102 static int snd_cmipci_suspend(struct pci_dev *pci, pm_message_t state)
3103 {
3104 struct snd_card *card = pci_get_drvdata(pci);
3105 struct cmipci *cm = card->private_data;
3106 int i;
3107
3108 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
3109
3110 snd_pcm_suspend_all(cm->pcm);
3111 snd_pcm_suspend_all(cm->pcm2);
3112 snd_pcm_suspend_all(cm->pcm_spdif);
3113
3114 /* save registers */
3115 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3116 cm->saved_regs[i] = snd_cmipci_read(cm, saved_regs[i]);
3117 for (i = 0; i < ARRAY_SIZE(saved_mixers); i++)
3118 cm->saved_mixers[i] = snd_cmipci_mixer_read(cm, saved_mixers[i]);
3119
3120 /* disable ints */
3121 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
3122
3123 pci_set_power_state(pci, PCI_D3hot);
3124 pci_disable_device(pci);
3125 pci_save_state(pci);
3126 return 0;
3127 }
3128
3129 static int snd_cmipci_resume(struct pci_dev *pci)
3130 {
3131 struct snd_card *card = pci_get_drvdata(pci);
3132 struct cmipci *cm = card->private_data;
3133 int i;
3134
3135 pci_restore_state(pci);
3136 pci_enable_device(pci);
3137 pci_set_power_state(pci, PCI_D0);
3138 pci_set_master(pci);
3139
3140 /* reset / initialize to a sane state */
3141 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
3142 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
3143 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
3144 snd_cmipci_mixer_write(cm, 0, 0);
3145
3146 /* restore registers */
3147 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3148 snd_cmipci_write(cm, saved_regs[i], cm->saved_regs[i]);
3149 for (i = 0; i < ARRAY_SIZE(saved_mixers); i++)
3150 snd_cmipci_mixer_write(cm, saved_mixers[i], cm->saved_mixers[i]);
3151
3152 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
3153 return 0;
3154 }
3155 #endif /* CONFIG_PM */
3156
3157 static struct pci_driver driver = {
3158 .name = "C-Media PCI",
3159 .id_table = snd_cmipci_ids,
3160 .probe = snd_cmipci_probe,
3161 .remove = __devexit_p(snd_cmipci_remove),
3162 #ifdef CONFIG_PM
3163 .suspend = snd_cmipci_suspend,
3164 .resume = snd_cmipci_resume,
3165 #endif
3166 };
3167
3168 static int __init alsa_card_cmipci_init(void)
3169 {
3170 return pci_register_driver(&driver);
3171 }
3172
3173 static void __exit alsa_card_cmipci_exit(void)
3174 {
3175 pci_unregister_driver(&driver);
3176 }
3177
3178 module_init(alsa_card_cmipci_init)
3179 module_exit(alsa_card_cmipci_exit)
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