1 /********************************************************************************
2 * QLOGIC LINUX SOFTWARE
4 * QLogic ISP2x00 device driver for Linux 2.6.x
5 * Copyright (C) 2003-2004 QLogic Corporation
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2, or (at your option) any
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
18 ******************************************************************************/
23 #include <linux/kernel.h>
24 #include <linux/init.h>
25 #include <linux/types.h>
26 #include <linux/module.h>
27 #include <linux/list.h>
28 #include <linux/pci.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/sched.h>
31 #include <linux/slab.h>
32 #include <linux/dmapool.h>
33 #include <linux/mempool.h>
34 #include <linux/spinlock.h>
35 #include <linux/completion.h>
36 #include <linux/interrupt.h>
37 #include <asm/semaphore.h>
39 #include <scsi/scsi.h>
40 #include <scsi/scsi_host.h>
41 #include <scsi/scsi_device.h>
42 #include <scsi/scsi_cmnd.h>
44 #if defined(CONFIG_SCSI_QLA21XX) || defined(CONFIG_SCSI_QLA21XX_MODULE)
45 #define IS_QLA2100(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2100)
47 #define IS_QLA2100(ha) 0
50 #if defined(CONFIG_SCSI_QLA22XX) || defined(CONFIG_SCSI_QLA22XX_MODULE)
51 #define IS_QLA2200(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2200)
53 #define IS_QLA2200(ha) 0
56 #if defined(CONFIG_SCSI_QLA2300) || defined(CONFIG_SCSI_QLA2300_MODULE)
57 #define IS_QLA2300(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2300)
58 #define IS_QLA2312(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2312)
60 #define IS_QLA2300(ha) 0
61 #define IS_QLA2312(ha) 0
64 #if defined(CONFIG_SCSI_QLA2322) || defined(CONFIG_SCSI_QLA2322_MODULE)
65 #define IS_QLA2322(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2322)
67 #define IS_QLA2322(ha) 0
70 #if defined(CONFIG_SCSI_QLA6312) || defined(CONFIG_SCSI_QLA6312_MODULE)
71 #define IS_QLA6312(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP6312)
72 #define IS_QLA6322(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP6322)
74 #define IS_QLA6312(ha) 0
75 #define IS_QLA6322(ha) 0
78 #if defined(CONFIG_SCSI_QLA24XX) || defined(CONFIG_SCSI_QLA24XX_MODULE)
79 #define IS_QLA2422(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422)
80 #define IS_QLA2432(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432)
82 #define IS_QLA2422(ha) 0
83 #define IS_QLA2432(ha) 0
86 #if defined(CONFIG_SCSI_QLA25XX) || defined(CONFIG_SCSI_QLA25XX_MODULE)
87 #define IS_QLA2512(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2512)
88 #define IS_QLA2522(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2522)
90 #define IS_QLA2512(ha) 0
91 #define IS_QLA2522(ha) 0
94 #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
95 IS_QLA6312(ha) || IS_QLA6322(ha))
97 #define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha))
98 #define IS_QLA25XX(ha) (IS_QLA2512(ha) || IS_QLA2522(ha))
101 * Only non-ISP2[12]00 have extended addressing support in the firmware.
103 #define HAS_EXTENDED_IDS(ha) (!IS_QLA2100(ha) && !IS_QLA2200(ha))
106 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places,
107 * but that's fine as we don't look at the last 24 ones for
110 #define MAILBOX_REGISTER_COUNT_2100 8
111 #define MAILBOX_REGISTER_COUNT 32
113 #define QLA2200A_RISC_ROM_VER 4
117 #include "qla_settings.h"
120 * Data bit definitions
134 #define BIT_12 0x1000
135 #define BIT_13 0x2000
136 #define BIT_14 0x4000
137 #define BIT_15 0x8000
138 #define BIT_16 0x10000
139 #define BIT_17 0x20000
140 #define BIT_18 0x40000
141 #define BIT_19 0x80000
142 #define BIT_20 0x100000
143 #define BIT_21 0x200000
144 #define BIT_22 0x400000
145 #define BIT_23 0x800000
146 #define BIT_24 0x1000000
147 #define BIT_25 0x2000000
148 #define BIT_26 0x4000000
149 #define BIT_27 0x8000000
150 #define BIT_28 0x10000000
151 #define BIT_29 0x20000000
152 #define BIT_30 0x40000000
153 #define BIT_31 0x80000000
155 #define LSB(x) ((uint8_t)(x))
156 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
158 #define LSW(x) ((uint16_t)(x))
159 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
161 #define LSD(x) ((uint32_t)((uint64_t)(x)))
162 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
169 #define RD_REG_BYTE(addr) readb(addr)
170 #define RD_REG_WORD(addr) readw(addr)
171 #define RD_REG_DWORD(addr) readl(addr)
172 #define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr)
173 #define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr)
174 #define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr)
175 #define WRT_REG_BYTE(addr, data) writeb(data,addr)
176 #define WRT_REG_WORD(addr, data) writew(data,addr)
177 #define WRT_REG_DWORD(addr, data) writel(data,addr)
180 * Fibre Channel device definitions.
182 #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */
183 #define MAX_FIBRE_DEVICES 512
184 #define MAX_FIBRE_LUNS 256
185 #define MAX_RSCN_COUNT 32
186 #define MAX_HOST_COUNT 16
189 * Host adapter default definitions.
191 #define MAX_BUSES 1 /* We only have one bus today */
192 #define MAX_TARGETS_2100 MAX_FIBRE_DEVICES
193 #define MAX_TARGETS_2200 MAX_FIBRE_DEVICES
194 #define MAX_TARGETS MAX_FIBRE_DEVICES
196 #define MAX_LUNS MAX_FIBRE_LUNS
197 #define MAX_CMDS_PER_LUN 255
200 * Fibre Channel device definitions.
202 #define SNS_LAST_LOOP_ID_2100 0xfe
203 #define SNS_LAST_LOOP_ID_2300 0x7ff
205 #define LAST_LOCAL_LOOP_ID 0x7d
206 #define SNS_FL_PORT 0x7e
207 #define FABRIC_CONTROLLER 0x7f
208 #define SIMPLE_NAME_SERVER 0x80
209 #define SNS_FIRST_LOOP_ID 0x81
210 #define MANAGEMENT_SERVER 0xfe
211 #define BROADCAST 0xff
214 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the
215 * valid range of an N-PORT id is 0 through 0x7ef.
217 #define NPH_LAST_HANDLE 0x7ef
218 #define NPH_SNS 0x7fc /* FFFFFC */
219 #define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */
220 #define NPH_F_PORT 0x7fe /* FFFFFE */
221 #define NPH_IP_BROADCAST 0x7ff /* FFFFFF */
223 #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */
227 * Timeout timer counts in seconds
229 #define PORT_RETRY_TIME 1
230 #define LOOP_DOWN_TIMEOUT 60
231 #define LOOP_DOWN_TIME 255 /* 240 */
232 #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30)
234 /* Maximum outstanding commands in ISP queues (1-65535) */
235 #define MAX_OUTSTANDING_COMMANDS 1024
237 /* ISP request and response entry counts (37-65535) */
238 #define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */
239 #define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */
240 #define REQUEST_ENTRY_CNT_2XXX_EXT_MEM 4096 /* Number of request entries. */
241 #define REQUEST_ENTRY_CNT_24XX 4096 /* Number of request entries. */
242 #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/
243 #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/
249 struct list_head list
;
251 struct scsi_qla_host
*ha
; /* HA the SP is queued on */
252 struct fc_port
*fcport
;
254 struct scsi_cmnd
*cmd
; /* Linux SCSI command pkt */
256 struct timer_list timer
; /* Command timer */
257 atomic_t ref_count
; /* Reference count for this structure */
263 /* Single transfer DMA context */
264 dma_addr_t dma_handle
;
266 uint32_t request_sense_length
;
267 uint8_t *request_sense_ptr
;
269 /* SRB magic number */
271 #define SRB_MAGIC 0x10CB
275 * SRB flag definitions
277 #define SRB_TIMEOUT BIT_0 /* Command timed out */
278 #define SRB_DMA_VALID BIT_1 /* Command sent to ISP */
279 #define SRB_WATCHDOG BIT_2 /* Command on watchdog list */
280 #define SRB_ABORT_PENDING BIT_3 /* Command abort sent to device */
282 #define SRB_ABORTED BIT_4 /* Command aborted command already */
283 #define SRB_RETRY BIT_5 /* Command needs retrying */
284 #define SRB_GOT_SENSE BIT_6 /* Command has sense data */
285 #define SRB_FAILOVER BIT_7 /* Command in failover state */
287 #define SRB_BUSY BIT_8 /* Command is in busy retry state */
288 #define SRB_FO_CANCEL BIT_9 /* Command don't need to do failover */
289 #define SRB_IOCTL BIT_10 /* IOCTL command. */
290 #define SRB_TAPE BIT_11 /* FCP2 (Tape) command. */
293 * SRB state definitions
295 #define SRB_FREE_STATE 0 /* returned back */
296 #define SRB_PENDING_STATE 1 /* queued in LUN Q */
297 #define SRB_ACTIVE_STATE 2 /* in Active Array */
298 #define SRB_DONE_STATE 3 /* queued in Done Queue */
299 #define SRB_RETRY_STATE 4 /* in Retry Queue */
300 #define SRB_SUSPENDED_STATE 5 /* in suspended state */
301 #define SRB_NO_QUEUE_STATE 6 /* is in between states */
302 #define SRB_ACTIVE_TIMEOUT_STATE 7 /* in Active Array but timed out */
303 #define SRB_FAILOVER_STATE 8 /* in Failover Queue */
304 #define SRB_SCSI_RETRY_STATE 9 /* in Scsi Retry Queue */
308 * ISP I/O Register Set structure definitions.
310 struct device_reg_2xxx
{
311 uint16_t flash_address
; /* Flash BIOS address */
312 uint16_t flash_data
; /* Flash BIOS data */
313 uint16_t unused_1
[1]; /* Gap */
314 uint16_t ctrl_status
; /* Control/Status */
315 #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */
316 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
317 #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */
319 uint16_t ictrl
; /* Interrupt control */
320 #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */
321 #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */
323 uint16_t istatus
; /* Interrupt status */
324 #define ISR_RISC_INT BIT_3 /* RISC interrupt */
326 uint16_t semaphore
; /* Semaphore */
327 uint16_t nvram
; /* NVRAM register. */
328 #define NVR_DESELECT 0
329 #define NVR_BUSY BIT_15
330 #define NVR_WRT_ENABLE BIT_14 /* Write enable */
331 #define NVR_PR_ENABLE BIT_13 /* Protection register enable */
332 #define NVR_DATA_IN BIT_3
333 #define NVR_DATA_OUT BIT_2
334 #define NVR_SELECT BIT_1
335 #define NVR_CLOCK BIT_0
347 uint16_t unused_2
[59]; /* Gap */
348 } __attribute__((packed
)) isp2100
;
351 uint16_t req_q_in
; /* In-Pointer */
352 uint16_t req_q_out
; /* Out-Pointer */
354 uint16_t rsp_q_in
; /* In-Pointer */
355 uint16_t rsp_q_out
; /* Out-Pointer */
357 /* RISC to Host Status */
358 uint32_t host_status
;
359 #define HSR_RISC_INT BIT_15 /* RISC interrupt */
360 #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */
362 /* Host to Host Semaphore */
363 uint16_t host_semaphore
;
364 uint16_t unused_3
[17]; /* Gap */
398 uint16_t unused_4
[10]; /* Gap */
399 } __attribute__((packed
)) isp2300
;
402 uint16_t fpm_diag_config
;
403 uint16_t unused_5
[0x6]; /* Gap */
404 uint16_t pcr
; /* Processor Control Register. */
405 uint16_t unused_6
[0x5]; /* Gap */
406 uint16_t mctr
; /* Memory Configuration and Timing. */
407 uint16_t unused_7
[0x3]; /* Gap */
408 uint16_t fb_cmd_2100
; /* Unused on 23XX */
409 uint16_t unused_8
[0x3]; /* Gap */
410 uint16_t hccr
; /* Host command & control register. */
411 #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */
412 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
414 #define HCCR_RESET_RISC 0x1000 /* Reset RISC */
415 #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */
416 #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */
417 #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */
418 #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */
419 #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */
420 #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */
421 #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */
423 uint16_t unused_9
[5]; /* Gap */
424 uint16_t gpiod
; /* GPIO Data register. */
425 uint16_t gpioe
; /* GPIO Enable register. */
426 #define GPIO_LED_MASK 0x00C0
427 #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
428 #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
429 #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080
430 #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0
434 uint16_t unused_10
[8]; /* Gap */
450 uint16_t mailbox23
; /* Also probe reg. */
451 } __attribute__((packed
)) isp2200
;
457 struct device_reg_2xxx isp
;
458 struct device_reg_24xx isp24
;
462 #define ISP_REQ_Q_IN(ha, reg) \
463 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
464 &(reg)->u.isp2100.mailbox4 : \
465 &(reg)->u.isp2300.req_q_in)
466 #define ISP_REQ_Q_OUT(ha, reg) \
467 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
468 &(reg)->u.isp2100.mailbox4 : \
469 &(reg)->u.isp2300.req_q_out)
470 #define ISP_RSP_Q_IN(ha, reg) \
471 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
472 &(reg)->u.isp2100.mailbox5 : \
473 &(reg)->u.isp2300.rsp_q_in)
474 #define ISP_RSP_Q_OUT(ha, reg) \
475 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
476 &(reg)->u.isp2100.mailbox5 : \
477 &(reg)->u.isp2300.rsp_q_out)
479 #define MAILBOX_REG(ha, reg, num) \
480 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
482 &(reg)->u.isp2100.mailbox0 + (num) : \
483 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
484 &(reg)->u.isp2300.mailbox0 + (num))
485 #define RD_MAILBOX_REG(ha, reg, num) \
486 RD_REG_WORD(MAILBOX_REG(ha, reg, num))
487 #define WRT_MAILBOX_REG(ha, reg, num, data) \
488 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data)
490 #define FB_CMD_REG(ha, reg) \
491 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
492 &(reg)->fb_cmd_2100 : \
493 &(reg)->u.isp2300.fb_cmd)
494 #define RD_FB_CMD_REG(ha, reg) \
495 RD_REG_WORD(FB_CMD_REG(ha, reg))
496 #define WRT_FB_CMD_REG(ha, reg, data) \
497 WRT_REG_WORD(FB_CMD_REG(ha, reg), data)
500 uint32_t out_mb
; /* outbound from driver */
501 uint32_t in_mb
; /* Incoming from RISC */
502 uint16_t mb
[MAILBOX_REGISTER_COUNT
];
507 #define MBX_DMA_IN BIT_0
508 #define MBX_DMA_OUT BIT_1
509 #define IOCTL_CMD BIT_2
512 #define MBX_TOV_SECONDS 30
515 * ISP product identification definitions in mailboxes after reset.
517 #define PROD_ID_1 0x4953
518 #define PROD_ID_2 0x0000
519 #define PROD_ID_2a 0x5020
520 #define PROD_ID_3 0x2020
523 * ISP mailbox Self-Test status codes
525 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */
526 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */
527 #define MBS_BUSY 4 /* Busy. */
530 * ISP mailbox command complete status codes
532 #define MBS_COMMAND_COMPLETE 0x4000
533 #define MBS_INVALID_COMMAND 0x4001
534 #define MBS_HOST_INTERFACE_ERROR 0x4002
535 #define MBS_TEST_FAILED 0x4003
536 #define MBS_COMMAND_ERROR 0x4005
537 #define MBS_COMMAND_PARAMETER_ERROR 0x4006
538 #define MBS_PORT_ID_USED 0x4007
539 #define MBS_LOOP_ID_USED 0x4008
540 #define MBS_ALL_IDS_IN_USE 0x4009
541 #define MBS_NOT_LOGGED_IN 0x400A
542 #define MBS_LINK_DOWN_ERROR 0x400B
543 #define MBS_DIAG_ECHO_TEST_ERROR 0x400C
546 * ISP mailbox asynchronous event status codes
548 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */
549 #define MBA_RESET 0x8001 /* Reset Detected. */
550 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */
551 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */
552 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */
553 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */
554 #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */
556 #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */
557 #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */
558 #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */
559 #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */
560 #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */
561 #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */
562 #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */
563 #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */
564 #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */
565 #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */
566 #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */
567 #define MBA_IP_RECEIVE 0x8023 /* IP Received. */
568 #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */
569 #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */
570 #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */
571 #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */
573 #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */
574 #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */
575 #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */
576 #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */
577 #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */
578 #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */
579 #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */
580 #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */
581 #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */
582 #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */
583 #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */
584 #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */
585 #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */
588 * Firmware options 1, 2, 3.
590 #define FO1_AE_ON_LIPF8 BIT_0
591 #define FO1_AE_ALL_LIP_RESET BIT_1
592 #define FO1_CTIO_RETRY BIT_3
593 #define FO1_DISABLE_LIP_F7_SW BIT_4
594 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5
595 #define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */
596 #define FO1_AE_ON_LOOP_INIT_ERR BIT_7
597 #define FO1_SET_EMPHASIS_SWING BIT_8
598 #define FO1_AE_AUTO_BYPASS BIT_9
599 #define FO1_ENABLE_PURE_IOCB BIT_10
600 #define FO1_AE_PLOGI_RJT BIT_11
601 #define FO1_ENABLE_ABORT_SEQUENCE BIT_12
602 #define FO1_AE_QUEUE_FULL BIT_13
604 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0
605 #define FO2_REV_LOOPBACK BIT_1
607 #define FO3_ENABLE_EMERG_IOCB BIT_0
608 #define FO3_AE_RND_ERROR BIT_1
610 /* 24XX additional firmware options */
611 #define ADD_FO_COUNT 3
612 #define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */
613 #define ADD_FO1_ENABLE_PUREX_IOCB BIT_10
615 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
617 #define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14
620 * ISP mailbox commands
622 #define MBC_LOAD_RAM 1 /* Load RAM. */
623 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */
624 #define MBC_WRITE_RAM_WORD 4 /* Write RAM word. */
625 #define MBC_READ_RAM_WORD 5 /* Read RAM word. */
626 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */
627 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */
628 #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */
629 #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */
630 #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */
631 #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */
632 #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */
633 #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */
634 #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */
635 #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */
636 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */
637 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */
638 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */
639 #define MBC_RESET 0x18 /* Reset. */
640 #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */
641 #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */
642 #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */
643 #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */
644 #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */
645 #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */
646 #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */
647 #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */
648 #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */
649 #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */
650 #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */
651 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */
652 #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */
653 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */
654 #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */
655 #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */
656 #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */
657 #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */
658 #define MBC_GET_RNID_PARAMS 0x5a /* Data Rate */
659 #define MBC_DATA_RATE 0x5d /* Get RNID parameters */
660 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */
661 #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */
662 /* Initialization Procedure */
663 #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */
664 #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */
665 #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */
666 #define MBC_TARGET_RESET 0x66 /* Target Reset. */
667 #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */
668 #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */
669 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */
670 #define MBC_GET_PORT_NAME 0x6a /* Get port name. */
671 #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */
672 #define MBC_LIP_RESET 0x6c /* LIP reset. */
673 #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */
675 #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */
676 #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */
677 #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */
678 #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */
679 #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */
680 #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */
681 #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */
682 #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */
683 #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */
684 #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */
685 #define MBC_LUN_RESET 0x7E /* Send LUN reset */
688 * ISP24xx mailbox commands
690 #define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */
691 #define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */
692 #define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */
693 #define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */
694 #define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */
695 #define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */
696 #define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */
697 #define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */
698 #define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */
699 #define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */
700 #define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */
701 #define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */
703 /* Firmware return data sizes */
704 #define FCAL_MAP_SIZE 128
706 /* Mailbox bit definitions for out_mb and in_mb */
707 #define MBX_31 BIT_31
708 #define MBX_30 BIT_30
709 #define MBX_29 BIT_29
710 #define MBX_28 BIT_28
711 #define MBX_27 BIT_27
712 #define MBX_26 BIT_26
713 #define MBX_25 BIT_25
714 #define MBX_24 BIT_24
715 #define MBX_23 BIT_23
716 #define MBX_22 BIT_22
717 #define MBX_21 BIT_21
718 #define MBX_20 BIT_20
719 #define MBX_19 BIT_19
720 #define MBX_18 BIT_18
721 #define MBX_17 BIT_17
722 #define MBX_16 BIT_16
723 #define MBX_15 BIT_15
724 #define MBX_14 BIT_14
725 #define MBX_13 BIT_13
726 #define MBX_12 BIT_12
727 #define MBX_11 BIT_11
728 #define MBX_10 BIT_10
741 * Firmware state codes from get firmware state mailbox command
743 #define FSTATE_CONFIG_WAIT 0
744 #define FSTATE_WAIT_AL_PA 1
745 #define FSTATE_WAIT_LOGIN 2
746 #define FSTATE_READY 3
747 #define FSTATE_LOSS_OF_SYNC 4
748 #define FSTATE_ERROR 5
749 #define FSTATE_REINIT 6
750 #define FSTATE_NON_PART 7
752 #define FSTATE_CONFIG_CORRECT 0
753 #define FSTATE_P2P_RCV_LIP 1
754 #define FSTATE_P2P_CHOOSE_LOOP 2
755 #define FSTATE_P2P_RCV_UNIDEN_LIP 3
756 #define FSTATE_FATAL_ERROR 4
757 #define FSTATE_LOOP_BACK_CONN 5
760 * Port Database structure definition
761 * Little endian except where noted.
763 #define PORT_DATABASE_SIZE 128 /* bytes */
767 uint8_t master_state
;
770 uint8_t hard_address
;
773 uint8_t node_name
[WWN_SIZE
];
774 uint8_t port_name
[WWN_SIZE
];
775 uint16_t execution_throttle
;
776 uint16_t execution_count
;
779 uint16_t resource_allocation
;
780 uint16_t current_allocation
;
783 uint16_t transmit_execution_list_next
;
784 uint16_t transmit_execution_list_previous
;
785 uint16_t common_features
;
786 uint16_t total_concurrent_sequences
;
787 uint16_t RO_by_information_category
;
790 uint16_t receive_data_size
;
791 uint16_t concurrent_sequences
;
792 uint16_t open_sequences_per_exchange
;
793 uint16_t lun_abort_flags
;
794 uint16_t lun_stop_flags
;
795 uint16_t stop_queue_head
;
796 uint16_t stop_queue_tail
;
797 uint16_t port_retry_timer
;
798 uint16_t next_sequence_id
;
799 uint16_t frame_count
;
800 uint16_t PRLI_payload_length
;
801 uint8_t prli_svc_param_word_0
[2]; /* Big endian */
802 /* Bits 15-0 of word 0 */
803 uint8_t prli_svc_param_word_3
[2]; /* Big endian */
804 /* Bits 15-0 of word 3 */
806 uint16_t extended_lun_info_list_pointer
;
807 uint16_t extended_lun_stop_list_pointer
;
811 * Port database slave/master states
813 #define PD_STATE_DISCOVERY 0
814 #define PD_STATE_WAIT_DISCOVERY_ACK 1
815 #define PD_STATE_PORT_LOGIN 2
816 #define PD_STATE_WAIT_PORT_LOGIN_ACK 3
817 #define PD_STATE_PROCESS_LOGIN 4
818 #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5
819 #define PD_STATE_PORT_LOGGED_IN 6
820 #define PD_STATE_PORT_UNAVAILABLE 7
821 #define PD_STATE_PROCESS_LOGOUT 8
822 #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9
823 #define PD_STATE_PORT_LOGOUT 10
824 #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11
828 * ISP Initialization Control Block.
829 * Little endian except where noted.
831 #define ICB_VERSION 1
837 * LSB BIT 0 = Enable Hard Loop Id
838 * LSB BIT 1 = Enable Fairness
839 * LSB BIT 2 = Enable Full-Duplex
840 * LSB BIT 3 = Enable Fast Posting
841 * LSB BIT 4 = Enable Target Mode
842 * LSB BIT 5 = Disable Initiator Mode
843 * LSB BIT 6 = Enable ADISC
844 * LSB BIT 7 = Enable Target Inquiry Data
846 * MSB BIT 0 = Enable PDBC Notify
847 * MSB BIT 1 = Non Participating LIP
848 * MSB BIT 2 = Descending Loop ID Search
849 * MSB BIT 3 = Acquire Loop ID in LIPA
850 * MSB BIT 4 = Stop PortQ on Full Status
851 * MSB BIT 5 = Full Login after LIP
852 * MSB BIT 6 = Node Name Option
853 * MSB BIT 7 = Ext IFWCB enable bit
855 uint8_t firmware_options
[2];
857 uint16_t frame_payload_size
;
858 uint16_t max_iocb_allocation
;
859 uint16_t execution_throttle
;
861 uint8_t retry_delay
; /* unused */
862 uint8_t port_name
[WWN_SIZE
]; /* Big endian. */
863 uint16_t hard_address
;
864 uint8_t inquiry_data
;
865 uint8_t login_timeout
;
866 uint8_t node_name
[WWN_SIZE
]; /* Big endian. */
868 uint16_t request_q_outpointer
;
869 uint16_t response_q_inpointer
;
870 uint16_t request_q_length
;
871 uint16_t response_q_length
;
872 uint32_t request_q_address
[2];
873 uint32_t response_q_address
[2];
875 uint16_t lun_enables
;
876 uint8_t command_resource_count
;
877 uint8_t immediate_notify_resource_count
;
879 uint8_t reserved_2
[2];
882 * LSB BIT 0 = Timer Operation mode bit 0
883 * LSB BIT 1 = Timer Operation mode bit 1
884 * LSB BIT 2 = Timer Operation mode bit 2
885 * LSB BIT 3 = Timer Operation mode bit 3
886 * LSB BIT 4 = Init Config Mode bit 0
887 * LSB BIT 5 = Init Config Mode bit 1
888 * LSB BIT 6 = Init Config Mode bit 2
889 * LSB BIT 7 = Enable Non part on LIHA failure
891 * MSB BIT 0 = Enable class 2
892 * MSB BIT 1 = Enable ACK0
895 * MSB BIT 4 = FC Tape Enable
896 * MSB BIT 5 = Enable FC Confirm
897 * MSB BIT 6 = Enable command queuing in target mode
898 * MSB BIT 7 = No Logo On Link Down
900 uint8_t add_firmware_options
[2];
902 uint8_t response_accumulation_timer
;
903 uint8_t interrupt_delay_timer
;
906 * LSB BIT 0 = Enable Read xfr_rdy
907 * LSB BIT 1 = Soft ID only
910 * LSB BIT 4 = FCP RSP Payload [0]
911 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
912 * LSB BIT 6 = Enable Out-of-Order frame handling
913 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
915 * MSB BIT 0 = Sbus enable - 2300
920 * MSB BIT 5 = enable 50 ohm termination
921 * MSB BIT 6 = Data Rate (2300 only)
922 * MSB BIT 7 = Data Rate (2300 only)
924 uint8_t special_options
[2];
926 uint8_t reserved_3
[26];
930 * Get Link Status mailbox command return buffer.
932 #define GLSO_SEND_RPS BIT_0
933 #define GLSO_USE_DID BIT_3
936 uint32_t link_fail_cnt
;
937 uint32_t loss_sync_cnt
;
938 uint32_t loss_sig_cnt
;
939 uint32_t prim_seq_err_cnt
;
940 uint32_t inval_xmit_word_cnt
;
941 uint32_t inval_crc_cnt
;
945 * NVRAM Command values.
947 #define NV_START_BIT BIT_2
948 #define NV_WRITE_OP (BIT_26+BIT_24)
949 #define NV_READ_OP (BIT_26+BIT_25)
950 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
951 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
952 #define NV_DELAY_COUNT 10
955 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition.
962 uint8_t nvram_version
;
966 * NVRAM RISC parameter block
968 uint8_t parameter_block_version
;
972 * LSB BIT 0 = Enable Hard Loop Id
973 * LSB BIT 1 = Enable Fairness
974 * LSB BIT 2 = Enable Full-Duplex
975 * LSB BIT 3 = Enable Fast Posting
976 * LSB BIT 4 = Enable Target Mode
977 * LSB BIT 5 = Disable Initiator Mode
978 * LSB BIT 6 = Enable ADISC
979 * LSB BIT 7 = Enable Target Inquiry Data
981 * MSB BIT 0 = Enable PDBC Notify
982 * MSB BIT 1 = Non Participating LIP
983 * MSB BIT 2 = Descending Loop ID Search
984 * MSB BIT 3 = Acquire Loop ID in LIPA
985 * MSB BIT 4 = Stop PortQ on Full Status
986 * MSB BIT 5 = Full Login after LIP
987 * MSB BIT 6 = Node Name Option
988 * MSB BIT 7 = Ext IFWCB enable bit
990 uint8_t firmware_options
[2];
992 uint16_t frame_payload_size
;
993 uint16_t max_iocb_allocation
;
994 uint16_t execution_throttle
;
996 uint8_t retry_delay
; /* unused */
997 uint8_t port_name
[WWN_SIZE
]; /* Big endian. */
998 uint16_t hard_address
;
999 uint8_t inquiry_data
;
1000 uint8_t login_timeout
;
1001 uint8_t node_name
[WWN_SIZE
]; /* Big endian. */
1004 * LSB BIT 0 = Timer Operation mode bit 0
1005 * LSB BIT 1 = Timer Operation mode bit 1
1006 * LSB BIT 2 = Timer Operation mode bit 2
1007 * LSB BIT 3 = Timer Operation mode bit 3
1008 * LSB BIT 4 = Init Config Mode bit 0
1009 * LSB BIT 5 = Init Config Mode bit 1
1010 * LSB BIT 6 = Init Config Mode bit 2
1011 * LSB BIT 7 = Enable Non part on LIHA failure
1013 * MSB BIT 0 = Enable class 2
1014 * MSB BIT 1 = Enable ACK0
1017 * MSB BIT 4 = FC Tape Enable
1018 * MSB BIT 5 = Enable FC Confirm
1019 * MSB BIT 6 = Enable command queuing in target mode
1020 * MSB BIT 7 = No Logo On Link Down
1022 uint8_t add_firmware_options
[2];
1024 uint8_t response_accumulation_timer
;
1025 uint8_t interrupt_delay_timer
;
1028 * LSB BIT 0 = Enable Read xfr_rdy
1029 * LSB BIT 1 = Soft ID only
1032 * LSB BIT 4 = FCP RSP Payload [0]
1033 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
1034 * LSB BIT 6 = Enable Out-of-Order frame handling
1035 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
1037 * MSB BIT 0 = Sbus enable - 2300
1042 * MSB BIT 5 = enable 50 ohm termination
1043 * MSB BIT 6 = Data Rate (2300 only)
1044 * MSB BIT 7 = Data Rate (2300 only)
1046 uint8_t special_options
[2];
1048 /* Reserved for expanded RISC parameter block */
1049 uint8_t reserved_2
[22];
1052 * LSB BIT 0 = Tx Sensitivity 1G bit 0
1053 * LSB BIT 1 = Tx Sensitivity 1G bit 1
1054 * LSB BIT 2 = Tx Sensitivity 1G bit 2
1055 * LSB BIT 3 = Tx Sensitivity 1G bit 3
1056 * LSB BIT 4 = Rx Sensitivity 1G bit 0
1057 * LSB BIT 5 = Rx Sensitivity 1G bit 1
1058 * LSB BIT 6 = Rx Sensitivity 1G bit 2
1059 * LSB BIT 7 = Rx Sensitivity 1G bit 3
1061 * MSB BIT 0 = Tx Sensitivity 2G bit 0
1062 * MSB BIT 1 = Tx Sensitivity 2G bit 1
1063 * MSB BIT 2 = Tx Sensitivity 2G bit 2
1064 * MSB BIT 3 = Tx Sensitivity 2G bit 3
1065 * MSB BIT 4 = Rx Sensitivity 2G bit 0
1066 * MSB BIT 5 = Rx Sensitivity 2G bit 1
1067 * MSB BIT 6 = Rx Sensitivity 2G bit 2
1068 * MSB BIT 7 = Rx Sensitivity 2G bit 3
1070 * LSB BIT 0 = Output Swing 1G bit 0
1071 * LSB BIT 1 = Output Swing 1G bit 1
1072 * LSB BIT 2 = Output Swing 1G bit 2
1073 * LSB BIT 3 = Output Emphasis 1G bit 0
1074 * LSB BIT 4 = Output Emphasis 1G bit 1
1075 * LSB BIT 5 = Output Swing 2G bit 0
1076 * LSB BIT 6 = Output Swing 2G bit 1
1077 * LSB BIT 7 = Output Swing 2G bit 2
1079 * MSB BIT 0 = Output Emphasis 2G bit 0
1080 * MSB BIT 1 = Output Emphasis 2G bit 1
1081 * MSB BIT 2 = Output Enable
1088 uint8_t seriallink_options
[4];
1091 * NVRAM host parameter block
1093 * LSB BIT 0 = Enable spinup delay
1094 * LSB BIT 1 = Disable BIOS
1095 * LSB BIT 2 = Enable Memory Map BIOS
1096 * LSB BIT 3 = Enable Selectable Boot
1097 * LSB BIT 4 = Disable RISC code load
1098 * LSB BIT 5 = Set cache line size 1
1099 * LSB BIT 6 = PCI Parity Disable
1100 * LSB BIT 7 = Enable extended logging
1102 * MSB BIT 0 = Enable 64bit addressing
1103 * MSB BIT 1 = Enable lip reset
1104 * MSB BIT 2 = Enable lip full login
1105 * MSB BIT 3 = Enable target reset
1106 * MSB BIT 4 = Enable database storage
1107 * MSB BIT 5 = Enable cache flush read
1108 * MSB BIT 6 = Enable database load
1109 * MSB BIT 7 = Enable alternate WWN
1113 uint8_t boot_node_name
[WWN_SIZE
];
1114 uint8_t boot_lun_number
;
1115 uint8_t reset_delay
;
1116 uint8_t port_down_retry_count
;
1117 uint8_t boot_id_number
;
1118 uint16_t max_luns_per_target
;
1119 uint8_t fcode_boot_port_name
[WWN_SIZE
];
1120 uint8_t alternate_port_name
[WWN_SIZE
];
1121 uint8_t alternate_node_name
[WWN_SIZE
];
1124 * BIT 0 = Selective Login
1125 * BIT 1 = Alt-Boot Enable
1127 * BIT 3 = Boot Order List
1129 * BIT 5 = Selective LUN
1133 uint8_t efi_parameters
;
1135 uint8_t link_down_timeout
;
1137 uint8_t adapter_id_0
[4];
1138 uint8_t adapter_id_1
[4];
1139 uint8_t adapter_id_2
[4];
1140 uint8_t adapter_id_3
[4];
1142 uint8_t alt1_boot_node_name
[WWN_SIZE
];
1143 uint16_t alt1_boot_lun_number
;
1144 uint8_t alt2_boot_node_name
[WWN_SIZE
];
1145 uint16_t alt2_boot_lun_number
;
1146 uint8_t alt3_boot_node_name
[WWN_SIZE
];
1147 uint16_t alt3_boot_lun_number
;
1148 uint8_t alt4_boot_node_name
[WWN_SIZE
];
1149 uint16_t alt4_boot_lun_number
;
1150 uint8_t alt5_boot_node_name
[WWN_SIZE
];
1151 uint16_t alt5_boot_lun_number
;
1152 uint8_t alt6_boot_node_name
[WWN_SIZE
];
1153 uint16_t alt6_boot_lun_number
;
1154 uint8_t alt7_boot_node_name
[WWN_SIZE
];
1155 uint16_t alt7_boot_lun_number
;
1157 uint8_t reserved_3
[2];
1159 /* Offset 200-215 : Model Number */
1160 uint8_t model_number
[16];
1162 /* OEM related items */
1163 uint8_t oem_specific
[16];
1166 * NVRAM Adapter Features offset 232-239
1168 * LSB BIT 0 = External GBIC
1169 * LSB BIT 1 = Risc RAM parity
1170 * LSB BIT 2 = Buffer Plus Module
1171 * LSB BIT 3 = Multi Chip Adapter
1172 * LSB BIT 4 = Internal connector
1186 uint8_t adapter_features
[2];
1188 uint8_t reserved_4
[16];
1190 /* Subsystem vendor ID for ISP2200 */
1191 uint16_t subsystem_vendor_id_2200
;
1193 /* Subsystem device ID for ISP2200 */
1194 uint16_t subsystem_device_id_2200
;
1201 * ISP queue - response queue entry definition.
1206 #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */
1217 #define SET_TARGET_ID(ha, to, from) \
1219 if (HAS_EXTENDED_IDS(ha)) \
1220 to.extended = cpu_to_le16(from); \
1222 to.id.standard = (uint8_t)from; \
1226 * ISP queue - command entry structure definition.
1228 #define COMMAND_TYPE 0x11 /* Command entry */
1230 uint8_t entry_type
; /* Entry type. */
1231 uint8_t entry_count
; /* Entry count. */
1232 uint8_t sys_define
; /* System defined. */
1233 uint8_t entry_status
; /* Entry Status. */
1234 uint32_t handle
; /* System handle. */
1235 target_id_t target
; /* SCSI ID */
1236 uint16_t lun
; /* SCSI LUN */
1237 uint16_t control_flags
; /* Control flags. */
1238 #define CF_WRITE BIT_6
1239 #define CF_READ BIT_5
1240 #define CF_SIMPLE_TAG BIT_3
1241 #define CF_ORDERED_TAG BIT_2
1242 #define CF_HEAD_TAG BIT_1
1243 uint16_t reserved_1
;
1244 uint16_t timeout
; /* Command timeout. */
1245 uint16_t dseg_count
; /* Data segment count. */
1246 uint8_t scsi_cdb
[MAX_CMDSZ
]; /* SCSI command words. */
1247 uint32_t byte_count
; /* Total byte count. */
1248 uint32_t dseg_0_address
; /* Data segment 0 address. */
1249 uint32_t dseg_0_length
; /* Data segment 0 length. */
1250 uint32_t dseg_1_address
; /* Data segment 1 address. */
1251 uint32_t dseg_1_length
; /* Data segment 1 length. */
1252 uint32_t dseg_2_address
; /* Data segment 2 address. */
1253 uint32_t dseg_2_length
; /* Data segment 2 length. */
1257 * ISP queue - 64-Bit addressing, command entry structure definition.
1259 #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */
1261 uint8_t entry_type
; /* Entry type. */
1262 uint8_t entry_count
; /* Entry count. */
1263 uint8_t sys_define
; /* System defined. */
1264 uint8_t entry_status
; /* Entry Status. */
1265 uint32_t handle
; /* System handle. */
1266 target_id_t target
; /* SCSI ID */
1267 uint16_t lun
; /* SCSI LUN */
1268 uint16_t control_flags
; /* Control flags. */
1269 uint16_t reserved_1
;
1270 uint16_t timeout
; /* Command timeout. */
1271 uint16_t dseg_count
; /* Data segment count. */
1272 uint8_t scsi_cdb
[MAX_CMDSZ
]; /* SCSI command words. */
1273 uint32_t byte_count
; /* Total byte count. */
1274 uint32_t dseg_0_address
[2]; /* Data segment 0 address. */
1275 uint32_t dseg_0_length
; /* Data segment 0 length. */
1276 uint32_t dseg_1_address
[2]; /* Data segment 1 address. */
1277 uint32_t dseg_1_length
; /* Data segment 1 length. */
1278 } cmd_a64_entry_t
, request_t
;
1281 * ISP queue - continuation entry structure definition.
1283 #define CONTINUE_TYPE 0x02 /* Continuation entry. */
1285 uint8_t entry_type
; /* Entry type. */
1286 uint8_t entry_count
; /* Entry count. */
1287 uint8_t sys_define
; /* System defined. */
1288 uint8_t entry_status
; /* Entry Status. */
1290 uint32_t dseg_0_address
; /* Data segment 0 address. */
1291 uint32_t dseg_0_length
; /* Data segment 0 length. */
1292 uint32_t dseg_1_address
; /* Data segment 1 address. */
1293 uint32_t dseg_1_length
; /* Data segment 1 length. */
1294 uint32_t dseg_2_address
; /* Data segment 2 address. */
1295 uint32_t dseg_2_length
; /* Data segment 2 length. */
1296 uint32_t dseg_3_address
; /* Data segment 3 address. */
1297 uint32_t dseg_3_length
; /* Data segment 3 length. */
1298 uint32_t dseg_4_address
; /* Data segment 4 address. */
1299 uint32_t dseg_4_length
; /* Data segment 4 length. */
1300 uint32_t dseg_5_address
; /* Data segment 5 address. */
1301 uint32_t dseg_5_length
; /* Data segment 5 length. */
1302 uint32_t dseg_6_address
; /* Data segment 6 address. */
1303 uint32_t dseg_6_length
; /* Data segment 6 length. */
1307 * ISP queue - 64-Bit addressing, continuation entry structure definition.
1309 #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */
1311 uint8_t entry_type
; /* Entry type. */
1312 uint8_t entry_count
; /* Entry count. */
1313 uint8_t sys_define
; /* System defined. */
1314 uint8_t entry_status
; /* Entry Status. */
1315 uint32_t dseg_0_address
[2]; /* Data segment 0 address. */
1316 uint32_t dseg_0_length
; /* Data segment 0 length. */
1317 uint32_t dseg_1_address
[2]; /* Data segment 1 address. */
1318 uint32_t dseg_1_length
; /* Data segment 1 length. */
1319 uint32_t dseg_2_address
[2]; /* Data segment 2 address. */
1320 uint32_t dseg_2_length
; /* Data segment 2 length. */
1321 uint32_t dseg_3_address
[2]; /* Data segment 3 address. */
1322 uint32_t dseg_3_length
; /* Data segment 3 length. */
1323 uint32_t dseg_4_address
[2]; /* Data segment 4 address. */
1324 uint32_t dseg_4_length
; /* Data segment 4 length. */
1328 * ISP queue - status entry structure definition.
1330 #define STATUS_TYPE 0x03 /* Status entry. */
1332 uint8_t entry_type
; /* Entry type. */
1333 uint8_t entry_count
; /* Entry count. */
1334 uint8_t sys_define
; /* System defined. */
1335 uint8_t entry_status
; /* Entry Status. */
1336 uint32_t handle
; /* System handle. */
1337 uint16_t scsi_status
; /* SCSI status. */
1338 uint16_t comp_status
; /* Completion status. */
1339 uint16_t state_flags
; /* State flags. */
1340 uint16_t status_flags
; /* Status flags. */
1341 uint16_t rsp_info_len
; /* Response Info Length. */
1342 uint16_t req_sense_length
; /* Request sense data length. */
1343 uint32_t residual_length
; /* Residual transfer length. */
1344 uint8_t rsp_info
[8]; /* FCP response information. */
1345 uint8_t req_sense_data
[32]; /* Request sense data. */
1349 * Status entry entry status
1351 #define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */
1352 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
1353 #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */
1354 #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */
1355 #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */
1356 #define RF_BUSY BIT_1 /* Busy */
1357 #define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \
1358 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY)
1359 #define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \
1363 * Status entry SCSI status bit definitions.
1365 #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/
1366 #define SS_RESIDUAL_UNDER BIT_11
1367 #define SS_RESIDUAL_OVER BIT_10
1368 #define SS_SENSE_LEN_VALID BIT_9
1369 #define SS_RESPONSE_INFO_LEN_VALID BIT_8
1371 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
1372 #define SS_BUSY_CONDITION BIT_3
1373 #define SS_CONDITION_MET BIT_2
1374 #define SS_CHECK_CONDITION BIT_1
1377 * Status entry completion status
1379 #define CS_COMPLETE 0x0 /* No errors */
1380 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */
1381 #define CS_DMA 0x2 /* A DMA direction error. */
1382 #define CS_TRANSPORT 0x3 /* Transport error. */
1383 #define CS_RESET 0x4 /* SCSI bus reset occurred */
1384 #define CS_ABORTED 0x5 /* System aborted command. */
1385 #define CS_TIMEOUT 0x6 /* Timeout error. */
1386 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */
1388 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */
1389 #define CS_QUEUE_FULL 0x1C /* Queue Full. */
1390 #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */
1391 /* (selection timeout) */
1392 #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */
1393 #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */
1394 #define CS_PORT_BUSY 0x2B /* Port Busy */
1395 #define CS_COMPLETE_CHKCOND 0x30 /* Error? */
1396 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */
1397 #define CS_UNKNOWN 0x81 /* Driver defined */
1398 #define CS_RETRY 0x82 /* Driver defined */
1399 #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */
1402 * Status entry status flags
1404 #define SF_ABTS_TERMINATED BIT_10
1405 #define SF_LOGOUT_SENT BIT_13
1408 * ISP queue - status continuation entry structure definition.
1410 #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */
1412 uint8_t entry_type
; /* Entry type. */
1413 uint8_t entry_count
; /* Entry count. */
1414 uint8_t sys_define
; /* System defined. */
1415 uint8_t entry_status
; /* Entry Status. */
1416 uint8_t data
[60]; /* data */
1420 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles)
1421 * structure definition.
1423 #define STATUS_TYPE_21 0x21 /* Status entry. */
1425 uint8_t entry_type
; /* Entry type. */
1426 uint8_t entry_count
; /* Entry count. */
1427 uint8_t handle_count
; /* Handle count. */
1428 uint8_t entry_status
; /* Entry Status. */
1429 uint32_t handle
[15]; /* System handles. */
1433 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles)
1434 * structure definition.
1436 #define STATUS_TYPE_22 0x22 /* Status entry. */
1438 uint8_t entry_type
; /* Entry type. */
1439 uint8_t entry_count
; /* Entry count. */
1440 uint8_t handle_count
; /* Handle count. */
1441 uint8_t entry_status
; /* Entry Status. */
1442 uint16_t handle
[30]; /* System handles. */
1446 * ISP queue - marker entry structure definition.
1448 #define MARKER_TYPE 0x04 /* Marker entry. */
1450 uint8_t entry_type
; /* Entry type. */
1451 uint8_t entry_count
; /* Entry count. */
1452 uint8_t handle_count
; /* Handle count. */
1453 uint8_t entry_status
; /* Entry Status. */
1454 uint32_t sys_define_2
; /* System defined. */
1455 target_id_t target
; /* SCSI ID */
1456 uint8_t modifier
; /* Modifier (7-0). */
1457 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
1458 #define MK_SYNC_ID 1 /* Synchronize ID */
1459 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
1460 #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */
1461 /* clear port changed, */
1462 /* use sequence number. */
1464 uint16_t sequence_number
; /* Sequence number of event */
1465 uint16_t lun
; /* SCSI LUN */
1466 uint8_t reserved_2
[48];
1470 * ISP queue - Management Server entry structure definition.
1472 #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */
1474 uint8_t entry_type
; /* Entry type. */
1475 uint8_t entry_count
; /* Entry count. */
1476 uint8_t handle_count
; /* Handle count. */
1477 uint8_t entry_status
; /* Entry Status. */
1478 uint32_t handle1
; /* System handle. */
1479 target_id_t loop_id
;
1481 uint16_t control_flags
; /* Control flags. */
1484 uint16_t cmd_dsd_count
;
1485 uint16_t total_dsd_count
;
1491 uint32_t rsp_bytecount
;
1492 uint32_t req_bytecount
;
1493 uint32_t dseg_req_address
[2]; /* Data segment 0 address. */
1494 uint32_t dseg_req_length
; /* Data segment 0 length. */
1495 uint32_t dseg_rsp_address
[2]; /* Data segment 1 address. */
1496 uint32_t dseg_rsp_length
; /* Data segment 1 length. */
1501 * ISP queue - Mailbox Command entry structure definition.
1503 #define MBX_IOCB_TYPE 0x39
1506 uint8_t entry_count
;
1507 uint8_t sys_define1
;
1508 /* Use sys_define1 for source type */
1509 #define SOURCE_SCSI 0x00
1510 #define SOURCE_IP 0x01
1511 #define SOURCE_VI 0x02
1512 #define SOURCE_SCTP 0x03
1513 #define SOURCE_MP 0x04
1514 #define SOURCE_MPIOCTL 0x05
1515 #define SOURCE_ASYNC_IOCB 0x07
1517 uint8_t entry_status
;
1520 target_id_t loop_id
;
1523 uint16_t state_flags
;
1524 uint16_t status_flags
;
1526 uint32_t sys_define2
[2];
1536 uint32_t reserved_2
[2];
1537 uint8_t node_name
[WWN_SIZE
];
1538 uint8_t port_name
[WWN_SIZE
];
1542 * ISP request and response queue entry sizes
1544 #define RESPONSE_ENTRY_SIZE (sizeof(response_t))
1545 #define REQUEST_ENTRY_SIZE (sizeof(request_t))
1549 * 24 bit port ID type definition.
1566 #define INVALID_PORT_ID 0xFFFFFF
1569 * Switch info gathering structure.
1573 uint8_t node_name
[WWN_SIZE
];
1574 uint8_t port_name
[WWN_SIZE
];
1578 * Inquiry command structure.
1580 #define INQ_DATA_SIZE 36
1583 * Inquiry mailbox IOCB packet definition.
1587 cmd_a64_entry_t cmd
;
1589 struct cmd_type_7 cmd24
;
1590 struct sts_entry_24xx rsp24
;
1592 uint8_t inq
[INQ_DATA_SIZE
];
1596 * Report LUN command structure.
1598 #define CHAR_TO_SHORT(a, b) (uint16_t)((uint8_t)b << 8 | (uint8_t)a)
1608 uint8_t address_method
: 2;
1616 rpt_lun_t lst
[MAX_LUNS
];
1620 * Report Lun mailbox IOCB packet definition.
1624 cmd_a64_entry_t cmd
;
1626 struct cmd_type_7 cmd24
;
1627 struct sts_entry_24xx rsp24
;
1630 } rpt_lun_cmd_rsp_t
;
1634 * Fibre channel port type.
1646 * Fibre channel port structure.
1648 typedef struct fc_port
{
1649 struct list_head list
;
1650 struct scsi_qla_host
*ha
;
1651 struct scsi_qla_host
*vis_ha
; /* only used when suspending lun */
1653 uint8_t node_name
[WWN_SIZE
];
1654 uint8_t port_name
[WWN_SIZE
];
1657 uint16_t old_loop_id
;
1659 fc_port_type_t port_type
;
1664 unsigned int os_target_id
;
1666 uint16_t iodesc_idx_sent
;
1668 int port_login_retry_count
;
1670 atomic_t port_down_timer
;
1672 uint8_t device_type
;
1675 uint8_t mp_byte
; /* multi-path byte (not used) */
1676 uint8_t cur_path
; /* current path id */
1678 struct fc_rport
*rport
;
1682 * Fibre channel port/lun states.
1684 #define FCS_UNCONFIGURED 1
1685 #define FCS_DEVICE_DEAD 2
1686 #define FCS_DEVICE_LOST 3
1687 #define FCS_ONLINE 4
1688 #define FCS_NOT_SUPPORTED 5
1689 #define FCS_FAILOVER 6
1690 #define FCS_FAILOVER_FAILED 7
1695 #define FCF_FABRIC_DEVICE BIT_0
1696 #define FCF_LOGIN_NEEDED BIT_1
1697 #define FCF_FO_MASKED BIT_2
1698 #define FCF_FAILOVER_NEEDED BIT_3
1699 #define FCF_RESET_NEEDED BIT_4
1700 #define FCF_PERSISTENT_BOUND BIT_5
1701 #define FCF_TAPE_PRESENT BIT_6
1702 #define FCF_FARP_DONE BIT_7
1703 #define FCF_FARP_FAILED BIT_8
1704 #define FCF_FARP_REPLY_NEEDED BIT_9
1705 #define FCF_AUTH_REQ BIT_10
1706 #define FCF_SEND_AUTH_REQ BIT_11
1707 #define FCF_RECEIVE_AUTH_REQ BIT_12
1708 #define FCF_AUTH_SUCCESS BIT_13
1709 #define FCF_RLC_SUPPORT BIT_14
1710 #define FCF_CONFIG BIT_15 /* Needed? */
1711 #define FCF_RESCAN_NEEDED BIT_16
1712 #define FCF_XP_DEVICE BIT_17
1713 #define FCF_MSA_DEVICE BIT_18
1714 #define FCF_EVA_DEVICE BIT_19
1715 #define FCF_MSA_PORT_ACTIVE BIT_20
1716 #define FCF_FAILBACK_DISABLE BIT_21
1717 #define FCF_FAILOVER_DISABLE BIT_22
1718 #define FCF_DSXXX_DEVICE BIT_23
1719 #define FCF_AA_EVA_DEVICE BIT_24
1720 #define FCF_AA_MSA_DEVICE BIT_25
1722 /* No loop ID flag. */
1723 #define FC_NO_LOOP_ID 0x1000
1728 * NOTE: All structures are big-endian in form.
1731 #define CT_REJECT_RESPONSE 0x8001
1732 #define CT_ACCEPT_RESPONSE 0x8002
1734 #define NS_N_PORT_TYPE 0x01
1735 #define NS_NL_PORT_TYPE 0x02
1736 #define NS_NX_PORT_TYPE 0x7F
1738 #define GA_NXT_CMD 0x100
1739 #define GA_NXT_REQ_SIZE (16 + 4)
1740 #define GA_NXT_RSP_SIZE (16 + 620)
1742 #define GID_PT_CMD 0x1A1
1743 #define GID_PT_REQ_SIZE (16 + 4)
1744 #define GID_PT_RSP_SIZE (16 + (MAX_FIBRE_DEVICES * 4))
1746 #define GPN_ID_CMD 0x112
1747 #define GPN_ID_REQ_SIZE (16 + 4)
1748 #define GPN_ID_RSP_SIZE (16 + 8)
1750 #define GNN_ID_CMD 0x113
1751 #define GNN_ID_REQ_SIZE (16 + 4)
1752 #define GNN_ID_RSP_SIZE (16 + 8)
1754 #define GFT_ID_CMD 0x117
1755 #define GFT_ID_REQ_SIZE (16 + 4)
1756 #define GFT_ID_RSP_SIZE (16 + 32)
1758 #define RFT_ID_CMD 0x217
1759 #define RFT_ID_REQ_SIZE (16 + 4 + 32)
1760 #define RFT_ID_RSP_SIZE 16
1762 #define RFF_ID_CMD 0x21F
1763 #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1)
1764 #define RFF_ID_RSP_SIZE 16
1766 #define RNN_ID_CMD 0x213
1767 #define RNN_ID_REQ_SIZE (16 + 4 + 8)
1768 #define RNN_ID_RSP_SIZE 16
1770 #define RSNN_NN_CMD 0x239
1771 #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255)
1772 #define RSNN_NN_RSP_SIZE 16
1774 /* CT command header -- request/response common fields */
1784 /* CT command request */
1786 struct ct_cmd_hdr header
;
1788 uint16_t max_rsp_size
;
1789 uint8_t fragment_id
;
1790 uint8_t reserved
[3];
1793 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID */
1809 uint8_t fc4_types
[32];
1816 uint8_t fc4_feature
;
1823 uint8_t node_name
[8];
1827 uint8_t node_name
[8];
1829 uint8_t sym_node_name
[255];
1834 /* CT command response header */
1836 struct ct_cmd_hdr header
;
1839 uint8_t fragment_id
;
1840 uint8_t reason_code
;
1841 uint8_t explanation_code
;
1842 uint8_t vendor_unique
;
1845 struct ct_sns_gid_pt_data
{
1846 uint8_t control_byte
;
1851 struct ct_rsp_hdr header
;
1857 uint8_t port_name
[8];
1858 uint8_t sym_port_name_len
;
1859 uint8_t sym_port_name
[255];
1860 uint8_t node_name
[8];
1861 uint8_t sym_node_name_len
;
1862 uint8_t sym_node_name
[255];
1863 uint8_t init_proc_assoc
[8];
1864 uint8_t node_ip_addr
[16];
1865 uint8_t class_of_service
[4];
1866 uint8_t fc4_types
[32];
1867 uint8_t ip_address
[16];
1868 uint8_t fabric_port_name
[8];
1870 uint8_t hard_address
[3];
1874 struct ct_sns_gid_pt_data entries
[MAX_FIBRE_DEVICES
];
1878 uint8_t port_name
[8];
1882 uint8_t node_name
[8];
1886 uint8_t fc4_types
[32];
1893 struct ct_sns_req req
;
1894 struct ct_sns_rsp rsp
;
1899 * SNS command structures -- for 2200 compatability.
1901 #define RFT_ID_SNS_SCMD_LEN 22
1902 #define RFT_ID_SNS_CMD_SIZE 60
1903 #define RFT_ID_SNS_DATA_SIZE 16
1905 #define RNN_ID_SNS_SCMD_LEN 10
1906 #define RNN_ID_SNS_CMD_SIZE 36
1907 #define RNN_ID_SNS_DATA_SIZE 16
1909 #define GA_NXT_SNS_SCMD_LEN 6
1910 #define GA_NXT_SNS_CMD_SIZE 28
1911 #define GA_NXT_SNS_DATA_SIZE (620 + 16)
1913 #define GID_PT_SNS_SCMD_LEN 6
1914 #define GID_PT_SNS_CMD_SIZE 28
1915 #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES * 4 + 16)
1917 #define GPN_ID_SNS_SCMD_LEN 6
1918 #define GPN_ID_SNS_CMD_SIZE 28
1919 #define GPN_ID_SNS_DATA_SIZE (8 + 16)
1921 #define GNN_ID_SNS_SCMD_LEN 6
1922 #define GNN_ID_SNS_CMD_SIZE 28
1923 #define GNN_ID_SNS_DATA_SIZE (8 + 16)
1925 struct sns_cmd_pkt
{
1928 uint16_t buffer_length
;
1929 uint16_t reserved_1
;
1930 uint32_t buffer_address
[2];
1931 uint16_t subcommand_length
;
1932 uint16_t reserved_2
;
1933 uint16_t subcommand
;
1935 uint32_t reserved_3
;
1939 uint8_t rft_data
[RFT_ID_SNS_DATA_SIZE
];
1940 uint8_t rnn_data
[RNN_ID_SNS_DATA_SIZE
];
1941 uint8_t gan_data
[GA_NXT_SNS_DATA_SIZE
];
1942 uint8_t gid_data
[GID_PT_SNS_DATA_SIZE
];
1943 uint8_t gpn_data
[GPN_ID_SNS_DATA_SIZE
];
1944 uint8_t gnn_data
[GNN_ID_SNS_DATA_SIZE
];
1948 /* IO descriptors */
1949 #define MAX_IO_DESCRIPTORS 32
1951 #define ABORT_IOCB_CB 0
1952 #define ADISC_PORT_IOCB_CB 1
1953 #define LOGOUT_PORT_IOCB_CB 2
1954 #define LOGIN_PORT_IOCB_CB 3
1955 #define LAST_IOCB_CB 4
1957 #define IODESC_INVALID_INDEX 0xFFFF
1958 #define IODESC_ADISC_NEEDED 0xFFFE
1959 #define IODESC_LOGIN_NEEDED 0xFFFD
1961 struct io_descriptor
{
1966 struct timer_list timer
;
1968 struct scsi_qla_host
*ha
;
1971 fc_port_t
*remote_fcport
;
1976 struct qla_fw_info
{
1977 unsigned short addressing
; /* addressing method used to load fw */
1978 #define FW_INFO_ADDR_NORMAL 0
1979 #define FW_INFO_ADDR_EXTENDED 1
1980 #define FW_INFO_ADDR_NOMORE 0xffff
1981 unsigned short *fwcode
; /* pointer to FW array */
1982 unsigned short *fwlen
; /* number of words in array */
1983 unsigned short *fwstart
; /* start address for F/W */
1984 unsigned long *lfwstart
; /* start address (long) for F/W */
1987 struct qla_board_info
{
1991 struct qla_fw_info
*fw_info
;
1993 struct scsi_host_template
*sht
;
1996 /* Return data from MBC_GET_ID_LIST call. */
1997 struct gid_list_info
{
2001 uint8_t loop_id_2100
; /* ISP2100/ISP2200 -- 4 bytes. */
2002 uint16_t loop_id
; /* ISP23XX -- 6 bytes. */
2003 uint16_t reserved_1
; /* ISP24XX -- 8 bytes. */
2005 #define GID_LIST_SIZE (sizeof(struct gid_list_info) * MAX_FIBRE_DEVICES)
2010 struct isp_operations
{
2012 int (*pci_config
) (struct scsi_qla_host
*);
2013 void (*reset_chip
) (struct scsi_qla_host
*);
2014 int (*chip_diag
) (struct scsi_qla_host
*);
2015 void (*config_rings
) (struct scsi_qla_host
*);
2016 void (*reset_adapter
) (struct scsi_qla_host
*);
2017 int (*nvram_config
) (struct scsi_qla_host
*);
2018 void (*update_fw_options
) (struct scsi_qla_host
*);
2019 int (*load_risc
) (struct scsi_qla_host
*, uint32_t *);
2021 char * (*pci_info_str
) (struct scsi_qla_host
*, char *);
2022 char * (*fw_version_str
) (struct scsi_qla_host
*, char *);
2024 irqreturn_t (*intr_handler
) (int, void *, struct pt_regs
*);
2025 void (*enable_intrs
) (struct scsi_qla_host
*);
2026 void (*disable_intrs
) (struct scsi_qla_host
*);
2028 int (*abort_command
) (struct scsi_qla_host
*, srb_t
*);
2029 int (*abort_target
) (struct fc_port
*);
2030 int (*fabric_login
) (struct scsi_qla_host
*, uint16_t, uint8_t,
2031 uint8_t, uint8_t, uint16_t *, uint8_t);
2032 int (*fabric_logout
) (struct scsi_qla_host
*, uint16_t, uint8_t,
2035 uint16_t (*calc_req_entries
) (uint16_t);
2036 void (*build_iocbs
) (srb_t
*, cmd_entry_t
*, uint16_t);
2037 void * (*prep_ms_iocb
) (struct scsi_qla_host
*, uint32_t, uint32_t);
2039 uint8_t * (*read_nvram
) (struct scsi_qla_host
*, uint8_t *,
2040 uint32_t, uint32_t);
2041 int (*write_nvram
) (struct scsi_qla_host
*, uint8_t *, uint32_t,
2044 void (*fw_dump
) (struct scsi_qla_host
*, int);
2045 void (*ascii_fw_dump
) (struct scsi_qla_host
*);
2049 * Linux Host Adapter structure
2051 typedef struct scsi_qla_host
{
2052 struct list_head list
;
2054 /* Commonly used flags and state information. */
2055 struct Scsi_Host
*host
;
2056 struct pci_dev
*pdev
;
2058 unsigned long host_no
;
2059 unsigned long instance
;
2062 uint32_t init_done
:1;
2064 uint32_t mbox_int
:1;
2065 uint32_t mbox_busy
:1;
2066 uint32_t rscn_queue_overflow
:1;
2067 uint32_t reset_active
:1;
2069 uint32_t management_server_logged_in
:1;
2070 uint32_t process_response_queue
:1;
2072 uint32_t disable_risc_code_load
:1;
2073 uint32_t enable_64bit_addressing
:1;
2074 uint32_t enable_lip_reset
:1;
2075 uint32_t enable_lip_full_login
:1;
2076 uint32_t enable_target_reset
:1;
2077 uint32_t enable_led_scheme
:1;
2078 uint32_t msi_enabled
:1;
2079 uint32_t msix_enabled
:1;
2082 atomic_t loop_state
;
2083 #define LOOP_TIMEOUT 1
2086 #define LOOP_UPDATE 4
2087 #define LOOP_READY 5
2090 unsigned long dpc_flags
;
2091 #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */
2092 #define RESET_ACTIVE 1
2093 #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */
2094 #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */
2095 #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */
2096 #define LOOP_RESYNC_ACTIVE 5
2097 #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */
2098 #define RSCN_UPDATE 7 /* Perform an RSCN update. */
2099 #define MAILBOX_RETRY 8
2100 #define ISP_RESET_NEEDED 9 /* Initiate a ISP reset. */
2101 #define FAILOVER_EVENT_NEEDED 10
2102 #define FAILOVER_EVENT 11
2103 #define FAILOVER_NEEDED 12
2104 #define SCSI_RESTART_NEEDED 13 /* Processes SCSI retry queue. */
2105 #define PORT_RESTART_NEEDED 14 /* Processes Retry queue. */
2106 #define RESTART_QUEUES_NEEDED 15 /* Restarts the Lun queue. */
2107 #define ABORT_QUEUES_NEEDED 16
2108 #define RELOGIN_NEEDED 17
2109 #define LOGIN_RETRY_NEEDED 18 /* Initiate required fabric logins. */
2110 #define REGISTER_FC4_NEEDED 19 /* SNS FC4 registration required. */
2111 #define ISP_ABORT_RETRY 20 /* ISP aborted. */
2112 #define FCPORT_RESCAN_NEEDED 21 /* IO descriptor processing needed */
2113 #define IODESC_PROCESS_NEEDED 22 /* IO descriptor processing needed */
2114 #define IOCTL_ERROR_RECOVERY 23
2115 #define LOOP_RESET_NEEDED 24
2116 #define BEACON_BLINK_NEEDED 25
2118 uint32_t device_flags
;
2119 #define DFLG_LOCAL_DEVICES BIT_0
2120 #define DFLG_RETRY_LOCAL_DEVICES BIT_1
2121 #define DFLG_FABRIC_DEVICES BIT_2
2122 #define SWITCH_FOUND BIT_3
2123 #define DFLG_NO_CABLE BIT_4
2126 #define SRB_MIN_REQ 128
2127 mempool_t
*srb_mempool
;
2129 /* This spinlock is used to protect "io transactions", you must
2130 * aquire it before doing any IO to the card, eg with RD_REG*() and
2131 * WRT_REG*() for the duration of your entire commandtransaction.
2133 * This spinlock is of lower priority than the io request lock.
2136 spinlock_t hardware_lock ____cacheline_aligned
;
2138 device_reg_t __iomem
*iobase
; /* Base I/O address */
2139 unsigned long pio_address
;
2140 unsigned long pio_length
;
2141 #define MIN_IOBASE_LEN 0x100
2143 /* ISP ring lock, rings, and indexes */
2144 dma_addr_t request_dma
; /* Physical address. */
2145 request_t
*request_ring
; /* Base virtual address */
2146 request_t
*request_ring_ptr
; /* Current address. */
2147 uint16_t req_ring_index
; /* Current index. */
2148 uint16_t req_q_cnt
; /* Number of available entries. */
2149 uint16_t request_q_length
;
2151 dma_addr_t response_dma
; /* Physical address. */
2152 response_t
*response_ring
; /* Base virtual address */
2153 response_t
*response_ring_ptr
; /* Current address. */
2154 uint16_t rsp_ring_index
; /* Current index. */
2155 uint16_t response_q_length
;
2157 struct isp_operations isp_ops
;
2159 /* Outstandings ISP commands. */
2160 srb_t
*outstanding_cmds
[MAX_OUTSTANDING_COMMANDS
];
2161 uint32_t current_outstanding_cmd
;
2162 srb_t
*status_srb
; /* Status continuation entry. */
2167 /* ISP configuration data. */
2168 uint16_t loop_id
; /* Host adapter loop id */
2171 port_id_t d_id
; /* Host adapter port id */
2172 uint16_t max_public_loop_ids
;
2173 uint16_t min_external_loopid
; /* First external loop Id */
2175 uint16_t link_data_rate
; /* F/W operating speed */
2177 uint8_t current_topology
;
2178 uint8_t prev_topology
;
2179 #define ISP_CFG_NL 1
2181 #define ISP_CFG_FL 4
2184 uint8_t operating_mode
; /* F/W operating mode */
2190 uint8_t marker_needed
;
2192 uint8_t interrupts_on
;
2194 /* HBA serial number */
2199 /* NVRAM configuration data */
2200 uint16_t nvram_size
;
2201 uint16_t nvram_base
;
2203 uint16_t loop_reset_delay
;
2204 uint8_t retry_count
;
2205 uint8_t login_timeout
;
2207 int port_down_retry_count
;
2209 uint16_t last_loop_id
;
2211 uint32_t login_retry_count
;
2213 /* Fibre Channel Device List. */
2214 struct list_head fcports
;
2215 struct list_head rscn_fcports
;
2217 struct io_descriptor io_descriptors
[MAX_IO_DESCRIPTORS
];
2218 uint16_t iodesc_signature
;
2221 uint32_t rscn_queue
[MAX_RSCN_COUNT
];
2222 uint8_t rscn_in_ptr
;
2223 uint8_t rscn_out_ptr
;
2225 /* SNS command interfaces. */
2226 ms_iocb_entry_t
*ms_iocb
;
2227 dma_addr_t ms_iocb_dma
;
2228 struct ct_sns_pkt
*ct_sns
;
2229 dma_addr_t ct_sns_dma
;
2230 /* SNS command interfaces for 2200. */
2231 struct sns_cmd_pkt
*sns_cmd
;
2232 dma_addr_t sns_cmd_dma
;
2236 struct completion dpc_inited
;
2237 struct completion dpc_exited
;
2238 struct semaphore
*dpc_wait
;
2239 uint8_t dpc_active
; /* DPC routine is active */
2241 /* Timeout timers. */
2242 uint8_t loop_down_abort_time
; /* port down timer */
2243 atomic_t loop_down_timer
; /* loop down timer */
2244 uint8_t link_down_timeout
; /* link down timeout */
2246 uint32_t timer_active
;
2247 struct timer_list timer
;
2249 dma_addr_t gid_list_dma
;
2250 struct gid_list_info
*gid_list
;
2251 int gid_list_info_size
;
2253 dma_addr_t rlc_rsp_dma
;
2254 rpt_lun_cmd_rsp_t
*rlc_rsp
;
2256 /* Small DMA pool allocations -- maximum 256 bytes in length. */
2257 #define DMA_POOL_SIZE 256
2258 struct dma_pool
*s_dma_pool
;
2260 dma_addr_t init_cb_dma
;
2264 dma_addr_t iodesc_pd_dma
;
2265 port_database_t
*iodesc_pd
;
2267 /* These are used by mailbox operations. */
2268 volatile uint16_t mailbox_out
[MAILBOX_REGISTER_COUNT
];
2271 unsigned long mbx_cmd_flags
;
2272 #define MBX_INTERRUPT 1
2273 #define MBX_INTR_WAIT 2
2274 #define MBX_UPDATE_FLASH_ACTIVE 3
2276 spinlock_t mbx_reg_lock
; /* Mbx Cmd Register Lock */
2278 struct semaphore mbx_cmd_sem
; /* Serialialize mbx access */
2279 struct semaphore mbx_intr_sem
; /* Used for completion notification */
2282 #define MBX_IN_PROGRESS BIT_0
2283 #define MBX_BUSY BIT_1 /* Got the Access */
2284 #define MBX_SLEEPING_ON_SEM BIT_2
2285 #define MBX_POLLING_FOR_COMP BIT_3
2286 #define MBX_COMPLETED BIT_4
2287 #define MBX_TIMEDOUT BIT_5
2288 #define MBX_ACCESS_TIMEDOUT BIT_6
2292 /* Basic firmware related information. */
2293 struct qla_board_info
*brd_info
;
2294 uint16_t fw_major_version
;
2295 uint16_t fw_minor_version
;
2296 uint16_t fw_subminor_version
;
2297 uint16_t fw_attributes
;
2298 uint32_t fw_memory_size
;
2299 uint32_t fw_transfer_size
;
2301 uint16_t fw_options
[16]; /* slots: 1,2,3,10,11 */
2302 uint8_t fw_seriallink_options
[4];
2303 uint16_t fw_seriallink_options24
[4];
2305 /* Firmware dump information. */
2308 int fw_dump_reading
;
2309 char *fw_dump_buffer
;
2310 int fw_dump_buffer_len
;
2316 uint8_t host_str
[16];
2319 uint16_t product_id
[4];
2321 uint8_t model_number
[16+1];
2322 #define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"
2327 uint32_t isp_abort_cnt
;
2329 /* Needed for BEACON */
2330 uint16_t beacon_blink_led
;
2331 uint16_t beacon_green_on
;
2336 * Macros to help code, maintain, etc.
2338 #define LOOP_TRANSITION(ha) \
2339 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
2340 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags))
2342 #define LOOP_NOT_READY(ha) \
2343 ((test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
2344 test_bit(ABORT_ISP_ACTIVE, &ha->dpc_flags) || \
2345 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
2346 test_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) || \
2347 atomic_read(&ha->loop_state) == LOOP_DOWN)
2349 #define LOOP_RDY(ha) (!LOOP_NOT_READY(ha))
2351 #define TGT_Q(ha, t) (ha->otgt[t])
2353 #define to_qla_host(x) ((scsi_qla_host_t *) (x)->hostdata)
2355 #define qla_printk(level, ha, format, arg...) \
2356 dev_printk(level , &((ha)->pdev->dev) , format , ## arg)
2359 * qla2x00 local function return status codes
2361 #define MBS_MASK 0x3fff
2363 #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK)
2364 #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK)
2365 #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK)
2366 #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK)
2367 #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK)
2368 #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK)
2369 #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK)
2370 #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK)
2371 #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK)
2372 #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK)
2374 #define QLA_FUNCTION_TIMEOUT 0x100
2375 #define QLA_FUNCTION_PARAMETER_ERROR 0x101
2376 #define QLA_FUNCTION_FAILED 0x102
2377 #define QLA_MEMORY_ALLOC_FAILED 0x103
2378 #define QLA_LOCK_TIMEOUT 0x104
2379 #define QLA_ABORTED 0x105
2380 #define QLA_SUSPENDED 0x106
2381 #define QLA_BUSY 0x107
2382 #define QLA_RSCNS_HANDLED 0x108
2385 * Stat info for all adpaters
2387 struct _qla2x00stats
{
2388 unsigned long mboxtout
; /* mailbox timeouts */
2389 unsigned long mboxerr
; /* mailbox errors */
2390 unsigned long ispAbort
; /* ISP aborts */
2391 unsigned long debugNo
;
2392 unsigned long loop_resync
;
2393 unsigned long outarray_full
;
2394 unsigned long retry_q_cnt
;
2397 #define NVRAM_DELAY() udelay(10)
2399 #define INVALID_HANDLE (MAX_OUTSTANDING_COMMANDS+1)
2402 * Flash support definitions
2404 #define FLASH_IMAGE_SIZE 131072
2406 #include "qla_gbl.h"
2407 #include "qla_dbg.h"
2408 #include "qla_inline.h"
2413 #define LINESIZE 256
2416 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
2417 #define CMD_COMPL_STATUS(Cmnd) ((Cmnd)->SCp.this_residual)
2418 #define CMD_RESID_LEN(Cmnd) ((Cmnd)->SCp.buffers_residual)
2419 #define CMD_SCSI_STATUS(Cmnd) ((Cmnd)->SCp.Status)
2420 #define CMD_ACTUAL_SNSLEN(Cmnd) ((Cmnd)->SCp.Message)
2421 #define CMD_ENTRY_STATUS(Cmnd) ((Cmnd)->SCp.have_data_in)