2 * IBM eServer eHCA Infiniband device driver for Linux on POWER
4 * eHCA register definitions
6 * Authors: Waleri Fomin <fomin@de.ibm.com>
7 * Christoph Raisch <raisch@de.ibm.com>
8 * Reinhard Ernst <rernst@de.ibm.com>
10 * Copyright (c) 2005 IBM Corporation
12 * All rights reserved.
14 * This source code is distributed under a dual license of GPL v2.0 and OpenIB
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are met:
22 * Redistributions of source code must retain the above copyright notice, this
23 * list of conditions and the following disclaimer.
25 * Redistributions in binary form must reproduce the above copyright notice,
26 * this list of conditions and the following disclaimer in the documentation
27 * and/or other materials
28 * provided with the distribution.
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
33 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
34 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
35 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
36 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
37 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
38 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
39 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
40 * POSSIBILITY OF SUCH DAMAGE.
46 #include "ehca_tools.h"
48 /* QP Table Entry Memory Map */
154 u64 reserved
[(0x400 - 0x298) / 8];
155 /* 0x400 extended data */
156 u64 reserved_ext
[(0x500 - 0x400) / 8];
158 u64 reserved2
[(0x1000 - 0x500) / 8];
162 #define QPX_SQADDER EHCA_BMASK_IBM(48,63)
163 #define QPX_RQADDER EHCA_BMASK_IBM(48,63)
165 #define QPTEMM_OFFSET(x) offsetof(struct hipz_qptemm,x)
167 /* MRMWPT Entry Memory Map */
181 u64 reserved4
[(0x200 - 0x40) / 8];
187 #define MRMWMM_OFFSET(x) offsetof(struct hipz_mrmwmm,x)
191 u64 reserved0
[(0x400) / 8];
238 #define QPEDMM_OFFSET(x) offsetof(struct hipz_qpedmm,x)
240 /* CQ Table Entry Memory Map */
259 u64 reserved2
[(0x1000 - 0x60) / 8];
263 #define CQX_FEC_CQE_CNT EHCA_BMASK_IBM(32,63)
264 #define CQX_FECADDER EHCA_BMASK_IBM(32,63)
265 #define CQX_N0_GENERATE_SOLICITED_COMP_EVENT EHCA_BMASK_IBM(0,0)
266 #define CQX_N1_GENERATE_COMP_EVENT EHCA_BMASK_IBM(0,0)
268 #define CQTEMM_OFFSET(x) offsetof(struct hipz_cqtemm,x)
270 /* EQ Table Entry Memory Map */
293 #define EQTEMM_OFFSET(x) offsetof(struct hipz_eqtemm,x)
295 /* access control defines for MR/MW */
296 #define HIPZ_ACCESSCTRL_L_WRITE 0x00800000
297 #define HIPZ_ACCESSCTRL_R_WRITE 0x00400000
298 #define HIPZ_ACCESSCTRL_R_READ 0x00200000
299 #define HIPZ_ACCESSCTRL_R_ATOMIC 0x00100000
300 #define HIPZ_ACCESSCTRL_MW_BIND 0x00080000
302 /* query hca response block */
303 struct hipz_query_hca
{
312 u32 cur_qp_attached_mcast_grp
;
326 u32 max_special_mrwpte
;
327 u32 max_rd_ee_context
;
329 u32 max_total_mcast_qp_attach
;
330 u32 max_mcast_qp_attach
;
333 u32 internal_clock_frequency
;
339 u32 max_rr_ee_context
;
342 u32 max_act_wqs_ee_context
;
346 u32 memory_page_size_supported
;
348 u32 local_ca_ack_delay
;
354 u64 hca_cap_indicators
;
355 u32 data_counter_register_size
;
359 } __attribute__ ((packed
));
361 /* query port response block */
362 struct hipz_query_port
{
377 u16 pkey_entries
[16];
385 u64 guid_entries
[255];
386 } __attribute__ ((packed
));