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[TG3]: Add tagged status support.
[linux-2.6/verdex.git] / drivers / atm / iphase.h
blobb8d0bd4d6c307d01ff934867b94f57a3af3650f5
1 /******************************************************************************
2 Device driver for Interphase ATM PCI adapter cards
3 Author: Peter Wang <pwang@iphase.com>
4 Interphase Corporation <www.iphase.com>
5 Version: 1.0
6 iphase.h: This is the header file for iphase.c.
7 *******************************************************************************
8
9 This software may be used and distributed according to the terms
10 of the GNU General Public License (GPL), incorporated herein by reference.
11 Drivers based on this skeleton fall under the GPL and must retain
12 the authorship (implicit copyright) notice.
13
14 This program is distributed in the hope that it will be useful, but
15 WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 General Public License for more details.
18
19 Modified from an incomplete driver for Interphase 5575 1KVC 1M card which
20 was originally written by Monalisa Agrawal at UNH. Now this driver
21 supports a variety of varients of Interphase ATM PCI (i)Chip adapter
22 card family (See www.iphase.com/products/ClassSheet.cfm?ClassID=ATM)
23 in terms of PHY type, the size of control memory and the size of
24 packet memory. The followings are the change log and history:
25
26 Bugfix the Mona's UBR driver.
27 Modify the basic memory allocation and dma logic.
28 Port the driver to the latest kernel from 2.0.46.
29 Complete the ABR logic of the driver, and added the ABR work-
30 around for the hardware anormalies.
31 Add the CBR support.
32 Add the flow control logic to the driver to allow rate-limit VC.
33 Add 4K VC support to the board with 512K control memory.
34 Add the support of all the variants of the Interphase ATM PCI
35 (i)Chip adapter cards including x575 (155M OC3 and UTP155), x525
36 (25M UTP25) and x531 (DS3 and E3).
37 Add SMP support.
38
39 Support and updates available at: ftp://ftp.iphase.com/pub/atm
40
41 *******************************************************************************/
42
43 #ifndef IPHASE_H
44 #define IPHASE_H
45
46 #include <linux/config.h>
47
48 /************************ IADBG DEFINE *********************************/
49 /* IADebugFlag Bit Map */
50 #define IF_IADBG_INIT_ADAPTER 0x00000001 // init adapter info
51 #define IF_IADBG_TX 0x00000002 // debug TX
52 #define IF_IADBG_RX 0x00000004 // debug RX
53 #define IF_IADBG_QUERY_INFO 0x00000008 // debug Request call
54 #define IF_IADBG_SHUTDOWN 0x00000010 // debug shutdown event
55 #define IF_IADBG_INTR 0x00000020 // debug interrupt DPC
56 #define IF_IADBG_TXPKT 0x00000040 // debug TX PKT
57 #define IF_IADBG_RXPKT 0x00000080 // debug RX PKT
58 #define IF_IADBG_ERR 0x00000100 // debug system error
59 #define IF_IADBG_EVENT 0x00000200 // debug event
60 #define IF_IADBG_DIS_INTR 0x00001000 // debug disable interrupt
61 #define IF_IADBG_EN_INTR 0x00002000 // debug enable interrupt
62 #define IF_IADBG_LOUD 0x00004000 // debugging info
63 #define IF_IADBG_VERY_LOUD 0x00008000 // excessive debugging info
64 #define IF_IADBG_CBR 0x00100000 //
65 #define IF_IADBG_UBR 0x00200000 //
66 #define IF_IADBG_ABR 0x00400000 //
67 #define IF_IADBG_DESC 0x01000000 //
68 #define IF_IADBG_SUNI_STAT 0x02000000 // suni statistics
69 #define IF_IADBG_RESET 0x04000000
70
71 #define IF_IADBG(f) if (IADebugFlag & (f))
72
73 #ifdef CONFIG_ATM_IA_DEBUG /* Debug build */
74
75 #define IF_LOUD(A) IF_IADBG(IF_IADBG_LOUD) { A }
76 #define IF_ERR(A) IF_IADBG(IF_IADBG_ERR) { A }
77 #define IF_VERY_LOUD(A) IF_IADBG( IF_IADBG_VERY_LOUD ) { A }
78
79 #define IF_INIT_ADAPTER(A) IF_IADBG( IF_IADBG_INIT_ADAPTER ) { A }
80 #define IF_INIT(A) IF_IADBG( IF_IADBG_INIT_ADAPTER ) { A }
81 #define IF_SUNI_STAT(A) IF_IADBG( IF_IADBG_SUNI_STAT ) { A }
82 #define IF_QUERY_INFO(A) IF_IADBG( IF_IADBG_QUERY_INFO ) { A }
83 #define IF_COPY_OVER(A) IF_IADBG( IF_IADBG_COPY_OVER ) { A }
84
85 #define IF_INTR(A) IF_IADBG( IF_IADBG_INTR ) { A }
86 #define IF_DIS_INTR(A) IF_IADBG( IF_IADBG_DIS_INTR ) { A }
87 #define IF_EN_INTR(A) IF_IADBG( IF_IADBG_EN_INTR ) { A }
88
89 #define IF_TX(A) IF_IADBG( IF_IADBG_TX ) { A }
90 #define IF_RX(A) IF_IADBG( IF_IADBG_RX ) { A }
91 #define IF_TXPKT(A) IF_IADBG( IF_IADBG_TXPKT ) { A }
92 #define IF_RXPKT(A) IF_IADBG( IF_IADBG_RXPKT ) { A }
93
94 #define IF_SHUTDOWN(A) IF_IADBG(IF_IADBG_SHUTDOWN) { A }
95 #define IF_CBR(A) IF_IADBG( IF_IADBG_CBR ) { A }
96 #define IF_UBR(A) IF_IADBG( IF_IADBG_UBR ) { A }
97 #define IF_ABR(A) IF_IADBG( IF_IADBG_ABR ) { A }
98 #define IF_EVENT(A) IF_IADBG( IF_IADBG_EVENT) { A }
99
100 #else /* free build */
101 #define IF_LOUD(A)
102 #define IF_VERY_LOUD(A)
103 #define IF_INIT_ADAPTER(A)
104 #define IF_INIT(A)
105 #define IF_SUNI_STAT(A)
106 #define IF_PVC_CHKPKT(A)
107 #define IF_QUERY_INFO(A)
108 #define IF_COPY_OVER(A)
109 #define IF_HANG(A)
110 #define IF_INTR(A)
111 #define IF_DIS_INTR(A)
112 #define IF_EN_INTR(A)
113 #define IF_TX(A)
114 #define IF_RX(A)
115 #define IF_TXDEBUG(A)
116 #define IF_VC(A)
117 #define IF_ERR(A)
118 #define IF_CBR(A)
119 #define IF_UBR(A)
120 #define IF_ABR(A)
121 #define IF_SHUTDOWN(A)
122 #define DbgPrint(A)
123 #define IF_EVENT(A)
124 #define IF_TXPKT(A)
125 #define IF_RXPKT(A)
126 #endif /* CONFIG_ATM_IA_DEBUG */
127
128 #define isprint(a) ((a >=' ')&&(a <= '~'))
129 #define ATM_DESC(skb) (skb->protocol)
130 #define IA_SKB_STATE(skb) (skb->protocol)
131 #define IA_DLED 1
132 #define IA_TX_DONE 2
133
134 /* iadbg defines */
135 #define IA_CMD 0x7749
136 typedef struct {
137 int cmd;
138 int sub_cmd;
139 int len;
140 u32 maddr;
141 int status;
142 void __user *buf;
143 } IA_CMDBUF, *PIA_CMDBUF;
144
145 /* cmds */
146 #define MEMDUMP 0x01
147
148 /* sub_cmds */
149 #define MEMDUMP_SEGREG 0x2
150 #define MEMDUMP_DEV 0x1
151 #define MEMDUMP_REASSREG 0x3
152 #define MEMDUMP_FFL 0x4
153 #define READ_REG 0x5
154 #define WAKE_DBG_WAIT 0x6
155
156 /************************ IADBG DEFINE END ***************************/
157
158 #define Boolean(x) ((x) ? 1 : 0)
159 #define NR_VCI 1024 /* number of VCIs */
160 #define NR_VCI_LD 10 /* log2(NR_VCI) */
161 #define NR_VCI_4K 4096 /* number of VCIs */
162 #define NR_VCI_4K_LD 12 /* log2(NR_VCI) */
163 #define MEM_VALID 0xfffffff0 /* mask base address with this */
164
165 #ifndef PCI_VENDOR_ID_IPHASE
166 #define PCI_VENDOR_ID_IPHASE 0x107e
167 #endif
168 #ifndef PCI_DEVICE_ID_IPHASE_5575
169 #define PCI_DEVICE_ID_IPHASE_5575 0x0008
170 #endif
171 #define DEV_LABEL "ia"
172 #define PCR 207692
173 #define ICR 100000
174 #define MCR 0
175 #define TBE 1000
176 #define FRTT 1
177 #define RIF 2
178 #define RDF 4
179 #define NRMCODE 5 /* 0 - 7 */
180 #define TRMCODE 3 /* 0 - 7 */
181 #define CDFCODE 6
182 #define ATDFCODE 2 /* 0 - 15 */
183
184 /*---------------------- Packet/Cell Memory ------------------------*/
185 #define TX_PACKET_RAM 0x00000 /* start of Trasnmit Packet memory - 0 */
186 #define DFL_TX_BUF_SZ 10240 /* 10 K buffers */
187 #define DFL_TX_BUFFERS 50 /* number of packet buffers for Tx
188 - descriptor 0 unused */
189 #define REASS_RAM_SIZE 0x10000 /* for 64K 1K VC board */
190 #define RX_PACKET_RAM 0x80000 /* start of Receive Packet memory - 512K */
191 #define DFL_RX_BUF_SZ 10240 /* 10k buffers */
192 #define DFL_RX_BUFFERS 50 /* number of packet buffers for Rx
193 - descriptor 0 unused */
194
195 struct cpcs_trailer
196 {
197 u_short control;
198 u_short length;
199 u_int crc32;
200 };
201
202 struct cpcs_trailer_desc
203 {
204 struct cpcs_trailer *cpcs;
205 dma_addr_t dma_addr;
206 };
207
208 struct ia_vcc
209 {
210 int rxing;
211 int txing;
212 int NumCbrEntry;
213 u32 pcr;
214 u32 saved_tx_quota;
215 int flow_inc;
216 struct sk_buff_head txing_skb;
217 int ltimeout;
218 u8 vc_desc_cnt;
219
220 };
221
222 struct abr_vc_table
223 {
224 u_char status;
225 u_char rdf;
226 u_short air;
227 u_int res[3];
228 u_int req_rm_cell_data1;
229 u_int req_rm_cell_data2;
230 u_int add_rm_cell_data1;
231 u_int add_rm_cell_data2;
232 };
233
234 /* 32 byte entries */
235 struct main_vc
236 {
237 u_short type;
238 #define ABR 0x8000
239 #define UBR 0xc000
240 #define CBR 0x0000
241 /* ABR fields */
242 u_short nrm;
243 u_short trm;
244 u_short rm_timestamp_hi;
245 u_short rm_timestamp_lo:8,
246 crm:8;
247 u_short remainder; /* ABR and UBR fields - last 10 bits*/
248 u_short next_vc_sched;
249 u_short present_desc; /* all classes */
250 u_short last_cell_slot; /* ABR and UBR */
251 u_short pcr;
252 u_short fraction;
253 u_short icr;
254 u_short atdf;
255 u_short mcr;
256 u_short acr;
257 u_short unack:8,
258 status:8; /* all classes */
259 #define UIOLI 0x80
260 #define CRC_APPEND 0x40 /* for status field - CRC-32 append */
261 #define ABR_STATE 0x02
262
263 };
264
265
266 /* 8 byte entries */
267 struct ext_vc
268 {
269 u_short atm_hdr1;
270 u_short atm_hdr2;
271 u_short last_desc;
272 u_short out_of_rate_link; /* reserved for UBR and CBR */
273 };
274
275
276 #define DLE_ENTRIES 256
277 #define DMA_INT_ENABLE 0x0002 /* use for both Tx and Rx */
278 #define TX_DLE_PSI 0x0001
279 #define DLE_TOTAL_SIZE (sizeof(struct dle)*DLE_ENTRIES)
280
281 /* Descriptor List Entries (DLE) */
282 struct dle
283 {
284 u32 sys_pkt_addr;
285 u32 local_pkt_addr;
286 u32 bytes;
287 u16 prq_wr_ptr_data;
288 u16 mode;
289 };
290
291 struct dle_q
292 {
293 struct dle *start;
294 struct dle *end;
295 struct dle *read;
296 struct dle *write;
297 };
298
299 struct free_desc_q
300 {
301 int desc; /* Descriptor number */
302 struct free_desc_q *next;
303 };
304
305 struct tx_buf_desc {
306 unsigned short desc_mode;
307 unsigned short vc_index;
308 unsigned short res1; /* reserved field */
309 unsigned short bytes;
310 unsigned short buf_start_hi;
311 unsigned short buf_start_lo;
312 unsigned short res2[10]; /* reserved field */
313 };
314
315
316 struct rx_buf_desc {
317 unsigned short desc_mode;
318 unsigned short vc_index;
319 unsigned short vpi;
320 unsigned short bytes;
321 unsigned short buf_start_hi;
322 unsigned short buf_start_lo;
323 unsigned short dma_start_hi;
324 unsigned short dma_start_lo;
325 unsigned short crc_upper;
326 unsigned short crc_lower;
327 unsigned short res:8, timeout:8;
328 unsigned short res2[5]; /* reserved field */
329 };
330
331 /*--------SAR stuff ---------------------*/
332
333 #define EPROM_SIZE 0x40000 /* says 64K in the docs ??? */
334 #define MAC1_LEN 4
335 #define MAC2_LEN 2
336
337 /*------------ PCI Memory Space Map, 128K SAR memory ----------------*/
338 #define IPHASE5575_PCI_CONFIG_REG_BASE 0x0000
339 #define IPHASE5575_BUS_CONTROL_REG_BASE 0x1000 /* offsets 0x00 - 0x3c */
340 #define IPHASE5575_FRAG_CONTROL_REG_BASE 0x2000
341 #define IPHASE5575_REASS_CONTROL_REG_BASE 0x3000
342 #define IPHASE5575_DMA_CONTROL_REG_BASE 0x4000
343 #define IPHASE5575_FRONT_END_REG_BASE IPHASE5575_DMA_CONTROL_REG_BASE
344 #define IPHASE5575_FRAG_CONTROL_RAM_BASE 0x10000
345 #define IPHASE5575_REASS_CONTROL_RAM_BASE 0x20000
346
347 /*------------ Bus interface control registers -----------------*/
348 #define IPHASE5575_BUS_CONTROL_REG 0x00
349 #define IPHASE5575_BUS_STATUS_REG 0x01 /* actual offset 0x04 */
350 #define IPHASE5575_MAC1 0x02
351 #define IPHASE5575_REV 0x03
352 #define IPHASE5575_MAC2 0x03 /*actual offset 0x0e-reg 0x0c*/
353 #define IPHASE5575_EXT_RESET 0x04
354 #define IPHASE5575_INT_RESET 0x05 /* addr 1c ?? reg 0x06 */
355 #define IPHASE5575_PCI_ADDR_PAGE 0x07 /* reg 0x08, 0x09 ?? */
356 #define IPHASE5575_EEPROM_ACCESS 0x0a /* actual offset 0x28 */
357 #define IPHASE5575_CELL_FIFO_QUEUE_SZ 0x0b
358 #define IPHASE5575_CELL_FIFO_MARK_STATE 0x0c
359 #define IPHASE5575_CELL_FIFO_READ_PTR 0x0d
360 #define IPHASE5575_CELL_FIFO_WRITE_PTR 0x0e
361 #define IPHASE5575_CELL_FIFO_CELLS_AVL 0x0f /* actual offset 0x3c */
362
363 /* Bus Interface Control Register bits */
364 #define CTRL_FE_RST 0x80000000
365 #define CTRL_LED 0x40000000
366 #define CTRL_25MBPHY 0x10000000
367 #define CTRL_ENCMBMEM 0x08000000
368 #define CTRL_ENOFFSEG 0x01000000
369 #define CTRL_ERRMASK 0x00400000
370 #define CTRL_DLETMASK 0x00100000
371 #define CTRL_DLERMASK 0x00080000
372 #define CTRL_FEMASK 0x00040000
373 #define CTRL_SEGMASK 0x00020000
374 #define CTRL_REASSMASK 0x00010000
375 #define CTRL_CSPREEMPT 0x00002000
376 #define CTRL_B128 0x00000200
377 #define CTRL_B64 0x00000100
378 #define CTRL_B48 0x00000080
379 #define CTRL_B32 0x00000040
380 #define CTRL_B16 0x00000020
381 #define CTRL_B8 0x00000010
382
383 /* Bus Interface Status Register bits */
384 #define STAT_CMEMSIZ 0xc0000000
385 #define STAT_ADPARCK 0x20000000
386 #define STAT_RESVD 0x1fffff80
387 #define STAT_ERRINT 0x00000040
388 #define STAT_MARKINT 0x00000020
389 #define STAT_DLETINT 0x00000010
390 #define STAT_DLERINT 0x00000008
391 #define STAT_FEINT 0x00000004
392 #define STAT_SEGINT 0x00000002
393 #define STAT_REASSINT 0x00000001
394
395
396 /*--------------- Segmentation control registers -----------------*/
397 /* The segmentation registers are 16 bits access and the addresses
398 are defined as such so the addresses are the actual "offsets" */
399 #define IDLEHEADHI 0x00
400 #define IDLEHEADLO 0x01
401 #define MAXRATE 0x02
402 /* Values for MAXRATE register for 155Mbps and 25.6 Mbps operation */
403 #define RATE155 0x64b1 // 16 bits float format
404 #define MAX_ATM_155 352768 // Cells/second p.118
405 #define RATE25 0x5f9d
406
407 #define STPARMS 0x03
408 #define STPARMS_1K 0x008c
409 #define STPARMS_2K 0x0049
410 #define STPARMS_4K 0x0026
411 #define COMP_EN 0x4000
412 #define CBR_EN 0x2000
413 #define ABR_EN 0x0800
414 #define UBR_EN 0x0400
415
416 #define ABRUBR_ARB 0x04
417 #define RM_TYPE 0x05
418 /*Value for RM_TYPE register for ATM Forum Traffic Mangement4.0 support*/
419 #define RM_TYPE_4_0 0x0100
420
421 #define SEG_COMMAND_REG 0x17
422 /* Values for the command register */
423 #define RESET_SEG 0x0055
424 #define RESET_SEG_STATE 0x00aa
425 #define RESET_TX_CELL_CTR 0x00cc
426
427 #define CBR_PTR_BASE 0x20
428 #define ABR_SBPTR_BASE 0x22
429 #define UBR_SBPTR_BASE 0x23
430 #define ABRWQ_BASE 0x26
431 #define UBRWQ_BASE 0x27
432 #define VCT_BASE 0x28
433 #define VCTE_BASE 0x29
434 #define CBR_TAB_BEG 0x2c
435 #define CBR_TAB_END 0x2d
436 #define PRQ_ST_ADR 0x30
437 #define PRQ_ED_ADR 0x31
438 #define PRQ_RD_PTR 0x32
439 #define PRQ_WR_PTR 0x33
440 #define TCQ_ST_ADR 0x34
441 #define TCQ_ED_ADR 0x35
442 #define TCQ_RD_PTR 0x36
443 #define TCQ_WR_PTR 0x37
444 #define SEG_QUEUE_BASE 0x40
445 #define SEG_DESC_BASE 0x41
446 #define MODE_REG_0 0x45
447 #define T_ONLINE 0x0002 /* (i)chipSAR is online */
448
449 #define MODE_REG_1 0x46
450 #define MODE_REG_1_VAL 0x0400 /*for propoer device operation*/
451
452 #define SEG_INTR_STATUS_REG 0x47
453 #define SEG_MASK_REG 0x48
454 #define TRANSMIT_DONE 0x0200
455 #define TCQ_NOT_EMPTY 0x1000 /* this can be used for both the interrupt
456 status registers as well as the mask register */
457
458 #define CELL_CTR_HIGH_AUTO 0x49
459 #define CELL_CTR_HIGH_NOAUTO 0xc9
460 #define CELL_CTR_LO_AUTO 0x4a
461 #define CELL_CTR_LO_NOAUTO 0xca
462
463 /* Diagnostic registers */
464 #define NEXTDESC 0x59
465 #define NEXTVC 0x5a
466 #define PSLOTCNT 0x5d
467 #define NEWDN 0x6a
468 #define NEWVC 0x6b
469 #define SBPTR 0x6c
470 #define ABRWQ_WRPTR 0x6f
471 #define ABRWQ_RDPTR 0x70
472 #define UBRWQ_WRPTR 0x71
473 #define UBRWQ_RDPTR 0x72
474 #define CBR_VC 0x73
475 #define ABR_SBVC 0x75
476 #define UBR_SBVC 0x76
477 #define ABRNEXTLINK 0x78
478 #define UBRNEXTLINK 0x79
479
480
481 /*----------------- Reassembly control registers ---------------------*/
482 /* The reassembly registers are 16 bits access and the addresses
483 are defined as such so the addresses are the actual "offsets" */
484 #define MODE_REG 0x00
485 #define R_ONLINE 0x0002 /* (i)chip is online */
486 #define IGN_RAW_FL 0x0004
487
488 #define PROTOCOL_ID 0x01
489 #define REASS_MASK_REG 0x02
490 #define REASS_INTR_STATUS_REG 0x03
491 /* Interrupt Status register bits */
492 #define RX_PKT_CTR_OF 0x8000
493 #define RX_ERR_CTR_OF 0x4000
494 #define RX_CELL_CTR_OF 0x1000
495 #define RX_FREEQ_EMPT 0x0200
496 #define RX_EXCPQ_FL 0x0080
497 #define RX_RAWQ_FL 0x0010
498 #define RX_EXCP_RCVD 0x0008
499 #define RX_PKT_RCVD 0x0004
500 #define RX_RAW_RCVD 0x0001
501
502 #define DRP_PKT_CNTR 0x04
503 #define ERR_CNTR 0x05
504 #define RAW_BASE_ADR 0x08
505 #define CELL_CTR0 0x0c
506 #define CELL_CTR1 0x0d
507 #define REASS_COMMAND_REG 0x0f
508 /* Values for command register */
509 #define RESET_REASS 0x0055
510 #define RESET_REASS_STATE 0x00aa
511 #define RESET_DRP_PKT_CNTR 0x00f1
512 #define RESET_ERR_CNTR 0x00f2
513 #define RESET_CELL_CNTR 0x00f8
514 #define RESET_REASS_ALL_REGS 0x00ff
515
516 #define REASS_DESC_BASE 0x10
517 #define VC_LKUP_BASE 0x11
518 #define REASS_TABLE_BASE 0x12
519 #define REASS_QUEUE_BASE 0x13
520 #define PKT_TM_CNT 0x16
521 #define TMOUT_RANGE 0x17
522 #define INTRVL_CNTR 0x18
523 #define TMOUT_INDX 0x19
524 #define VP_LKUP_BASE 0x1c
525 #define VP_FILTER 0x1d
526 #define ABR_LKUP_BASE 0x1e
527 #define FREEQ_ST_ADR 0x24
528 #define FREEQ_ED_ADR 0x25
529 #define FREEQ_RD_PTR 0x26
530 #define FREEQ_WR_PTR 0x27
531 #define PCQ_ST_ADR 0x28
532 #define PCQ_ED_ADR 0x29
533 #define PCQ_RD_PTR 0x2a
534 #define PCQ_WR_PTR 0x2b
535 #define EXCP_Q_ST_ADR 0x2c
536 #define EXCP_Q_ED_ADR 0x2d
537 #define EXCP_Q_RD_PTR 0x2e
538 #define EXCP_Q_WR_PTR 0x2f
539 #define CC_FIFO_ST_ADR 0x34
540 #define CC_FIFO_ED_ADR 0x35
541 #define CC_FIFO_RD_PTR 0x36
542 #define CC_FIFO_WR_PTR 0x37
543 #define STATE_REG 0x38
544 #define BUF_SIZE 0x42
545 #define XTRA_RM_OFFSET 0x44
546 #define DRP_PKT_CNTR_NC 0x84
547 #define ERR_CNTR_NC 0x85
548 #define CELL_CNTR0_NC 0x8c
549 #define CELL_CNTR1_NC 0x8d
550
551 /* State Register bits */
552 #define EXCPQ_EMPTY 0x0040
553 #define PCQ_EMPTY 0x0010
554 #define FREEQ_EMPTY 0x0004
555
556
557 /*----------------- Front End registers/ DMA control --------------*/
558 /* There is a lot of documentation error regarding these offsets ???
559 eg:- 2 offsets given 800, a00 for rx counter
560 similarly many others
561 Remember again that the offsets are to be 4*register number, so
562 correct the #defines here
563 */
564 #define IPHASE5575_TX_COUNTER 0x200 /* offset - 0x800 */
565 #define IPHASE5575_RX_COUNTER 0x280 /* offset - 0xa00 */
566 #define IPHASE5575_TX_LIST_ADDR 0x300 /* offset - 0xc00 */
567 #define IPHASE5575_RX_LIST_ADDR 0x380 /* offset - 0xe00 */
568
569 /*--------------------------- RAM ---------------------------*/
570 /* These memory maps are actually offsets from the segmentation and reassembly RAM base addresses */
571
572 /* Segmentation Control Memory map */
573 #define TX_DESC_BASE 0x0000 /* Buffer Decriptor Table */
574 #define TX_COMP_Q 0x1000 /* Transmit Complete Queue */
575 #define PKT_RDY_Q 0x1400 /* Packet Ready Queue */
576 #define CBR_SCHED_TABLE 0x1800 /* CBR Table */
577 #define UBR_SCHED_TABLE 0x3000 /* UBR Table */
578 #define UBR_WAIT_Q 0x4000 /* UBR Wait Queue */
579 #define ABR_SCHED_TABLE 0x5000 /* ABR Table */
580 #define ABR_WAIT_Q 0x5800 /* ABR Wait Queue */
581 #define EXT_VC_TABLE 0x6000 /* Extended VC Table */
582 #define MAIN_VC_TABLE 0x8000 /* Main VC Table */
583 #define SCHEDSZ 1024 /* ABR and UBR Scheduling Table size */
584 #define TX_DESC_TABLE_SZ 128 /* Number of entries in the Transmit
585 Buffer Descriptor Table */
586
587 /* These are used as table offsets in Descriptor Table address generation */
588 #define DESC_MODE 0x0
589 #define VC_INDEX 0x1
590 #define BYTE_CNT 0x3
591 #define PKT_START_HI 0x4
592 #define PKT_START_LO 0x5
593
594 /* Descriptor Mode Word Bits */
595 #define EOM_EN 0x0800
596 #define AAL5 0x0100
597 #define APP_CRC32 0x0400
598 #define CMPL_INT 0x1000
599
600 #define TABLE_ADDRESS(db, dn, to) \
601 (((unsigned long)(db & 0x04)) << 16) | (dn << 5) | (to << 1)
602
603 /* Reassembly Control Memory Map */
604 #define RX_DESC_BASE 0x0000 /* Buffer Descriptor Table */
605 #define VP_TABLE 0x5c00 /* VP Table */
606 #define EXCEPTION_Q 0x5e00 /* Exception Queue */
607 #define FREE_BUF_DESC_Q 0x6000 /* Free Buffer Descriptor Queue */
608 #define PKT_COMP_Q 0x6800 /* Packet Complete Queue */
609 #define REASS_TABLE 0x7000 /* Reassembly Table */
610 #define RX_VC_TABLE 0x7800 /* VC Table */
611 #define ABR_VC_TABLE 0x8000 /* ABR VC Table */
612 #define RX_DESC_TABLE_SZ 736 /* Number of entries in the Receive
613 Buffer Descriptor Table */
614 #define VP_TABLE_SZ 256 /* Number of entries in VPTable */
615 #define RX_VC_TABLE_SZ 1024 /* Number of entries in VC Table */
616 #define REASS_TABLE_SZ 1024 /* Number of entries in Reassembly Table */
617 /* Buffer Descriptor Table */
618 #define RX_ACT 0x8000
619 #define RX_VPVC 0x4000
620 #define RX_CNG 0x0040
621 #define RX_CER 0x0008
622 #define RX_PTE 0x0004
623 #define RX_OFL 0x0002
624 #define NUM_RX_EXCP 32
625
626 /* Reassembly Table */
627 #define NO_AAL5_PKT 0x0000
628 #define AAL5_PKT_REASSEMBLED 0x4000
629 #define AAL5_PKT_TERMINATED 0x8000
630 #define RAW_PKT 0xc000
631 #define REASS_ABR 0x2000
632
633 /*-------------------- Base Registers --------------------*/
634 #define REG_BASE IPHASE5575_BUS_CONTROL_REG_BASE
635 #define RAM_BASE IPHASE5575_FRAG_CONTROL_RAM_BASE
636 #define PHY_BASE IPHASE5575_FRONT_END_REG_BASE
637 #define SEG_BASE IPHASE5575_FRAG_CONTROL_REG_BASE
638 #define REASS_BASE IPHASE5575_REASS_CONTROL_REG_BASE
639
640 typedef volatile u_int freg_t;
641 typedef u_int rreg_t;
642
643 typedef struct _ffredn_t {
644 freg_t idlehead_high; /* Idle cell header (high) */
645 freg_t idlehead_low; /* Idle cell header (low) */
646 freg_t maxrate; /* Maximum rate */
647 freg_t stparms; /* Traffic Management Parameters */
648 freg_t abrubr_abr; /* ABRUBR Priority Byte 1, TCR Byte 0 */
649 freg_t rm_type; /* */
650 u_int filler5[0x17 - 0x06];
651 freg_t cmd_reg; /* Command register */
652 u_int filler18[0x20 - 0x18];
653 freg_t cbr_base; /* CBR Pointer Base */
654 freg_t vbr_base; /* VBR Pointer Base */
655 freg_t abr_base; /* ABR Pointer Base */
656 freg_t ubr_base; /* UBR Pointer Base */
657 u_int filler24;
658 freg_t vbrwq_base; /* VBR Wait Queue Base */
659 freg_t abrwq_base; /* ABR Wait Queue Base */
660 freg_t ubrwq_base; /* UBR Wait Queue Base */
661 freg_t vct_base; /* Main VC Table Base */
662 freg_t vcte_base; /* Extended Main VC Table Base */
663 u_int filler2a[0x2C - 0x2A];
664 freg_t cbr_tab_beg; /* CBR Table Begin */
665 freg_t cbr_tab_end; /* CBR Table End */
666 freg_t cbr_pointer; /* CBR Pointer */
667 u_int filler2f[0x30 - 0x2F];
668 freg_t prq_st_adr; /* Packet Ready Queue Start Address */
669 freg_t prq_ed_adr; /* Packet Ready Queue End Address */
670 freg_t prq_rd_ptr; /* Packet Ready Queue read pointer */
671 freg_t prq_wr_ptr; /* Packet Ready Queue write pointer */
672 freg_t tcq_st_adr; /* Transmit Complete Queue Start Address*/
673 freg_t tcq_ed_adr; /* Transmit Complete Queue End Address */
674 freg_t tcq_rd_ptr; /* Transmit Complete Queue read pointer */
675 freg_t tcq_wr_ptr; /* Transmit Complete Queue write pointer*/
676 u_int filler38[0x40 - 0x38];
677 freg_t queue_base; /* Base address for PRQ and TCQ */
678 freg_t desc_base; /* Base address of descriptor table */
679 u_int filler42[0x45 - 0x42];
680 freg_t mode_reg_0; /* Mode register 0 */
681 freg_t mode_reg_1; /* Mode register 1 */
682 freg_t intr_status_reg;/* Interrupt Status register */
683 freg_t mask_reg; /* Mask Register */
684 freg_t cell_ctr_high1; /* Total cell transfer count (high) */
685 freg_t cell_ctr_lo1; /* Total cell transfer count (low) */
686 freg_t state_reg; /* Status register */
687 u_int filler4c[0x58 - 0x4c];
688 freg_t curr_desc_num; /* Contains the current descriptor num */
689 freg_t next_desc; /* Next descriptor */
690 freg_t next_vc; /* Next VC */
691 u_int filler5b[0x5d - 0x5b];
692 freg_t present_slot_cnt;/* Present slot count */
693 u_int filler5e[0x6a - 0x5e];
694 freg_t new_desc_num; /* New descriptor number */
695 freg_t new_vc; /* New VC */
696 freg_t sched_tbl_ptr; /* Schedule table pointer */
697 freg_t vbrwq_wptr; /* VBR wait queue write pointer */
698 freg_t vbrwq_rptr; /* VBR wait queue read pointer */
699 freg_t abrwq_wptr; /* ABR wait queue write pointer */
700 freg_t abrwq_rptr; /* ABR wait queue read pointer */
701 freg_t ubrwq_wptr; /* UBR wait queue write pointer */
702 freg_t ubrwq_rptr; /* UBR wait queue read pointer */
703 freg_t cbr_vc; /* CBR VC */
704 freg_t vbr_sb_vc; /* VBR SB VC */
705 freg_t abr_sb_vc; /* ABR SB VC */
706 freg_t ubr_sb_vc; /* UBR SB VC */
707 freg_t vbr_next_link; /* VBR next link */
708 freg_t abr_next_link; /* ABR next link */
709 freg_t ubr_next_link; /* UBR next link */
710 u_int filler7a[0x7c-0x7a];
711 freg_t out_rate_head; /* Out of rate head */
712 u_int filler7d[0xca-0x7d]; /* pad out to full address space */
713 freg_t cell_ctr_high1_nc;/* Total cell transfer count (high) */
714 freg_t cell_ctr_lo1_nc;/* Total cell transfer count (low) */
715 u_int fillercc[0x100-0xcc]; /* pad out to full address space */
716 } ffredn_t;
717
718 typedef struct _rfredn_t {
719 rreg_t mode_reg_0; /* Mode register 0 */
720 rreg_t protocol_id; /* Protocol ID */
721 rreg_t mask_reg; /* Mask Register */
722 rreg_t intr_status_reg;/* Interrupt status register */
723 rreg_t drp_pkt_cntr; /* Dropped packet cntr (clear on read) */
724 rreg_t err_cntr; /* Error Counter (cleared on read) */
725 u_int filler6[0x08 - 0x06];
726 rreg_t raw_base_adr; /* Base addr for raw cell Q */
727 u_int filler2[0x0c - 0x09];
728 rreg_t cell_ctr0; /* Cell Counter 0 (cleared when read) */
729 rreg_t cell_ctr1; /* Cell Counter 1 (cleared when read) */
730 u_int filler3[0x0f - 0x0e];
731 rreg_t cmd_reg; /* Command register */
732 rreg_t desc_base; /* Base address for description table */
733 rreg_t vc_lkup_base; /* Base address for VC lookup table */
734 rreg_t reass_base; /* Base address for reassembler table */
735 rreg_t queue_base; /* Base address for Communication queue */
736 u_int filler14[0x16 - 0x14];
737 rreg_t pkt_tm_cnt; /* Packet Timeout and count register */
738 rreg_t tmout_range; /* Range of reassembley IDs for timeout */
739 rreg_t intrvl_cntr; /* Packet aging interval counter */
740 rreg_t tmout_indx; /* index of pkt being tested for aging */
741 u_int filler1a[0x1c - 0x1a];
742 rreg_t vp_lkup_base; /* Base address for VP lookup table */
743 rreg_t vp_filter; /* VP filter register */
744 rreg_t abr_lkup_base; /* Base address of ABR VC Table */
745 u_int filler1f[0x24 - 0x1f];
746 rreg_t fdq_st_adr; /* Free desc queue start address */
747 rreg_t fdq_ed_adr; /* Free desc queue end address */
748 rreg_t fdq_rd_ptr; /* Free desc queue read pointer */
749 rreg_t fdq_wr_ptr; /* Free desc queue write pointer */
750 rreg_t pcq_st_adr; /* Packet Complete queue start address */
751 rreg_t pcq_ed_adr; /* Packet Complete queue end address */
752 rreg_t pcq_rd_ptr; /* Packet Complete queue read pointer */
753 rreg_t pcq_wr_ptr; /* Packet Complete queue write pointer */
754 rreg_t excp_st_adr; /* Exception queue start address */
755 rreg_t excp_ed_adr; /* Exception queue end address */
756 rreg_t excp_rd_ptr; /* Exception queue read pointer */
757 rreg_t excp_wr_ptr; /* Exception queue write pointer */
758 u_int filler30[0x34 - 0x30];
759 rreg_t raw_st_adr; /* Raw Cell start address */
760 rreg_t raw_ed_adr; /* Raw Cell end address */
761 rreg_t raw_rd_ptr; /* Raw Cell read pointer */
762 rreg_t raw_wr_ptr; /* Raw Cell write pointer */
763 rreg_t state_reg; /* State Register */
764 u_int filler39[0x42 - 0x39];
765 rreg_t buf_size; /* Buffer size */
766 u_int filler43;
767 rreg_t xtra_rm_offset; /* Offset of the additional turnaround RM */
768 u_int filler45[0x84 - 0x45];
769 rreg_t drp_pkt_cntr_nc;/* Dropped Packet cntr, Not clear on rd */
770 rreg_t err_cntr_nc; /* Error Counter, Not clear on read */
771 u_int filler86[0x8c - 0x86];
772 rreg_t cell_ctr0_nc; /* Cell Counter 0, Not clear on read */
773 rreg_t cell_ctr1_nc; /* Cell Counter 1, Not clear on read */
774 u_int filler8e[0x100-0x8e]; /* pad out to full address space */
775 } rfredn_t;
776
777 typedef struct {
778 /* Atlantic */
779 ffredn_t ffredn; /* F FRED */
780 rfredn_t rfredn; /* R FRED */
781 } ia_regs_t;
782
783 typedef struct {
784 u_short f_vc_type; /* VC type */
785 u_short f_nrm; /* Nrm */
786 u_short f_nrmexp; /* Nrm Exp */
787 u_short reserved6; /* */
788 u_short f_crm; /* Crm */
789 u_short reserved10; /* Reserved */
790 u_short reserved12; /* Reserved */
791 u_short reserved14; /* Reserved */
792 u_short last_cell_slot; /* last_cell_slot_count */
793 u_short f_pcr; /* Peak Cell Rate */
794 u_short fraction; /* fraction */
795 u_short f_icr; /* Initial Cell Rate */
796 u_short f_cdf; /* */
797 u_short f_mcr; /* Minimum Cell Rate */
798 u_short f_acr; /* Allowed Cell Rate */
799 u_short f_status; /* */
800 } f_vc_abr_entry;
801
802 typedef struct {
803 u_short r_status_rdf; /* status + RDF */
804 u_short r_air; /* AIR */
805 u_short reserved4[14]; /* Reserved */
806 } r_vc_abr_entry;
807
808 #define MRM 3
809
810 typedef struct srv_cls_param {
811 u32 class_type; /* CBR/VBR/ABR/UBR; use the enum above */
812 u32 pcr; /* Peak Cell Rate (24-bit) */
813 /* VBR parameters */
814 u32 scr; /* sustainable cell rate */
815 u32 max_burst_size; /* ?? cell rate or data rate */
816
817 /* ABR only UNI 4.0 Parameters */
818 u32 mcr; /* Min Cell Rate (24-bit) */
819 u32 icr; /* Initial Cell Rate (24-bit) */
820 u32 tbe; /* Transient Buffer Exposure (24-bit) */
821 u32 frtt; /* Fixed Round Trip Time (24-bit) */
822
823 #if 0 /* Additional Parameters of TM 4.0 */
824 bits 31 30 29 28 27-25 24-22 21-19 18-9
825 -----------------------------------------------------------------------------
826 | NRM present | TRM prsnt | CDF prsnt | ADTF prsnt | NRM | TRM | CDF | ADTF |
827 -----------------------------------------------------------------------------
828 #endif /* 0 */
829
830 u8 nrm; /* Max # of Cells for each forward RM
831 cell (3-bit) */
832 u8 trm; /* Time between forward RM cells (3-bit) */
833 u16 adtf; /* ACR Decrease Time Factor (10-bit) */
834 u8 cdf; /* Cutoff Decrease Factor (3-bit) */
835 u8 rif; /* Rate Increment Factor (4-bit) */
836 u8 rdf; /* Rate Decrease Factor (4-bit) */
837 u8 reserved; /* 8 bits to keep structure word aligned */
838 } srv_cls_param_t;
839
840 struct testTable_t {
841 u16 lastTime;
842 u16 fract;
843 u8 vc_status;
844 };
845
846 typedef struct {
847 u16 vci;
848 u16 error;
849 } RX_ERROR_Q;
850
851 typedef struct {
852 u8 active: 1;
853 u8 abr: 1;
854 u8 ubr: 1;
855 u8 cnt: 5;
856 #define VC_ACTIVE 0x01
857 #define VC_ABR 0x02
858 #define VC_UBR 0x04
859 } vcstatus_t;
860
861 struct ia_rfL_t {
862 u32 fdq_st; /* Free desc queue start address */
863 u32 fdq_ed; /* Free desc queue end address */
864 u32 fdq_rd; /* Free desc queue read pointer */
865 u32 fdq_wr; /* Free desc queue write pointer */
866 u32 pcq_st; /* Packet Complete queue start address */
867 u32 pcq_ed; /* Packet Complete queue end address */
868 u32 pcq_rd; /* Packet Complete queue read pointer */
869 u32 pcq_wr; /* Packet Complete queue write pointer */
870 };
871
872 struct ia_ffL_t {
873 u32 prq_st; /* Packet Ready Queue Start Address */
874 u32 prq_ed; /* Packet Ready Queue End Address */
875 u32 prq_wr; /* Packet Ready Queue write pointer */
876 u32 tcq_st; /* Transmit Complete Queue Start Address*/
877 u32 tcq_ed; /* Transmit Complete Queue End Address */
878 u32 tcq_rd; /* Transmit Complete Queue read pointer */
879 };
880
881 struct desc_tbl_t {
882 u32 timestamp;
883 struct ia_vcc *iavcc;
884 struct sk_buff *txskb;
885 };
886
887 typedef struct ia_rtn_q {
888 struct desc_tbl_t data;
889 struct ia_rtn_q *next, *tail;
890 } IARTN_Q;
891
892 #define SUNI_LOSV 0x04
893 typedef struct {
894 u32 suni_master_reset; /* SUNI Master Reset and Identity */
895 u32 suni_master_config; /* SUNI Master Configuration */
896 u32 suni_master_intr_stat; /* SUNI Master Interrupt Status */
897 u32 suni_reserved1; /* Reserved */
898 u32 suni_master_clk_monitor;/* SUNI Master Clock Monitor */
899 u32 suni_master_control; /* SUNI Master Clock Monitor */
900 u32 suni_reserved2[10]; /* Reserved */
901
902 u32 suni_rsop_control; /* RSOP Control/Interrupt Enable */
903 u32 suni_rsop_status; /* RSOP Status/Interrupt States */
904 u32 suni_rsop_section_bip8l;/* RSOP Section BIP-8 LSB */
905 u32 suni_rsop_section_bip8m;/* RSOP Section BIP-8 MSB */
906
907 u32 suni_tsop_control; /* TSOP Control */
908 u32 suni_tsop_diag; /* TSOP Disgnostics */
909 u32 suni_tsop_reserved[2]; /* TSOP Reserved */
910
911 u32 suni_rlop_cs; /* RLOP Control/Status */
912 u32 suni_rlop_intr; /* RLOP Interrupt Enable/Status */
913 u32 suni_rlop_line_bip24l; /* RLOP Line BIP-24 LSB */
914 u32 suni_rlop_line_bip24; /* RLOP Line BIP-24 */
915 u32 suni_rlop_line_bip24m; /* RLOP Line BIP-24 MSB */
916 u32 suni_rlop_line_febel; /* RLOP Line FEBE LSB */
917 u32 suni_rlop_line_febe; /* RLOP Line FEBE */
918 u32 suni_rlop_line_febem; /* RLOP Line FEBE MSB */
919
920 u32 suni_tlop_control; /* TLOP Control */
921 u32 suni_tlop_disg; /* TLOP Disgnostics */
922 u32 suni_tlop_reserved[14]; /* TLOP Reserved */
923
924 u32 suni_rpop_cs; /* RPOP Status/Control */
925 u32 suni_rpop_intr; /* RPOP Interrupt/Status */
926 u32 suni_rpop_reserved; /* RPOP Reserved */
927 u32 suni_rpop_intr_ena; /* RPOP Interrupt Enable */
928 u32 suni_rpop_reserved1[3]; /* RPOP Reserved */
929 u32 suni_rpop_path_sig; /* RPOP Path Signal Label */
930 u32 suni_rpop_bip8l; /* RPOP Path BIP-8 LSB */
931 u32 suni_rpop_bip8m; /* RPOP Path BIP-8 MSB */
932 u32 suni_rpop_febel; /* RPOP Path FEBE LSB */
933 u32 suni_rpop_febem; /* RPOP Path FEBE MSB */
934 u32 suni_rpop_reserved2[4]; /* RPOP Reserved */
935
936 u32 suni_tpop_cntrl_daig; /* TPOP Control/Disgnostics */
937 u32 suni_tpop_pointer_ctrl; /* TPOP Pointer Control */
938 u32 suni_tpop_sourcer_ctrl; /* TPOP Source Control */
939 u32 suni_tpop_reserved1[2]; /* TPOP Reserved */
940 u32 suni_tpop_arb_prtl; /* TPOP Arbitrary Pointer LSB */
941 u32 suni_tpop_arb_prtm; /* TPOP Arbitrary Pointer MSB */
942 u32 suni_tpop_reserved2; /* TPOP Reserved */
943 u32 suni_tpop_path_sig; /* TPOP Path Signal Lable */
944 u32 suni_tpop_path_status; /* TPOP Path Status */
945 u32 suni_tpop_reserved3[6]; /* TPOP Reserved */
946
947 u32 suni_racp_cs; /* RACP Control/Status */
948 u32 suni_racp_intr; /* RACP Interrupt Enable/Status */
949 u32 suni_racp_hdr_pattern; /* RACP Match Header Pattern */
950 u32 suni_racp_hdr_mask; /* RACP Match Header Mask */
951 u32 suni_racp_corr_hcs; /* RACP Correctable HCS Error Count */
952 u32 suni_racp_uncorr_hcs; /* RACP Uncorrectable HCS Error Count */
953 u32 suni_racp_reserved[10]; /* RACP Reserved */
954
955 u32 suni_tacp_control; /* TACP Control */
956 u32 suni_tacp_idle_hdr_pat; /* TACP Idle Cell Header Pattern */
957 u32 suni_tacp_idle_pay_pay; /* TACP Idle Cell Payld Octet Pattern */
958 u32 suni_tacp_reserved[5]; /* TACP Reserved */
959
960 u32 suni_reserved3[24]; /* Reserved */
961
962 u32 suni_master_test; /* SUNI Master Test */
963 u32 suni_reserved_test; /* SUNI Reserved for Test */
964 } IA_SUNI;
965
966
967 typedef struct _SUNI_STATS_
968 {
969 u32 valid; // 1 = oc3 PHY card
970 u32 carrier_detect; // GPIN input
971 // RSOP: receive section overhead processor
972 u16 rsop_oof_state; // 1 = out of frame
973 u16 rsop_lof_state; // 1 = loss of frame
974 u16 rsop_los_state; // 1 = loss of signal
975 u32 rsop_los_count; // loss of signal count
976 u32 rsop_bse_count; // section BIP-8 error count
977 // RLOP: receive line overhead processor
978 u16 rlop_ferf_state; // 1 = far end receive failure
979 u16 rlop_lais_state; // 1 = line AIS
980 u32 rlop_lbe_count; // BIP-24 count
981 u32 rlop_febe_count; // FEBE count;
982 // RPOP: receive path overhead processor
983 u16 rpop_lop_state; // 1 = LOP
984 u16 rpop_pais_state; // 1 = path AIS
985 u16 rpop_pyel_state; // 1 = path yellow alert
986 u32 rpop_bip_count; // path BIP-8 error count
987 u32 rpop_febe_count; // path FEBE error count
988 u16 rpop_psig; // path signal label value
989 // RACP: receive ATM cell processor
990 u16 racp_hp_state; // hunt/presync state
991 u32 racp_fu_count; // FIFO underrun count
992 u32 racp_fo_count; // FIFO overrun count
993 u32 racp_chcs_count; // correctable HCS error count
994 u32 racp_uchcs_count; // uncorrectable HCS error count
995 } IA_SUNI_STATS;
996
997 typedef struct iadev_t {
998 /*-----base pointers into (i)chipSAR+ address space */
999 u32 __iomem *phy; /* base pointer into phy(SUNI) */
1000 u32 __iomem *dma; /* base pointer into DMA control
1001 registers */
1002 u32 __iomem *reg; /* base pointer to SAR registers
1003 - Bus Interface Control Regs */
1004 u32 __iomem *seg_reg; /* base pointer to segmentation engine
1005 internal registers */
1006 u32 __iomem *reass_reg; /* base pointer to reassemble engine
1007 internal registers */
1008 u32 __iomem *ram; /* base pointer to SAR RAM */
1009 void __iomem *seg_ram;
1010 void __iomem *reass_ram;
1011 struct dle_q tx_dle_q;
1012 struct free_desc_q *tx_free_desc_qhead;
1013 struct sk_buff_head tx_dma_q, tx_backlog;
1014 spinlock_t tx_lock;
1015 IARTN_Q tx_return_q;
1016 u32 close_pending;
1017 wait_queue_head_t close_wait;
1018 wait_queue_head_t timeout_wait;
1019 struct cpcs_trailer_desc *tx_buf;
1020 u16 num_tx_desc, tx_buf_sz, rate_limit;
1021 u32 tx_cell_cnt, tx_pkt_cnt;
1022 void __iomem *MAIN_VC_TABLE_ADDR, *EXT_VC_TABLE_ADDR, *ABR_SCHED_TABLE_ADDR;
1023 struct dle_q rx_dle_q;
1024 struct free_desc_q *rx_free_desc_qhead;
1025 struct sk_buff_head rx_dma_q;
1026 spinlock_t rx_lock, misc_lock;
1027 struct atm_vcc **rx_open; /* list of all open VCs */
1028 u16 num_rx_desc, rx_buf_sz, rxing;
1029 u32 rx_pkt_ram, rx_tmp_cnt, rx_tmp_jif;
1030 void __iomem *RX_DESC_BASE_ADDR;
1031 u32 drop_rxpkt, drop_rxcell, rx_cell_cnt, rx_pkt_cnt;
1032 struct atm_dev *next_board; /* other iphase devices */
1033 struct pci_dev *pci;
1034 int mem;
1035 unsigned int real_base; /* real and virtual base address */
1036 void __iomem *base;
1037 unsigned int pci_map_size; /*pci map size of board */
1038 unsigned char irq;
1039 unsigned char bus;
1040 unsigned char dev_fn;
1041 u_short phy_type;
1042 u_short num_vc, memSize, memType;
1043 struct ia_ffL_t ffL;
1044 struct ia_rfL_t rfL;
1045 /* Suni stat */
1046 // IA_SUNI_STATS suni_stats;
1047 unsigned char carrier_detect;
1048 /* CBR related */
1049 // transmit DMA & Receive
1050 unsigned int tx_dma_cnt; // number of elements on dma queue
1051 unsigned int rx_dma_cnt; // number of elements on rx dma queue
1052 unsigned int NumEnabledCBR; // number of CBR VCI's enabled. CBR
1053 // receive MARK for Cell FIFO
1054 unsigned int rx_mark_cnt; // number of elements on mark queue
1055 unsigned int CbrTotEntries; // Total CBR Entries in Scheduling Table.
1056 unsigned int CbrRemEntries; // Remaining CBR Entries in Scheduling Table.
1057 unsigned int CbrEntryPt; // CBR Sched Table Entry Point.
1058 unsigned int Granularity; // CBR Granularity given Table Size.
1059 /* ABR related */
1060 unsigned int sum_mcr, sum_cbr, LineRate;
1061 unsigned int n_abr;
1062 struct desc_tbl_t *desc_tbl;
1063 u_short host_tcq_wr;
1064 struct testTable_t **testTable;
1065 dma_addr_t tx_dle_dma;
1066 dma_addr_t rx_dle_dma;
1067 } IADEV;
1068
1069
1070 #define INPH_IA_DEV(d) ((IADEV *) (d)->dev_data)
1071 #define INPH_IA_VCC(v) ((struct ia_vcc *) (v)->dev_data)
1072
1073 /******************* IDT77105 25MB/s PHY DEFINE *****************************/
1074 typedef struct {
1075 u_int mb25_master_ctrl; /* Master control */
1076 u_int mb25_intr_status; /* Interrupt status */
1077 u_int mb25_diag_control; /* Diagnostic control */
1078 u_int mb25_led_hec; /* LED driver and HEC status/control */
1079 u_int mb25_low_byte_counter; /* Low byte counter */
1080 u_int mb25_high_byte_counter; /* High byte counter */
1081 } ia_mb25_t;
1082
1083 /*
1084 * Master Control
1085 */
1086 #define MB25_MC_UPLO 0x80 /* UPLO */
1087 #define MB25_MC_DREC 0x40 /* Discard receive cell errors */
1088 #define MB25_MC_ECEIO 0x20 /* Enable Cell Error Interrupts Only */
1089 #define MB25_MC_TDPC 0x10 /* Transmit data parity check */
1090 #define MB25_MC_DRIC 0x08 /* Discard receive idle cells */
1091 #define MB25_MC_HALTTX 0x04 /* Halt Tx */
1092 #define MB25_MC_UMS 0x02 /* UTOPIA mode select */
1093 #define MB25_MC_ENABLED 0x01 /* Enable interrupt */
1094
1095 /*
1096 * Interrupt Status
1097 */
1098 #define MB25_IS_GSB 0x40 /* GOOD Symbol Bit */
1099 #define MB25_IS_HECECR 0x20 /* HEC error cell received */
1100 #define MB25_IS_SCR 0x10 /* "Short Cell" Received */
1101 #define MB25_IS_TPE 0x08 /* Trnamsit Parity Error */
1102 #define MB25_IS_RSCC 0x04 /* Receive Signal Condition change */
1103 #define MB25_IS_RCSE 0x02 /* Received Cell Symbol Error */
1104 #define MB25_IS_RFIFOO 0x01 /* Received FIFO Overrun */
1105
1106 /*
1107 * Diagnostic Control
1108 */
1109 #define MB25_DC_FTXCD 0x80 /* Force TxClav deassert */
1110 #define MB25_DC_RXCOS 0x40 /* RxClav operation select */
1111 #define MB25_DC_ECEIO 0x20 /* Single/Multi-PHY config select */
1112 #define MB25_DC_RLFLUSH 0x10 /* Clear receive FIFO */
1113 #define MB25_DC_IXPE 0x08 /* Insert xmit payload error */
1114 #define MB25_DC_IXHECE 0x04 /* Insert Xmit HEC Error */
1115 #define MB25_DC_LB_MASK 0x03 /* Loopback control mask */
1116
1117 #define MB25_DC_LL 0x03 /* Line Loopback */
1118 #define MB25_DC_PL 0x02 /* PHY Loopback */
1119 #define MB25_DC_NM 0x00
1120
1121 #define FE_MASK 0x00F0
1122 #define FE_MULTI_MODE 0x0000
1123 #define FE_SINGLE_MODE 0x0010
1124 #define FE_UTP_OPTION 0x0020
1125 #define FE_25MBIT_PHY 0x0040
1126 #define FE_DS3_PHY 0x0080 /* DS3 */
1127 #define FE_E3_PHY 0x0090 /* E3 */
1128
1129 /*********************** SUNI_PM7345 PHY DEFINE HERE *********************/
1130 typedef struct _suni_pm7345_t
1131 {
1132 u_int suni_config; /* SUNI Configuration */
1133 u_int suni_intr_enbl; /* SUNI Interrupt Enable */
1134 u_int suni_intr_stat; /* SUNI Interrupt Status */
1135 u_int suni_control; /* SUNI Control */
1136 u_int suni_id_reset; /* SUNI Reset and Identity */
1137 u_int suni_data_link_ctrl;
1138 u_int suni_rboc_conf_intr_enbl;
1139 u_int suni_rboc_stat;
1140 u_int suni_ds3_frm_cfg;
1141 u_int suni_ds3_frm_intr_enbl;
1142 u_int suni_ds3_frm_intr_stat;
1143 u_int suni_ds3_frm_stat;
1144 u_int suni_rfdl_cfg;
1145 u_int suni_rfdl_enbl_stat;
1146 u_int suni_rfdl_stat;
1147 u_int suni_rfdl_data;
1148 u_int suni_pmon_chng;
1149 u_int suni_pmon_intr_enbl_stat;
1150 u_int suni_reserved1[0x13-0x11];
1151 u_int suni_pmon_lcv_evt_cnt_lsb;
1152 u_int suni_pmon_lcv_evt_cnt_msb;
1153 u_int suni_pmon_fbe_evt_cnt_lsb;
1154 u_int suni_pmon_fbe_evt_cnt_msb;
1155 u_int suni_pmon_sez_det_cnt_lsb;
1156 u_int suni_pmon_sez_det_cnt_msb;
1157 u_int suni_pmon_pe_evt_cnt_lsb;
1158 u_int suni_pmon_pe_evt_cnt_msb;
1159 u_int suni_pmon_ppe_evt_cnt_lsb;
1160 u_int suni_pmon_ppe_evt_cnt_msb;
1161 u_int suni_pmon_febe_evt_cnt_lsb;
1162 u_int suni_pmon_febe_evt_cnt_msb;
1163 u_int suni_ds3_tran_cfg;
1164 u_int suni_ds3_tran_diag;
1165 u_int suni_reserved2[0x23-0x21];
1166 u_int suni_xfdl_cfg;
1167 u_int suni_xfdl_intr_st;
1168 u_int suni_xfdl_xmit_data;
1169 u_int suni_xboc_code;
1170 u_int suni_splr_cfg;
1171 u_int suni_splr_intr_en;
1172 u_int suni_splr_intr_st;
1173 u_int suni_splr_status;
1174 u_int suni_splt_cfg;
1175 u_int suni_splt_cntl;
1176 u_int suni_splt_diag_g1;
1177 u_int suni_splt_f1;
1178 u_int suni_cppm_loc_meters;
1179 u_int suni_cppm_chng_of_cppm_perf_meter;
1180 u_int suni_cppm_b1_err_cnt_lsb;
1181 u_int suni_cppm_b1_err_cnt_msb;
1182 u_int suni_cppm_framing_err_cnt_lsb;
1183 u_int suni_cppm_framing_err_cnt_msb;
1184 u_int suni_cppm_febe_cnt_lsb;
1185 u_int suni_cppm_febe_cnt_msb;
1186 u_int suni_cppm_hcs_err_cnt_lsb;
1187 u_int suni_cppm_hcs_err_cnt_msb;
1188 u_int suni_cppm_idle_un_cell_cnt_lsb;
1189 u_int suni_cppm_idle_un_cell_cnt_msb;
1190 u_int suni_cppm_rcv_cell_cnt_lsb;
1191 u_int suni_cppm_rcv_cell_cnt_msb;
1192 u_int suni_cppm_xmit_cell_cnt_lsb;
1193 u_int suni_cppm_xmit_cell_cnt_msb;
1194 u_int suni_rxcp_ctrl;
1195 u_int suni_rxcp_fctrl;
1196 u_int suni_rxcp_intr_en_sts;
1197 u_int suni_rxcp_idle_pat_h1;
1198 u_int suni_rxcp_idle_pat_h2;
1199 u_int suni_rxcp_idle_pat_h3;
1200 u_int suni_rxcp_idle_pat_h4;
1201 u_int suni_rxcp_idle_mask_h1;
1202 u_int suni_rxcp_idle_mask_h2;
1203 u_int suni_rxcp_idle_mask_h3;
1204 u_int suni_rxcp_idle_mask_h4;
1205 u_int suni_rxcp_cell_pat_h1;
1206 u_int suni_rxcp_cell_pat_h2;
1207 u_int suni_rxcp_cell_pat_h3;
1208 u_int suni_rxcp_cell_pat_h4;
1209 u_int suni_rxcp_cell_mask_h1;
1210 u_int suni_rxcp_cell_mask_h2;
1211 u_int suni_rxcp_cell_mask_h3;
1212 u_int suni_rxcp_cell_mask_h4;
1213 u_int suni_rxcp_hcs_cs;
1214 u_int suni_rxcp_lcd_cnt_threshold;
1215 u_int suni_reserved3[0x57-0x54];
1216 u_int suni_txcp_ctrl;
1217 u_int suni_txcp_intr_en_sts;
1218 u_int suni_txcp_idle_pat_h1;
1219 u_int suni_txcp_idle_pat_h2;
1220 u_int suni_txcp_idle_pat_h3;
1221 u_int suni_txcp_idle_pat_h4;
1222 u_int suni_txcp_idle_pat_h5;
1223 u_int suni_txcp_idle_payload;
1224 u_int suni_e3_frm_fram_options;
1225 u_int suni_e3_frm_maint_options;
1226 u_int suni_e3_frm_fram_intr_enbl;
1227 u_int suni_e3_frm_fram_intr_ind_stat;
1228 u_int suni_e3_frm_maint_intr_enbl;
1229 u_int suni_e3_frm_maint_intr_ind;
1230 u_int suni_e3_frm_maint_stat;
1231 u_int suni_reserved4;
1232 u_int suni_e3_tran_fram_options;
1233 u_int suni_e3_tran_stat_diag_options;
1234 u_int suni_e3_tran_bip_8_err_mask;
1235 u_int suni_e3_tran_maint_adapt_options;
1236 u_int suni_ttb_ctrl;
1237 u_int suni_ttb_trail_trace_id_stat;
1238 u_int suni_ttb_ind_addr;
1239 u_int suni_ttb_ind_data;
1240 u_int suni_ttb_exp_payload_type;
1241 u_int suni_ttb_payload_type_ctrl_stat;
1242 u_int suni_pad5[0x7f-0x71];
1243 u_int suni_master_test;
1244 u_int suni_pad6[0xff-0x80];
1245 }suni_pm7345_t;
1246
1247 #define SUNI_PM7345_T suni_pm7345_t
1248 #define SUNI_PM7345 0x20 /* Suni chip type */
1249 #define SUNI_PM5346 0x30 /* Suni chip type */
1250 /*
1251 * SUNI_PM7345 Configuration
1252 */
1253 #define SUNI_PM7345_CLB 0x01 /* Cell loopback */
1254 #define SUNI_PM7345_PLB 0x02 /* Payload loopback */
1255 #define SUNI_PM7345_DLB 0x04 /* Diagnostic loopback */
1256 #define SUNI_PM7345_LLB 0x80 /* Line loopback */
1257 #define SUNI_PM7345_E3ENBL 0x40 /* E3 enable bit */
1258 #define SUNI_PM7345_LOOPT 0x10 /* LOOPT enable bit */
1259 #define SUNI_PM7345_FIFOBP 0x20 /* FIFO bypass */
1260 #define SUNI_PM7345_FRMRBP 0x08 /* Framer bypass */
1261 /*
1262 * DS3 FRMR Interrupt Enable
1263 */
1264 #define SUNI_DS3_COFAE 0x80 /* Enable change of frame align */
1265 #define SUNI_DS3_REDE 0x40 /* Enable DS3 RED state intr */
1266 #define SUNI_DS3_CBITE 0x20 /* Enable Appl ID channel intr */
1267 #define SUNI_DS3_FERFE 0x10 /* Enable Far End Receive Failure intr*/
1268 #define SUNI_DS3_IDLE 0x08 /* Enable Idle signal intr */
1269 #define SUNI_DS3_AISE 0x04 /* Enable Alarm Indication signal intr*/
1270 #define SUNI_DS3_OOFE 0x02 /* Enable Out of frame intr */
1271 #define SUNI_DS3_LOSE 0x01 /* Enable Loss of signal intr */
1272
1273 /*
1274 * DS3 FRMR Status
1275 */
1276 #define SUNI_DS3_ACE 0x80 /* Additional Configuration Reg */
1277 #define SUNI_DS3_REDV 0x40 /* DS3 RED state */
1278 #define SUNI_DS3_CBITV 0x20 /* Application ID channel state */
1279 #define SUNI_DS3_FERFV 0x10 /* Far End Receive Failure state*/
1280 #define SUNI_DS3_IDLV 0x08 /* Idle signal state */
1281 #define SUNI_DS3_AISV 0x04 /* Alarm Indication signal state*/
1282 #define SUNI_DS3_OOFV 0x02 /* Out of frame state */
1283 #define SUNI_DS3_LOSV 0x01 /* Loss of signal state */
1284
1285 /*
1286 * E3 FRMR Interrupt/Status
1287 */
1288 #define SUNI_E3_CZDI 0x40 /* Consecutive Zeros indicator */
1289 #define SUNI_E3_LOSI 0x20 /* Loss of signal intr status */
1290 #define SUNI_E3_LCVI 0x10 /* Line code violation intr */
1291 #define SUNI_E3_COFAI 0x08 /* Change of frame align intr */
1292 #define SUNI_E3_OOFI 0x04 /* Out of frame intr status */
1293 #define SUNI_E3_LOS 0x02 /* Loss of signal state */
1294 #define SUNI_E3_OOF 0x01 /* Out of frame state */
1295
1296 /*
1297 * E3 FRMR Maintenance Status
1298 */
1299 #define SUNI_E3_AISD 0x80 /* Alarm Indication signal state*/
1300 #define SUNI_E3_FERF_RAI 0x40 /* FERF/RAI indicator */
1301 #define SUNI_E3_FEBE 0x20 /* Far End Block Error indicator*/
1302
1303 /*
1304 * RXCP Control/Status
1305 */
1306 #define SUNI_DS3_HCSPASS 0x80 /* Pass cell with HEC errors */
1307 #define SUNI_DS3_HCSDQDB 0x40 /* Control octets in HCS calc */
1308 #define SUNI_DS3_HCSADD 0x20 /* Add coset poly */
1309 #define SUNI_DS3_HCK 0x10 /* Control FIFO data path integ chk*/
1310 #define SUNI_DS3_BLOCK 0x08 /* Enable cell filtering */
1311 #define SUNI_DS3_DSCR 0x04 /* Disable payload descrambling */
1312 #define SUNI_DS3_OOCDV 0x02 /* Cell delineation state */
1313 #define SUNI_DS3_FIFORST 0x01 /* Cell FIFO reset */
1314
1315 /*
1316 * RXCP Interrupt Enable/Status
1317 */
1318 #define SUNI_DS3_OOCDE 0x80 /* Intr enable, change in CDS */
1319 #define SUNI_DS3_HCSE 0x40 /* Intr enable, corr HCS errors */
1320 #define SUNI_DS3_FIFOE 0x20 /* Intr enable, unco HCS errors */
1321 #define SUNI_DS3_OOCDI 0x10 /* SYNC state */
1322 #define SUNI_DS3_UHCSI 0x08 /* Uncorr. HCS errors detected */
1323 #define SUNI_DS3_COCAI 0x04 /* Corr. HCS errors detected */
1324 #define SUNI_DS3_FOVRI 0x02 /* FIFO overrun */
1325 #define SUNI_DS3_FUDRI 0x01 /* FIFO underrun */
1326
1327 ///////////////////SUNI_PM7345 PHY DEFINE END /////////////////////////////
1328
1329 /* ia_eeprom define*/
1330 #define MEM_SIZE_MASK 0x000F /* mask of 4 bits defining memory size*/
1331 #define MEM_SIZE_128K 0x0000 /* board has 128k buffer */
1332 #define MEM_SIZE_512K 0x0001 /* board has 512K of buffer */
1333 #define MEM_SIZE_1M 0x0002 /* board has 1M of buffer */
1334 /* 0x3 to 0xF are reserved for future */
1335
1336 #define FE_MASK 0x00F0 /* mask of 4 bits defining FE type */
1337 #define FE_MULTI_MODE 0x0000 /* 155 MBit multimode fiber */
1338 #define FE_SINGLE_MODE 0x0010 /* 155 MBit single mode laser */
1339 #define FE_UTP_OPTION 0x0020 /* 155 MBit UTP front end */
1340
1341 #define NOVRAM_SIZE 64
1342 #define CMD_LEN 10
1343
1344 /***********
1345 *
1346 * Switches and defines for header files.
1347 *
1348 * The following defines are used to turn on and off
1349 * various options in the header files. Primarily useful
1350 * for debugging.
1351 *
1352 ***********/
1353
1354 /*
1355 * a list of the commands that can be sent to the NOVRAM
1356 */
1357
1358 #define EXTEND 0x100
1359 #define IAWRITE 0x140
1360 #define IAREAD 0x180
1361 #define ERASE 0x1c0
1362
1363 #define EWDS 0x00
1364 #define WRAL 0x10
1365 #define ERAL 0x20
1366 #define EWEN 0x30
1367
1368 /*
1369 * these bits duplicate the hw_flip.h register settings
1370 * note: how the data in / out bits are defined in the flipper specification
1371 */
1372
1373 #define NVCE 0x02
1374 #define NVSK 0x01
1375 #define NVDO 0x08
1376 #define NVDI 0x04
1377 /***********************
1378 *
1379 * This define ands the value and the current config register and puts
1380 * the result in the config register
1381 *
1382 ***********************/
1383
1384 #define CFG_AND(val) { \
1385 u32 t; \
1386 t = readl(iadev->reg+IPHASE5575_EEPROM_ACCESS); \
1387 t &= (val); \
1388 writel(t, iadev->reg+IPHASE5575_EEPROM_ACCESS); \
1389 }
1390
1391 /***********************
1392 *
1393 * This define ors the value and the current config register and puts
1394 * the result in the config register
1395 *
1396 ***********************/
1397
1398 #define CFG_OR(val) { \
1399 u32 t; \
1400 t = readl(iadev->reg+IPHASE5575_EEPROM_ACCESS); \
1401 t |= (val); \
1402 writel(t, iadev->reg+IPHASE5575_EEPROM_ACCESS); \
1403 }
1404
1405 /***********************
1406 *
1407 * Send a command to the NOVRAM, the command is in cmd.
1408 *
1409 * clear CE and SK. Then assert CE.
1410 * Clock each of the command bits out in the correct order with SK
1411 * exit with CE still asserted
1412 *
1413 ***********************/
1414
1415 #define NVRAM_CMD(cmd) { \
1416 int i; \
1417 u_short c = cmd; \
1418 CFG_AND(~(NVCE|NVSK)); \
1419 CFG_OR(NVCE); \
1420 for (i=0; i<CMD_LEN; i++) { \
1421 NVRAM_CLKOUT((c & (1 << (CMD_LEN - 1))) ? 1 : 0); \
1422 c <<= 1; \
1423 } \
1424 }
1425
1426 /***********************
1427 *
1428 * clear the CE, this must be used after each command is complete
1429 *
1430 ***********************/
1431
1432 #define NVRAM_CLR_CE {CFG_AND(~NVCE)}
1433
1434 /***********************
1435 *
1436 * clock the data bit in bitval out to the NOVRAM. The bitval must be
1437 * a 1 or 0, or the clockout operation is undefined
1438 *
1439 ***********************/
1440
1441 #define NVRAM_CLKOUT(bitval) { \
1442 CFG_AND(~NVDI); \
1443 CFG_OR((bitval) ? NVDI : 0); \
1444 CFG_OR(NVSK); \
1445 CFG_AND( ~NVSK); \
1446 }
1447
1448 /***********************
1449 *
1450 * clock the data bit in and return a 1 or 0, depending on the value
1451 * that was received from the NOVRAM
1452 *
1453 ***********************/
1454
1455 #define NVRAM_CLKIN(value) { \
1456 u32 _t; \
1457 CFG_OR(NVSK); \
1458 CFG_AND(~NVSK); \
1459 _t = readl(iadev->reg+IPHASE5575_EEPROM_ACCESS); \
1460 value = (_t & NVDO) ? 1 : 0; \
1461 }
1462
1463
1464 #endif /* IPHASE_H */
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