[TG3]: Add tagged status support.
[linux-2.6/verdex.git] / drivers / mtd / nand / ppchameleonevb.c
blobe510a83d7bdbc24768185fd2668e93ddf16e6a5a
1 /*
2 * drivers/mtd/nand/ppchameleonevb.c
4 * Copyright (C) 2003 DAVE Srl (info@wawnet.biz)
6 * Derived from drivers/mtd/nand/edb7312.c
9 * $Id: ppchameleonevb.c,v 1.6 2004/11/05 16:07:16 kalev Exp $
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
15 * Overview:
16 * This is a device driver for the NAND flash devices found on the
17 * PPChameleon/PPChameleonEVB system.
18 * PPChameleon options (autodetected):
19 * - BA model: no NAND
20 * - ME model: 32MB (Samsung K9F5608U0B)
21 * - HI model: 128MB (Samsung K9F1G08UOM)
22 * PPChameleonEVB options:
23 * - 32MB (Samsung K9F5608U0B)
26 #include <linux/init.h>
27 #include <linux/slab.h>
28 #include <linux/module.h>
29 #include <linux/mtd/mtd.h>
30 #include <linux/mtd/nand.h>
31 #include <linux/mtd/partitions.h>
32 #include <asm/io.h>
33 #include <platforms/PPChameleonEVB.h>
35 #undef USE_READY_BUSY_PIN
36 #define USE_READY_BUSY_PIN
37 /* see datasheets (tR) */
38 #define NAND_BIG_DELAY_US 25
39 #define NAND_SMALL_DELAY_US 10
41 /* handy sizes */
42 #define SZ_4M 0x00400000
43 #define NAND_SMALL_SIZE 0x02000000
44 #define NAND_MTD_NAME "ppchameleon-nand"
45 #define NAND_EVB_MTD_NAME "ppchameleonevb-nand"
47 /* GPIO pins used to drive NAND chip mounted on processor module */
48 #define NAND_nCE_GPIO_PIN (0x80000000 >> 1)
49 #define NAND_CLE_GPIO_PIN (0x80000000 >> 2)
50 #define NAND_ALE_GPIO_PIN (0x80000000 >> 3)
51 #define NAND_RB_GPIO_PIN (0x80000000 >> 4)
52 /* GPIO pins used to drive NAND chip mounted on EVB */
53 #define NAND_EVB_nCE_GPIO_PIN (0x80000000 >> 14)
54 #define NAND_EVB_CLE_GPIO_PIN (0x80000000 >> 15)
55 #define NAND_EVB_ALE_GPIO_PIN (0x80000000 >> 16)
56 #define NAND_EVB_RB_GPIO_PIN (0x80000000 >> 31)
59 * MTD structure for PPChameleonEVB board
61 static struct mtd_info *ppchameleon_mtd = NULL;
62 static struct mtd_info *ppchameleonevb_mtd = NULL;
65 * Module stuff
67 static unsigned long ppchameleon_fio_pbase = CFG_NAND0_PADDR;
68 static unsigned long ppchameleonevb_fio_pbase = CFG_NAND1_PADDR;
70 #ifdef MODULE
71 module_param(ppchameleon_fio_pbase, ulong, 0);
72 module_param(ppchameleonevb_fio_pbase, ulong, 0);
73 #else
74 __setup("ppchameleon_fio_pbase=",ppchameleon_fio_pbase);
75 __setup("ppchameleonevb_fio_pbase=",ppchameleonevb_fio_pbase);
76 #endif
78 #ifdef CONFIG_MTD_PARTITIONS
80 * Define static partitions for flash devices
82 static struct mtd_partition partition_info_hi[] = {
83 { name: "PPChameleon HI Nand Flash",
84 offset: 0,
85 size: 128*1024*1024 }
88 static struct mtd_partition partition_info_me[] = {
89 { name: "PPChameleon ME Nand Flash",
90 offset: 0,
91 size: 32*1024*1024 }
94 static struct mtd_partition partition_info_evb[] = {
95 { name: "PPChameleonEVB Nand Flash",
96 offset: 0,
97 size: 32*1024*1024 }
100 #define NUM_PARTITIONS 1
102 extern int parse_cmdline_partitions(struct mtd_info *master,
103 struct mtd_partition **pparts,
104 const char *mtd_id);
105 #endif
109 * hardware specific access to control-lines
111 static void ppchameleon_hwcontrol(struct mtd_info *mtdinfo, int cmd)
113 switch(cmd) {
115 case NAND_CTL_SETCLE:
116 MACRO_NAND_CTL_SETCLE((unsigned long)CFG_NAND0_PADDR);
117 break;
118 case NAND_CTL_CLRCLE:
119 MACRO_NAND_CTL_CLRCLE((unsigned long)CFG_NAND0_PADDR);
120 break;
121 case NAND_CTL_SETALE:
122 MACRO_NAND_CTL_SETALE((unsigned long)CFG_NAND0_PADDR);
123 break;
124 case NAND_CTL_CLRALE:
125 MACRO_NAND_CTL_CLRALE((unsigned long)CFG_NAND0_PADDR);
126 break;
127 case NAND_CTL_SETNCE:
128 MACRO_NAND_ENABLE_CE((unsigned long)CFG_NAND0_PADDR);
129 break;
130 case NAND_CTL_CLRNCE:
131 MACRO_NAND_DISABLE_CE((unsigned long)CFG_NAND0_PADDR);
132 break;
136 static void ppchameleonevb_hwcontrol(struct mtd_info *mtdinfo, int cmd)
138 switch(cmd) {
140 case NAND_CTL_SETCLE:
141 MACRO_NAND_CTL_SETCLE((unsigned long)CFG_NAND1_PADDR);
142 break;
143 case NAND_CTL_CLRCLE:
144 MACRO_NAND_CTL_CLRCLE((unsigned long)CFG_NAND1_PADDR);
145 break;
146 case NAND_CTL_SETALE:
147 MACRO_NAND_CTL_SETALE((unsigned long)CFG_NAND1_PADDR);
148 break;
149 case NAND_CTL_CLRALE:
150 MACRO_NAND_CTL_CLRALE((unsigned long)CFG_NAND1_PADDR);
151 break;
152 case NAND_CTL_SETNCE:
153 MACRO_NAND_ENABLE_CE((unsigned long)CFG_NAND1_PADDR);
154 break;
155 case NAND_CTL_CLRNCE:
156 MACRO_NAND_DISABLE_CE((unsigned long)CFG_NAND1_PADDR);
157 break;
161 #ifdef USE_READY_BUSY_PIN
163 * read device ready pin
165 static int ppchameleon_device_ready(struct mtd_info *minfo)
167 if (in_be32((volatile unsigned*)GPIO0_IR) & NAND_RB_GPIO_PIN)
168 return 1;
169 return 0;
172 static int ppchameleonevb_device_ready(struct mtd_info *minfo)
174 if (in_be32((volatile unsigned*)GPIO0_IR) & NAND_EVB_RB_GPIO_PIN)
175 return 1;
176 return 0;
178 #endif
180 #ifdef CONFIG_MTD_PARTITIONS
181 const char *part_probes[] = { "cmdlinepart", NULL };
182 const char *part_probes_evb[] = { "cmdlinepart", NULL };
183 #endif
186 * Main initialization routine
188 static int __init ppchameleonevb_init (void)
190 struct nand_chip *this;
191 const char *part_type = 0;
192 int mtd_parts_nb = 0;
193 struct mtd_partition *mtd_parts = 0;
194 void __iomem *ppchameleon_fio_base;
195 void __iomem *ppchameleonevb_fio_base;
198 /*********************************
199 * Processor module NAND (if any) *
200 *********************************/
201 /* Allocate memory for MTD device structure and private data */
202 ppchameleon_mtd = kmalloc(sizeof(struct mtd_info) +
203 sizeof(struct nand_chip), GFP_KERNEL);
204 if (!ppchameleon_mtd) {
205 printk("Unable to allocate PPChameleon NAND MTD device structure.\n");
206 return -ENOMEM;
209 /* map physical address */
210 ppchameleon_fio_base = ioremap(ppchameleon_fio_pbase, SZ_4M);
211 if(!ppchameleon_fio_base) {
212 printk("ioremap PPChameleon NAND flash failed\n");
213 kfree(ppchameleon_mtd);
214 return -EIO;
217 /* Get pointer to private data */
218 this = (struct nand_chip *) (&ppchameleon_mtd[1]);
220 /* Initialize structures */
221 memset((char *) ppchameleon_mtd, 0, sizeof(struct mtd_info));
222 memset((char *) this, 0, sizeof(struct nand_chip));
224 /* Link the private data with the MTD structure */
225 ppchameleon_mtd->priv = this;
227 /* Initialize GPIOs */
228 /* Pin mapping for NAND chip */
230 CE GPIO_01
231 CLE GPIO_02
232 ALE GPIO_03
233 R/B GPIO_04
235 /* output select */
236 out_be32((volatile unsigned*)GPIO0_OSRH, in_be32((volatile unsigned*)GPIO0_OSRH) & 0xC0FFFFFF);
237 /* three-state select */
238 out_be32((volatile unsigned*)GPIO0_TSRH, in_be32((volatile unsigned*)GPIO0_TSRH) & 0xC0FFFFFF);
239 /* enable output driver */
240 out_be32((volatile unsigned*)GPIO0_TCR, in_be32((volatile unsigned*)GPIO0_TCR) | NAND_nCE_GPIO_PIN | NAND_CLE_GPIO_PIN | NAND_ALE_GPIO_PIN);
241 #ifdef USE_READY_BUSY_PIN
242 /* three-state select */
243 out_be32((volatile unsigned*)GPIO0_TSRH, in_be32((volatile unsigned*)GPIO0_TSRH) & 0xFF3FFFFF);
244 /* high-impedecence */
245 out_be32((volatile unsigned*)GPIO0_TCR, in_be32((volatile unsigned*)GPIO0_TCR) & (~NAND_RB_GPIO_PIN));
246 /* input select */
247 out_be32((volatile unsigned*)GPIO0_ISR1H, (in_be32((volatile unsigned*)GPIO0_ISR1H) & 0xFF3FFFFF) | 0x00400000);
248 #endif
250 /* insert callbacks */
251 this->IO_ADDR_R = ppchameleon_fio_base;
252 this->IO_ADDR_W = ppchameleon_fio_base;
253 this->hwcontrol = ppchameleon_hwcontrol;
254 #ifdef USE_READY_BUSY_PIN
255 this->dev_ready = ppchameleon_device_ready;
256 #endif
257 this->chip_delay = NAND_BIG_DELAY_US;
258 /* ECC mode */
259 this->eccmode = NAND_ECC_SOFT;
261 /* Scan to find existence of the device (it could not be mounted) */
262 if (nand_scan (ppchameleon_mtd, 1)) {
263 iounmap((void *)ppchameleon_fio_base);
264 kfree (ppchameleon_mtd);
265 goto nand_evb_init;
268 #ifndef USE_READY_BUSY_PIN
269 /* Adjust delay if necessary */
270 if (ppchameleon_mtd->size == NAND_SMALL_SIZE)
271 this->chip_delay = NAND_SMALL_DELAY_US;
272 #endif
274 #ifdef CONFIG_MTD_PARTITIONS
275 ppchameleon_mtd->name = "ppchameleon-nand";
276 mtd_parts_nb = parse_mtd_partitions(ppchameleon_mtd, part_probes, &mtd_parts, 0);
277 if (mtd_parts_nb > 0)
278 part_type = "command line";
279 else
280 mtd_parts_nb = 0;
281 #endif
282 if (mtd_parts_nb == 0)
284 if (ppchameleon_mtd->size == NAND_SMALL_SIZE)
285 mtd_parts = partition_info_me;
286 else
287 mtd_parts = partition_info_hi;
288 mtd_parts_nb = NUM_PARTITIONS;
289 part_type = "static";
292 /* Register the partitions */
293 printk(KERN_NOTICE "Using %s partition definition\n", part_type);
294 add_mtd_partitions(ppchameleon_mtd, mtd_parts, mtd_parts_nb);
296 nand_evb_init:
297 /****************************
298 * EVB NAND (always present) *
299 ****************************/
300 /* Allocate memory for MTD device structure and private data */
301 ppchameleonevb_mtd = kmalloc(sizeof(struct mtd_info) +
302 sizeof(struct nand_chip), GFP_KERNEL);
303 if (!ppchameleonevb_mtd) {
304 printk("Unable to allocate PPChameleonEVB NAND MTD device structure.\n");
305 return -ENOMEM;
308 /* map physical address */
309 ppchameleonevb_fio_base = ioremap(ppchameleonevb_fio_pbase, SZ_4M);
310 if(!ppchameleonevb_fio_base) {
311 printk("ioremap PPChameleonEVB NAND flash failed\n");
312 kfree(ppchameleonevb_mtd);
313 return -EIO;
316 /* Get pointer to private data */
317 this = (struct nand_chip *) (&ppchameleonevb_mtd[1]);
319 /* Initialize structures */
320 memset((char *) ppchameleonevb_mtd, 0, sizeof(struct mtd_info));
321 memset((char *) this, 0, sizeof(struct nand_chip));
323 /* Link the private data with the MTD structure */
324 ppchameleonevb_mtd->priv = this;
326 /* Initialize GPIOs */
327 /* Pin mapping for NAND chip */
329 CE GPIO_14
330 CLE GPIO_15
331 ALE GPIO_16
332 R/B GPIO_31
334 /* output select */
335 out_be32((volatile unsigned*)GPIO0_OSRH, in_be32((volatile unsigned*)GPIO0_OSRH) & 0xFFFFFFF0);
336 out_be32((volatile unsigned*)GPIO0_OSRL, in_be32((volatile unsigned*)GPIO0_OSRL) & 0x3FFFFFFF);
337 /* three-state select */
338 out_be32((volatile unsigned*)GPIO0_TSRH, in_be32((volatile unsigned*)GPIO0_TSRH) & 0xFFFFFFF0);
339 out_be32((volatile unsigned*)GPIO0_TSRL, in_be32((volatile unsigned*)GPIO0_TSRL) & 0x3FFFFFFF);
340 /* enable output driver */
341 out_be32((volatile unsigned*)GPIO0_TCR, in_be32((volatile unsigned*)GPIO0_TCR) | NAND_EVB_nCE_GPIO_PIN |
342 NAND_EVB_CLE_GPIO_PIN | NAND_EVB_ALE_GPIO_PIN);
343 #ifdef USE_READY_BUSY_PIN
344 /* three-state select */
345 out_be32((volatile unsigned*)GPIO0_TSRL, in_be32((volatile unsigned*)GPIO0_TSRL) & 0xFFFFFFFC);
346 /* high-impedecence */
347 out_be32((volatile unsigned*)GPIO0_TCR, in_be32((volatile unsigned*)GPIO0_TCR) & (~NAND_EVB_RB_GPIO_PIN));
348 /* input select */
349 out_be32((volatile unsigned*)GPIO0_ISR1L, (in_be32((volatile unsigned*)GPIO0_ISR1L) & 0xFFFFFFFC) | 0x00000001);
350 #endif
352 /* insert callbacks */
353 this->IO_ADDR_R = ppchameleonevb_fio_base;
354 this->IO_ADDR_W = ppchameleonevb_fio_base;
355 this->hwcontrol = ppchameleonevb_hwcontrol;
356 #ifdef USE_READY_BUSY_PIN
357 this->dev_ready = ppchameleonevb_device_ready;
358 #endif
359 this->chip_delay = NAND_SMALL_DELAY_US;
361 /* ECC mode */
362 this->eccmode = NAND_ECC_SOFT;
364 /* Scan to find existence of the device */
365 if (nand_scan (ppchameleonevb_mtd, 1)) {
366 iounmap((void *)ppchameleonevb_fio_base);
367 kfree (ppchameleonevb_mtd);
368 return -ENXIO;
371 #ifdef CONFIG_MTD_PARTITIONS
372 ppchameleonevb_mtd->name = NAND_EVB_MTD_NAME;
373 mtd_parts_nb = parse_mtd_partitions(ppchameleonevb_mtd, part_probes_evb, &mtd_parts, 0);
374 if (mtd_parts_nb > 0)
375 part_type = "command line";
376 else
377 mtd_parts_nb = 0;
378 #endif
379 if (mtd_parts_nb == 0)
381 mtd_parts = partition_info_evb;
382 mtd_parts_nb = NUM_PARTITIONS;
383 part_type = "static";
386 /* Register the partitions */
387 printk(KERN_NOTICE "Using %s partition definition\n", part_type);
388 add_mtd_partitions(ppchameleonevb_mtd, mtd_parts, mtd_parts_nb);
390 /* Return happy */
391 return 0;
393 module_init(ppchameleonevb_init);
396 * Clean up routine
398 static void __exit ppchameleonevb_cleanup (void)
400 struct nand_chip *this;
402 /* Release resources, unregister device(s) */
403 nand_release (ppchameleon_mtd);
404 nand_release (ppchameleonevb_mtd);
406 /* Release iomaps */
407 this = (struct nand_chip *) &ppchameleon_mtd[1];
408 iounmap((void *) this->IO_ADDR_R;
409 this = (struct nand_chip *) &ppchameleonevb_mtd[1];
410 iounmap((void *) this->IO_ADDR_R;
412 /* Free the MTD device structure */
413 kfree (ppchameleon_mtd);
414 kfree (ppchameleonevb_mtd);
416 module_exit(ppchameleonevb_cleanup);
418 MODULE_LICENSE("GPL");
419 MODULE_AUTHOR("DAVE Srl <support-ppchameleon@dave-tech.it>");
420 MODULE_DESCRIPTION("MTD map driver for DAVE Srl PPChameleonEVB board");