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[TG3]: Add tagged status support.
[linux-2.6/verdex.git] / drivers / net / amd8111e.c
blobf2e937abf7b4d8c639675100dd5ffc74c5323ebe
1
2 /* Advanced Micro Devices Inc. AMD8111E Linux Network Driver
3 * Copyright (C) 2004 Advanced Micro Devices
4 *
5 *
6 * Copyright 2001,2002 Jeff Garzik <jgarzik@mandrakesoft.com> [ 8139cp.c,tg3.c ]
7 * Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com)[ tg3.c]
8 * Copyright 1996-1999 Thomas Bogendoerfer [ pcnet32.c ]
9 * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
10 * Copyright 1993 United States Government as represented by the
11 * Director, National Security Agency.[ pcnet32.c ]
12 * Carsten Langgaard, carstenl@mips.com [ pcnet32.c ]
13 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
14 *
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
29 * USA
30
31 Module Name:
32
33 amd8111e.c
34
35 Abstract:
36
37 AMD8111 based 10/100 Ethernet Controller Driver.
38
39 Environment:
40
41 Kernel Mode
42
43 Revision History:
44 3.0.0
45 Initial Revision.
46 3.0.1
47 1. Dynamic interrupt coalescing.
48 2. Removed prev_stats.
49 3. MII support.
50 4. Dynamic IPG support
51 3.0.2 05/29/2003
52 1. Bug fix: Fixed failure to send jumbo packets larger than 4k.
53 2. Bug fix: Fixed VLAN support failure.
54 3. Bug fix: Fixed receive interrupt coalescing bug.
55 4. Dynamic IPG support is disabled by default.
56 3.0.3 06/05/2003
57 1. Bug fix: Fixed failure to close the interface if SMP is enabled.
58 3.0.4 12/09/2003
59 1. Added set_mac_address routine for bonding driver support.
60 2. Tested the driver for bonding support
61 3. Bug fix: Fixed mismach in actual receive buffer lenth and lenth
62 indicated to the h/w.
63 4. Modified amd8111e_rx() routine to receive all the received packets
64 in the first interrupt.
65 5. Bug fix: Corrected rx_errors reported in get_stats() function.
66 3.0.5 03/22/2004
67 1. Added NAPI support
68
69 */
70
71
72 #include <linux/config.h>
73 #include <linux/module.h>
74 #include <linux/kernel.h>
75 #include <linux/types.h>
76 #include <linux/compiler.h>
77 #include <linux/slab.h>
78 #include <linux/delay.h>
79 #include <linux/init.h>
80 #include <linux/ioport.h>
81 #include <linux/pci.h>
82 #include <linux/netdevice.h>
83 #include <linux/etherdevice.h>
84 #include <linux/skbuff.h>
85 #include <linux/ethtool.h>
86 #include <linux/mii.h>
87 #include <linux/if_vlan.h>
88 #include <linux/ctype.h>
89 #include <linux/crc32.h>
90
91 #include <asm/system.h>
92 #include <asm/io.h>
93 #include <asm/byteorder.h>
94 #include <asm/uaccess.h>
95
96 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
97 #define AMD8111E_VLAN_TAG_USED 1
98 #else
99 #define AMD8111E_VLAN_TAG_USED 0
100 #endif
101
102 #include "amd8111e.h"
103 #define MODULE_NAME "amd8111e"
104 #define MODULE_VERS "3.0.5"
105 MODULE_AUTHOR("Advanced Micro Devices, Inc.");
106 MODULE_DESCRIPTION ("AMD8111 based 10/100 Ethernet Controller. Driver Version 3.0.3");
107 MODULE_LICENSE("GPL");
108 MODULE_DEVICE_TABLE(pci, amd8111e_pci_tbl);
109 module_param_array(speed_duplex, int, NULL, 0);
110 MODULE_PARM_DESC(speed_duplex, "Set device speed and duplex modes, 0: Auto Negotitate, 1: 10Mbps Half Duplex, 2: 10Mbps Full Duplex, 3: 100Mbps Half Duplex, 4: 100Mbps Full Duplex");
111 module_param_array(coalesce, bool, NULL, 0);
112 MODULE_PARM_DESC(coalesce, "Enable or Disable interrupt coalescing, 1: Enable, 0: Disable");
113 module_param_array(dynamic_ipg, bool, NULL, 0);
114 MODULE_PARM_DESC(dynamic_ipg, "Enable or Disable dynamic IPG, 1: Enable, 0: Disable");
115
116 static struct pci_device_id amd8111e_pci_tbl[] = {
117
118 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD8111E_7462,
119 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
120 { 0, }
121
122 };
123 /*
124 This function will read the PHY registers.
125 */
126 static int amd8111e_read_phy(struct amd8111e_priv* lp, int phy_id, int reg, u32* val)
127 {
128 void __iomem *mmio = lp->mmio;
129 unsigned int reg_val;
130 unsigned int repeat= REPEAT_CNT;
131
132 reg_val = readl(mmio + PHY_ACCESS);
133 while (reg_val & PHY_CMD_ACTIVE)
134 reg_val = readl( mmio + PHY_ACCESS );
135
136 writel( PHY_RD_CMD | ((phy_id & 0x1f) << 21) |
137 ((reg & 0x1f) << 16), mmio +PHY_ACCESS);
138 do{
139 reg_val = readl(mmio + PHY_ACCESS);
140 udelay(30); /* It takes 30 us to read/write data */
141 } while (--repeat && (reg_val & PHY_CMD_ACTIVE));
142 if(reg_val & PHY_RD_ERR)
143 goto err_phy_read;
144
145 *val = reg_val & 0xffff;
146 return 0;
147 err_phy_read:
148 *val = 0;
149 return -EINVAL;
150
151 }
152
153 /*
154 This function will write into PHY registers.
155 */
156 static int amd8111e_write_phy(struct amd8111e_priv* lp,int phy_id, int reg, u32 val)
157 {
158 unsigned int repeat = REPEAT_CNT
159 void __iomem *mmio = lp->mmio;
160 unsigned int reg_val;
161
162 reg_val = readl(mmio + PHY_ACCESS);
163 while (reg_val & PHY_CMD_ACTIVE)
164 reg_val = readl( mmio + PHY_ACCESS );
165
166 writel( PHY_WR_CMD | ((phy_id & 0x1f) << 21) |
167 ((reg & 0x1f) << 16)|val, mmio + PHY_ACCESS);
168
169 do{
170 reg_val = readl(mmio + PHY_ACCESS);
171 udelay(30); /* It takes 30 us to read/write the data */
172 } while (--repeat && (reg_val & PHY_CMD_ACTIVE));
173
174 if(reg_val & PHY_RD_ERR)
175 goto err_phy_write;
176
177 return 0;
178
179 err_phy_write:
180 return -EINVAL;
181
182 }
183 /*
184 This is the mii register read function provided to the mii interface.
185 */
186 static int amd8111e_mdio_read(struct net_device * dev, int phy_id, int reg_num)
187 {
188 struct amd8111e_priv* lp = netdev_priv(dev);
189 unsigned int reg_val;
190
191 amd8111e_read_phy(lp,phy_id,reg_num,&reg_val);
192 return reg_val;
193
194 }
195
196 /*
197 This is the mii register write function provided to the mii interface.
198 */
199 static void amd8111e_mdio_write(struct net_device * dev, int phy_id, int reg_num, int val)
200 {
201 struct amd8111e_priv* lp = netdev_priv(dev);
202
203 amd8111e_write_phy(lp, phy_id, reg_num, val);
204 }
205
206 /*
207 This function will set PHY speed. During initialization sets the original speed to 100 full.
208 */
209 static void amd8111e_set_ext_phy(struct net_device *dev)
210 {
211 struct amd8111e_priv *lp = netdev_priv(dev);
212 u32 bmcr,advert,tmp;
213
214 /* Determine mii register values to set the speed */
215 advert = amd8111e_mdio_read(dev, lp->ext_phy_addr, MII_ADVERTISE);
216 tmp = advert & ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
217 switch (lp->ext_phy_option){
218
219 default:
220 case SPEED_AUTONEG: /* advertise all values */
221 tmp |= ( ADVERTISE_10HALF|ADVERTISE_10FULL|
222 ADVERTISE_100HALF|ADVERTISE_100FULL) ;
223 break;
224 case SPEED10_HALF:
225 tmp |= ADVERTISE_10HALF;
226 break;
227 case SPEED10_FULL:
228 tmp |= ADVERTISE_10FULL;
229 break;
230 case SPEED100_HALF:
231 tmp |= ADVERTISE_100HALF;
232 break;
233 case SPEED100_FULL:
234 tmp |= ADVERTISE_100FULL;
235 break;
236 }
237
238 if(advert != tmp)
239 amd8111e_mdio_write(dev, lp->ext_phy_addr, MII_ADVERTISE, tmp);
240 /* Restart auto negotiation */
241 bmcr = amd8111e_mdio_read(dev, lp->ext_phy_addr, MII_BMCR);
242 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
243 amd8111e_mdio_write(dev, lp->ext_phy_addr, MII_BMCR, bmcr);
244
245 }
246
247 /*
248 This function will unmap skb->data space and will free
249 all transmit and receive skbuffs.
250 */
251 static int amd8111e_free_skbs(struct net_device *dev)
252 {
253 struct amd8111e_priv *lp = netdev_priv(dev);
254 struct sk_buff* rx_skbuff;
255 int i;
256
257 /* Freeing transmit skbs */
258 for(i = 0; i < NUM_TX_BUFFERS; i++){
259 if(lp->tx_skbuff[i]){
260 pci_unmap_single(lp->pci_dev,lp->tx_dma_addr[i], lp->tx_skbuff[i]->len,PCI_DMA_TODEVICE);
261 dev_kfree_skb (lp->tx_skbuff[i]);
262 lp->tx_skbuff[i] = NULL;
263 lp->tx_dma_addr[i] = 0;
264 }
265 }
266 /* Freeing previously allocated receive buffers */
267 for (i = 0; i < NUM_RX_BUFFERS; i++){
268 rx_skbuff = lp->rx_skbuff[i];
269 if(rx_skbuff != NULL){
270 pci_unmap_single(lp->pci_dev,lp->rx_dma_addr[i],
271 lp->rx_buff_len - 2,PCI_DMA_FROMDEVICE);
272 dev_kfree_skb(lp->rx_skbuff[i]);
273 lp->rx_skbuff[i] = NULL;
274 lp->rx_dma_addr[i] = 0;
275 }
276 }
277
278 return 0;
279 }
280
281 /*
282 This will set the receive buffer length corresponding to the mtu size of networkinterface.
283 */
284 static inline void amd8111e_set_rx_buff_len(struct net_device* dev)
285 {
286 struct amd8111e_priv* lp = netdev_priv(dev);
287 unsigned int mtu = dev->mtu;
288
289 if (mtu > ETH_DATA_LEN){
290 /* MTU + ethernet header + FCS
291 + optional VLAN tag + skb reserve space 2 */
292
293 lp->rx_buff_len = mtu + ETH_HLEN + 10;
294 lp->options |= OPTION_JUMBO_ENABLE;
295 } else{
296 lp->rx_buff_len = PKT_BUFF_SZ;
297 lp->options &= ~OPTION_JUMBO_ENABLE;
298 }
299 }
300
301 /*
302 This function will free all the previously allocated buffers, determine new receive buffer length and will allocate new receive buffers. This function also allocates and initializes both the transmitter and receive hardware descriptors.
303 */
304 static int amd8111e_init_ring(struct net_device *dev)
305 {
306 struct amd8111e_priv *lp = netdev_priv(dev);
307 int i;
308
309 lp->rx_idx = lp->tx_idx = 0;
310 lp->tx_complete_idx = 0;
311 lp->tx_ring_idx = 0;
312
313
314 if(lp->opened)
315 /* Free previously allocated transmit and receive skbs */
316 amd8111e_free_skbs(dev);
317
318 else{
319 /* allocate the tx and rx descriptors */
320 if((lp->tx_ring = pci_alloc_consistent(lp->pci_dev,
321 sizeof(struct amd8111e_tx_dr)*NUM_TX_RING_DR,
322 &lp->tx_ring_dma_addr)) == NULL)
323
324 goto err_no_mem;
325
326 if((lp->rx_ring = pci_alloc_consistent(lp->pci_dev,
327 sizeof(struct amd8111e_rx_dr)*NUM_RX_RING_DR,
328 &lp->rx_ring_dma_addr)) == NULL)
329
330 goto err_free_tx_ring;
331
332 }
333 /* Set new receive buff size */
334 amd8111e_set_rx_buff_len(dev);
335
336 /* Allocating receive skbs */
337 for (i = 0; i < NUM_RX_BUFFERS; i++) {
338
339 if (!(lp->rx_skbuff[i] = dev_alloc_skb(lp->rx_buff_len))) {
340 /* Release previos allocated skbs */
341 for(--i; i >= 0 ;i--)
342 dev_kfree_skb(lp->rx_skbuff[i]);
343 goto err_free_rx_ring;
344 }
345 skb_reserve(lp->rx_skbuff[i],2);
346 }
347 /* Initilaizing receive descriptors */
348 for (i = 0; i < NUM_RX_BUFFERS; i++) {
349 lp->rx_dma_addr[i] = pci_map_single(lp->pci_dev,
350 lp->rx_skbuff[i]->data,lp->rx_buff_len-2, PCI_DMA_FROMDEVICE);
351
352 lp->rx_ring[i].buff_phy_addr = cpu_to_le32(lp->rx_dma_addr[i]);
353 lp->rx_ring[i].buff_count = cpu_to_le16(lp->rx_buff_len-2);
354 wmb();
355 lp->rx_ring[i].rx_flags = cpu_to_le16(OWN_BIT);
356 }
357
358 /* Initializing transmit descriptors */
359 for (i = 0; i < NUM_TX_RING_DR; i++) {
360 lp->tx_ring[i].buff_phy_addr = 0;
361 lp->tx_ring[i].tx_flags = 0;
362 lp->tx_ring[i].buff_count = 0;
363 }
364
365 return 0;
366
367 err_free_rx_ring:
368
369 pci_free_consistent(lp->pci_dev,
370 sizeof(struct amd8111e_rx_dr)*NUM_RX_RING_DR,lp->rx_ring,
371 lp->rx_ring_dma_addr);
372
373 err_free_tx_ring:
374
375 pci_free_consistent(lp->pci_dev,
376 sizeof(struct amd8111e_tx_dr)*NUM_TX_RING_DR,lp->tx_ring,
377 lp->tx_ring_dma_addr);
378
379 err_no_mem:
380 return -ENOMEM;
381 }
382 /* This function will set the interrupt coalescing according to the input arguments */
383 static int amd8111e_set_coalesce(struct net_device * dev, enum coal_mode cmod)
384 {
385 unsigned int timeout;
386 unsigned int event_count;
387
388 struct amd8111e_priv *lp = netdev_priv(dev);
389 void __iomem *mmio = lp->mmio;
390 struct amd8111e_coalesce_conf * coal_conf = &lp->coal_conf;
391
392
393 switch(cmod)
394 {
395 case RX_INTR_COAL :
396 timeout = coal_conf->rx_timeout;
397 event_count = coal_conf->rx_event_count;
398 if( timeout > MAX_TIMEOUT ||
399 event_count > MAX_EVENT_COUNT )
400 return -EINVAL;
401
402 timeout = timeout * DELAY_TIMER_CONV;
403 writel(VAL0|STINTEN, mmio+INTEN0);
404 writel((u32)DLY_INT_A_R0|( event_count<< 16 )|timeout,
405 mmio+DLY_INT_A);
406 break;
407
408 case TX_INTR_COAL :
409 timeout = coal_conf->tx_timeout;
410 event_count = coal_conf->tx_event_count;
411 if( timeout > MAX_TIMEOUT ||
412 event_count > MAX_EVENT_COUNT )
413 return -EINVAL;
414
415
416 timeout = timeout * DELAY_TIMER_CONV;
417 writel(VAL0|STINTEN,mmio+INTEN0);
418 writel((u32)DLY_INT_B_T0|( event_count<< 16 )|timeout,
419 mmio+DLY_INT_B);
420 break;
421
422 case DISABLE_COAL:
423 writel(0,mmio+STVAL);
424 writel(STINTEN, mmio+INTEN0);
425 writel(0, mmio +DLY_INT_B);
426 writel(0, mmio+DLY_INT_A);
427 break;
428 case ENABLE_COAL:
429 /* Start the timer */
430 writel((u32)SOFT_TIMER_FREQ, mmio+STVAL); /* 0.5 sec */
431 writel(VAL0|STINTEN, mmio+INTEN0);
432 break;
433 default:
434 break;
435
436 }
437 return 0;
438
439 }
440
441 /*
442 This function initializes the device registers and starts the device.
443 */
444 static int amd8111e_restart(struct net_device *dev)
445 {
446 struct amd8111e_priv *lp = netdev_priv(dev);
447 void __iomem *mmio = lp->mmio;
448 int i,reg_val;
449
450 /* stop the chip */
451 writel(RUN, mmio + CMD0);
452
453 if(amd8111e_init_ring(dev))
454 return -ENOMEM;
455
456 /* enable the port manager and set auto negotiation always */
457 writel((u32) VAL1|EN_PMGR, mmio + CMD3 );
458 writel((u32)XPHYANE|XPHYRST , mmio + CTRL2);
459
460 amd8111e_set_ext_phy(dev);
461
462 /* set control registers */
463 reg_val = readl(mmio + CTRL1);
464 reg_val &= ~XMTSP_MASK;
465 writel( reg_val| XMTSP_128 | CACHE_ALIGN, mmio + CTRL1 );
466
467 /* enable interrupt */
468 writel( APINT5EN | APINT4EN | APINT3EN | APINT2EN | APINT1EN |
469 APINT0EN | MIIPDTINTEN | MCCIINTEN | MCCINTEN | MREINTEN |
470 SPNDINTEN | MPINTEN | SINTEN | STINTEN, mmio + INTEN0);
471
472 writel(VAL3 | LCINTEN | VAL1 | TINTEN0 | VAL0 | RINTEN0, mmio + INTEN0);
473
474 /* initialize tx and rx ring base addresses */
475 writel((u32)lp->tx_ring_dma_addr,mmio + XMT_RING_BASE_ADDR0);
476 writel((u32)lp->rx_ring_dma_addr,mmio+ RCV_RING_BASE_ADDR0);
477
478 writew((u32)NUM_TX_RING_DR, mmio + XMT_RING_LEN0);
479 writew((u16)NUM_RX_RING_DR, mmio + RCV_RING_LEN0);
480
481 /* set default IPG to 96 */
482 writew((u32)DEFAULT_IPG,mmio+IPG);
483 writew((u32)(DEFAULT_IPG-IFS1_DELTA), mmio + IFS1);
484
485 if(lp->options & OPTION_JUMBO_ENABLE){
486 writel((u32)VAL2|JUMBO, mmio + CMD3);
487 /* Reset REX_UFLO */
488 writel( REX_UFLO, mmio + CMD2);
489 /* Should not set REX_UFLO for jumbo frames */
490 writel( VAL0 | APAD_XMT|REX_RTRY , mmio + CMD2);
491 }else{
492 writel( VAL0 | APAD_XMT | REX_RTRY|REX_UFLO, mmio + CMD2);
493 writel((u32)JUMBO, mmio + CMD3);
494 }
495
496 #if AMD8111E_VLAN_TAG_USED
497 writel((u32) VAL2|VSIZE|VL_TAG_DEL, mmio + CMD3);
498 #endif
499 writel( VAL0 | APAD_XMT | REX_RTRY, mmio + CMD2 );
500
501 /* Setting the MAC address to the device */
502 for(i = 0; i < ETH_ADDR_LEN; i++)
503 writeb( dev->dev_addr[i], mmio + PADR + i );
504
505 /* Enable interrupt coalesce */
506 if(lp->options & OPTION_INTR_COAL_ENABLE){
507 printk(KERN_INFO "%s: Interrupt Coalescing Enabled.\n",
508 dev->name);
509 amd8111e_set_coalesce(dev,ENABLE_COAL);
510 }
511
512 /* set RUN bit to start the chip */
513 writel(VAL2 | RDMD0, mmio + CMD0);
514 writel(VAL0 | INTREN | RUN, mmio + CMD0);
515
516 /* To avoid PCI posting bug */
517 readl(mmio+CMD0);
518 return 0;
519 }
520 /*
521 This function clears necessary the device registers.
522 */
523 static void amd8111e_init_hw_default( struct amd8111e_priv* lp)
524 {
525 unsigned int reg_val;
526 unsigned int logic_filter[2] ={0,};
527 void __iomem *mmio = lp->mmio;
528
529
530 /* stop the chip */
531 writel(RUN, mmio + CMD0);
532
533 /* AUTOPOLL0 Register *//*TBD default value is 8100 in FPS */
534 writew( 0x8100 | lp->ext_phy_addr, mmio + AUTOPOLL0);
535
536 /* Clear RCV_RING_BASE_ADDR */
537 writel(0, mmio + RCV_RING_BASE_ADDR0);
538
539 /* Clear XMT_RING_BASE_ADDR */
540 writel(0, mmio + XMT_RING_BASE_ADDR0);
541 writel(0, mmio + XMT_RING_BASE_ADDR1);
542 writel(0, mmio + XMT_RING_BASE_ADDR2);
543 writel(0, mmio + XMT_RING_BASE_ADDR3);
544
545 /* Clear CMD0 */
546 writel(CMD0_CLEAR,mmio + CMD0);
547
548 /* Clear CMD2 */
549 writel(CMD2_CLEAR, mmio +CMD2);
550
551 /* Clear CMD7 */
552 writel(CMD7_CLEAR , mmio + CMD7);
553
554 /* Clear DLY_INT_A and DLY_INT_B */
555 writel(0x0, mmio + DLY_INT_A);
556 writel(0x0, mmio + DLY_INT_B);
557
558 /* Clear FLOW_CONTROL */
559 writel(0x0, mmio + FLOW_CONTROL);
560
561 /* Clear INT0 write 1 to clear register */
562 reg_val = readl(mmio + INT0);
563 writel(reg_val, mmio + INT0);
564
565 /* Clear STVAL */
566 writel(0x0, mmio + STVAL);
567
568 /* Clear INTEN0 */
569 writel( INTEN0_CLEAR, mmio + INTEN0);
570
571 /* Clear LADRF */
572 writel(0x0 , mmio + LADRF);
573
574 /* Set SRAM_SIZE & SRAM_BOUNDARY registers */
575 writel( 0x80010,mmio + SRAM_SIZE);
576
577 /* Clear RCV_RING0_LEN */
578 writel(0x0, mmio + RCV_RING_LEN0);
579
580 /* Clear XMT_RING0/1/2/3_LEN */
581 writel(0x0, mmio + XMT_RING_LEN0);
582 writel(0x0, mmio + XMT_RING_LEN1);
583 writel(0x0, mmio + XMT_RING_LEN2);
584 writel(0x0, mmio + XMT_RING_LEN3);
585
586 /* Clear XMT_RING_LIMIT */
587 writel(0x0, mmio + XMT_RING_LIMIT);
588
589 /* Clear MIB */
590 writew(MIB_CLEAR, mmio + MIB_ADDR);
591
592 /* Clear LARF */
593 amd8111e_writeq(*(u64*)logic_filter,mmio+LADRF);
594
595 /* SRAM_SIZE register */
596 reg_val = readl(mmio + SRAM_SIZE);
597
598 if(lp->options & OPTION_JUMBO_ENABLE)
599 writel( VAL2|JUMBO, mmio + CMD3);
600 #if AMD8111E_VLAN_TAG_USED
601 writel(VAL2|VSIZE|VL_TAG_DEL, mmio + CMD3 );
602 #endif
603 /* Set default value to CTRL1 Register */
604 writel(CTRL1_DEFAULT, mmio + CTRL1);
605
606 /* To avoid PCI posting bug */
607 readl(mmio + CMD2);
608
609 }
610
611 /*
612 This function disables the interrupt and clears all the pending
613 interrupts in INT0
614 */
615 static void amd8111e_disable_interrupt(struct amd8111e_priv* lp)
616 {
617 u32 intr0;
618
619 /* Disable interrupt */
620 writel(INTREN, lp->mmio + CMD0);
621
622 /* Clear INT0 */
623 intr0 = readl(lp->mmio + INT0);
624 writel(intr0, lp->mmio + INT0);
625
626 /* To avoid PCI posting bug */
627 readl(lp->mmio + INT0);
628
629 }
630
631 /*
632 This function stops the chip.
633 */
634 static void amd8111e_stop_chip(struct amd8111e_priv* lp)
635 {
636 writel(RUN, lp->mmio + CMD0);
637
638 /* To avoid PCI posting bug */
639 readl(lp->mmio + CMD0);
640 }
641
642 /*
643 This function frees the transmiter and receiver descriptor rings.
644 */
645 static void amd8111e_free_ring(struct amd8111e_priv* lp)
646 {
647
648 /* Free transmit and receive skbs */
649 amd8111e_free_skbs(lp->amd8111e_net_dev);
650
651 /* Free transmit and receive descriptor rings */
652 if(lp->rx_ring){
653 pci_free_consistent(lp->pci_dev,
654 sizeof(struct amd8111e_rx_dr)*NUM_RX_RING_DR,
655 lp->rx_ring, lp->rx_ring_dma_addr);
656 lp->rx_ring = NULL;
657 }
658
659 if(lp->tx_ring){
660 pci_free_consistent(lp->pci_dev,
661 sizeof(struct amd8111e_tx_dr)*NUM_TX_RING_DR,
662 lp->tx_ring, lp->tx_ring_dma_addr);
663
664 lp->tx_ring = NULL;
665 }
666
667 }
668 #if AMD8111E_VLAN_TAG_USED
669 /*
670 This is the receive indication function for packets with vlan tag.
671 */
672 static int amd8111e_vlan_rx(struct amd8111e_priv *lp, struct sk_buff *skb, u16 vlan_tag)
673 {
674 #ifdef CONFIG_AMD8111E_NAPI
675 return vlan_hwaccel_receive_skb(skb, lp->vlgrp,vlan_tag);
676 #else
677 return vlan_hwaccel_rx(skb, lp->vlgrp, vlan_tag);
678 #endif /* CONFIG_AMD8111E_NAPI */
679 }
680 #endif
681
682 /*
683 This function will free all the transmit skbs that are actually transmitted by the device. It will check the ownership of the skb before freeing the skb.
684 */
685 static int amd8111e_tx(struct net_device *dev)
686 {
687 struct amd8111e_priv* lp = netdev_priv(dev);
688 int tx_index = lp->tx_complete_idx & TX_RING_DR_MOD_MASK;
689 int status;
690 /* Complete all the transmit packet */
691 while (lp->tx_complete_idx != lp->tx_idx){
692 tx_index = lp->tx_complete_idx & TX_RING_DR_MOD_MASK;
693 status = le16_to_cpu(lp->tx_ring[tx_index].tx_flags);
694
695 if(status & OWN_BIT)
696 break; /* It still hasn't been Txed */
697
698 lp->tx_ring[tx_index].buff_phy_addr = 0;
699
700 /* We must free the original skb */
701 if (lp->tx_skbuff[tx_index]) {
702 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[tx_index],
703 lp->tx_skbuff[tx_index]->len,
704 PCI_DMA_TODEVICE);
705 dev_kfree_skb_irq (lp->tx_skbuff[tx_index]);
706 lp->tx_skbuff[tx_index] = NULL;
707 lp->tx_dma_addr[tx_index] = 0;
708 }
709 lp->tx_complete_idx++;
710 /*COAL update tx coalescing parameters */
711 lp->coal_conf.tx_packets++;
712 lp->coal_conf.tx_bytes += lp->tx_ring[tx_index].buff_count;
713
714 if (netif_queue_stopped(dev) &&
715 lp->tx_complete_idx > lp->tx_idx - NUM_TX_BUFFERS +2){
716 /* The ring is no longer full, clear tbusy. */
717 /* lp->tx_full = 0; */
718 netif_wake_queue (dev);
719 }
720 }
721 return 0;
722 }
723
724 #ifdef CONFIG_AMD8111E_NAPI
725 /* This function handles the driver receive operation in polling mode */
726 static int amd8111e_rx_poll(struct net_device *dev, int * budget)
727 {
728 struct amd8111e_priv *lp = netdev_priv(dev);
729 int rx_index = lp->rx_idx & RX_RING_DR_MOD_MASK;
730 void __iomem *mmio = lp->mmio;
731 struct sk_buff *skb,*new_skb;
732 int min_pkt_len, status;
733 unsigned int intr0;
734 int num_rx_pkt = 0;
735 /*int max_rx_pkt = NUM_RX_BUFFERS;*/
736 short pkt_len;
737 #if AMD8111E_VLAN_TAG_USED
738 short vtag;
739 #endif
740 int rx_pkt_limit = dev->quota;
741
742 do{
743 /* process receive packets until we use the quota*/
744 /* If we own the next entry, it's a new packet. Send it up. */
745 while(1) {
746 status = le16_to_cpu(lp->rx_ring[rx_index].rx_flags);
747 if (status & OWN_BIT)
748 break;
749
750 /*
751 * There is a tricky error noted by John Murphy,
752 * <murf@perftech.com> to Russ Nelson: Even with
753 * full-sized * buffers it's possible for a
754 * jabber packet to use two buffers, with only
755 * the last correctly noting the error.
756 */
757
758 if(status & ERR_BIT) {
759 /* reseting flags */
760 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
761 goto err_next_pkt;
762 }
763 /* check for STP and ENP */
764 if(!((status & STP_BIT) && (status & ENP_BIT))){
765 /* reseting flags */
766 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
767 goto err_next_pkt;
768 }
769 pkt_len = le16_to_cpu(lp->rx_ring[rx_index].msg_count) - 4;
770
771 #if AMD8111E_VLAN_TAG_USED
772 vtag = status & TT_MASK;
773 /*MAC will strip vlan tag*/
774 if(lp->vlgrp != NULL && vtag !=0)
775 min_pkt_len =MIN_PKT_LEN - 4;
776 else
777 #endif
778 min_pkt_len =MIN_PKT_LEN;
779
780 if (pkt_len < min_pkt_len) {
781 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
782 lp->drv_rx_errors++;
783 goto err_next_pkt;
784 }
785 if(--rx_pkt_limit < 0)
786 goto rx_not_empty;
787 if(!(new_skb = dev_alloc_skb(lp->rx_buff_len))){
788 /* if allocation fail,
789 ignore that pkt and go to next one */
790 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
791 lp->drv_rx_errors++;
792 goto err_next_pkt;
793 }
794
795 skb_reserve(new_skb, 2);
796 skb = lp->rx_skbuff[rx_index];
797 pci_unmap_single(lp->pci_dev,lp->rx_dma_addr[rx_index],
798 lp->rx_buff_len-2, PCI_DMA_FROMDEVICE);
799 skb_put(skb, pkt_len);
800 skb->dev = dev;
801 lp->rx_skbuff[rx_index] = new_skb;
802 new_skb->dev = dev;
803 lp->rx_dma_addr[rx_index] = pci_map_single(lp->pci_dev,
804 new_skb->data,
805 lp->rx_buff_len-2,
806 PCI_DMA_FROMDEVICE);
807
808 skb->protocol = eth_type_trans(skb, dev);
809
810 #if AMD8111E_VLAN_TAG_USED
811 if(lp->vlgrp != NULL && (vtag == TT_VLAN_TAGGED)){
812 amd8111e_vlan_rx(lp, skb,
813 le16_to_cpu(lp->rx_ring[rx_index].tag_ctrl_info));
814 } else
815 #endif
816 netif_receive_skb(skb);
817 /*COAL update rx coalescing parameters*/
818 lp->coal_conf.rx_packets++;
819 lp->coal_conf.rx_bytes += pkt_len;
820 num_rx_pkt++;
821 dev->last_rx = jiffies;
822
823 err_next_pkt:
824 lp->rx_ring[rx_index].buff_phy_addr
825 = cpu_to_le32(lp->rx_dma_addr[rx_index]);
826 lp->rx_ring[rx_index].buff_count =
827 cpu_to_le16(lp->rx_buff_len-2);
828 wmb();
829 lp->rx_ring[rx_index].rx_flags |= cpu_to_le16(OWN_BIT);
830 rx_index = (++lp->rx_idx) & RX_RING_DR_MOD_MASK;
831 }
832 /* Check the interrupt status register for more packets in the
833 mean time. Process them since we have not used up our quota.*/
834
835 intr0 = readl(mmio + INT0);
836 /*Ack receive packets */
837 writel(intr0 & RINT0,mmio + INT0);
838
839 } while(intr0 & RINT0);
840
841 /* Receive descriptor is empty now */
842 dev->quota -= num_rx_pkt;
843 *budget -= num_rx_pkt;
844 netif_rx_complete(dev);
845 /* enable receive interrupt */
846 writel(VAL0|RINTEN0, mmio + INTEN0);
847 writel(VAL2 | RDMD0, mmio + CMD0);
848 return 0;
849 rx_not_empty:
850 /* Do not call a netif_rx_complete */
851 dev->quota -= num_rx_pkt;
852 *budget -= num_rx_pkt;
853 return 1;
854
855
856 }
857
858 #else
859 /*
860 This function will check the ownership of receive buffers and descriptors. It will indicate to kernel up to half the number of maximum receive buffers in the descriptor ring, in a single receive interrupt. It will also replenish the descriptors with new skbs.
861 */
862 static int amd8111e_rx(struct net_device *dev)
863 {
864 struct amd8111e_priv *lp = netdev_priv(dev);
865 struct sk_buff *skb,*new_skb;
866 int rx_index = lp->rx_idx & RX_RING_DR_MOD_MASK;
867 int min_pkt_len, status;
868 int num_rx_pkt = 0;
869 int max_rx_pkt = NUM_RX_BUFFERS;
870 short pkt_len;
871 #if AMD8111E_VLAN_TAG_USED
872 short vtag;
873 #endif
874
875 /* If we own the next entry, it's a new packet. Send it up. */
876 while(++num_rx_pkt <= max_rx_pkt){
877 status = le16_to_cpu(lp->rx_ring[rx_index].rx_flags);
878 if(status & OWN_BIT)
879 return 0;
880
881 /* check if err summary bit is set */
882 if(status & ERR_BIT){
883 /*
884 * There is a tricky error noted by John Murphy,
885 * <murf@perftech.com> to Russ Nelson: Even with full-sized
886 * buffers it's possible for a jabber packet to use two
887 * buffers, with only the last correctly noting the error. */
888 /* reseting flags */
889 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
890 goto err_next_pkt;
891 }
892 /* check for STP and ENP */
893 if(!((status & STP_BIT) && (status & ENP_BIT))){
894 /* reseting flags */
895 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
896 goto err_next_pkt;
897 }
898 pkt_len = le16_to_cpu(lp->rx_ring[rx_index].msg_count) - 4;
899
900 #if AMD8111E_VLAN_TAG_USED
901 vtag = status & TT_MASK;
902 /*MAC will strip vlan tag*/
903 if(lp->vlgrp != NULL && vtag !=0)
904 min_pkt_len =MIN_PKT_LEN - 4;
905 else
906 #endif
907 min_pkt_len =MIN_PKT_LEN;
908
909 if (pkt_len < min_pkt_len) {
910 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
911 lp->drv_rx_errors++;
912 goto err_next_pkt;
913 }
914 if(!(new_skb = dev_alloc_skb(lp->rx_buff_len))){
915 /* if allocation fail,
916 ignore that pkt and go to next one */
917 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
918 lp->drv_rx_errors++;
919 goto err_next_pkt;
920 }
921
922 skb_reserve(new_skb, 2);
923 skb = lp->rx_skbuff[rx_index];
924 pci_unmap_single(lp->pci_dev,lp->rx_dma_addr[rx_index],
925 lp->rx_buff_len-2, PCI_DMA_FROMDEVICE);
926 skb_put(skb, pkt_len);
927 skb->dev = dev;
928 lp->rx_skbuff[rx_index] = new_skb;
929 new_skb->dev = dev;
930 lp->rx_dma_addr[rx_index] = pci_map_single(lp->pci_dev,
931 new_skb->data, lp->rx_buff_len-2,PCI_DMA_FROMDEVICE);
932
933 skb->protocol = eth_type_trans(skb, dev);
934
935 #if AMD8111E_VLAN_TAG_USED
936 if(lp->vlgrp != NULL && (vtag == TT_VLAN_TAGGED)){
937 amd8111e_vlan_rx(lp, skb,
938 le16_to_cpu(lp->rx_ring[rx_index].tag_ctrl_info));
939 } else
940 #endif
941
942 netif_rx (skb);
943 /*COAL update rx coalescing parameters*/
944 lp->coal_conf.rx_packets++;
945 lp->coal_conf.rx_bytes += pkt_len;
946
947 dev->last_rx = jiffies;
948
949 err_next_pkt:
950 lp->rx_ring[rx_index].buff_phy_addr
951 = cpu_to_le32(lp->rx_dma_addr[rx_index]);
952 lp->rx_ring[rx_index].buff_count =
953 cpu_to_le16(lp->rx_buff_len-2);
954 wmb();
955 lp->rx_ring[rx_index].rx_flags |= cpu_to_le16(OWN_BIT);
956 rx_index = (++lp->rx_idx) & RX_RING_DR_MOD_MASK;
957 }
958
959 return 0;
960 }
961 #endif /* CONFIG_AMD8111E_NAPI */
962 /*
963 This function will indicate the link status to the kernel.
964 */
965 static int amd8111e_link_change(struct net_device* dev)
966 {
967 struct amd8111e_priv *lp = netdev_priv(dev);
968 int status0,speed;
969
970 /* read the link change */
971 status0 = readl(lp->mmio + STAT0);
972
973 if(status0 & LINK_STATS){
974 if(status0 & AUTONEG_COMPLETE)
975 lp->link_config.autoneg = AUTONEG_ENABLE;
976 else
977 lp->link_config.autoneg = AUTONEG_DISABLE;
978
979 if(status0 & FULL_DPLX)
980 lp->link_config.duplex = DUPLEX_FULL;
981 else
982 lp->link_config.duplex = DUPLEX_HALF;
983 speed = (status0 & SPEED_MASK) >> 7;
984 if(speed == PHY_SPEED_10)
985 lp->link_config.speed = SPEED_10;
986 else if(speed == PHY_SPEED_100)
987 lp->link_config.speed = SPEED_100;
988
989 printk(KERN_INFO "%s: Link is Up. Speed is %s Mbps %s Duplex\n", dev->name,
990 (lp->link_config.speed == SPEED_100) ? "100": "10",
991 (lp->link_config.duplex == DUPLEX_FULL)? "Full": "Half");
992 netif_carrier_on(dev);
993 }
994 else{
995 lp->link_config.speed = SPEED_INVALID;
996 lp->link_config.duplex = DUPLEX_INVALID;
997 lp->link_config.autoneg = AUTONEG_INVALID;
998 printk(KERN_INFO "%s: Link is Down.\n",dev->name);
999 netif_carrier_off(dev);
1000 }
1001
1002 return 0;
1003 }
1004 /*
1005 This function reads the mib counters.
1006 */
1007 static int amd8111e_read_mib(void __iomem *mmio, u8 MIB_COUNTER)
1008 {
1009 unsigned int status;
1010 unsigned int data;
1011 unsigned int repeat = REPEAT_CNT;
1012
1013 writew( MIB_RD_CMD | MIB_COUNTER, mmio + MIB_ADDR);
1014 do {
1015 status = readw(mmio + MIB_ADDR);
1016 udelay(2); /* controller takes MAX 2 us to get mib data */
1017 }
1018 while (--repeat && (status & MIB_CMD_ACTIVE));
1019
1020 data = readl(mmio + MIB_DATA);
1021 return data;
1022 }
1023
1024 /*
1025 This function reads the mib registers and returns the hardware statistics. It updates previous internal driver statistics with new values.
1026 */
1027 static struct net_device_stats *amd8111e_get_stats(struct net_device * dev)
1028 {
1029 struct amd8111e_priv *lp = netdev_priv(dev);
1030 void __iomem *mmio = lp->mmio;
1031 unsigned long flags;
1032 /* struct net_device_stats *prev_stats = &lp->prev_stats; */
1033 struct net_device_stats* new_stats = &lp->stats;
1034
1035 if(!lp->opened)
1036 return &lp->stats;
1037 spin_lock_irqsave (&lp->lock, flags);
1038
1039 /* stats.rx_packets */
1040 new_stats->rx_packets = amd8111e_read_mib(mmio, rcv_broadcast_pkts)+
1041 amd8111e_read_mib(mmio, rcv_multicast_pkts)+
1042 amd8111e_read_mib(mmio, rcv_unicast_pkts);
1043
1044 /* stats.tx_packets */
1045 new_stats->tx_packets = amd8111e_read_mib(mmio, xmt_packets);
1046
1047 /*stats.rx_bytes */
1048 new_stats->rx_bytes = amd8111e_read_mib(mmio, rcv_octets);
1049
1050 /* stats.tx_bytes */
1051 new_stats->tx_bytes = amd8111e_read_mib(mmio, xmt_octets);
1052
1053 /* stats.rx_errors */
1054 /* hw errors + errors driver reported */
1055 new_stats->rx_errors = amd8111e_read_mib(mmio, rcv_undersize_pkts)+
1056 amd8111e_read_mib(mmio, rcv_fragments)+
1057 amd8111e_read_mib(mmio, rcv_jabbers)+
1058 amd8111e_read_mib(mmio, rcv_alignment_errors)+
1059 amd8111e_read_mib(mmio, rcv_fcs_errors)+
1060 amd8111e_read_mib(mmio, rcv_miss_pkts)+
1061 lp->drv_rx_errors;
1062
1063 /* stats.tx_errors */
1064 new_stats->tx_errors = amd8111e_read_mib(mmio, xmt_underrun_pkts);
1065
1066 /* stats.rx_dropped*/
1067 new_stats->rx_dropped = amd8111e_read_mib(mmio, rcv_miss_pkts);
1068
1069 /* stats.tx_dropped*/
1070 new_stats->tx_dropped = amd8111e_read_mib(mmio, xmt_underrun_pkts);
1071
1072 /* stats.multicast*/
1073 new_stats->multicast = amd8111e_read_mib(mmio, rcv_multicast_pkts);
1074
1075 /* stats.collisions*/
1076 new_stats->collisions = amd8111e_read_mib(mmio, xmt_collisions);
1077
1078 /* stats.rx_length_errors*/
1079 new_stats->rx_length_errors =
1080 amd8111e_read_mib(mmio, rcv_undersize_pkts)+
1081 amd8111e_read_mib(mmio, rcv_oversize_pkts);
1082
1083 /* stats.rx_over_errors*/
1084 new_stats->rx_over_errors = amd8111e_read_mib(mmio, rcv_miss_pkts);
1085
1086 /* stats.rx_crc_errors*/
1087 new_stats->rx_crc_errors = amd8111e_read_mib(mmio, rcv_fcs_errors);
1088
1089 /* stats.rx_frame_errors*/
1090 new_stats->rx_frame_errors =
1091 amd8111e_read_mib(mmio, rcv_alignment_errors);
1092
1093 /* stats.rx_fifo_errors */
1094 new_stats->rx_fifo_errors = amd8111e_read_mib(mmio, rcv_miss_pkts);
1095
1096 /* stats.rx_missed_errors */
1097 new_stats->rx_missed_errors = amd8111e_read_mib(mmio, rcv_miss_pkts);
1098
1099 /* stats.tx_aborted_errors*/
1100 new_stats->tx_aborted_errors =
1101 amd8111e_read_mib(mmio, xmt_excessive_collision);
1102
1103 /* stats.tx_carrier_errors*/
1104 new_stats->tx_carrier_errors =
1105 amd8111e_read_mib(mmio, xmt_loss_carrier);
1106
1107 /* stats.tx_fifo_errors*/
1108 new_stats->tx_fifo_errors = amd8111e_read_mib(mmio, xmt_underrun_pkts);
1109
1110 /* stats.tx_window_errors*/
1111 new_stats->tx_window_errors =
1112 amd8111e_read_mib(mmio, xmt_late_collision);
1113
1114 /* Reset the mibs for collecting new statistics */
1115 /* writew(MIB_CLEAR, mmio + MIB_ADDR);*/
1116
1117 spin_unlock_irqrestore (&lp->lock, flags);
1118
1119 return new_stats;
1120 }
1121 /* This function recalculate the interupt coalescing mode on every interrupt
1122 according to the datarate and the packet rate.
1123 */
1124 static int amd8111e_calc_coalesce(struct net_device *dev)
1125 {
1126 struct amd8111e_priv *lp = netdev_priv(dev);
1127 struct amd8111e_coalesce_conf * coal_conf = &lp->coal_conf;
1128 int tx_pkt_rate;
1129 int rx_pkt_rate;
1130 int tx_data_rate;
1131 int rx_data_rate;
1132 int rx_pkt_size;
1133 int tx_pkt_size;
1134
1135 tx_pkt_rate = coal_conf->tx_packets - coal_conf->tx_prev_packets;
1136 coal_conf->tx_prev_packets = coal_conf->tx_packets;
1137
1138 tx_data_rate = coal_conf->tx_bytes - coal_conf->tx_prev_bytes;
1139 coal_conf->tx_prev_bytes = coal_conf->tx_bytes;
1140
1141 rx_pkt_rate = coal_conf->rx_packets - coal_conf->rx_prev_packets;
1142 coal_conf->rx_prev_packets = coal_conf->rx_packets;
1143
1144 rx_data_rate = coal_conf->rx_bytes - coal_conf->rx_prev_bytes;
1145 coal_conf->rx_prev_bytes = coal_conf->rx_bytes;
1146
1147 if(rx_pkt_rate < 800){
1148 if(coal_conf->rx_coal_type != NO_COALESCE){
1149
1150 coal_conf->rx_timeout = 0x0;
1151 coal_conf->rx_event_count = 0;
1152 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1153 coal_conf->rx_coal_type = NO_COALESCE;
1154 }
1155 }
1156 else{
1157
1158 rx_pkt_size = rx_data_rate/rx_pkt_rate;
1159 if (rx_pkt_size < 128){
1160 if(coal_conf->rx_coal_type != NO_COALESCE){
1161
1162 coal_conf->rx_timeout = 0;
1163 coal_conf->rx_event_count = 0;
1164 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1165 coal_conf->rx_coal_type = NO_COALESCE;
1166 }
1167
1168 }
1169 else if ( (rx_pkt_size >= 128) && (rx_pkt_size < 512) ){
1170
1171 if(coal_conf->rx_coal_type != LOW_COALESCE){
1172 coal_conf->rx_timeout = 1;
1173 coal_conf->rx_event_count = 4;
1174 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1175 coal_conf->rx_coal_type = LOW_COALESCE;
1176 }
1177 }
1178 else if ((rx_pkt_size >= 512) && (rx_pkt_size < 1024)){
1179
1180 if(coal_conf->rx_coal_type != MEDIUM_COALESCE){
1181 coal_conf->rx_timeout = 1;
1182 coal_conf->rx_event_count = 4;
1183 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1184 coal_conf->rx_coal_type = MEDIUM_COALESCE;
1185 }
1186
1187 }
1188 else if(rx_pkt_size >= 1024){
1189 if(coal_conf->rx_coal_type != HIGH_COALESCE){
1190 coal_conf->rx_timeout = 2;
1191 coal_conf->rx_event_count = 3;
1192 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1193 coal_conf->rx_coal_type = HIGH_COALESCE;
1194 }
1195 }
1196 }
1197 /* NOW FOR TX INTR COALESC */
1198 if(tx_pkt_rate < 800){
1199 if(coal_conf->tx_coal_type != NO_COALESCE){
1200
1201 coal_conf->tx_timeout = 0x0;
1202 coal_conf->tx_event_count = 0;
1203 amd8111e_set_coalesce(dev,TX_INTR_COAL);
1204 coal_conf->tx_coal_type = NO_COALESCE;
1205 }
1206 }
1207 else{
1208
1209 tx_pkt_size = tx_data_rate/tx_pkt_rate;
1210 if (tx_pkt_size < 128){
1211
1212 if(coal_conf->tx_coal_type != NO_COALESCE){
1213
1214 coal_conf->tx_timeout = 0;
1215 coal_conf->tx_event_count = 0;
1216 amd8111e_set_coalesce(dev,TX_INTR_COAL);
1217 coal_conf->tx_coal_type = NO_COALESCE;
1218 }
1219
1220 }
1221 else if ( (tx_pkt_size >= 128) && (tx_pkt_size < 512) ){
1222
1223 if(coal_conf->tx_coal_type != LOW_COALESCE){
1224 coal_conf->tx_timeout = 1;
1225 coal_conf->tx_event_count = 2;
1226 amd8111e_set_coalesce(dev,TX_INTR_COAL);
1227 coal_conf->tx_coal_type = LOW_COALESCE;
1228
1229 }
1230 }
1231 else if ((tx_pkt_size >= 512) && (tx_pkt_size < 1024)){
1232
1233 if(coal_conf->tx_coal_type != MEDIUM_COALESCE){
1234 coal_conf->tx_timeout = 2;
1235 coal_conf->tx_event_count = 5;
1236 amd8111e_set_coalesce(dev,TX_INTR_COAL);
1237 coal_conf->tx_coal_type = MEDIUM_COALESCE;
1238 }
1239
1240 }
1241 else if(tx_pkt_size >= 1024){
1242 if (tx_pkt_size >= 1024){
1243 if(coal_conf->tx_coal_type != HIGH_COALESCE){
1244 coal_conf->tx_timeout = 4;
1245 coal_conf->tx_event_count = 8;
1246 amd8111e_set_coalesce(dev,TX_INTR_COAL);
1247 coal_conf->tx_coal_type = HIGH_COALESCE;
1248 }
1249 }
1250 }
1251 }
1252 return 0;
1253
1254 }
1255 /*
1256 This is device interrupt function. It handles transmit, receive,link change and hardware timer interrupts.
1257 */
1258 static irqreturn_t amd8111e_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1259 {
1260
1261 struct net_device * dev = (struct net_device *) dev_id;
1262 struct amd8111e_priv *lp = netdev_priv(dev);
1263 void __iomem *mmio = lp->mmio;
1264 unsigned int intr0;
1265 unsigned int handled = 1;
1266
1267 if(dev == NULL)
1268 return IRQ_NONE;
1269
1270 if (regs) spin_lock (&lp->lock);
1271 /* disabling interrupt */
1272 writel(INTREN, mmio + CMD0);
1273
1274 /* Read interrupt status */
1275 intr0 = readl(mmio + INT0);
1276
1277 /* Process all the INT event until INTR bit is clear. */
1278
1279 if (!(intr0 & INTR)){
1280 handled = 0;
1281 goto err_no_interrupt;
1282 }
1283
1284 /* Current driver processes 4 interrupts : RINT,TINT,LCINT,STINT */
1285 writel(intr0, mmio + INT0);
1286
1287 /* Check if Receive Interrupt has occurred. */
1288 #if CONFIG_AMD8111E_NAPI
1289 if(intr0 & RINT0){
1290 if(netif_rx_schedule_prep(dev)){
1291 /* Disable receive interupts */
1292 writel(RINTEN0, mmio + INTEN0);
1293 /* Schedule a polling routine */
1294 __netif_rx_schedule(dev);
1295 }
1296 else {
1297 printk("************Driver bug! \
1298 interrupt while in poll\n");
1299 /* Fix by disabling interrupts */
1300 writel(RINT0, mmio + INT0);
1301 }
1302 }
1303 #else
1304 if(intr0 & RINT0){
1305 amd8111e_rx(dev);
1306 writel(VAL2 | RDMD0, mmio + CMD0);
1307 }
1308 #endif /* CONFIG_AMD8111E_NAPI */
1309 /* Check if Transmit Interrupt has occurred. */
1310 if(intr0 & TINT0)
1311 amd8111e_tx(dev);
1312
1313 /* Check if Link Change Interrupt has occurred. */
1314 if (intr0 & LCINT)
1315 amd8111e_link_change(dev);
1316
1317 /* Check if Hardware Timer Interrupt has occurred. */
1318 if (intr0 & STINT)
1319 amd8111e_calc_coalesce(dev);
1320
1321 err_no_interrupt:
1322 writel( VAL0 | INTREN,mmio + CMD0);
1323
1324 if (regs) spin_unlock(&lp->lock);
1325
1326 return IRQ_RETVAL(handled);
1327 }
1328
1329 #ifdef CONFIG_NET_POLL_CONTROLLER
1330 static void amd8111e_poll(struct net_device *dev)
1331 {
1332 unsigned long flags;
1333 local_save_flags(flags);
1334 local_irq_disable();
1335 amd8111e_interrupt(0, dev, NULL);
1336 local_irq_restore(flags);
1337 }
1338 #endif
1339
1340
1341 /*
1342 This function closes the network interface and updates the statistics so that most recent statistics will be available after the interface is down.
1343 */
1344 static int amd8111e_close(struct net_device * dev)
1345 {
1346 struct amd8111e_priv *lp = netdev_priv(dev);
1347 netif_stop_queue(dev);
1348
1349 spin_lock_irq(&lp->lock);
1350
1351 amd8111e_disable_interrupt(lp);
1352 amd8111e_stop_chip(lp);
1353 amd8111e_free_ring(lp);
1354
1355 netif_carrier_off(lp->amd8111e_net_dev);
1356
1357 /* Delete ipg timer */
1358 if(lp->options & OPTION_DYN_IPG_ENABLE)
1359 del_timer_sync(&lp->ipg_data.ipg_timer);
1360
1361 spin_unlock_irq(&lp->lock);
1362 free_irq(dev->irq, dev);
1363
1364 /* Update the statistics before closing */
1365 amd8111e_get_stats(dev);
1366 lp->opened = 0;
1367 return 0;
1368 }
1369 /* This function opens new interface.It requests irq for the device, initializes the device,buffers and descriptors, and starts the device.
1370 */
1371 static int amd8111e_open(struct net_device * dev )
1372 {
1373 struct amd8111e_priv *lp = netdev_priv(dev);
1374
1375 if(dev->irq ==0 || request_irq(dev->irq, amd8111e_interrupt, SA_SHIRQ,
1376 dev->name, dev))
1377 return -EAGAIN;
1378
1379 spin_lock_irq(&lp->lock);
1380
1381 amd8111e_init_hw_default(lp);
1382
1383 if(amd8111e_restart(dev)){
1384 spin_unlock_irq(&lp->lock);
1385 if (dev->irq)
1386 free_irq(dev->irq, dev);
1387 return -ENOMEM;
1388 }
1389 /* Start ipg timer */
1390 if(lp->options & OPTION_DYN_IPG_ENABLE){
1391 add_timer(&lp->ipg_data.ipg_timer);
1392 printk(KERN_INFO "%s: Dynamic IPG Enabled.\n",dev->name);
1393 }
1394
1395 lp->opened = 1;
1396
1397 spin_unlock_irq(&lp->lock);
1398
1399 netif_start_queue(dev);
1400
1401 return 0;
1402 }
1403 /*
1404 This function checks if there is any transmit descriptors available to queue more packet.
1405 */
1406 static int amd8111e_tx_queue_avail(struct amd8111e_priv* lp )
1407 {
1408 int tx_index = lp->tx_idx & TX_BUFF_MOD_MASK;
1409 if(lp->tx_skbuff[tx_index] != 0)
1410 return -1;
1411 else
1412 return 0;
1413
1414 }
1415 /*
1416 This function will queue the transmit packets to the descriptors and will trigger the send operation. It also initializes the transmit descriptors with buffer physical address, byte count, ownership to hardware etc.
1417 */
1418
1419 static int amd8111e_start_xmit(struct sk_buff *skb, struct net_device * dev)
1420 {
1421 struct amd8111e_priv *lp = netdev_priv(dev);
1422 int tx_index;
1423 unsigned long flags;
1424
1425 spin_lock_irqsave(&lp->lock, flags);
1426
1427 tx_index = lp->tx_idx & TX_RING_DR_MOD_MASK;
1428
1429 lp->tx_ring[tx_index].buff_count = cpu_to_le16(skb->len);
1430
1431 lp->tx_skbuff[tx_index] = skb;
1432 lp->tx_ring[tx_index].tx_flags = 0;
1433
1434 #if AMD8111E_VLAN_TAG_USED
1435 if((lp->vlgrp != NULL) && vlan_tx_tag_present(skb)){
1436 lp->tx_ring[tx_index].tag_ctrl_cmd |=
1437 cpu_to_le16(TCC_VLAN_INSERT);
1438 lp->tx_ring[tx_index].tag_ctrl_info =
1439 cpu_to_le16(vlan_tx_tag_get(skb));
1440
1441 }
1442 #endif
1443 lp->tx_dma_addr[tx_index] =
1444 pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
1445 lp->tx_ring[tx_index].buff_phy_addr =
1446 (u32) cpu_to_le32(lp->tx_dma_addr[tx_index]);
1447
1448 /* Set FCS and LTINT bits */
1449 wmb();
1450 lp->tx_ring[tx_index].tx_flags |=
1451 cpu_to_le16(OWN_BIT | STP_BIT | ENP_BIT|ADD_FCS_BIT|LTINT_BIT);
1452
1453 lp->tx_idx++;
1454
1455 /* Trigger an immediate send poll. */
1456 writel( VAL1 | TDMD0, lp->mmio + CMD0);
1457 writel( VAL2 | RDMD0,lp->mmio + CMD0);
1458
1459 dev->trans_start = jiffies;
1460
1461 if(amd8111e_tx_queue_avail(lp) < 0){
1462 netif_stop_queue(dev);
1463 }
1464 spin_unlock_irqrestore(&lp->lock, flags);
1465 return 0;
1466 }
1467 /*
1468 This function returns all the memory mapped registers of the device.
1469 */
1470 static void amd8111e_read_regs(struct amd8111e_priv *lp, u32 *buf)
1471 {
1472 void __iomem *mmio = lp->mmio;
1473 /* Read only necessary registers */
1474 buf[0] = readl(mmio + XMT_RING_BASE_ADDR0);
1475 buf[1] = readl(mmio + XMT_RING_LEN0);
1476 buf[2] = readl(mmio + RCV_RING_BASE_ADDR0);
1477 buf[3] = readl(mmio + RCV_RING_LEN0);
1478 buf[4] = readl(mmio + CMD0);
1479 buf[5] = readl(mmio + CMD2);
1480 buf[6] = readl(mmio + CMD3);
1481 buf[7] = readl(mmio + CMD7);
1482 buf[8] = readl(mmio + INT0);
1483 buf[9] = readl(mmio + INTEN0);
1484 buf[10] = readl(mmio + LADRF);
1485 buf[11] = readl(mmio + LADRF+4);
1486 buf[12] = readl(mmio + STAT0);
1487 }
1488
1489 /*
1490 amd8111e crc generator implementation is different from the kernel
1491 ether_crc() function.
1492 */
1493 static int amd8111e_ether_crc(int len, char* mac_addr)
1494 {
1495 int i,byte;
1496 unsigned char octet;
1497 u32 crc= INITCRC;
1498
1499 for(byte=0; byte < len; byte++){
1500 octet = mac_addr[byte];
1501 for( i=0;i < 8; i++){
1502 /*If the next bit form the input stream is 1,subtract the divisor (CRC32) from the dividend(crc).*/
1503 if( (octet & 0x1) ^ (crc & 0x1) ){
1504 crc >>= 1;
1505 crc ^= CRC32;
1506 }
1507 else
1508 crc >>= 1;
1509
1510 octet >>= 1;
1511 }
1512 }
1513 return crc;
1514 }
1515 /*
1516 This function sets promiscuos mode, all-multi mode or the multicast address
1517 list to the device.
1518 */
1519 static void amd8111e_set_multicast_list(struct net_device *dev)
1520 {
1521 struct dev_mc_list* mc_ptr;
1522 struct amd8111e_priv *lp = netdev_priv(dev);
1523 u32 mc_filter[2] ;
1524 int i,bit_num;
1525 if(dev->flags & IFF_PROMISC){
1526 printk(KERN_INFO "%s: Setting promiscuous mode.\n",dev->name);
1527 writel( VAL2 | PROM, lp->mmio + CMD2);
1528 return;
1529 }
1530 else
1531 writel( PROM, lp->mmio + CMD2);
1532 if(dev->flags & IFF_ALLMULTI || dev->mc_count > MAX_FILTER_SIZE){
1533 /* get all multicast packet */
1534 mc_filter[1] = mc_filter[0] = 0xffffffff;
1535 lp->mc_list = dev->mc_list;
1536 lp->options |= OPTION_MULTICAST_ENABLE;
1537 amd8111e_writeq(*(u64*)mc_filter,lp->mmio + LADRF);
1538 return;
1539 }
1540 if( dev->mc_count == 0 ){
1541 /* get only own packets */
1542 mc_filter[1] = mc_filter[0] = 0;
1543 lp->mc_list = NULL;
1544 lp->options &= ~OPTION_MULTICAST_ENABLE;
1545 amd8111e_writeq(*(u64*)mc_filter,lp->mmio + LADRF);
1546 /* disable promiscous mode */
1547 writel(PROM, lp->mmio + CMD2);
1548 return;
1549 }
1550 /* load all the multicast addresses in the logic filter */
1551 lp->options |= OPTION_MULTICAST_ENABLE;
1552 lp->mc_list = dev->mc_list;
1553 mc_filter[1] = mc_filter[0] = 0;
1554 for (i = 0, mc_ptr = dev->mc_list; mc_ptr && i < dev->mc_count;
1555 i++, mc_ptr = mc_ptr->next) {
1556 bit_num = ( amd8111e_ether_crc(ETH_ALEN,mc_ptr->dmi_addr) >> 26 ) & 0x3f;
1557 mc_filter[bit_num >> 5] |= 1 << (bit_num & 31);
1558 }
1559 amd8111e_writeq(*(u64*)mc_filter,lp->mmio+ LADRF);
1560
1561 /* To eliminate PCI posting bug */
1562 readl(lp->mmio + CMD2);
1563
1564 }
1565
1566 static void amd8111e_get_drvinfo(struct net_device* dev, struct ethtool_drvinfo *info)
1567 {
1568 struct amd8111e_priv *lp = netdev_priv(dev);
1569 struct pci_dev *pci_dev = lp->pci_dev;
1570 strcpy (info->driver, MODULE_NAME);
1571 strcpy (info->version, MODULE_VERS);
1572 sprintf(info->fw_version,"%u",chip_version);
1573 strcpy (info->bus_info, pci_name(pci_dev));
1574 }
1575
1576 static int amd8111e_get_regs_len(struct net_device *dev)
1577 {
1578 return AMD8111E_REG_DUMP_LEN;
1579 }
1580
1581 static void amd8111e_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
1582 {
1583 struct amd8111e_priv *lp = netdev_priv(dev);
1584 regs->version = 0;
1585 amd8111e_read_regs(lp, buf);
1586 }
1587
1588 static int amd8111e_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1589 {
1590 struct amd8111e_priv *lp = netdev_priv(dev);
1591 spin_lock_irq(&lp->lock);
1592 mii_ethtool_gset(&lp->mii_if, ecmd);
1593 spin_unlock_irq(&lp->lock);
1594 return 0;
1595 }
1596
1597 static int amd8111e_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1598 {
1599 struct amd8111e_priv *lp = netdev_priv(dev);
1600 int res;
1601 spin_lock_irq(&lp->lock);
1602 res = mii_ethtool_sset(&lp->mii_if, ecmd);
1603 spin_unlock_irq(&lp->lock);
1604 return res;
1605 }
1606
1607 static int amd8111e_nway_reset(struct net_device *dev)
1608 {
1609 struct amd8111e_priv *lp = netdev_priv(dev);
1610 return mii_nway_restart(&lp->mii_if);
1611 }
1612
1613 static u32 amd8111e_get_link(struct net_device *dev)
1614 {
1615 struct amd8111e_priv *lp = netdev_priv(dev);
1616 return mii_link_ok(&lp->mii_if);
1617 }
1618
1619 static void amd8111e_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol_info)
1620 {
1621 struct amd8111e_priv *lp = netdev_priv(dev);
1622 wol_info->supported = WAKE_MAGIC|WAKE_PHY;
1623 if (lp->options & OPTION_WOL_ENABLE)
1624 wol_info->wolopts = WAKE_MAGIC;
1625 }
1626
1627 static int amd8111e_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol_info)
1628 {
1629 struct amd8111e_priv *lp = netdev_priv(dev);
1630 if (wol_info->wolopts & ~(WAKE_MAGIC|WAKE_PHY))
1631 return -EINVAL;
1632 spin_lock_irq(&lp->lock);
1633 if (wol_info->wolopts & WAKE_MAGIC)
1634 lp->options |=
1635 (OPTION_WOL_ENABLE | OPTION_WAKE_MAGIC_ENABLE);
1636 else if(wol_info->wolopts & WAKE_PHY)
1637 lp->options |=
1638 (OPTION_WOL_ENABLE | OPTION_WAKE_PHY_ENABLE);
1639 else
1640 lp->options &= ~OPTION_WOL_ENABLE;
1641 spin_unlock_irq(&lp->lock);
1642 return 0;
1643 }
1644
1645 static struct ethtool_ops ops = {
1646 .get_drvinfo = amd8111e_get_drvinfo,
1647 .get_regs_len = amd8111e_get_regs_len,
1648 .get_regs = amd8111e_get_regs,
1649 .get_settings = amd8111e_get_settings,
1650 .set_settings = amd8111e_set_settings,
1651 .nway_reset = amd8111e_nway_reset,
1652 .get_link = amd8111e_get_link,
1653 .get_wol = amd8111e_get_wol,
1654 .set_wol = amd8111e_set_wol,
1655 };
1656
1657 /*
1658 This function handles all the ethtool ioctls. It gives driver info, gets/sets driver speed, gets memory mapped register values, forces auto negotiation, sets/gets WOL options for ethtool application.
1659 */
1660
1661 static int amd8111e_ioctl(struct net_device * dev , struct ifreq *ifr, int cmd)
1662 {
1663 struct mii_ioctl_data *data = if_mii(ifr);
1664 struct amd8111e_priv *lp = netdev_priv(dev);
1665 int err;
1666 u32 mii_regval;
1667
1668 if (!capable(CAP_NET_ADMIN))
1669 return -EPERM;
1670
1671 switch(cmd) {
1672 case SIOCGMIIPHY:
1673 data->phy_id = lp->ext_phy_addr;
1674
1675 /* fallthru */
1676 case SIOCGMIIREG:
1677
1678 spin_lock_irq(&lp->lock);
1679 err = amd8111e_read_phy(lp, data->phy_id,
1680 data->reg_num & PHY_REG_ADDR_MASK, &mii_regval);
1681 spin_unlock_irq(&lp->lock);
1682
1683 data->val_out = mii_regval;
1684 return err;
1685
1686 case SIOCSMIIREG:
1687
1688 spin_lock_irq(&lp->lock);
1689 err = amd8111e_write_phy(lp, data->phy_id,
1690 data->reg_num & PHY_REG_ADDR_MASK, data->val_in);
1691 spin_unlock_irq(&lp->lock);
1692
1693 return err;
1694
1695 default:
1696 /* do nothing */
1697 break;
1698 }
1699 return -EOPNOTSUPP;
1700 }
1701 static int amd8111e_set_mac_address(struct net_device *dev, void *p)
1702 {
1703 struct amd8111e_priv *lp = netdev_priv(dev);
1704 int i;
1705 struct sockaddr *addr = p;
1706
1707 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1708 spin_lock_irq(&lp->lock);
1709 /* Setting the MAC address to the device */
1710 for(i = 0; i < ETH_ADDR_LEN; i++)
1711 writeb( dev->dev_addr[i], lp->mmio + PADR + i );
1712
1713 spin_unlock_irq(&lp->lock);
1714
1715 return 0;
1716 }
1717
1718 /*
1719 This function changes the mtu of the device. It restarts the device to initialize the descriptor with new receive buffers.
1720 */
1721 static int amd8111e_change_mtu(struct net_device *dev, int new_mtu)
1722 {
1723 struct amd8111e_priv *lp = netdev_priv(dev);
1724 int err;
1725
1726 if ((new_mtu < AMD8111E_MIN_MTU) || (new_mtu > AMD8111E_MAX_MTU))
1727 return -EINVAL;
1728
1729 if (!netif_running(dev)) {
1730 /* new_mtu will be used
1731 when device starts netxt time */
1732 dev->mtu = new_mtu;
1733 return 0;
1734 }
1735
1736 spin_lock_irq(&lp->lock);
1737
1738 /* stop the chip */
1739 writel(RUN, lp->mmio + CMD0);
1740
1741 dev->mtu = new_mtu;
1742
1743 err = amd8111e_restart(dev);
1744 spin_unlock_irq(&lp->lock);
1745 if(!err)
1746 netif_start_queue(dev);
1747 return err;
1748 }
1749
1750 #if AMD8111E_VLAN_TAG_USED
1751 static void amd8111e_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1752 {
1753 struct amd8111e_priv *lp = netdev_priv(dev);
1754 spin_lock_irq(&lp->lock);
1755 lp->vlgrp = grp;
1756 spin_unlock_irq(&lp->lock);
1757 }
1758
1759 static void amd8111e_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
1760 {
1761 struct amd8111e_priv *lp = netdev_priv(dev);
1762 spin_lock_irq(&lp->lock);
1763 if (lp->vlgrp)
1764 lp->vlgrp->vlan_devices[vid] = NULL;
1765 spin_unlock_irq(&lp->lock);
1766 }
1767 #endif
1768 static int amd8111e_enable_magicpkt(struct amd8111e_priv* lp)
1769 {
1770 writel( VAL1|MPPLBA, lp->mmio + CMD3);
1771 writel( VAL0|MPEN_SW, lp->mmio + CMD7);
1772
1773 /* To eliminate PCI posting bug */
1774 readl(lp->mmio + CMD7);
1775 return 0;
1776 }
1777
1778 static int amd8111e_enable_link_change(struct amd8111e_priv* lp)
1779 {
1780
1781 /* Adapter is already stoped/suspended/interrupt-disabled */
1782 writel(VAL0|LCMODE_SW,lp->mmio + CMD7);
1783
1784 /* To eliminate PCI posting bug */
1785 readl(lp->mmio + CMD7);
1786 return 0;
1787 }
1788 /* This function is called when a packet transmission fails to complete within a resonable period, on the assumption that an interrupts have been failed or the interface is locked up. This function will reinitialize the hardware */
1789
1790 static void amd8111e_tx_timeout(struct net_device *dev)
1791 {
1792 struct amd8111e_priv* lp = netdev_priv(dev);
1793 int err;
1794
1795 printk(KERN_ERR "%s: transmit timed out, resetting\n",
1796 dev->name);
1797 spin_lock_irq(&lp->lock);
1798 err = amd8111e_restart(dev);
1799 spin_unlock_irq(&lp->lock);
1800 if(!err)
1801 netif_wake_queue(dev);
1802 }
1803 static int amd8111e_suspend(struct pci_dev *pci_dev, pm_message_t state)
1804 {
1805 struct net_device *dev = pci_get_drvdata(pci_dev);
1806 struct amd8111e_priv *lp = netdev_priv(dev);
1807
1808 if (!netif_running(dev))
1809 return 0;
1810
1811 /* disable the interrupt */
1812 spin_lock_irq(&lp->lock);
1813 amd8111e_disable_interrupt(lp);
1814 spin_unlock_irq(&lp->lock);
1815
1816 netif_device_detach(dev);
1817
1818 /* stop chip */
1819 spin_lock_irq(&lp->lock);
1820 if(lp->options & OPTION_DYN_IPG_ENABLE)
1821 del_timer_sync(&lp->ipg_data.ipg_timer);
1822 amd8111e_stop_chip(lp);
1823 spin_unlock_irq(&lp->lock);
1824
1825 if(lp->options & OPTION_WOL_ENABLE){
1826 /* enable wol */
1827 if(lp->options & OPTION_WAKE_MAGIC_ENABLE)
1828 amd8111e_enable_magicpkt(lp);
1829 if(lp->options & OPTION_WAKE_PHY_ENABLE)
1830 amd8111e_enable_link_change(lp);
1831
1832 pci_enable_wake(pci_dev, PCI_D3hot, 1);
1833 pci_enable_wake(pci_dev, PCI_D3cold, 1);
1834
1835 }
1836 else{
1837 pci_enable_wake(pci_dev, PCI_D3hot, 0);
1838 pci_enable_wake(pci_dev, PCI_D3cold, 0);
1839 }
1840
1841 pci_save_state(pci_dev);
1842 pci_set_power_state(pci_dev, PCI_D3hot);
1843
1844 return 0;
1845 }
1846 static int amd8111e_resume(struct pci_dev *pci_dev)
1847 {
1848 struct net_device *dev = pci_get_drvdata(pci_dev);
1849 struct amd8111e_priv *lp = netdev_priv(dev);
1850
1851 if (!netif_running(dev))
1852 return 0;
1853
1854 pci_set_power_state(pci_dev, PCI_D0);
1855 pci_restore_state(pci_dev);
1856
1857 pci_enable_wake(pci_dev, PCI_D3hot, 0);
1858 pci_enable_wake(pci_dev, PCI_D3cold, 0); /* D3 cold */
1859
1860 netif_device_attach(dev);
1861
1862 spin_lock_irq(&lp->lock);
1863 amd8111e_restart(dev);
1864 /* Restart ipg timer */
1865 if(lp->options & OPTION_DYN_IPG_ENABLE)
1866 mod_timer(&lp->ipg_data.ipg_timer,
1867 jiffies + IPG_CONVERGE_JIFFIES);
1868 spin_unlock_irq(&lp->lock);
1869
1870 return 0;
1871 }
1872
1873
1874 static void __devexit amd8111e_remove_one(struct pci_dev *pdev)
1875 {
1876 struct net_device *dev = pci_get_drvdata(pdev);
1877 if (dev) {
1878 unregister_netdev(dev);
1879 iounmap(((struct amd8111e_priv *)netdev_priv(dev))->mmio);
1880 free_netdev(dev);
1881 pci_release_regions(pdev);
1882 pci_disable_device(pdev);
1883 pci_set_drvdata(pdev, NULL);
1884 }
1885 }
1886 static void amd8111e_config_ipg(struct net_device* dev)
1887 {
1888 struct amd8111e_priv *lp = netdev_priv(dev);
1889 struct ipg_info* ipg_data = &lp->ipg_data;
1890 void __iomem *mmio = lp->mmio;
1891 unsigned int prev_col_cnt = ipg_data->col_cnt;
1892 unsigned int total_col_cnt;
1893 unsigned int tmp_ipg;
1894
1895 if(lp->link_config.duplex == DUPLEX_FULL){
1896 ipg_data->ipg = DEFAULT_IPG;
1897 return;
1898 }
1899
1900 if(ipg_data->ipg_state == SSTATE){
1901
1902 if(ipg_data->timer_tick == IPG_STABLE_TIME){
1903
1904 ipg_data->timer_tick = 0;
1905 ipg_data->ipg = MIN_IPG - IPG_STEP;
1906 ipg_data->current_ipg = MIN_IPG;
1907 ipg_data->diff_col_cnt = 0xFFFFFFFF;
1908 ipg_data->ipg_state = CSTATE;
1909 }
1910 else
1911 ipg_data->timer_tick++;
1912 }
1913
1914 if(ipg_data->ipg_state == CSTATE){
1915
1916 /* Get the current collision count */
1917
1918 total_col_cnt = ipg_data->col_cnt =
1919 amd8111e_read_mib(mmio, xmt_collisions);
1920
1921 if ((total_col_cnt - prev_col_cnt) <
1922 (ipg_data->diff_col_cnt)){
1923
1924 ipg_data->diff_col_cnt =
1925 total_col_cnt - prev_col_cnt ;
1926
1927 ipg_data->ipg = ipg_data->current_ipg;
1928 }
1929
1930 ipg_data->current_ipg += IPG_STEP;
1931
1932 if (ipg_data->current_ipg <= MAX_IPG)
1933 tmp_ipg = ipg_data->current_ipg;
1934 else{
1935 tmp_ipg = ipg_data->ipg;
1936 ipg_data->ipg_state = SSTATE;
1937 }
1938 writew((u32)tmp_ipg, mmio + IPG);
1939 writew((u32)(tmp_ipg - IFS1_DELTA), mmio + IFS1);
1940 }
1941 mod_timer(&lp->ipg_data.ipg_timer, jiffies + IPG_CONVERGE_JIFFIES);
1942 return;
1943
1944 }
1945
1946 static void __devinit amd8111e_probe_ext_phy(struct net_device* dev)
1947 {
1948 struct amd8111e_priv *lp = netdev_priv(dev);
1949 int i;
1950
1951 for (i = 0x1e; i >= 0; i--) {
1952 u32 id1, id2;
1953
1954 if (amd8111e_read_phy(lp, i, MII_PHYSID1, &id1))
1955 continue;
1956 if (amd8111e_read_phy(lp, i, MII_PHYSID2, &id2))
1957 continue;
1958 lp->ext_phy_id = (id1 << 16) | id2;
1959 lp->ext_phy_addr = i;
1960 return;
1961 }
1962 lp->ext_phy_id = 0;
1963 lp->ext_phy_addr = 1;
1964 }
1965
1966 static int __devinit amd8111e_probe_one(struct pci_dev *pdev,
1967 const struct pci_device_id *ent)
1968 {
1969 int err,i,pm_cap;
1970 unsigned long reg_addr,reg_len;
1971 struct amd8111e_priv* lp;
1972 struct net_device* dev;
1973
1974 err = pci_enable_device(pdev);
1975 if(err){
1976 printk(KERN_ERR "amd8111e: Cannot enable new PCI device,"
1977 "exiting.\n");
1978 return err;
1979 }
1980
1981 if(!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)){
1982 printk(KERN_ERR "amd8111e: Cannot find PCI base address"
1983 "exiting.\n");
1984 err = -ENODEV;
1985 goto err_disable_pdev;
1986 }
1987
1988 err = pci_request_regions(pdev, MODULE_NAME);
1989 if(err){
1990 printk(KERN_ERR "amd8111e: Cannot obtain PCI resources, "
1991 "exiting.\n");
1992 goto err_disable_pdev;
1993 }
1994
1995 pci_set_master(pdev);
1996
1997 /* Find power-management capability. */
1998 if((pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM))==0){
1999 printk(KERN_ERR "amd8111e: No Power Management capability, "
2000 "exiting.\n");
2001 goto err_free_reg;
2002 }
2003
2004 /* Initialize DMA */
2005 if(!pci_dma_supported(pdev, 0xffffffff)){
2006 printk(KERN_ERR "amd8111e: DMA not supported,"
2007 "exiting.\n");
2008 goto err_free_reg;
2009 } else
2010 pdev->dma_mask = 0xffffffff;
2011
2012 reg_addr = pci_resource_start(pdev, 0);
2013 reg_len = pci_resource_len(pdev, 0);
2014
2015 dev = alloc_etherdev(sizeof(struct amd8111e_priv));
2016 if (!dev) {
2017 printk(KERN_ERR "amd8111e: Etherdev alloc failed, exiting.\n");
2018 err = -ENOMEM;
2019 goto err_free_reg;
2020 }
2021
2022 SET_MODULE_OWNER(dev);
2023 SET_NETDEV_DEV(dev, &pdev->dev);
2024
2025 #if AMD8111E_VLAN_TAG_USED
2026 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX ;
2027 dev->vlan_rx_register =amd8111e_vlan_rx_register;
2028 dev->vlan_rx_kill_vid = amd8111e_vlan_rx_kill_vid;
2029 #endif
2030
2031 lp = netdev_priv(dev);
2032 lp->pci_dev = pdev;
2033 lp->amd8111e_net_dev = dev;
2034 lp->pm_cap = pm_cap;
2035
2036 spin_lock_init(&lp->lock);
2037
2038 lp->mmio = ioremap(reg_addr, reg_len);
2039 if (lp->mmio == 0) {
2040 printk(KERN_ERR "amd8111e: Cannot map device registers, "
2041 "exiting\n");
2042 err = -ENOMEM;
2043 goto err_free_dev;
2044 }
2045
2046 /* Initializing MAC address */
2047 for(i = 0; i < ETH_ADDR_LEN; i++)
2048 dev->dev_addr[i] =readb(lp->mmio + PADR + i);
2049
2050 /* Setting user defined parametrs */
2051 lp->ext_phy_option = speed_duplex[card_idx];
2052 if(coalesce[card_idx])
2053 lp->options |= OPTION_INTR_COAL_ENABLE;
2054 if(dynamic_ipg[card_idx++])
2055 lp->options |= OPTION_DYN_IPG_ENABLE;
2056
2057 /* Initialize driver entry points */
2058 dev->open = amd8111e_open;
2059 dev->hard_start_xmit = amd8111e_start_xmit;
2060 dev->stop = amd8111e_close;
2061 dev->get_stats = amd8111e_get_stats;
2062 dev->set_multicast_list = amd8111e_set_multicast_list;
2063 dev->set_mac_address = amd8111e_set_mac_address;
2064 dev->do_ioctl = amd8111e_ioctl;
2065 dev->change_mtu = amd8111e_change_mtu;
2066 SET_ETHTOOL_OPS(dev, &ops);
2067 dev->irq =pdev->irq;
2068 dev->tx_timeout = amd8111e_tx_timeout;
2069 dev->watchdog_timeo = AMD8111E_TX_TIMEOUT;
2070 #ifdef CONFIG_AMD8111E_NAPI
2071 dev->poll = amd8111e_rx_poll;
2072 dev->weight = 32;
2073 #endif
2074 #ifdef CONFIG_NET_POLL_CONTROLLER
2075 dev->poll_controller = amd8111e_poll;
2076 #endif
2077
2078 #if AMD8111E_VLAN_TAG_USED
2079 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2080 dev->vlan_rx_register =amd8111e_vlan_rx_register;
2081 dev->vlan_rx_kill_vid = amd8111e_vlan_rx_kill_vid;
2082 #endif
2083 /* Probe the external PHY */
2084 amd8111e_probe_ext_phy(dev);
2085
2086 /* setting mii default values */
2087 lp->mii_if.dev = dev;
2088 lp->mii_if.mdio_read = amd8111e_mdio_read;
2089 lp->mii_if.mdio_write = amd8111e_mdio_write;
2090 lp->mii_if.phy_id = lp->ext_phy_addr;
2091
2092 /* Set receive buffer length and set jumbo option*/
2093 amd8111e_set_rx_buff_len(dev);
2094
2095
2096 err = register_netdev(dev);
2097 if (err) {
2098 printk(KERN_ERR "amd8111e: Cannot register net device, "
2099 "exiting.\n");
2100 goto err_iounmap;
2101 }
2102
2103 pci_set_drvdata(pdev, dev);
2104
2105 /* Initialize software ipg timer */
2106 if(lp->options & OPTION_DYN_IPG_ENABLE){
2107 init_timer(&lp->ipg_data.ipg_timer);
2108 lp->ipg_data.ipg_timer.data = (unsigned long) dev;
2109 lp->ipg_data.ipg_timer.function = (void *)&amd8111e_config_ipg;
2110 lp->ipg_data.ipg_timer.expires = jiffies +
2111 IPG_CONVERGE_JIFFIES;
2112 lp->ipg_data.ipg = DEFAULT_IPG;
2113 lp->ipg_data.ipg_state = CSTATE;
2114 };
2115
2116 /* display driver and device information */
2117
2118 chip_version = (readl(lp->mmio + CHIPID) & 0xf0000000)>>28;
2119 printk(KERN_INFO "%s: AMD-8111e Driver Version: %s\n", dev->name,MODULE_VERS);
2120 printk(KERN_INFO "%s: [ Rev %x ] PCI 10/100BaseT Ethernet ", dev->name, chip_version);
2121 for (i = 0; i < 6; i++)
2122 printk("%2.2x%c",dev->dev_addr[i],i == 5 ? ' ' : ':');
2123 printk( "\n");
2124 if (lp->ext_phy_id)
2125 printk(KERN_INFO "%s: Found MII PHY ID 0x%08x at address 0x%02x\n",
2126 dev->name, lp->ext_phy_id, lp->ext_phy_addr);
2127 else
2128 printk(KERN_INFO "%s: Couldn't detect MII PHY, assuming address 0x01\n",
2129 dev->name);
2130 return 0;
2131 err_iounmap:
2132 iounmap(lp->mmio);
2133
2134 err_free_dev:
2135 free_netdev(dev);
2136
2137 err_free_reg:
2138 pci_release_regions(pdev);
2139
2140 err_disable_pdev:
2141 pci_disable_device(pdev);
2142 pci_set_drvdata(pdev, NULL);
2143 return err;
2144
2145 }
2146
2147 static struct pci_driver amd8111e_driver = {
2148 .name = MODULE_NAME,
2149 .id_table = amd8111e_pci_tbl,
2150 .probe = amd8111e_probe_one,
2151 .remove = __devexit_p(amd8111e_remove_one),
2152 .suspend = amd8111e_suspend,
2153 .resume = amd8111e_resume
2154 };
2155
2156 static int __init amd8111e_init(void)
2157 {
2158 return pci_module_init(&amd8111e_driver);
2159 }
2160
2161 static void __exit amd8111e_cleanup(void)
2162 {
2163 pci_unregister_driver(&amd8111e_driver);
2164 }
2165
2166 module_init(amd8111e_init);
2167 module_exit(amd8111e_cleanup);
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