drivers/net/gt64240eth.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2001 Patton Electronics Company
   7  * Copyright (C) 2002 Momentum Computer
   8  *
   9  * Copyright 2000 MontaVista Software Inc.
  10  * Author: MontaVista Software, Inc.
  11  *              stevel@mvista.com or support@mvista.com
  12  *
  13  *  This program is free software; you can distribute it and/or modify it
  14  *  under the terms of the GNU General Public License (Version 2) as
  15  *  published by the Free Software Foundation.
  16  *
  17  *  This program is distributed in the hope it will be useful, but WITHOUT
  18  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  19  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  20  *  for more details.
  21  *
  22  *  You should have received a copy of the GNU General Public License along
  23  *  with this program; if not, write to the Free Software Foundation, Inc.,
  24  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  25  *
  26  * Ethernet driver definitions for the MIPS GT96100 Advanced
  27  * Communication Controller.
  28  *
  29  * Modified for the Marvellous GT64240 Retarded Communication Controller.
  30  */
  31 #ifndef _GT64240ETH_H
  32 #define _GT64240ETH_H
  33
  34 #include <asm/gt64240.h>
  35
  36 #define ETHERNET_PORTS_DIFFERENCE_OFFSETS       0x400
  37
  38 /* Translate those weanie names from Galileo/VxWorks header files: */
  39
  40 #define GT64240_MRR                    MAIN_ROUTING_REGISTER
  41 #define GT64240_CIU_ARBITER_CONFIG     COMM_UNIT_ARBITER_CONFIGURATION_REGISTER
  42 #define GT64240_CIU_ARBITER_CONTROL    COMM_UNIT_ARBITER_CONTROL
  43 #define GT64240_MAIN_LOW_CAUSE         LOW_INTERRUPT_CAUSE_REGISTER
  44 #define GT64240_MAIN_HIGH_CAUSE        HIGH_INTERRUPT_CAUSE_REGISTER
  45 #define GT64240_CPU_LOW_MASK           CPU_INTERRUPT_MASK_REGISTER_LOW
  46 #define GT64240_CPU_HIGH_MASK          CPU_INTERRUPT_MASK_REGISTER_HIGH
  47 #define GT64240_CPU_SELECT_CAUSE       CPU_SELECT_CAUSE_REGISTER
  48
  49 #define GT64240_ETH_PHY_ADDR_REG       ETHERNET_PHY_ADDRESS_REGISTER
  50 #define GT64240_ETH_PORT_CONFIG        ETHERNET0_PORT_CONFIGURATION_REGISTER
  51 #define GT64240_ETH_PORT_CONFIG_EXT    ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER
  52 #define GT64240_ETH_PORT_COMMAND       ETHERNET0_PORT_COMMAND_REGISTER
  53 #define GT64240_ETH_PORT_STATUS        ETHERNET0_PORT_STATUS_REGISTER
  54 #define GT64240_ETH_IO_SIZE            ETHERNET_PORTS_DIFFERENCE_OFFSETS
  55 #define GT64240_ETH_SMI_REG            ETHERNET_SMI_REGISTER
  56 #define GT64240_ETH_MIB_COUNT_BASE     ETHERNET0_MIB_COUNTER_BASE
  57 #define GT64240_ETH_SDMA_CONFIG        ETHERNET0_SDMA_CONFIGURATION_REGISTER
  58 #define GT64240_ETH_SDMA_COMM          ETHERNET0_SDMA_COMMAND_REGISTER
  59 #define GT64240_ETH_INT_MASK           ETHERNET0_INTERRUPT_MASK_REGISTER
  60 #define GT64240_ETH_INT_CAUSE          ETHERNET0_INTERRUPT_CAUSE_REGISTER
  61 #define GT64240_ETH_CURR_TX_DESC_PTR0  ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0
  62 #define GT64240_ETH_CURR_TX_DESC_PTR1  ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER1
  63 #define GT64240_ETH_1ST_RX_DESC_PTR0   ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0
  64 #define GT64240_ETH_CURR_RX_DESC_PTR0  ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0
  65 #define GT64240_ETH_HASH_TBL_PTR       ETHERNET0_HASH_TABLE_POINTER_REGISTER
  66
  67 /* Turn on NAPI by default */
  68
  69 #define GT64240_NAPI                    1
  70
  71 /* Some 64240 settings that SHOULD eventually be setup in PROM monitor: */
  72 /* (Board-specific to the DSL3224 Rev A board ONLY!)                    */
  73 #define D3224_MPP_CTRL0_SETTING         0x66669900
  74 #define D3224_MPP_CTRL1_SETTING         0x00000000
  75 #define D3224_MPP_CTRL2_SETTING         0x00887700
  76 #define D3224_MPP_CTRL3_SETTING         0x00000044
  77 #define D3224_GPP_IO_CTRL_SETTING       0x0000e800
  78 #define D3224_GPP_LEVEL_CTRL_SETTING    0xf001f703
  79 #define D3224_GPP_VALUE_SETTING         0x00000000
  80
  81 /* Keep the ring sizes a power of two for efficiency. */
  82 //-#define TX_RING_SIZE 16
  83 #define TX_RING_SIZE    64      /* TESTING !!! */
  84 #define RX_RING_SIZE    32
  85 #define PKT_BUF_SZ      1536    /* Size of each temporary Rx buffer. */
  86
  87 #define RX_HASH_TABLE_SIZE 16384
  88 #define HASH_HOP_NUMBER 12
  89
  90 #define NUM_INTERFACES 3
  91
  92 #define GT64240ETH_TX_TIMEOUT HZ/4
  93
  94 #define MIPS_GT64240_BASE 0xf4000000
  95 #define GT64240_ETH0_BASE (MIPS_GT64240_BASE + GT64240_ETH_PORT_CONFIG)
  96 #define GT64240_ETH1_BASE (GT64240_ETH0_BASE + GT64240_ETH_IO_SIZE)
  97 #define GT64240_ETH2_BASE (GT64240_ETH1_BASE + GT64240_ETH_IO_SIZE)
  98
  99 #if defined(CONFIG_MIPS_DSL3224)
 100 #define GT64240_ETHER0_IRQ 4
 101 #define GT64240_ETHER1_IRQ 4
 102 #else
 103 #define GT64240_ETHER0_IRQ -1
 104 #define GT64240_ETHER1_IRQ -1
 105 #endif
 106
 107 #define REV_GT64240  0x1
 108 #define REV_GT64240A 0x10
 109
 110 #define GT64240ETH_READ(gp, offset)                                     \
 111         GT_READ((gp)->port_offset + (offset))
 112
 113 #define GT64240ETH_WRITE(gp, offset, data)                              \
 114         GT_WRITE((gp)->port_offset + (offset), (data))
 115
 116 #define GT64240ETH_SETBIT(gp, offset, bits)                             \
 117         GT64240ETH_WRITE((gp), (offset),                                \
 118                          GT64240ETH_READ((gp), (offset)) | (bits))
 119
 120 #define GT64240ETH_CLRBIT(gp, offset, bits)                             \
 121         GT64240ETH_WRITE((gp), (offset),                                \
 122                          GT64240ETH_READ((gp), (offset)) & ~(bits))
 123
 124 #define GT64240_READ(ofs)               GT_READ(ofs)
 125 #define GT64240_WRITE(ofs, data)        GT_WRITE((ofs), (data))
 126
 127 /* Bit definitions of the SMI Reg */
 128 enum {
 129         smirDataMask = 0xffff,
 130         smirPhyAdMask = 0x1f << 16,
 131         smirPhyAdBit = 16,
 132         smirRegAdMask = 0x1f << 21,
 133         smirRegAdBit = 21,
 134         smirOpCode = 1 << 26,
 135         smirReadValid = 1 << 27,
 136         smirBusy = 1 << 28
 137 };
 138
 139 /* Bit definitions of the Port Config Reg */
 140 enum pcr_bits {
 141         pcrPM = 1 << 0,
 142         pcrRBM = 1 << 1,
 143         pcrPBF = 1 << 2,
 144         pcrEN = 1 << 7,
 145         pcrLPBKMask = 0x3 << 8,
 146         pcrLPBKBit = 1 << 8,
 147         pcrFC = 1 << 10,
 148         pcrHS = 1 << 12,
 149         pcrHM = 1 << 13,
 150         pcrHDM = 1 << 14,
 151         pcrHD = 1 << 15,
 152         pcrISLMask = 0x7 << 28,
 153         pcrISLBit = 28,
 154         pcrACCS = 1 << 31
 155 };
 156
 157 /* Bit definitions of the Port Config Extend Reg */
 158 enum pcxr_bits {
 159         pcxrIGMP = 1,
 160         pcxrSPAN = 2,
 161         pcxrPAR = 4,
 162         pcxrPRIOtxMask = 0x7 << 3,
 163         pcxrPRIOtxBit = 3,
 164         pcxrPRIOrxMask = 0x3 << 6,
 165         pcxrPRIOrxBit = 6,
 166         pcxrPRIOrxOverride = 1 << 8,
 167         pcxrDPLXen = 1 << 9,
 168         pcxrFCTLen = 1 << 10,
 169         pcxrFLP = 1 << 11,
 170         pcxrFCTL = 1 << 12,
 171         pcxrMFLMask = 0x3 << 14,
 172         pcxrMFLBit = 14,
 173         pcxrMIBclrMode = 1 << 16,
 174         pcxrSpeed = 1 << 18,
 175         pcxrSpeeden = 1 << 19,
 176         pcxrRMIIen = 1 << 20,
 177         pcxrDSCPen = 1 << 21
 178 };
 179
 180 /* Bit definitions of the Port Command Reg */
 181 enum pcmr_bits {
 182         pcmrFJ = 1 << 15
 183 };
 184
 185
 186 /* Bit definitions of the Port Status Reg */
 187 enum psr_bits {
 188         psrSpeed = 1,
 189         psrDuplex = 2,
 190         psrFctl = 4,
 191         psrLink = 8,
 192         psrPause = 1 << 4,
 193         psrTxLow = 1 << 5,
 194         psrTxHigh = 1 << 6,
 195         psrTxInProg = 1 << 7
 196 };
 197
 198 /* Bit definitions of the SDMA Config Reg */
 199 enum sdcr_bits {
 200         sdcrRCMask = 0xf << 2,
 201         sdcrRCBit = 2,
 202         sdcrBLMR = 1 << 6,
 203         sdcrBLMT = 1 << 7,
 204         sdcrPOVR = 1 << 8,
 205         sdcrRIFB = 1 << 9,
 206         sdcrBSZMask = 0x3 << 12,
 207         sdcrBSZBit = 12
 208 };
 209
 210 /* Bit definitions of the SDMA Command Reg */
 211 enum sdcmr_bits {
 212         sdcmrERD = 1 << 7,
 213         sdcmrAR = 1 << 15,
 214         sdcmrSTDH = 1 << 16,
 215         sdcmrSTDL = 1 << 17,
 216         sdcmrTXDH = 1 << 23,
 217         sdcmrTXDL = 1 << 24,
 218         sdcmrAT = 1 << 31
 219 };
 220
 221 /* Bit definitions of the Interrupt Cause Reg */
 222 enum icr_bits {
 223         icrRxBuffer = 1,
 224         icrTxBufferHigh = 1 << 2,
 225         icrTxBufferLow = 1 << 3,
 226         icrTxEndHigh = 1 << 6,
 227         icrTxEndLow = 1 << 7,
 228         icrRxError = 1 << 8,
 229         icrTxErrorHigh = 1 << 10,
 230         icrTxErrorLow = 1 << 11,
 231         icrRxOVR = 1 << 12,
 232         icrTxUdr = 1 << 13,
 233         icrRxBufferQ0 = 1 << 16,
 234         icrRxBufferQ1 = 1 << 17,
 235         icrRxBufferQ2 = 1 << 18,
 236         icrRxBufferQ3 = 1 << 19,
 237         icrRxErrorQ0 = 1 << 20,
 238         icrRxErrorQ1 = 1 << 21,
 239         icrRxErrorQ2 = 1 << 22,
 240         icrRxErrorQ3 = 1 << 23,
 241         icrMIIPhySTC = 1 << 28,
 242         icrSMIdone = 1 << 29,
 243         icrEtherIntSum = 1 << 31
 244 };
 245
 246
 247 /* The Rx and Tx descriptor lists. */
 248 #ifdef __LITTLE_ENDIAN
 249 typedef struct {
 250         u32 cmdstat;
 251         u16 reserved;           //-prk21aug01    u32 reserved:16;
 252         u16 byte_cnt;           //-prk21aug01    u32 byte_cnt:16;
 253         u32 buff_ptr;
 254         u32 next;
 255 } gt64240_td_t;
 256
 257 typedef struct {
 258         u32 cmdstat;
 259         u16 byte_cnt;           //-prk21aug01    u32 byte_cnt:16;
 260         u16 buff_sz;            //-prk21aug01    u32 buff_sz:16;
 261         u32 buff_ptr;
 262         u32 next;
 263 } gt64240_rd_t;
 264 #elif defined(__BIG_ENDIAN)
 265 typedef struct {
 266         u16 byte_cnt;           //-prk21aug01    u32 byte_cnt:16;
 267         u16 reserved;           //-prk21aug01    u32 reserved:16;
 268         u32 cmdstat;
 269         u32 next;
 270         u32 buff_ptr;
 271 } gt64240_td_t;
 272
 273 typedef struct {
 274         u16 buff_sz;            //-prk21aug01    u32 buff_sz:16;
 275         u16 byte_cnt;           //-prk21aug01    u32 byte_cnt:16;
 276         u32 cmdstat;
 277         u32 next;
 278         u32 buff_ptr;
 279 } gt64240_rd_t;
 280 #else
 281 #error Either __BIG_ENDIAN or __LITTLE_ENDIAN must be defined!
 282 #endif
 283
 284
 285 /* Values for the Tx command-status descriptor entry. */
 286 enum td_cmdstat {
 287         txOwn = 1 << 31,
 288         txAutoMode = 1 << 30,
 289         txEI = 1 << 23,
 290         txGenCRC = 1 << 22,
 291         txPad = 1 << 18,
 292         txFirst = 1 << 17,
 293         txLast = 1 << 16,
 294         txErrorSummary = 1 << 15,
 295         txReTxCntMask = 0x0f << 10,
 296         txReTxCntBit = 10,
 297         txCollision = 1 << 9,
 298         txReTxLimit = 1 << 8,
 299         txUnderrun = 1 << 6,
 300         txLateCollision = 1 << 5
 301 };
 302
 303
 304 /* Values for the Rx command-status descriptor entry. */
 305 enum rd_cmdstat {
 306         rxOwn = 1 << 31,
 307         rxAutoMode = 1 << 30,
 308         rxEI = 1 << 23,
 309         rxFirst = 1 << 17,
 310         rxLast = 1 << 16,
 311         rxErrorSummary = 1 << 15,
 312         rxIGMP = 1 << 14,
 313         rxHashExpired = 1 << 13,
 314         rxMissedFrame = 1 << 12,
 315         rxFrameType = 1 << 11,
 316         rxShortFrame = 1 << 8,
 317         rxMaxFrameLen = 1 << 7,
 318         rxOverrun = 1 << 6,
 319         rxCollision = 1 << 4,
 320         rxCRCError = 1
 321 };
 322
 323 /* Bit fields of a Hash Table Entry */
 324 enum hash_table_entry {
 325         hteValid = 1,
 326         hteSkip = 2,
 327         hteRD = 4
 328 };
 329
 330 // The MIB counters
 331 typedef struct {
 332         u32 byteReceived;
 333         u32 byteSent;
 334         u32 framesReceived;
 335         u32 framesSent;
 336         u32 totalByteReceived;
 337         u32 totalFramesReceived;
 338         u32 broadcastFramesReceived;
 339         u32 multicastFramesReceived;
 340         u32 cRCError;
 341         u32 oversizeFrames;
 342         u32 fragments;
 343         u32 jabber;
 344         u32 collision;
 345         u32 lateCollision;
 346         u32 frames64;
 347         u32 frames65_127;
 348         u32 frames128_255;
 349         u32 frames256_511;
 350         u32 frames512_1023;
 351         u32 frames1024_MaxSize;
 352         u32 macRxError;
 353         u32 droppedFrames;
 354         u32 outMulticastFrames;
 355         u32 outBroadcastFrames;
 356         u32 undersizeFrames;
 357 } mib_counters_t;
 358
 359
 360 struct gt64240_private {
 361         gt64240_rd_t *rx_ring;
 362         gt64240_td_t *tx_ring;
 363         // The Rx and Tx rings must be 16-byte aligned
 364         dma_addr_t rx_ring_dma;
 365         dma_addr_t tx_ring_dma;
 366         char *hash_table;
 367         // The Hash Table must be 8-byte aligned
 368         dma_addr_t hash_table_dma;
 369         int hash_mode;
 370
 371         // The Rx buffers must be 8-byte aligned
 372         char *rx_buff;
 373         dma_addr_t rx_buff_dma;
 374         // Tx buffers (tx_skbuff[i]->data) with less than 8 bytes
 375         // of payload must be 8-byte aligned
 376         struct sk_buff *tx_skbuff[TX_RING_SIZE];
 377         int rx_next_out;        /* The next free ring entry to receive */
 378         int tx_next_in;         /* The next free ring entry to send */
 379         int tx_next_out;        /* The last ring entry the ISR processed */
 380         int tx_count;           /* current # of pkts waiting to be sent in Tx ring */
 381         int intr_work_done;     /* number of Rx and Tx pkts processed in the isr */
 382         int tx_full;            /* Tx ring is full */
 383
 384         mib_counters_t mib;
 385         struct net_device_stats stats;
 386
 387         int io_size;
 388         int port_num;           // 0 or 1
 389         u32 port_offset;
 390
 391         int phy_addr;           // PHY address
 392         u32 last_psr;           // last value of the port status register
 393
 394         int options;            /* User-settable misc. driver options. */
 395         int drv_flags;
 396         spinlock_t lock;        /* Serialise access to device */
 397         struct mii_if_info mii_if;
 398
 399         u32 msg_enable;
 400 };
 401
 402 #endif /* _GT64240ETH_H */