?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
[TG3]: Add tagged status support.
[linux-2.6/verdex.git] / drivers / net / irda / nsc-ircc.c
blob805714ec9a8a185db963f1285c2caf0929b14f28
1 /*********************************************************************
2 *
3 * Filename: nsc-ircc.c
4 * Version: 1.0
5 * Description: Driver for the NSC PC'108 and PC'338 IrDA chipsets
6 * Status: Stable.
7 * Author: Dag Brattli <dagb@cs.uit.no>
8 * Created at: Sat Nov 7 21:43:15 1998
9 * Modified at: Wed Mar 1 11:29:34 2000
10 * Modified by: Dag Brattli <dagb@cs.uit.no>
11 *
12 * Copyright (c) 1998-2000 Dag Brattli <dagb@cs.uit.no>
13 * Copyright (c) 1998 Lichen Wang, <lwang@actisys.com>
14 * Copyright (c) 1998 Actisys Corp., www.actisys.com
15 * All Rights Reserved
16 *
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
21 *
22 * Neither Dag Brattli nor University of Tromsø admit liability nor
23 * provide warranty for any of this software. This material is
24 * provided "AS-IS" and at no charge.
25 *
26 * Notice that all functions that needs to access the chip in _any_
27 * way, must save BSR register on entry, and restore it on exit.
28 * It is _very_ important to follow this policy!
29 *
30 * __u8 bank;
31 *
32 * bank = inb(iobase+BSR);
33 *
34 * do_your_stuff_here();
35 *
36 * outb(bank, iobase+BSR);
37 *
38 * If you find bugs in this file, its very likely that the same bug
39 * will also be in w83977af_ir.c since the implementations are quite
40 * similar.
41 *
42 ********************************************************************/
43
44 #include <linux/module.h>
45
46 #include <linux/kernel.h>
47 #include <linux/types.h>
48 #include <linux/skbuff.h>
49 #include <linux/netdevice.h>
50 #include <linux/ioport.h>
51 #include <linux/delay.h>
52 #include <linux/slab.h>
53 #include <linux/init.h>
54 #include <linux/rtnetlink.h>
55 #include <linux/dma-mapping.h>
56
57 #include <asm/io.h>
58 #include <asm/dma.h>
59 #include <asm/byteorder.h>
60
61 #include <linux/pm.h>
62
63 #include <net/irda/wrapper.h>
64 #include <net/irda/irda.h>
65 #include <net/irda/irda_device.h>
66
67 #include "nsc-ircc.h"
68
69 #define CHIP_IO_EXTENT 8
70 #define BROKEN_DONGLE_ID
71
72 static char *driver_name = "nsc-ircc";
73
74 /* Module parameters */
75 static int qos_mtt_bits = 0x07; /* 1 ms or more */
76 static int dongle_id;
77
78 /* Use BIOS settions by default, but user may supply module parameters */
79 static unsigned int io[] = { ~0, ~0, ~0, ~0 };
80 static unsigned int irq[] = { 0, 0, 0, 0, 0 };
81 static unsigned int dma[] = { 0, 0, 0, 0, 0 };
82
83 static int nsc_ircc_probe_108(nsc_chip_t *chip, chipio_t *info);
84 static int nsc_ircc_probe_338(nsc_chip_t *chip, chipio_t *info);
85 static int nsc_ircc_probe_39x(nsc_chip_t *chip, chipio_t *info);
86 static int nsc_ircc_init_108(nsc_chip_t *chip, chipio_t *info);
87 static int nsc_ircc_init_338(nsc_chip_t *chip, chipio_t *info);
88 static int nsc_ircc_init_39x(nsc_chip_t *chip, chipio_t *info);
89
90 /* These are the known NSC chips */
91 static nsc_chip_t chips[] = {
92 /* Name, {cfg registers}, chip id index reg, chip id expected value, revision mask */
93 { "PC87108", { 0x150, 0x398, 0xea }, 0x05, 0x10, 0xf0,
94 nsc_ircc_probe_108, nsc_ircc_init_108 },
95 { "PC87338", { 0x398, 0x15c, 0x2e }, 0x08, 0xb0, 0xf8,
96 nsc_ircc_probe_338, nsc_ircc_init_338 },
97 /* Contributed by Steffen Pingel - IBM X40 */
98 { "PC8738x", { 0x164e, 0x4e, 0x0 }, 0x20, 0xf4, 0xff,
99 nsc_ircc_probe_39x, nsc_ircc_init_39x },
100 /* Contributed by Jan Frey - IBM A30/A31 */
101 { "PC8739x", { 0x2e, 0x4e, 0x0 }, 0x20, 0xea, 0xff,
102 nsc_ircc_probe_39x, nsc_ircc_init_39x },
103 { NULL }
104 };
105
106 /* Max 4 instances for now */
107 static struct nsc_ircc_cb *dev_self[] = { NULL, NULL, NULL, NULL };
108
109 static char *dongle_types[] = {
110 "Differential serial interface",
111 "Differential serial interface",
112 "Reserved",
113 "Reserved",
114 "Sharp RY5HD01",
115 "Reserved",
116 "Single-ended serial interface",
117 "Consumer-IR only",
118 "HP HSDL-2300, HP HSDL-3600/HSDL-3610",
119 "IBM31T1100 or Temic TFDS6000/TFDS6500",
120 "Reserved",
121 "Reserved",
122 "HP HSDL-1100/HSDL-2100",
123 "HP HSDL-1100/HSDL-2100",
124 "Supports SIR Mode only",
125 "No dongle connected",
126 };
127
128 /* Some prototypes */
129 static int nsc_ircc_open(int i, chipio_t *info);
130 static int nsc_ircc_close(struct nsc_ircc_cb *self);
131 static int nsc_ircc_setup(chipio_t *info);
132 static void nsc_ircc_pio_receive(struct nsc_ircc_cb *self);
133 static int nsc_ircc_dma_receive(struct nsc_ircc_cb *self);
134 static int nsc_ircc_dma_receive_complete(struct nsc_ircc_cb *self, int iobase);
135 static int nsc_ircc_hard_xmit_sir(struct sk_buff *skb, struct net_device *dev);
136 static int nsc_ircc_hard_xmit_fir(struct sk_buff *skb, struct net_device *dev);
137 static int nsc_ircc_pio_write(int iobase, __u8 *buf, int len, int fifo_size);
138 static void nsc_ircc_dma_xmit(struct nsc_ircc_cb *self, int iobase);
139 static __u8 nsc_ircc_change_speed(struct nsc_ircc_cb *self, __u32 baud);
140 static int nsc_ircc_is_receiving(struct nsc_ircc_cb *self);
141 static int nsc_ircc_read_dongle_id (int iobase);
142 static void nsc_ircc_init_dongle_interface (int iobase, int dongle_id);
143
144 static int nsc_ircc_net_open(struct net_device *dev);
145 static int nsc_ircc_net_close(struct net_device *dev);
146 static int nsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
147 static struct net_device_stats *nsc_ircc_net_get_stats(struct net_device *dev);
148 static int nsc_ircc_pmproc(struct pm_dev *dev, pm_request_t rqst, void *data);
149
150 /*
151 * Function nsc_ircc_init ()
152 *
153 * Initialize chip. Just try to find out how many chips we are dealing with
154 * and where they are
155 */
156 static int __init nsc_ircc_init(void)
157 {
158 chipio_t info;
159 nsc_chip_t *chip;
160 int ret = -ENODEV;
161 int cfg_base;
162 int cfg, id;
163 int reg;
164 int i = 0;
165
166 /* Probe for all the NSC chipsets we know about */
167 for (chip=chips; chip->name ; chip++) {
168 IRDA_DEBUG(2, "%s(), Probing for %s ...\n", __FUNCTION__,
169 chip->name);
170
171 /* Try all config registers for this chip */
172 for (cfg=0; cfg<3; cfg++) {
173 cfg_base = chip->cfg[cfg];
174 if (!cfg_base)
175 continue;
176
177 memset(&info, 0, sizeof(chipio_t));
178 info.cfg_base = cfg_base;
179 info.fir_base = io[i];
180 info.dma = dma[i];
181 info.irq = irq[i];
182
183 /* Read index register */
184 reg = inb(cfg_base);
185 if (reg == 0xff) {
186 IRDA_DEBUG(2, "%s() no chip at 0x%03x\n", __FUNCTION__, cfg_base);
187 continue;
188 }
189
190 /* Read chip identification register */
191 outb(chip->cid_index, cfg_base);
192 id = inb(cfg_base+1);
193 if ((id & chip->cid_mask) == chip->cid_value) {
194 IRDA_DEBUG(2, "%s() Found %s chip, revision=%d\n",
195 __FUNCTION__, chip->name, id & ~chip->cid_mask);
196 /*
197 * If the user supplies the base address, then
198 * we init the chip, if not we probe the values
199 * set by the BIOS
200 */
201 if (io[i] < 0x2000) {
202 chip->init(chip, &info);
203 } else
204 chip->probe(chip, &info);
205
206 if (nsc_ircc_open(i, &info) == 0)
207 ret = 0;
208 i++;
209 } else {
210 IRDA_DEBUG(2, "%s(), Wrong chip id=0x%02x\n", __FUNCTION__, id);
211 }
212 }
213
214 }
215
216 return ret;
217 }
218
219 /*
220 * Function nsc_ircc_cleanup ()
221 *
222 * Close all configured chips
223 *
224 */
225 static void __exit nsc_ircc_cleanup(void)
226 {
227 int i;
228
229 pm_unregister_all(nsc_ircc_pmproc);
230
231 for (i=0; i < 4; i++) {
232 if (dev_self[i])
233 nsc_ircc_close(dev_self[i]);
234 }
235 }
236
237 /*
238 * Function nsc_ircc_open (iobase, irq)
239 *
240 * Open driver instance
241 *
242 */
243 static int __init nsc_ircc_open(int i, chipio_t *info)
244 {
245 struct net_device *dev;
246 struct nsc_ircc_cb *self;
247 struct pm_dev *pmdev;
248 void *ret;
249 int err;
250
251 IRDA_DEBUG(2, "%s()\n", __FUNCTION__);
252
253 IRDA_MESSAGE("%s, Found chip at base=0x%03x\n", driver_name,
254 info->cfg_base);
255
256 if ((nsc_ircc_setup(info)) == -1)
257 return -1;
258
259 IRDA_MESSAGE("%s, driver loaded (Dag Brattli)\n", driver_name);
260
261 dev = alloc_irdadev(sizeof(struct nsc_ircc_cb));
262 if (dev == NULL) {
263 IRDA_ERROR("%s(), can't allocate memory for "
264 "control block!\n", __FUNCTION__);
265 return -ENOMEM;
266 }
267
268 self = dev->priv;
269 self->netdev = dev;
270 spin_lock_init(&self->lock);
271
272 /* Need to store self somewhere */
273 dev_self[i] = self;
274 self->index = i;
275
276 /* Initialize IO */
277 self->io.cfg_base = info->cfg_base;
278 self->io.fir_base = info->fir_base;
279 self->io.irq = info->irq;
280 self->io.fir_ext = CHIP_IO_EXTENT;
281 self->io.dma = info->dma;
282 self->io.fifo_size = 32;
283
284 /* Reserve the ioports that we need */
285 ret = request_region(self->io.fir_base, self->io.fir_ext, driver_name);
286 if (!ret) {
287 IRDA_WARNING("%s(), can't get iobase of 0x%03x\n",
288 __FUNCTION__, self->io.fir_base);
289 err = -ENODEV;
290 goto out1;
291 }
292
293 /* Initialize QoS for this device */
294 irda_init_max_qos_capabilies(&self->qos);
295
296 /* The only value we must override it the baudrate */
297 self->qos.baud_rate.bits = IR_9600|IR_19200|IR_38400|IR_57600|
298 IR_115200|IR_576000|IR_1152000 |(IR_4000000 << 8);
299
300 self->qos.min_turn_time.bits = qos_mtt_bits;
301 irda_qos_bits_to_value(&self->qos);
302
303 /* Max DMA buffer size needed = (data_size + 6) * (window_size) + 6; */
304 self->rx_buff.truesize = 14384;
305 self->tx_buff.truesize = 14384;
306
307 /* Allocate memory if needed */
308 self->rx_buff.head =
309 dma_alloc_coherent(NULL, self->rx_buff.truesize,
310 &self->rx_buff_dma, GFP_KERNEL);
311 if (self->rx_buff.head == NULL) {
312 err = -ENOMEM;
313 goto out2;
314
315 }
316 memset(self->rx_buff.head, 0, self->rx_buff.truesize);
317
318 self->tx_buff.head =
319 dma_alloc_coherent(NULL, self->tx_buff.truesize,
320 &self->tx_buff_dma, GFP_KERNEL);
321 if (self->tx_buff.head == NULL) {
322 err = -ENOMEM;
323 goto out3;
324 }
325 memset(self->tx_buff.head, 0, self->tx_buff.truesize);
326
327 self->rx_buff.in_frame = FALSE;
328 self->rx_buff.state = OUTSIDE_FRAME;
329 self->tx_buff.data = self->tx_buff.head;
330 self->rx_buff.data = self->rx_buff.head;
331
332 /* Reset Tx queue info */
333 self->tx_fifo.len = self->tx_fifo.ptr = self->tx_fifo.free = 0;
334 self->tx_fifo.tail = self->tx_buff.head;
335
336 /* Override the network functions we need to use */
337 SET_MODULE_OWNER(dev);
338 dev->hard_start_xmit = nsc_ircc_hard_xmit_sir;
339 dev->open = nsc_ircc_net_open;
340 dev->stop = nsc_ircc_net_close;
341 dev->do_ioctl = nsc_ircc_net_ioctl;
342 dev->get_stats = nsc_ircc_net_get_stats;
343
344 err = register_netdev(dev);
345 if (err) {
346 IRDA_ERROR("%s(), register_netdev() failed!\n", __FUNCTION__);
347 goto out4;
348 }
349 IRDA_MESSAGE("IrDA: Registered device %s\n", dev->name);
350
351 /* Check if user has supplied a valid dongle id or not */
352 if ((dongle_id <= 0) ||
353 (dongle_id >= (sizeof(dongle_types) / sizeof(dongle_types[0]))) ) {
354 dongle_id = nsc_ircc_read_dongle_id(self->io.fir_base);
355
356 IRDA_MESSAGE("%s, Found dongle: %s\n", driver_name,
357 dongle_types[dongle_id]);
358 } else {
359 IRDA_MESSAGE("%s, Using dongle: %s\n", driver_name,
360 dongle_types[dongle_id]);
361 }
362
363 self->io.dongle_id = dongle_id;
364 nsc_ircc_init_dongle_interface(self->io.fir_base, dongle_id);
365
366 pmdev = pm_register(PM_SYS_DEV, PM_SYS_IRDA, nsc_ircc_pmproc);
367 if (pmdev)
368 pmdev->data = self;
369
370 return 0;
371 out4:
372 dma_free_coherent(NULL, self->tx_buff.truesize,
373 self->tx_buff.head, self->tx_buff_dma);
374 out3:
375 dma_free_coherent(NULL, self->rx_buff.truesize,
376 self->rx_buff.head, self->rx_buff_dma);
377 out2:
378 release_region(self->io.fir_base, self->io.fir_ext);
379 out1:
380 free_netdev(dev);
381 dev_self[i] = NULL;
382 return err;
383 }
384
385 /*
386 * Function nsc_ircc_close (self)
387 *
388 * Close driver instance
389 *
390 */
391 static int __exit nsc_ircc_close(struct nsc_ircc_cb *self)
392 {
393 int iobase;
394
395 IRDA_DEBUG(4, "%s()\n", __FUNCTION__);
396
397 IRDA_ASSERT(self != NULL, return -1;);
398
399 iobase = self->io.fir_base;
400
401 /* Remove netdevice */
402 unregister_netdev(self->netdev);
403
404 /* Release the PORT that this driver is using */
405 IRDA_DEBUG(4, "%s(), Releasing Region %03x\n",
406 __FUNCTION__, self->io.fir_base);
407 release_region(self->io.fir_base, self->io.fir_ext);
408
409 if (self->tx_buff.head)
410 dma_free_coherent(NULL, self->tx_buff.truesize,
411 self->tx_buff.head, self->tx_buff_dma);
412
413 if (self->rx_buff.head)
414 dma_free_coherent(NULL, self->rx_buff.truesize,
415 self->rx_buff.head, self->rx_buff_dma);
416
417 dev_self[self->index] = NULL;
418 free_netdev(self->netdev);
419
420 return 0;
421 }
422
423 /*
424 * Function nsc_ircc_init_108 (iobase, cfg_base, irq, dma)
425 *
426 * Initialize the NSC '108 chip
427 *
428 */
429 static int nsc_ircc_init_108(nsc_chip_t *chip, chipio_t *info)
430 {
431 int cfg_base = info->cfg_base;
432 __u8 temp=0;
433
434 outb(2, cfg_base); /* Mode Control Register (MCTL) */
435 outb(0x00, cfg_base+1); /* Disable device */
436
437 /* Base Address and Interrupt Control Register (BAIC) */
438 outb(CFG_108_BAIC, cfg_base);
439 switch (info->fir_base) {
440 case 0x3e8: outb(0x14, cfg_base+1); break;
441 case 0x2e8: outb(0x15, cfg_base+1); break;
442 case 0x3f8: outb(0x16, cfg_base+1); break;
443 case 0x2f8: outb(0x17, cfg_base+1); break;
444 default: IRDA_ERROR("%s(), invalid base_address", __FUNCTION__);
445 }
446
447 /* Control Signal Routing Register (CSRT) */
448 switch (info->irq) {
449 case 3: temp = 0x01; break;
450 case 4: temp = 0x02; break;
451 case 5: temp = 0x03; break;
452 case 7: temp = 0x04; break;
453 case 9: temp = 0x05; break;
454 case 11: temp = 0x06; break;
455 case 15: temp = 0x07; break;
456 default: IRDA_ERROR("%s(), invalid irq", __FUNCTION__);
457 }
458 outb(CFG_108_CSRT, cfg_base);
459
460 switch (info->dma) {
461 case 0: outb(0x08+temp, cfg_base+1); break;
462 case 1: outb(0x10+temp, cfg_base+1); break;
463 case 3: outb(0x18+temp, cfg_base+1); break;
464 default: IRDA_ERROR("%s(), invalid dma", __FUNCTION__);
465 }
466
467 outb(CFG_108_MCTL, cfg_base); /* Mode Control Register (MCTL) */
468 outb(0x03, cfg_base+1); /* Enable device */
469
470 return 0;
471 }
472
473 /*
474 * Function nsc_ircc_probe_108 (chip, info)
475 *
476 *
477 *
478 */
479 static int nsc_ircc_probe_108(nsc_chip_t *chip, chipio_t *info)
480 {
481 int cfg_base = info->cfg_base;
482 int reg;
483
484 /* Read address and interrupt control register (BAIC) */
485 outb(CFG_108_BAIC, cfg_base);
486 reg = inb(cfg_base+1);
487
488 switch (reg & 0x03) {
489 case 0:
490 info->fir_base = 0x3e8;
491 break;
492 case 1:
493 info->fir_base = 0x2e8;
494 break;
495 case 2:
496 info->fir_base = 0x3f8;
497 break;
498 case 3:
499 info->fir_base = 0x2f8;
500 break;
501 }
502 info->sir_base = info->fir_base;
503 IRDA_DEBUG(2, "%s(), probing fir_base=0x%03x\n", __FUNCTION__,
504 info->fir_base);
505
506 /* Read control signals routing register (CSRT) */
507 outb(CFG_108_CSRT, cfg_base);
508 reg = inb(cfg_base+1);
509
510 switch (reg & 0x07) {
511 case 0:
512 info->irq = -1;
513 break;
514 case 1:
515 info->irq = 3;
516 break;
517 case 2:
518 info->irq = 4;
519 break;
520 case 3:
521 info->irq = 5;
522 break;
523 case 4:
524 info->irq = 7;
525 break;
526 case 5:
527 info->irq = 9;
528 break;
529 case 6:
530 info->irq = 11;
531 break;
532 case 7:
533 info->irq = 15;
534 break;
535 }
536 IRDA_DEBUG(2, "%s(), probing irq=%d\n", __FUNCTION__, info->irq);
537
538 /* Currently we only read Rx DMA but it will also be used for Tx */
539 switch ((reg >> 3) & 0x03) {
540 case 0:
541 info->dma = -1;
542 break;
543 case 1:
544 info->dma = 0;
545 break;
546 case 2:
547 info->dma = 1;
548 break;
549 case 3:
550 info->dma = 3;
551 break;
552 }
553 IRDA_DEBUG(2, "%s(), probing dma=%d\n", __FUNCTION__, info->dma);
554
555 /* Read mode control register (MCTL) */
556 outb(CFG_108_MCTL, cfg_base);
557 reg = inb(cfg_base+1);
558
559 info->enabled = reg & 0x01;
560 info->suspended = !((reg >> 1) & 0x01);
561
562 return 0;
563 }
564
565 /*
566 * Function nsc_ircc_init_338 (chip, info)
567 *
568 * Initialize the NSC '338 chip. Remember that the 87338 needs two
569 * consecutive writes to the data registers while CPU interrupts are
570 * disabled. The 97338 does not require this, but shouldn't be any
571 * harm if we do it anyway.
572 */
573 static int nsc_ircc_init_338(nsc_chip_t *chip, chipio_t *info)
574 {
575 /* No init yet */
576
577 return 0;
578 }
579
580 /*
581 * Function nsc_ircc_probe_338 (chip, info)
582 *
583 *
584 *
585 */
586 static int nsc_ircc_probe_338(nsc_chip_t *chip, chipio_t *info)
587 {
588 int cfg_base = info->cfg_base;
589 int reg, com = 0;
590 int pnp;
591
592 /* Read funtion enable register (FER) */
593 outb(CFG_338_FER, cfg_base);
594 reg = inb(cfg_base+1);
595
596 info->enabled = (reg >> 2) & 0x01;
597
598 /* Check if we are in Legacy or PnP mode */
599 outb(CFG_338_PNP0, cfg_base);
600 reg = inb(cfg_base+1);
601
602 pnp = (reg >> 3) & 0x01;
603 if (pnp) {
604 IRDA_DEBUG(2, "(), Chip is in PnP mode\n");
605 outb(0x46, cfg_base);
606 reg = (inb(cfg_base+1) & 0xfe) << 2;
607
608 outb(0x47, cfg_base);
609 reg |= ((inb(cfg_base+1) & 0xfc) << 8);
610
611 info->fir_base = reg;
612 } else {
613 /* Read function address register (FAR) */
614 outb(CFG_338_FAR, cfg_base);
615 reg = inb(cfg_base+1);
616
617 switch ((reg >> 4) & 0x03) {
618 case 0:
619 info->fir_base = 0x3f8;
620 break;
621 case 1:
622 info->fir_base = 0x2f8;
623 break;
624 case 2:
625 com = 3;
626 break;
627 case 3:
628 com = 4;
629 break;
630 }
631
632 if (com) {
633 switch ((reg >> 6) & 0x03) {
634 case 0:
635 if (com == 3)
636 info->fir_base = 0x3e8;
637 else
638 info->fir_base = 0x2e8;
639 break;
640 case 1:
641 if (com == 3)
642 info->fir_base = 0x338;
643 else
644 info->fir_base = 0x238;
645 break;
646 case 2:
647 if (com == 3)
648 info->fir_base = 0x2e8;
649 else
650 info->fir_base = 0x2e0;
651 break;
652 case 3:
653 if (com == 3)
654 info->fir_base = 0x220;
655 else
656 info->fir_base = 0x228;
657 break;
658 }
659 }
660 }
661 info->sir_base = info->fir_base;
662
663 /* Read PnP register 1 (PNP1) */
664 outb(CFG_338_PNP1, cfg_base);
665 reg = inb(cfg_base+1);
666
667 info->irq = reg >> 4;
668
669 /* Read PnP register 3 (PNP3) */
670 outb(CFG_338_PNP3, cfg_base);
671 reg = inb(cfg_base+1);
672
673 info->dma = (reg & 0x07) - 1;
674
675 /* Read power and test register (PTR) */
676 outb(CFG_338_PTR, cfg_base);
677 reg = inb(cfg_base+1);
678
679 info->suspended = reg & 0x01;
680
681 return 0;
682 }
683
684
685 /*
686 * Function nsc_ircc_init_39x (chip, info)
687 *
688 * Now that we know it's a '39x (see probe below), we need to
689 * configure it so we can use it.
690 *
691 * The NSC '338 chip is a Super I/O chip with a "bank" architecture,
692 * the configuration of the different functionality (serial, parallel,
693 * floppy...) are each in a different bank (Logical Device Number).
694 * The base address, irq and dma configuration registers are common
695 * to all functionalities (index 0x30 to 0x7F).
696 * There is only one configuration register specific to the
697 * serial port, CFG_39X_SPC.
698 * JeanII
699 *
700 * Note : this code was written by Jan Frey <janfrey@web.de>
701 */
702 static int nsc_ircc_init_39x(nsc_chip_t *chip, chipio_t *info)
703 {
704 int cfg_base = info->cfg_base;
705 int enabled;
706
707 /* User is shure about his config... accept it. */
708 IRDA_DEBUG(2, "%s(): nsc_ircc_init_39x (user settings): "
709 "io=0x%04x, irq=%d, dma=%d\n",
710 __FUNCTION__, info->fir_base, info->irq, info->dma);
711
712 /* Access bank for SP2 */
713 outb(CFG_39X_LDN, cfg_base);
714 outb(0x02, cfg_base+1);
715
716 /* Configure SP2 */
717
718 /* We want to enable the device if not enabled */
719 outb(CFG_39X_ACT, cfg_base);
720 enabled = inb(cfg_base+1) & 0x01;
721
722 if (!enabled) {
723 /* Enable the device */
724 outb(CFG_39X_SIOCF1, cfg_base);
725 outb(0x01, cfg_base+1);
726 /* May want to update info->enabled. Jean II */
727 }
728
729 /* Enable UART bank switching (bit 7) ; Sets the chip to normal
730 * power mode (wake up from sleep mode) (bit 1) */
731 outb(CFG_39X_SPC, cfg_base);
732 outb(0x82, cfg_base+1);
733
734 return 0;
735 }
736
737 /*
738 * Function nsc_ircc_probe_39x (chip, info)
739 *
740 * Test if we really have a '39x chip at the given address
741 *
742 * Note : this code was written by Jan Frey <janfrey@web.de>
743 */
744 static int nsc_ircc_probe_39x(nsc_chip_t *chip, chipio_t *info)
745 {
746 int cfg_base = info->cfg_base;
747 int reg1, reg2, irq, irqt, dma1, dma2;
748 int enabled, susp;
749
750 IRDA_DEBUG(2, "%s(), nsc_ircc_probe_39x, base=%d\n",
751 __FUNCTION__, cfg_base);
752
753 /* This function should be executed with irq off to avoid
754 * another driver messing with the Super I/O bank - Jean II */
755
756 /* Access bank for SP2 */
757 outb(CFG_39X_LDN, cfg_base);
758 outb(0x02, cfg_base+1);
759
760 /* Read infos about SP2 ; store in info struct */
761 outb(CFG_39X_BASEH, cfg_base);
762 reg1 = inb(cfg_base+1);
763 outb(CFG_39X_BASEL, cfg_base);
764 reg2 = inb(cfg_base+1);
765 info->fir_base = (reg1 << 8) | reg2;
766
767 outb(CFG_39X_IRQNUM, cfg_base);
768 irq = inb(cfg_base+1);
769 outb(CFG_39X_IRQSEL, cfg_base);
770 irqt = inb(cfg_base+1);
771 info->irq = irq;
772
773 outb(CFG_39X_DMA0, cfg_base);
774 dma1 = inb(cfg_base+1);
775 outb(CFG_39X_DMA1, cfg_base);
776 dma2 = inb(cfg_base+1);
777 info->dma = dma1 -1;
778
779 outb(CFG_39X_ACT, cfg_base);
780 info->enabled = enabled = inb(cfg_base+1) & 0x01;
781
782 outb(CFG_39X_SPC, cfg_base);
783 susp = 1 - ((inb(cfg_base+1) & 0x02) >> 1);
784
785 IRDA_DEBUG(2, "%s(): io=0x%02x%02x, irq=%d (type %d), rxdma=%d, txdma=%d, enabled=%d (suspended=%d)\n", __FUNCTION__, reg1,reg2,irq,irqt,dma1,dma2,enabled,susp);
786
787 /* Configure SP2 */
788
789 /* We want to enable the device if not enabled */
790 outb(CFG_39X_ACT, cfg_base);
791 enabled = inb(cfg_base+1) & 0x01;
792
793 if (!enabled) {
794 /* Enable the device */
795 outb(CFG_39X_SIOCF1, cfg_base);
796 outb(0x01, cfg_base+1);
797 /* May want to update info->enabled. Jean II */
798 }
799
800 /* Enable UART bank switching (bit 7) ; Sets the chip to normal
801 * power mode (wake up from sleep mode) (bit 1) */
802 outb(CFG_39X_SPC, cfg_base);
803 outb(0x82, cfg_base+1);
804
805 return 0;
806 }
807
808 /*
809 * Function nsc_ircc_setup (info)
810 *
811 * Returns non-negative on success.
812 *
813 */
814 static int nsc_ircc_setup(chipio_t *info)
815 {
816 int version;
817 int iobase = info->fir_base;
818
819 /* Read the Module ID */
820 switch_bank(iobase, BANK3);
821 version = inb(iobase+MID);
822
823 IRDA_DEBUG(2, "%s() Driver %s Found chip version %02x\n",
824 __FUNCTION__, driver_name, version);
825
826 /* Should be 0x2? */
827 if (0x20 != (version & 0xf0)) {
828 IRDA_ERROR("%s, Wrong chip version %02x\n",
829 driver_name, version);
830 return -1;
831 }
832
833 /* Switch to advanced mode */
834 switch_bank(iobase, BANK2);
835 outb(ECR1_EXT_SL, iobase+ECR1);
836 switch_bank(iobase, BANK0);
837
838 /* Set FIFO threshold to TX17, RX16, reset and enable FIFO's */
839 switch_bank(iobase, BANK0);
840 outb(FCR_RXTH|FCR_TXTH|FCR_TXSR|FCR_RXSR|FCR_FIFO_EN, iobase+FCR);
841
842 outb(0x03, iobase+LCR); /* 8 bit word length */
843 outb(MCR_SIR, iobase+MCR); /* Start at SIR-mode, also clears LSR*/
844
845 /* Set FIFO size to 32 */
846 switch_bank(iobase, BANK2);
847 outb(EXCR2_RFSIZ|EXCR2_TFSIZ, iobase+EXCR2);
848
849 /* IRCR2: FEND_MD is not set */
850 switch_bank(iobase, BANK5);
851 outb(0x02, iobase+4);
852
853 /* Make sure that some defaults are OK */
854 switch_bank(iobase, BANK6);
855 outb(0x20, iobase+0); /* Set 32 bits FIR CRC */
856 outb(0x0a, iobase+1); /* Set MIR pulse width */
857 outb(0x0d, iobase+2); /* Set SIR pulse width to 1.6us */
858 outb(0x2a, iobase+4); /* Set beginning frag, and preamble length */
859
860 /* Enable receive interrupts */
861 switch_bank(iobase, BANK0);
862 outb(IER_RXHDL_IE, iobase+IER);
863
864 return 0;
865 }
866
867 /*
868 * Function nsc_ircc_read_dongle_id (void)
869 *
870 * Try to read dongle indentification. This procedure needs to be executed
871 * once after power-on/reset. It also needs to be used whenever you suspect
872 * that the user may have plugged/unplugged the IrDA Dongle.
873 */
874 static int nsc_ircc_read_dongle_id (int iobase)
875 {
876 int dongle_id;
877 __u8 bank;
878
879 bank = inb(iobase+BSR);
880
881 /* Select Bank 7 */
882 switch_bank(iobase, BANK7);
883
884 /* IRCFG4: IRSL0_DS and IRSL21_DS are cleared */
885 outb(0x00, iobase+7);
886
887 /* ID0, 1, and 2 are pulled up/down very slowly */
888 udelay(50);
889
890 /* IRCFG1: read the ID bits */
891 dongle_id = inb(iobase+4) & 0x0f;
892
893 #ifdef BROKEN_DONGLE_ID
894 if (dongle_id == 0x0a)
895 dongle_id = 0x09;
896 #endif
897 /* Go back to bank 0 before returning */
898 switch_bank(iobase, BANK0);
899
900 outb(bank, iobase+BSR);
901
902 return dongle_id;
903 }
904
905 /*
906 * Function nsc_ircc_init_dongle_interface (iobase, dongle_id)
907 *
908 * This function initializes the dongle for the transceiver that is
909 * used. This procedure needs to be executed once after
910 * power-on/reset. It also needs to be used whenever you suspect that
911 * the dongle is changed.
912 */
913 static void nsc_ircc_init_dongle_interface (int iobase, int dongle_id)
914 {
915 int bank;
916
917 /* Save current bank */
918 bank = inb(iobase+BSR);
919
920 /* Select Bank 7 */
921 switch_bank(iobase, BANK7);
922
923 /* IRCFG4: set according to dongle_id */
924 switch (dongle_id) {
925 case 0x00: /* same as */
926 case 0x01: /* Differential serial interface */
927 IRDA_DEBUG(0, "%s(), %s not defined by irda yet\n",
928 __FUNCTION__, dongle_types[dongle_id]);
929 break;
930 case 0x02: /* same as */
931 case 0x03: /* Reserved */
932 IRDA_DEBUG(0, "%s(), %s not defined by irda yet\n",
933 __FUNCTION__, dongle_types[dongle_id]);
934 break;
935 case 0x04: /* Sharp RY5HD01 */
936 break;
937 case 0x05: /* Reserved, but this is what the Thinkpad reports */
938 IRDA_DEBUG(0, "%s(), %s not defined by irda yet\n",
939 __FUNCTION__, dongle_types[dongle_id]);
940 break;
941 case 0x06: /* Single-ended serial interface */
942 IRDA_DEBUG(0, "%s(), %s not defined by irda yet\n",
943 __FUNCTION__, dongle_types[dongle_id]);
944 break;
945 case 0x07: /* Consumer-IR only */
946 IRDA_DEBUG(0, "%s(), %s is not for IrDA mode\n",
947 __FUNCTION__, dongle_types[dongle_id]);
948 break;
949 case 0x08: /* HP HSDL-2300, HP HSDL-3600/HSDL-3610 */
950 IRDA_DEBUG(0, "%s(), %s\n",
951 __FUNCTION__, dongle_types[dongle_id]);
952 break;
953 case 0x09: /* IBM31T1100 or Temic TFDS6000/TFDS6500 */
954 outb(0x28, iobase+7); /* Set irsl[0-2] as output */
955 break;
956 case 0x0A: /* same as */
957 case 0x0B: /* Reserved */
958 IRDA_DEBUG(0, "%s(), %s not defined by irda yet\n",
959 __FUNCTION__, dongle_types[dongle_id]);
960 break;
961 case 0x0C: /* same as */
962 case 0x0D: /* HP HSDL-1100/HSDL-2100 */
963 /*
964 * Set irsl0 as input, irsl[1-2] as output, and separate
965 * inputs are used for SIR and MIR/FIR
966 */
967 outb(0x48, iobase+7);
968 break;
969 case 0x0E: /* Supports SIR Mode only */
970 outb(0x28, iobase+7); /* Set irsl[0-2] as output */
971 break;
972 case 0x0F: /* No dongle connected */
973 IRDA_DEBUG(0, "%s(), %s\n",
974 __FUNCTION__, dongle_types[dongle_id]);
975
976 switch_bank(iobase, BANK0);
977 outb(0x62, iobase+MCR);
978 break;
979 default:
980 IRDA_DEBUG(0, "%s(), invalid dongle_id %#x",
981 __FUNCTION__, dongle_id);
982 }
983
984 /* IRCFG1: IRSL1 and 2 are set to IrDA mode */
985 outb(0x00, iobase+4);
986
987 /* Restore bank register */
988 outb(bank, iobase+BSR);
989
990 } /* set_up_dongle_interface */
991
992 /*
993 * Function nsc_ircc_change_dongle_speed (iobase, speed, dongle_id)
994 *
995 * Change speed of the attach dongle
996 *
997 */
998 static void nsc_ircc_change_dongle_speed(int iobase, int speed, int dongle_id)
999 {
1000 __u8 bank;
1001
1002 /* Save current bank */
1003 bank = inb(iobase+BSR);
1004
1005 /* Select Bank 7 */
1006 switch_bank(iobase, BANK7);
1007
1008 /* IRCFG1: set according to dongle_id */
1009 switch (dongle_id) {
1010 case 0x00: /* same as */
1011 case 0x01: /* Differential serial interface */
1012 IRDA_DEBUG(0, "%s(), %s not defined by irda yet\n",
1013 __FUNCTION__, dongle_types[dongle_id]);
1014 break;
1015 case 0x02: /* same as */
1016 case 0x03: /* Reserved */
1017 IRDA_DEBUG(0, "%s(), %s not defined by irda yet\n",
1018 __FUNCTION__, dongle_types[dongle_id]);
1019 break;
1020 case 0x04: /* Sharp RY5HD01 */
1021 break;
1022 case 0x05: /* Reserved */
1023 IRDA_DEBUG(0, "%s(), %s not defined by irda yet\n",
1024 __FUNCTION__, dongle_types[dongle_id]);
1025 break;
1026 case 0x06: /* Single-ended serial interface */
1027 IRDA_DEBUG(0, "%s(), %s not defined by irda yet\n",
1028 __FUNCTION__, dongle_types[dongle_id]);
1029 break;
1030 case 0x07: /* Consumer-IR only */
1031 IRDA_DEBUG(0, "%s(), %s is not for IrDA mode\n",
1032 __FUNCTION__, dongle_types[dongle_id]);
1033 break;
1034 case 0x08: /* HP HSDL-2300, HP HSDL-3600/HSDL-3610 */
1035 IRDA_DEBUG(0, "%s(), %s\n",
1036 __FUNCTION__, dongle_types[dongle_id]);
1037 outb(0x00, iobase+4);
1038 if (speed > 115200)
1039 outb(0x01, iobase+4);
1040 break;
1041 case 0x09: /* IBM31T1100 or Temic TFDS6000/TFDS6500 */
1042 outb(0x01, iobase+4);
1043
1044 if (speed == 4000000) {
1045 /* There was a cli() there, but we now are already
1046 * under spin_lock_irqsave() - JeanII */
1047 outb(0x81, iobase+4);
1048 outb(0x80, iobase+4);
1049 } else
1050 outb(0x00, iobase+4);
1051 break;
1052 case 0x0A: /* same as */
1053 case 0x0B: /* Reserved */
1054 IRDA_DEBUG(0, "%s(), %s not defined by irda yet\n",
1055 __FUNCTION__, dongle_types[dongle_id]);
1056 break;
1057 case 0x0C: /* same as */
1058 case 0x0D: /* HP HSDL-1100/HSDL-2100 */
1059 break;
1060 case 0x0E: /* Supports SIR Mode only */
1061 break;
1062 case 0x0F: /* No dongle connected */
1063 IRDA_DEBUG(0, "%s(), %s is not for IrDA mode\n",
1064 __FUNCTION__, dongle_types[dongle_id]);
1065
1066 switch_bank(iobase, BANK0);
1067 outb(0x62, iobase+MCR);
1068 break;
1069 default:
1070 IRDA_DEBUG(0, "%s(), invalid data_rate\n", __FUNCTION__);
1071 }
1072 /* Restore bank register */
1073 outb(bank, iobase+BSR);
1074 }
1075
1076 /*
1077 * Function nsc_ircc_change_speed (self, baud)
1078 *
1079 * Change the speed of the device
1080 *
1081 * This function *must* be called with irq off and spin-lock.
1082 */
1083 static __u8 nsc_ircc_change_speed(struct nsc_ircc_cb *self, __u32 speed)
1084 {
1085 struct net_device *dev = self->netdev;
1086 __u8 mcr = MCR_SIR;
1087 int iobase;
1088 __u8 bank;
1089 __u8 ier; /* Interrupt enable register */
1090
1091 IRDA_DEBUG(2, "%s(), speed=%d\n", __FUNCTION__, speed);
1092
1093 IRDA_ASSERT(self != NULL, return 0;);
1094
1095 iobase = self->io.fir_base;
1096
1097 /* Update accounting for new speed */
1098 self->io.speed = speed;
1099
1100 /* Save current bank */
1101 bank = inb(iobase+BSR);
1102
1103 /* Disable interrupts */
1104 switch_bank(iobase, BANK0);
1105 outb(0, iobase+IER);
1106
1107 /* Select Bank 2 */
1108 switch_bank(iobase, BANK2);
1109
1110 outb(0x00, iobase+BGDH);
1111 switch (speed) {
1112 case 9600: outb(0x0c, iobase+BGDL); break;
1113 case 19200: outb(0x06, iobase+BGDL); break;
1114 case 38400: outb(0x03, iobase+BGDL); break;
1115 case 57600: outb(0x02, iobase+BGDL); break;
1116 case 115200: outb(0x01, iobase+BGDL); break;
1117 case 576000:
1118 switch_bank(iobase, BANK5);
1119
1120 /* IRCR2: MDRS is set */
1121 outb(inb(iobase+4) | 0x04, iobase+4);
1122
1123 mcr = MCR_MIR;
1124 IRDA_DEBUG(0, "%s(), handling baud of 576000\n", __FUNCTION__);
1125 break;
1126 case 1152000:
1127 mcr = MCR_MIR;
1128 IRDA_DEBUG(0, "%s(), handling baud of 1152000\n", __FUNCTION__);
1129 break;
1130 case 4000000:
1131 mcr = MCR_FIR;
1132 IRDA_DEBUG(0, "%s(), handling baud of 4000000\n", __FUNCTION__);
1133 break;
1134 default:
1135 mcr = MCR_FIR;
1136 IRDA_DEBUG(0, "%s(), unknown baud rate of %d\n",
1137 __FUNCTION__, speed);
1138 break;
1139 }
1140
1141 /* Set appropriate speed mode */
1142 switch_bank(iobase, BANK0);
1143 outb(mcr | MCR_TX_DFR, iobase+MCR);
1144
1145 /* Give some hits to the transceiver */
1146 nsc_ircc_change_dongle_speed(iobase, speed, self->io.dongle_id);
1147
1148 /* Set FIFO threshold to TX17, RX16 */
1149 switch_bank(iobase, BANK0);
1150 outb(0x00, iobase+FCR);
1151 outb(FCR_FIFO_EN, iobase+FCR);
1152 outb(FCR_RXTH| /* Set Rx FIFO threshold */
1153 FCR_TXTH| /* Set Tx FIFO threshold */
1154 FCR_TXSR| /* Reset Tx FIFO */
1155 FCR_RXSR| /* Reset Rx FIFO */
1156 FCR_FIFO_EN, /* Enable FIFOs */
1157 iobase+FCR);
1158
1159 /* Set FIFO size to 32 */
1160 switch_bank(iobase, BANK2);
1161 outb(EXCR2_RFSIZ|EXCR2_TFSIZ, iobase+EXCR2);
1162
1163 /* Enable some interrupts so we can receive frames */
1164 switch_bank(iobase, BANK0);
1165 if (speed > 115200) {
1166 /* Install FIR xmit handler */
1167 dev->hard_start_xmit = nsc_ircc_hard_xmit_fir;
1168 ier = IER_SFIF_IE;
1169 nsc_ircc_dma_receive(self);
1170 } else {
1171 /* Install SIR xmit handler */
1172 dev->hard_start_xmit = nsc_ircc_hard_xmit_sir;
1173 ier = IER_RXHDL_IE;
1174 }
1175 /* Set our current interrupt mask */
1176 outb(ier, iobase+IER);
1177
1178 /* Restore BSR */
1179 outb(bank, iobase+BSR);
1180
1181 /* Make sure interrupt handlers keep the proper interrupt mask */
1182 return(ier);
1183 }
1184
1185 /*
1186 * Function nsc_ircc_hard_xmit (skb, dev)
1187 *
1188 * Transmit the frame!
1189 *
1190 */
1191 static int nsc_ircc_hard_xmit_sir(struct sk_buff *skb, struct net_device *dev)
1192 {
1193 struct nsc_ircc_cb *self;
1194 unsigned long flags;
1195 int iobase;
1196 __s32 speed;
1197 __u8 bank;
1198
1199 self = (struct nsc_ircc_cb *) dev->priv;
1200
1201 IRDA_ASSERT(self != NULL, return 0;);
1202
1203 iobase = self->io.fir_base;
1204
1205 netif_stop_queue(dev);
1206
1207 /* Make sure tests *& speed change are atomic */
1208 spin_lock_irqsave(&self->lock, flags);
1209
1210 /* Check if we need to change the speed */
1211 speed = irda_get_next_speed(skb);
1212 if ((speed != self->io.speed) && (speed != -1)) {
1213 /* Check for empty frame. */
1214 if (!skb->len) {
1215 /* If we just sent a frame, we get called before
1216 * the last bytes get out (because of the SIR FIFO).
1217 * If this is the case, let interrupt handler change
1218 * the speed itself... Jean II */
1219 if (self->io.direction == IO_RECV) {
1220 nsc_ircc_change_speed(self, speed);
1221 /* TODO : For SIR->SIR, the next packet
1222 * may get corrupted - Jean II */
1223 netif_wake_queue(dev);
1224 } else {
1225 self->new_speed = speed;
1226 /* Queue will be restarted after speed change
1227 * to make sure packets gets through the
1228 * proper xmit handler - Jean II */
1229 }
1230 dev->trans_start = jiffies;
1231 spin_unlock_irqrestore(&self->lock, flags);
1232 dev_kfree_skb(skb);
1233 return 0;
1234 } else
1235 self->new_speed = speed;
1236 }
1237
1238 /* Save current bank */
1239 bank = inb(iobase+BSR);
1240
1241 self->tx_buff.data = self->tx_buff.head;
1242
1243 self->tx_buff.len = async_wrap_skb(skb, self->tx_buff.data,
1244 self->tx_buff.truesize);
1245
1246 self->stats.tx_bytes += self->tx_buff.len;
1247
1248 /* Add interrupt on tx low level (will fire immediately) */
1249 switch_bank(iobase, BANK0);
1250 outb(IER_TXLDL_IE, iobase+IER);
1251
1252 /* Restore bank register */
1253 outb(bank, iobase+BSR);
1254
1255 dev->trans_start = jiffies;
1256 spin_unlock_irqrestore(&self->lock, flags);
1257
1258 dev_kfree_skb(skb);
1259
1260 return 0;
1261 }
1262
1263 static int nsc_ircc_hard_xmit_fir(struct sk_buff *skb, struct net_device *dev)
1264 {
1265 struct nsc_ircc_cb *self;
1266 unsigned long flags;
1267 int iobase;
1268 __s32 speed;
1269 __u8 bank;
1270 int mtt, diff;
1271
1272 self = (struct nsc_ircc_cb *) dev->priv;
1273 iobase = self->io.fir_base;
1274
1275 netif_stop_queue(dev);
1276
1277 /* Make sure tests *& speed change are atomic */
1278 spin_lock_irqsave(&self->lock, flags);
1279
1280 /* Check if we need to change the speed */
1281 speed = irda_get_next_speed(skb);
1282 if ((speed != self->io.speed) && (speed != -1)) {
1283 /* Check for empty frame. */
1284 if (!skb->len) {
1285 /* If we are currently transmitting, defer to
1286 * interrupt handler. - Jean II */
1287 if(self->tx_fifo.len == 0) {
1288 nsc_ircc_change_speed(self, speed);
1289 netif_wake_queue(dev);
1290 } else {
1291 self->new_speed = speed;
1292 /* Keep queue stopped :
1293 * the speed change operation may change the
1294 * xmit handler, and we want to make sure
1295 * the next packet get through the proper
1296 * Tx path, so block the Tx queue until
1297 * the speed change has been done.
1298 * Jean II */
1299 }
1300 dev->trans_start = jiffies;
1301 spin_unlock_irqrestore(&self->lock, flags);
1302 dev_kfree_skb(skb);
1303 return 0;
1304 } else {
1305 /* Change speed after current frame */
1306 self->new_speed = speed;
1307 }
1308 }
1309
1310 /* Save current bank */
1311 bank = inb(iobase+BSR);
1312
1313 /* Register and copy this frame to DMA memory */
1314 self->tx_fifo.queue[self->tx_fifo.free].start = self->tx_fifo.tail;
1315 self->tx_fifo.queue[self->tx_fifo.free].len = skb->len;
1316 self->tx_fifo.tail += skb->len;
1317
1318 self->stats.tx_bytes += skb->len;
1319
1320 memcpy(self->tx_fifo.queue[self->tx_fifo.free].start, skb->data,
1321 skb->len);
1322
1323 self->tx_fifo.len++;
1324 self->tx_fifo.free++;
1325
1326 /* Start transmit only if there is currently no transmit going on */
1327 if (self->tx_fifo.len == 1) {
1328 /* Check if we must wait the min turn time or not */
1329 mtt = irda_get_mtt(skb);
1330 if (mtt) {
1331 /* Check how much time we have used already */
1332 do_gettimeofday(&self->now);
1333 diff = self->now.tv_usec - self->stamp.tv_usec;
1334 if (diff < 0)
1335 diff += 1000000;
1336
1337 /* Check if the mtt is larger than the time we have
1338 * already used by all the protocol processing
1339 */
1340 if (mtt > diff) {
1341 mtt -= diff;
1342
1343 /*
1344 * Use timer if delay larger than 125 us, and
1345 * use udelay for smaller values which should
1346 * be acceptable
1347 */
1348 if (mtt > 125) {
1349 /* Adjust for timer resolution */
1350 mtt = mtt / 125;
1351
1352 /* Setup timer */
1353 switch_bank(iobase, BANK4);
1354 outb(mtt & 0xff, iobase+TMRL);
1355 outb((mtt >> 8) & 0x0f, iobase+TMRH);
1356
1357 /* Start timer */
1358 outb(IRCR1_TMR_EN, iobase+IRCR1);
1359 self->io.direction = IO_XMIT;
1360
1361 /* Enable timer interrupt */
1362 switch_bank(iobase, BANK0);
1363 outb(IER_TMR_IE, iobase+IER);
1364
1365 /* Timer will take care of the rest */
1366 goto out;
1367 } else
1368 udelay(mtt);
1369 }
1370 }
1371 /* Enable DMA interrupt */
1372 switch_bank(iobase, BANK0);
1373 outb(IER_DMA_IE, iobase+IER);
1374
1375 /* Transmit frame */
1376 nsc_ircc_dma_xmit(self, iobase);
1377 }
1378 out:
1379 /* Not busy transmitting anymore if window is not full,
1380 * and if we don't need to change speed */
1381 if ((self->tx_fifo.free < MAX_TX_WINDOW) && (self->new_speed == 0))
1382 netif_wake_queue(self->netdev);
1383
1384 /* Restore bank register */
1385 outb(bank, iobase+BSR);
1386
1387 dev->trans_start = jiffies;
1388 spin_unlock_irqrestore(&self->lock, flags);
1389 dev_kfree_skb(skb);
1390
1391 return 0;
1392 }
1393
1394 /*
1395 * Function nsc_ircc_dma_xmit (self, iobase)
1396 *
1397 * Transmit data using DMA
1398 *
1399 */
1400 static void nsc_ircc_dma_xmit(struct nsc_ircc_cb *self, int iobase)
1401 {
1402 int bsr;
1403
1404 /* Save current bank */
1405 bsr = inb(iobase+BSR);
1406
1407 /* Disable DMA */
1408 switch_bank(iobase, BANK0);
1409 outb(inb(iobase+MCR) & ~MCR_DMA_EN, iobase+MCR);
1410
1411 self->io.direction = IO_XMIT;
1412
1413 /* Choose transmit DMA channel */
1414 switch_bank(iobase, BANK2);
1415 outb(ECR1_DMASWP|ECR1_DMANF|ECR1_EXT_SL, iobase+ECR1);
1416
1417 irda_setup_dma(self->io.dma,
1418 ((u8 *)self->tx_fifo.queue[self->tx_fifo.ptr].start -
1419 self->tx_buff.head) + self->tx_buff_dma,
1420 self->tx_fifo.queue[self->tx_fifo.ptr].len,
1421 DMA_TX_MODE);
1422
1423 /* Enable DMA and SIR interaction pulse */
1424 switch_bank(iobase, BANK0);
1425 outb(inb(iobase+MCR)|MCR_TX_DFR|MCR_DMA_EN|MCR_IR_PLS, iobase+MCR);
1426
1427 /* Restore bank register */
1428 outb(bsr, iobase+BSR);
1429 }
1430
1431 /*
1432 * Function nsc_ircc_pio_xmit (self, iobase)
1433 *
1434 * Transmit data using PIO. Returns the number of bytes that actually
1435 * got transferred
1436 *
1437 */
1438 static int nsc_ircc_pio_write(int iobase, __u8 *buf, int len, int fifo_size)
1439 {
1440 int actual = 0;
1441 __u8 bank;
1442
1443 IRDA_DEBUG(4, "%s()\n", __FUNCTION__);
1444
1445 /* Save current bank */
1446 bank = inb(iobase+BSR);
1447
1448 switch_bank(iobase, BANK0);
1449 if (!(inb_p(iobase+LSR) & LSR_TXEMP)) {
1450 IRDA_DEBUG(4, "%s(), warning, FIFO not empty yet!\n",
1451 __FUNCTION__);
1452
1453 /* FIFO may still be filled to the Tx interrupt threshold */
1454 fifo_size -= 17;
1455 }
1456
1457 /* Fill FIFO with current frame */
1458 while ((fifo_size-- > 0) && (actual < len)) {
1459 /* Transmit next byte */
1460 outb(buf[actual++], iobase+TXD);
1461 }
1462
1463 IRDA_DEBUG(4, "%s(), fifo_size %d ; %d sent of %d\n",
1464 __FUNCTION__, fifo_size, actual, len);
1465
1466 /* Restore bank */
1467 outb(bank, iobase+BSR);
1468
1469 return actual;
1470 }
1471
1472 /*
1473 * Function nsc_ircc_dma_xmit_complete (self)
1474 *
1475 * The transfer of a frame in finished. This function will only be called
1476 * by the interrupt handler
1477 *
1478 */
1479 static int nsc_ircc_dma_xmit_complete(struct nsc_ircc_cb *self)
1480 {
1481 int iobase;
1482 __u8 bank;
1483 int ret = TRUE;
1484
1485 IRDA_DEBUG(2, "%s()\n", __FUNCTION__);
1486
1487 iobase = self->io.fir_base;
1488
1489 /* Save current bank */
1490 bank = inb(iobase+BSR);
1491
1492 /* Disable DMA */
1493 switch_bank(iobase, BANK0);
1494 outb(inb(iobase+MCR) & ~MCR_DMA_EN, iobase+MCR);
1495
1496 /* Check for underrrun! */
1497 if (inb(iobase+ASCR) & ASCR_TXUR) {
1498 self->stats.tx_errors++;
1499 self->stats.tx_fifo_errors++;
1500
1501 /* Clear bit, by writing 1 into it */
1502 outb(ASCR_TXUR, iobase+ASCR);
1503 } else {
1504 self->stats.tx_packets++;
1505 }
1506
1507 /* Finished with this frame, so prepare for next */
1508 self->tx_fifo.ptr++;
1509 self->tx_fifo.len--;
1510
1511 /* Any frames to be sent back-to-back? */
1512 if (self->tx_fifo.len) {
1513 nsc_ircc_dma_xmit(self, iobase);
1514
1515 /* Not finished yet! */
1516 ret = FALSE;
1517 } else {
1518 /* Reset Tx FIFO info */
1519 self->tx_fifo.len = self->tx_fifo.ptr = self->tx_fifo.free = 0;
1520 self->tx_fifo.tail = self->tx_buff.head;
1521 }
1522
1523 /* Make sure we have room for more frames and
1524 * that we don't need to change speed */
1525 if ((self->tx_fifo.free < MAX_TX_WINDOW) && (self->new_speed == 0)) {
1526 /* Not busy transmitting anymore */
1527 /* Tell the network layer, that we can accept more frames */
1528 netif_wake_queue(self->netdev);
1529 }
1530
1531 /* Restore bank */
1532 outb(bank, iobase+BSR);
1533
1534 return ret;
1535 }
1536
1537 /*
1538 * Function nsc_ircc_dma_receive (self)
1539 *
1540 * Get ready for receiving a frame. The device will initiate a DMA
1541 * if it starts to receive a frame.
1542 *
1543 */
1544 static int nsc_ircc_dma_receive(struct nsc_ircc_cb *self)
1545 {
1546 int iobase;
1547 __u8 bsr;
1548
1549 iobase = self->io.fir_base;
1550
1551 /* Reset Tx FIFO info */
1552 self->tx_fifo.len = self->tx_fifo.ptr = self->tx_fifo.free = 0;
1553 self->tx_fifo.tail = self->tx_buff.head;
1554
1555 /* Save current bank */
1556 bsr = inb(iobase+BSR);
1557
1558 /* Disable DMA */
1559 switch_bank(iobase, BANK0);
1560 outb(inb(iobase+MCR) & ~MCR_DMA_EN, iobase+MCR);
1561
1562 /* Choose DMA Rx, DMA Fairness, and Advanced mode */
1563 switch_bank(iobase, BANK2);
1564 outb(ECR1_DMANF|ECR1_EXT_SL, iobase+ECR1);
1565
1566 self->io.direction = IO_RECV;
1567 self->rx_buff.data = self->rx_buff.head;
1568
1569 /* Reset Rx FIFO. This will also flush the ST_FIFO */
1570 switch_bank(iobase, BANK0);
1571 outb(FCR_RXSR|FCR_FIFO_EN, iobase+FCR);
1572
1573 self->st_fifo.len = self->st_fifo.pending_bytes = 0;
1574 self->st_fifo.tail = self->st_fifo.head = 0;
1575
1576 irda_setup_dma(self->io.dma, self->rx_buff_dma, self->rx_buff.truesize,
1577 DMA_RX_MODE);
1578
1579 /* Enable DMA */
1580 switch_bank(iobase, BANK0);
1581 outb(inb(iobase+MCR)|MCR_DMA_EN, iobase+MCR);
1582
1583 /* Restore bank register */
1584 outb(bsr, iobase+BSR);
1585
1586 return 0;
1587 }
1588
1589 /*
1590 * Function nsc_ircc_dma_receive_complete (self)
1591 *
1592 * Finished with receiving frames
1593 *
1594 *
1595 */
1596 static int nsc_ircc_dma_receive_complete(struct nsc_ircc_cb *self, int iobase)
1597 {
1598 struct st_fifo *st_fifo;
1599 struct sk_buff *skb;
1600 __u8 status;
1601 __u8 bank;
1602 int len;
1603
1604 st_fifo = &self->st_fifo;
1605
1606 /* Save current bank */
1607 bank = inb(iobase+BSR);
1608
1609 /* Read all entries in status FIFO */
1610 switch_bank(iobase, BANK5);
1611 while ((status = inb(iobase+FRM_ST)) & FRM_ST_VLD) {
1612 /* We must empty the status FIFO no matter what */
1613 len = inb(iobase+RFLFL) | ((inb(iobase+RFLFH) & 0x1f) << 8);
1614
1615 if (st_fifo->tail >= MAX_RX_WINDOW) {
1616 IRDA_DEBUG(0, "%s(), window is full!\n", __FUNCTION__);
1617 continue;
1618 }
1619
1620 st_fifo->entries[st_fifo->tail].status = status;
1621 st_fifo->entries[st_fifo->tail].len = len;
1622 st_fifo->pending_bytes += len;
1623 st_fifo->tail++;
1624 st_fifo->len++;
1625 }
1626 /* Try to process all entries in status FIFO */
1627 while (st_fifo->len > 0) {
1628 /* Get first entry */
1629 status = st_fifo->entries[st_fifo->head].status;
1630 len = st_fifo->entries[st_fifo->head].len;
1631 st_fifo->pending_bytes -= len;
1632 st_fifo->head++;
1633 st_fifo->len--;
1634
1635 /* Check for errors */
1636 if (status & FRM_ST_ERR_MSK) {
1637 if (status & FRM_ST_LOST_FR) {
1638 /* Add number of lost frames to stats */
1639 self->stats.rx_errors += len;
1640 } else {
1641 /* Skip frame */
1642 self->stats.rx_errors++;
1643
1644 self->rx_buff.data += len;
1645
1646 if (status & FRM_ST_MAX_LEN)
1647 self->stats.rx_length_errors++;
1648
1649 if (status & FRM_ST_PHY_ERR)
1650 self->stats.rx_frame_errors++;
1651
1652 if (status & FRM_ST_BAD_CRC)
1653 self->stats.rx_crc_errors++;
1654 }
1655 /* The errors below can be reported in both cases */
1656 if (status & FRM_ST_OVR1)
1657 self->stats.rx_fifo_errors++;
1658
1659 if (status & FRM_ST_OVR2)
1660 self->stats.rx_fifo_errors++;
1661 } else {
1662 /*
1663 * First we must make sure that the frame we
1664 * want to deliver is all in main memory. If we
1665 * cannot tell, then we check if the Rx FIFO is
1666 * empty. If not then we will have to take a nap
1667 * and try again later.
1668 */
1669 if (st_fifo->pending_bytes < self->io.fifo_size) {
1670 switch_bank(iobase, BANK0);
1671 if (inb(iobase+LSR) & LSR_RXDA) {
1672 /* Put this entry back in fifo */
1673 st_fifo->head--;
1674 st_fifo->len++;
1675 st_fifo->pending_bytes += len;
1676 st_fifo->entries[st_fifo->head].status = status;
1677 st_fifo->entries[st_fifo->head].len = len;
1678 /*
1679 * DMA not finished yet, so try again
1680 * later, set timer value, resolution
1681 * 125 us
1682 */
1683 switch_bank(iobase, BANK4);
1684 outb(0x02, iobase+TMRL); /* x 125 us */
1685 outb(0x00, iobase+TMRH);
1686
1687 /* Start timer */
1688 outb(IRCR1_TMR_EN, iobase+IRCR1);
1689
1690 /* Restore bank register */
1691 outb(bank, iobase+BSR);
1692
1693 return FALSE; /* I'll be back! */
1694 }
1695 }
1696
1697 /*
1698 * Remember the time we received this frame, so we can
1699 * reduce the min turn time a bit since we will know
1700 * how much time we have used for protocol processing
1701 */
1702 do_gettimeofday(&self->stamp);
1703
1704 skb = dev_alloc_skb(len+1);
1705 if (skb == NULL) {
1706 IRDA_WARNING("%s(), memory squeeze, "
1707 "dropping frame.\n",
1708 __FUNCTION__);
1709 self->stats.rx_dropped++;
1710
1711 /* Restore bank register */
1712 outb(bank, iobase+BSR);
1713
1714 return FALSE;
1715 }
1716
1717 /* Make sure IP header gets aligned */
1718 skb_reserve(skb, 1);
1719
1720 /* Copy frame without CRC */
1721 if (self->io.speed < 4000000) {
1722 skb_put(skb, len-2);
1723 memcpy(skb->data, self->rx_buff.data, len-2);
1724 } else {
1725 skb_put(skb, len-4);
1726 memcpy(skb->data, self->rx_buff.data, len-4);
1727 }
1728
1729 /* Move to next frame */
1730 self->rx_buff.data += len;
1731 self->stats.rx_bytes += len;
1732 self->stats.rx_packets++;
1733
1734 skb->dev = self->netdev;
1735 skb->mac.raw = skb->data;
1736 skb->protocol = htons(ETH_P_IRDA);
1737 netif_rx(skb);
1738 self->netdev->last_rx = jiffies;
1739 }
1740 }
1741 /* Restore bank register */
1742 outb(bank, iobase+BSR);
1743
1744 return TRUE;
1745 }
1746
1747 /*
1748 * Function nsc_ircc_pio_receive (self)
1749 *
1750 * Receive all data in receiver FIFO
1751 *
1752 */
1753 static void nsc_ircc_pio_receive(struct nsc_ircc_cb *self)
1754 {
1755 __u8 byte;
1756 int iobase;
1757
1758 iobase = self->io.fir_base;
1759
1760 /* Receive all characters in Rx FIFO */
1761 do {
1762 byte = inb(iobase+RXD);
1763 async_unwrap_char(self->netdev, &self->stats, &self->rx_buff,
1764 byte);
1765 } while (inb(iobase+LSR) & LSR_RXDA); /* Data available */
1766 }
1767
1768 /*
1769 * Function nsc_ircc_sir_interrupt (self, eir)
1770 *
1771 * Handle SIR interrupt
1772 *
1773 */
1774 static void nsc_ircc_sir_interrupt(struct nsc_ircc_cb *self, int eir)
1775 {
1776 int actual;
1777
1778 /* Check if transmit FIFO is low on data */
1779 if (eir & EIR_TXLDL_EV) {
1780 /* Write data left in transmit buffer */
1781 actual = nsc_ircc_pio_write(self->io.fir_base,
1782 self->tx_buff.data,
1783 self->tx_buff.len,
1784 self->io.fifo_size);
1785 self->tx_buff.data += actual;
1786 self->tx_buff.len -= actual;
1787
1788 self->io.direction = IO_XMIT;
1789
1790 /* Check if finished */
1791 if (self->tx_buff.len > 0)
1792 self->ier = IER_TXLDL_IE;
1793 else {
1794
1795 self->stats.tx_packets++;
1796 netif_wake_queue(self->netdev);
1797 self->ier = IER_TXEMP_IE;
1798 }
1799
1800 }
1801 /* Check if transmission has completed */
1802 if (eir & EIR_TXEMP_EV) {
1803 /* Turn around and get ready to receive some data */
1804 self->io.direction = IO_RECV;
1805 self->ier = IER_RXHDL_IE;
1806 /* Check if we need to change the speed?
1807 * Need to be after self->io.direction to avoid race with
1808 * nsc_ircc_hard_xmit_sir() - Jean II */
1809 if (self->new_speed) {
1810 IRDA_DEBUG(2, "%s(), Changing speed!\n", __FUNCTION__);
1811 self->ier = nsc_ircc_change_speed(self,
1812 self->new_speed);
1813 self->new_speed = 0;
1814 netif_wake_queue(self->netdev);
1815
1816 /* Check if we are going to FIR */
1817 if (self->io.speed > 115200) {
1818 /* No need to do anymore SIR stuff */
1819 return;
1820 }
1821 }
1822 }
1823
1824 /* Rx FIFO threshold or timeout */
1825 if (eir & EIR_RXHDL_EV) {
1826 nsc_ircc_pio_receive(self);
1827
1828 /* Keep receiving */
1829 self->ier = IER_RXHDL_IE;
1830 }
1831 }
1832
1833 /*
1834 * Function nsc_ircc_fir_interrupt (self, eir)
1835 *
1836 * Handle MIR/FIR interrupt
1837 *
1838 */
1839 static void nsc_ircc_fir_interrupt(struct nsc_ircc_cb *self, int iobase,
1840 int eir)
1841 {
1842 __u8 bank;
1843
1844 bank = inb(iobase+BSR);
1845
1846 /* Status FIFO event*/
1847 if (eir & EIR_SFIF_EV) {
1848 /* Check if DMA has finished */
1849 if (nsc_ircc_dma_receive_complete(self, iobase)) {
1850 /* Wait for next status FIFO interrupt */
1851 self->ier = IER_SFIF_IE;
1852 } else {
1853 self->ier = IER_SFIF_IE | IER_TMR_IE;
1854 }
1855 } else if (eir & EIR_TMR_EV) { /* Timer finished */
1856 /* Disable timer */
1857 switch_bank(iobase, BANK4);
1858 outb(0, iobase+IRCR1);
1859
1860 /* Clear timer event */
1861 switch_bank(iobase, BANK0);
1862 outb(ASCR_CTE, iobase+ASCR);
1863
1864 /* Check if this is a Tx timer interrupt */
1865 if (self->io.direction == IO_XMIT) {
1866 nsc_ircc_dma_xmit(self, iobase);
1867
1868 /* Interrupt on DMA */
1869 self->ier = IER_DMA_IE;
1870 } else {
1871 /* Check (again) if DMA has finished */
1872 if (nsc_ircc_dma_receive_complete(self, iobase)) {
1873 self->ier = IER_SFIF_IE;
1874 } else {
1875 self->ier = IER_SFIF_IE | IER_TMR_IE;
1876 }
1877 }
1878 } else if (eir & EIR_DMA_EV) {
1879 /* Finished with all transmissions? */
1880 if (nsc_ircc_dma_xmit_complete(self)) {
1881 if(self->new_speed != 0) {
1882 /* As we stop the Tx queue, the speed change
1883 * need to be done when the Tx fifo is
1884 * empty. Ask for a Tx done interrupt */
1885 self->ier = IER_TXEMP_IE;
1886 } else {
1887 /* Check if there are more frames to be
1888 * transmitted */
1889 if (irda_device_txqueue_empty(self->netdev)) {
1890 /* Prepare for receive */
1891 nsc_ircc_dma_receive(self);
1892 self->ier = IER_SFIF_IE;
1893 } else
1894 IRDA_WARNING("%s(), potential "
1895 "Tx queue lockup !\n",
1896 __FUNCTION__);
1897 }
1898 } else {
1899 /* Not finished yet, so interrupt on DMA again */
1900 self->ier = IER_DMA_IE;
1901 }
1902 } else if (eir & EIR_TXEMP_EV) {
1903 /* The Tx FIFO has totally drained out, so now we can change
1904 * the speed... - Jean II */
1905 self->ier = nsc_ircc_change_speed(self, self->new_speed);
1906 self->new_speed = 0;
1907 netif_wake_queue(self->netdev);
1908 /* Note : nsc_ircc_change_speed() restarted Rx fifo */
1909 }
1910
1911 outb(bank, iobase+BSR);
1912 }
1913
1914 /*
1915 * Function nsc_ircc_interrupt (irq, dev_id, regs)
1916 *
1917 * An interrupt from the chip has arrived. Time to do some work
1918 *
1919 */
1920 static irqreturn_t nsc_ircc_interrupt(int irq, void *dev_id,
1921 struct pt_regs *regs)
1922 {
1923 struct net_device *dev = (struct net_device *) dev_id;
1924 struct nsc_ircc_cb *self;
1925 __u8 bsr, eir;
1926 int iobase;
1927
1928 if (!dev) {
1929 IRDA_WARNING("%s: irq %d for unknown device.\n",
1930 driver_name, irq);
1931 return IRQ_NONE;
1932 }
1933 self = (struct nsc_ircc_cb *) dev->priv;
1934
1935 spin_lock(&self->lock);
1936
1937 iobase = self->io.fir_base;
1938
1939 bsr = inb(iobase+BSR); /* Save current bank */
1940
1941 switch_bank(iobase, BANK0);
1942 self->ier = inb(iobase+IER);
1943 eir = inb(iobase+EIR) & self->ier; /* Mask out the interesting ones */
1944
1945 outb(0, iobase+IER); /* Disable interrupts */
1946
1947 if (eir) {
1948 /* Dispatch interrupt handler for the current speed */
1949 if (self->io.speed > 115200)
1950 nsc_ircc_fir_interrupt(self, iobase, eir);
1951 else
1952 nsc_ircc_sir_interrupt(self, eir);
1953 }
1954
1955 outb(self->ier, iobase+IER); /* Restore interrupts */
1956 outb(bsr, iobase+BSR); /* Restore bank register */
1957
1958 spin_unlock(&self->lock);
1959 return IRQ_RETVAL(eir);
1960 }
1961
1962 /*
1963 * Function nsc_ircc_is_receiving (self)
1964 *
1965 * Return TRUE is we are currently receiving a frame
1966 *
1967 */
1968 static int nsc_ircc_is_receiving(struct nsc_ircc_cb *self)
1969 {
1970 unsigned long flags;
1971 int status = FALSE;
1972 int iobase;
1973 __u8 bank;
1974
1975 IRDA_ASSERT(self != NULL, return FALSE;);
1976
1977 spin_lock_irqsave(&self->lock, flags);
1978
1979 if (self->io.speed > 115200) {
1980 iobase = self->io.fir_base;
1981
1982 /* Check if rx FIFO is not empty */
1983 bank = inb(iobase+BSR);
1984 switch_bank(iobase, BANK2);
1985 if ((inb(iobase+RXFLV) & 0x3f) != 0) {
1986 /* We are receiving something */
1987 status = TRUE;
1988 }
1989 outb(bank, iobase+BSR);
1990 } else
1991 status = (self->rx_buff.state != OUTSIDE_FRAME);
1992
1993 spin_unlock_irqrestore(&self->lock, flags);
1994
1995 return status;
1996 }
1997
1998 /*
1999 * Function nsc_ircc_net_open (dev)
2000 *
2001 * Start the device
2002 *
2003 */
2004 static int nsc_ircc_net_open(struct net_device *dev)
2005 {
2006 struct nsc_ircc_cb *self;
2007 int iobase;
2008 char hwname[32];
2009 __u8 bank;
2010
2011 IRDA_DEBUG(4, "%s()\n", __FUNCTION__);
2012
2013 IRDA_ASSERT(dev != NULL, return -1;);
2014 self = (struct nsc_ircc_cb *) dev->priv;
2015
2016 IRDA_ASSERT(self != NULL, return 0;);
2017
2018 iobase = self->io.fir_base;
2019
2020 if (request_irq(self->io.irq, nsc_ircc_interrupt, 0, dev->name, dev)) {
2021 IRDA_WARNING("%s, unable to allocate irq=%d\n",
2022 driver_name, self->io.irq);
2023 return -EAGAIN;
2024 }
2025 /*
2026 * Always allocate the DMA channel after the IRQ, and clean up on
2027 * failure.
2028 */
2029 if (request_dma(self->io.dma, dev->name)) {
2030 IRDA_WARNING("%s, unable to allocate dma=%d\n",
2031 driver_name, self->io.dma);
2032 free_irq(self->io.irq, dev);
2033 return -EAGAIN;
2034 }
2035
2036 /* Save current bank */
2037 bank = inb(iobase+BSR);
2038
2039 /* turn on interrupts */
2040 switch_bank(iobase, BANK0);
2041 outb(IER_LS_IE | IER_RXHDL_IE, iobase+IER);
2042
2043 /* Restore bank register */
2044 outb(bank, iobase+BSR);
2045
2046 /* Ready to play! */
2047 netif_start_queue(dev);
2048
2049 /* Give self a hardware name */
2050 sprintf(hwname, "NSC-FIR @ 0x%03x", self->io.fir_base);
2051
2052 /*
2053 * Open new IrLAP layer instance, now that everything should be
2054 * initialized properly
2055 */
2056 self->irlap = irlap_open(dev, &self->qos, hwname);
2057
2058 return 0;
2059 }
2060
2061 /*
2062 * Function nsc_ircc_net_close (dev)
2063 *
2064 * Stop the device
2065 *
2066 */
2067 static int nsc_ircc_net_close(struct net_device *dev)
2068 {
2069 struct nsc_ircc_cb *self;
2070 int iobase;
2071 __u8 bank;
2072
2073 IRDA_DEBUG(4, "%s()\n", __FUNCTION__);
2074
2075 IRDA_ASSERT(dev != NULL, return -1;);
2076
2077 self = (struct nsc_ircc_cb *) dev->priv;
2078 IRDA_ASSERT(self != NULL, return 0;);
2079
2080 /* Stop device */
2081 netif_stop_queue(dev);
2082
2083 /* Stop and remove instance of IrLAP */
2084 if (self->irlap)
2085 irlap_close(self->irlap);
2086 self->irlap = NULL;
2087
2088 iobase = self->io.fir_base;
2089
2090 disable_dma(self->io.dma);
2091
2092 /* Save current bank */
2093 bank = inb(iobase+BSR);
2094
2095 /* Disable interrupts */
2096 switch_bank(iobase, BANK0);
2097 outb(0, iobase+IER);
2098
2099 free_irq(self->io.irq, dev);
2100 free_dma(self->io.dma);
2101
2102 /* Restore bank register */
2103 outb(bank, iobase+BSR);
2104
2105 return 0;
2106 }
2107
2108 /*
2109 * Function nsc_ircc_net_ioctl (dev, rq, cmd)
2110 *
2111 * Process IOCTL commands for this device
2112 *
2113 */
2114 static int nsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2115 {
2116 struct if_irda_req *irq = (struct if_irda_req *) rq;
2117 struct nsc_ircc_cb *self;
2118 unsigned long flags;
2119 int ret = 0;
2120
2121 IRDA_ASSERT(dev != NULL, return -1;);
2122
2123 self = dev->priv;
2124
2125 IRDA_ASSERT(self != NULL, return -1;);
2126
2127 IRDA_DEBUG(2, "%s(), %s, (cmd=0x%X)\n", __FUNCTION__, dev->name, cmd);
2128
2129 switch (cmd) {
2130 case SIOCSBANDWIDTH: /* Set bandwidth */
2131 if (!capable(CAP_NET_ADMIN)) {
2132 ret = -EPERM;
2133 break;
2134 }
2135 spin_lock_irqsave(&self->lock, flags);
2136 nsc_ircc_change_speed(self, irq->ifr_baudrate);
2137 spin_unlock_irqrestore(&self->lock, flags);
2138 break;
2139 case SIOCSMEDIABUSY: /* Set media busy */
2140 if (!capable(CAP_NET_ADMIN)) {
2141 ret = -EPERM;
2142 break;
2143 }
2144 irda_device_set_media_busy(self->netdev, TRUE);
2145 break;
2146 case SIOCGRECEIVING: /* Check if we are receiving right now */
2147 /* This is already protected */
2148 irq->ifr_receiving = nsc_ircc_is_receiving(self);
2149 break;
2150 default:
2151 ret = -EOPNOTSUPP;
2152 }
2153 return ret;
2154 }
2155
2156 static struct net_device_stats *nsc_ircc_net_get_stats(struct net_device *dev)
2157 {
2158 struct nsc_ircc_cb *self = (struct nsc_ircc_cb *) dev->priv;
2159
2160 return &self->stats;
2161 }
2162
2163 static void nsc_ircc_suspend(struct nsc_ircc_cb *self)
2164 {
2165 IRDA_MESSAGE("%s, Suspending\n", driver_name);
2166
2167 if (self->io.suspended)
2168 return;
2169
2170 nsc_ircc_net_close(self->netdev);
2171
2172 self->io.suspended = 1;
2173 }
2174
2175 static void nsc_ircc_wakeup(struct nsc_ircc_cb *self)
2176 {
2177 if (!self->io.suspended)
2178 return;
2179
2180 nsc_ircc_setup(&self->io);
2181 nsc_ircc_net_open(self->netdev);
2182
2183 IRDA_MESSAGE("%s, Waking up\n", driver_name);
2184
2185 self->io.suspended = 0;
2186 }
2187
2188 static int nsc_ircc_pmproc(struct pm_dev *dev, pm_request_t rqst, void *data)
2189 {
2190 struct nsc_ircc_cb *self = (struct nsc_ircc_cb*) dev->data;
2191 if (self) {
2192 switch (rqst) {
2193 case PM_SUSPEND:
2194 nsc_ircc_suspend(self);
2195 break;
2196 case PM_RESUME:
2197 nsc_ircc_wakeup(self);
2198 break;
2199 }
2200 }
2201 return 0;
2202 }
2203
2204 MODULE_AUTHOR("Dag Brattli <dagb@cs.uit.no>");
2205 MODULE_DESCRIPTION("NSC IrDA Device Driver");
2206 MODULE_LICENSE("GPL");
2207
2208
2209 module_param(qos_mtt_bits, int, 0);
2210 MODULE_PARM_DESC(qos_mtt_bits, "Minimum Turn Time");
2211 module_param_array(io, int, NULL, 0);
2212 MODULE_PARM_DESC(io, "Base I/O addresses");
2213 module_param_array(irq, int, NULL, 0);
2214 MODULE_PARM_DESC(irq, "IRQ lines");
2215 module_param_array(dma, int, NULL, 0);
2216 MODULE_PARM_DESC(dma, "DMA channels");
2217 module_param(dongle_id, int, 0);
2218 MODULE_PARM_DESC(dongle_id, "Type-id of used dongle");
2219
2220 module_init(nsc_ircc_init);
2221 module_exit(nsc_ircc_cleanup);
2222
Verdex Pro support