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[TG3]: Add tagged status support.
[linux-2.6/verdex.git] / drivers / net / pcnet32.c
blob17947e6c8793796b78bc809240d480817d3a8a27
1 /* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */
2 /*
3 * Copyright 1996-1999 Thomas Bogendoerfer
4 *
5 * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
6 *
7 * Copyright 1993 United States Government as represented by the
8 * Director, National Security Agency.
9 *
10 * This software may be used and distributed according to the terms
11 * of the GNU General Public License, incorporated herein by reference.
12 *
13 * This driver is for PCnet32 and PCnetPCI based ethercards
14 */
15 /**************************************************************************
16 * 23 Oct, 2000.
17 * Fixed a few bugs, related to running the controller in 32bit mode.
18 *
19 * Carsten Langgaard, carstenl@mips.com
20 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
21 *
22 *************************************************************************/
23
24 #define DRV_NAME "pcnet32"
25 #define DRV_VERSION "1.30i"
26 #define DRV_RELDATE "06.28.2004"
27 #define PFX DRV_NAME ": "
28
29 static const char *version =
30 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " tsbogend@alpha.franken.de\n";
31
32 #include <linux/module.h>
33 #include <linux/kernel.h>
34 #include <linux/string.h>
35 #include <linux/errno.h>
36 #include <linux/ioport.h>
37 #include <linux/slab.h>
38 #include <linux/interrupt.h>
39 #include <linux/pci.h>
40 #include <linux/delay.h>
41 #include <linux/init.h>
42 #include <linux/ethtool.h>
43 #include <linux/mii.h>
44 #include <linux/crc32.h>
45 #include <linux/netdevice.h>
46 #include <linux/etherdevice.h>
47 #include <linux/skbuff.h>
48 #include <linux/spinlock.h>
49 #include <linux/moduleparam.h>
50 #include <linux/bitops.h>
51
52 #include <asm/dma.h>
53 #include <asm/io.h>
54 #include <asm/uaccess.h>
55 #include <asm/irq.h>
56
57 /*
58 * PCI device identifiers for "new style" Linux PCI Device Drivers
59 */
60 static struct pci_device_id pcnet32_pci_tbl[] = {
61 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE_HOME, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
62 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
63 /*
64 * Adapters that were sold with IBM's RS/6000 or pSeries hardware have
65 * the incorrect vendor id.
66 */
67 { PCI_VENDOR_ID_TRIDENT, PCI_DEVICE_ID_AMD_LANCE, PCI_ANY_ID, PCI_ANY_ID,
68 PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, 0 },
69 { 0, }
70 };
71
72 MODULE_DEVICE_TABLE (pci, pcnet32_pci_tbl);
73
74 static int cards_found;
75
76 /*
77 * VLB I/O addresses
78 */
79 static unsigned int pcnet32_portlist[] __initdata =
80 { 0x300, 0x320, 0x340, 0x360, 0 };
81
82
83
84 static int pcnet32_debug = 0;
85 static int tx_start = 1; /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */
86 static int pcnet32vlb; /* check for VLB cards ? */
87
88 static struct net_device *pcnet32_dev;
89
90 static int max_interrupt_work = 2;
91 static int rx_copybreak = 200;
92
93 #define PCNET32_PORT_AUI 0x00
94 #define PCNET32_PORT_10BT 0x01
95 #define PCNET32_PORT_GPSI 0x02
96 #define PCNET32_PORT_MII 0x03
97
98 #define PCNET32_PORT_PORTSEL 0x03
99 #define PCNET32_PORT_ASEL 0x04
100 #define PCNET32_PORT_100 0x40
101 #define PCNET32_PORT_FD 0x80
102
103 #define PCNET32_DMA_MASK 0xffffffff
104
105 #define PCNET32_WATCHDOG_TIMEOUT (jiffies + (2 * HZ))
106 #define PCNET32_BLINK_TIMEOUT (jiffies + (HZ/4))
107
108 /*
109 * table to translate option values from tulip
110 * to internal options
111 */
112 static unsigned char options_mapping[] = {
113 PCNET32_PORT_ASEL, /* 0 Auto-select */
114 PCNET32_PORT_AUI, /* 1 BNC/AUI */
115 PCNET32_PORT_AUI, /* 2 AUI/BNC */
116 PCNET32_PORT_ASEL, /* 3 not supported */
117 PCNET32_PORT_10BT | PCNET32_PORT_FD, /* 4 10baseT-FD */
118 PCNET32_PORT_ASEL, /* 5 not supported */
119 PCNET32_PORT_ASEL, /* 6 not supported */
120 PCNET32_PORT_ASEL, /* 7 not supported */
121 PCNET32_PORT_ASEL, /* 8 not supported */
122 PCNET32_PORT_MII, /* 9 MII 10baseT */
123 PCNET32_PORT_MII | PCNET32_PORT_FD, /* 10 MII 10baseT-FD */
124 PCNET32_PORT_MII, /* 11 MII (autosel) */
125 PCNET32_PORT_10BT, /* 12 10BaseT */
126 PCNET32_PORT_MII | PCNET32_PORT_100, /* 13 MII 100BaseTx */
127 PCNET32_PORT_MII | PCNET32_PORT_100 | PCNET32_PORT_FD, /* 14 MII 100BaseTx-FD */
128 PCNET32_PORT_ASEL /* 15 not supported */
129 };
130
131 static const char pcnet32_gstrings_test[][ETH_GSTRING_LEN] = {
132 "Loopback test (offline)"
133 };
134 #define PCNET32_TEST_LEN (sizeof(pcnet32_gstrings_test) / ETH_GSTRING_LEN)
135
136 #define PCNET32_NUM_REGS 168
137
138 #define MAX_UNITS 8 /* More are supported, limit only on options */
139 static int options[MAX_UNITS];
140 static int full_duplex[MAX_UNITS];
141 static int homepna[MAX_UNITS];
142
143 /*
144 * Theory of Operation
145 *
146 * This driver uses the same software structure as the normal lance
147 * driver. So look for a verbose description in lance.c. The differences
148 * to the normal lance driver is the use of the 32bit mode of PCnet32
149 * and PCnetPCI chips. Because these chips are 32bit chips, there is no
150 * 16MB limitation and we don't need bounce buffers.
151 */
152
153 /*
154 * History:
155 * v0.01: Initial version
156 * only tested on Alpha Noname Board
157 * v0.02: changed IRQ handling for new interrupt scheme (dev_id)
158 * tested on a ASUS SP3G
159 * v0.10: fixed an odd problem with the 79C974 in a Compaq Deskpro XL
160 * looks like the 974 doesn't like stopping and restarting in a
161 * short period of time; now we do a reinit of the lance; the
162 * bug was triggered by doing ifconfig eth0 <ip> broadcast <addr>
163 * and hangs the machine (thanks to Klaus Liedl for debugging)
164 * v0.12: by suggestion from Donald Becker: Renamed driver to pcnet32,
165 * made it standalone (no need for lance.c)
166 * v0.13: added additional PCI detecting for special PCI devices (Compaq)
167 * v0.14: stripped down additional PCI probe (thanks to David C Niemi
168 * and sveneric@xs4all.nl for testing this on their Compaq boxes)
169 * v0.15: added 79C965 (VLB) probe
170 * added interrupt sharing for PCI chips
171 * v0.16: fixed set_multicast_list on Alpha machines
172 * v0.17: removed hack from dev.c; now pcnet32 uses ethif_probe in Space.c
173 * v0.19: changed setting of autoselect bit
174 * v0.20: removed additional Compaq PCI probe; there is now a working one
175 * in arch/i386/bios32.c
176 * v0.21: added endian conversion for ppc, from work by cort@cs.nmt.edu
177 * v0.22: added printing of status to ring dump
178 * v0.23: changed enet_statistics to net_devive_stats
179 * v0.90: added multicast filter
180 * added module support
181 * changed irq probe to new style
182 * added PCnetFast chip id
183 * added fix for receive stalls with Intel saturn chipsets
184 * added in-place rx skbs like in the tulip driver
185 * minor cleanups
186 * v0.91: added PCnetFast+ chip id
187 * back port to 2.0.x
188 * v1.00: added some stuff from Donald Becker's 2.0.34 version
189 * added support for byte counters in net_dev_stats
190 * v1.01: do ring dumps, only when debugging the driver
191 * increased the transmit timeout
192 * v1.02: fixed memory leak in pcnet32_init_ring()
193 * v1.10: workaround for stopped transmitter
194 * added port selection for modules
195 * detect special T1/E1 WAN card and setup port selection
196 * v1.11: fixed wrong checking of Tx errors
197 * v1.20: added check of return value kmalloc (cpeterso@cs.washington.edu)
198 * added save original kmalloc addr for freeing (mcr@solidum.com)
199 * added support for PCnetHome chip (joe@MIT.EDU)
200 * rewritten PCI card detection
201 * added dwio mode to get driver working on some PPC machines
202 * v1.21: added mii selection and mii ioctl
203 * v1.22: changed pci scanning code to make PPC people happy
204 * fixed switching to 32bit mode in pcnet32_open() (thanks
205 * to Michael Richard <mcr@solidum.com> for noticing this one)
206 * added sub vendor/device id matching (thanks again to
207 * Michael Richard <mcr@solidum.com>)
208 * added chip id for 79c973/975 (thanks to Zach Brown <zab@zabbo.net>)
209 * v1.23 fixed small bug, when manual selecting MII speed/duplex
210 * v1.24 Applied Thomas' patch to use TxStartPoint and thus decrease TxFIFO
211 * underflows. Added tx_start_pt module parameter. Increased
212 * TX_RING_SIZE from 16 to 32. Added #ifdef'd code to use DXSUFLO
213 * for FAST[+] chipsets. <kaf@fc.hp.com>
214 * v1.24ac Added SMP spinlocking - Alan Cox <alan@redhat.com>
215 * v1.25kf Added No Interrupt on successful Tx for some Tx's <kaf@fc.hp.com>
216 * v1.26 Converted to pci_alloc_consistent, Jamey Hicks / George France
217 * <jamey@crl.dec.com>
218 * - Fixed a few bugs, related to running the controller in 32bit mode.
219 * 23 Oct, 2000. Carsten Langgaard, carstenl@mips.com
220 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
221 * v1.26p Fix oops on rmmod+insmod; plug i/o resource leak - Paul Gortmaker
222 * v1.27 improved CSR/PROM address detection, lots of cleanups,
223 * new pcnet32vlb module option, HP-PARISC support,
224 * added module parameter descriptions,
225 * initial ethtool support - Helge Deller <deller@gmx.de>
226 * v1.27a Sun Feb 10 2002 Go Taniguchi <go@turbolinux.co.jp>
227 * use alloc_etherdev and register_netdev
228 * fix pci probe not increment cards_found
229 * FD auto negotiate error workaround for xSeries250
230 * clean up and using new mii module
231 * v1.27b Sep 30 2002 Kent Yoder <yoder1@us.ibm.com>
232 * Added timer for cable connection state changes.
233 * v1.28 20 Feb 2004 Don Fry <brazilnut@us.ibm.com>
234 * Jon Mason <jonmason@us.ibm.com>, Chinmay Albal <albal@in.ibm.com>
235 * Now uses ethtool_ops, netif_msg_* and generic_mii_ioctl.
236 * Fixes bogus 'Bus master arbitration failure', pci_[un]map_single
237 * length errors, and transmit hangs. Cleans up after errors in open.
238 * Jim Lewis <jklewis@us.ibm.com> added ethernet loopback test.
239 * Thomas Munck Steenholdt <tmus@tmus.dk> non-mii ioctl corrections.
240 * v1.29 6 Apr 2004 Jim Lewis <jklewis@us.ibm.com> added physical
241 * identification code (blink led's) and register dump.
242 * Don Fry added timer for 971/972 so skbufs don't remain on tx ring
243 * forever.
244 * v1.30 18 May 2004 Don Fry removed timer and Last Transmit Interrupt
245 * (ltint) as they added complexity and didn't give good throughput.
246 * v1.30a 22 May 2004 Don Fry limit frames received during interrupt.
247 * v1.30b 24 May 2004 Don Fry fix bogus tx carrier errors with 79c973,
248 * assisted by Bruce Penrod <bmpenrod@endruntechnologies.com>.
249 * v1.30c 25 May 2004 Don Fry added netif_wake_queue after pcnet32_restart.
250 * v1.30d 01 Jun 2004 Don Fry discard oversize rx packets.
251 * v1.30e 11 Jun 2004 Don Fry recover after fifo error and rx hang.
252 * v1.30f 16 Jun 2004 Don Fry cleanup IRQ to allow 0 and 1 for PCI,
253 * expanding on suggestions from Ralf Baechle <ralf@linux-mips.org>,
254 * and Brian Murphy <brian@murphy.dk>.
255 * v1.30g 22 Jun 2004 Patrick Simmons <psimmons@flash.net> added option
256 * homepna for selecting HomePNA mode for PCNet/Home 79C978.
257 * v1.30h 24 Jun 2004 Don Fry correctly select auto, speed, duplex in bcr32.
258 * v1.30i 28 Jun 2004 Don Fry change to use module_param.
259 */
260
261
262 /*
263 * Set the number of Tx and Rx buffers, using Log_2(# buffers).
264 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
265 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
266 */
267 #ifndef PCNET32_LOG_TX_BUFFERS
268 #define PCNET32_LOG_TX_BUFFERS 4
269 #define PCNET32_LOG_RX_BUFFERS 5
270 #endif
271
272 #define TX_RING_SIZE (1 << (PCNET32_LOG_TX_BUFFERS))
273 #define TX_RING_MOD_MASK (TX_RING_SIZE - 1)
274 #define TX_RING_LEN_BITS ((PCNET32_LOG_TX_BUFFERS) << 12)
275
276 #define RX_RING_SIZE (1 << (PCNET32_LOG_RX_BUFFERS))
277 #define RX_RING_MOD_MASK (RX_RING_SIZE - 1)
278 #define RX_RING_LEN_BITS ((PCNET32_LOG_RX_BUFFERS) << 4)
279
280 #define PKT_BUF_SZ 1544
281
282 /* Offsets from base I/O address. */
283 #define PCNET32_WIO_RDP 0x10
284 #define PCNET32_WIO_RAP 0x12
285 #define PCNET32_WIO_RESET 0x14
286 #define PCNET32_WIO_BDP 0x16
287
288 #define PCNET32_DWIO_RDP 0x10
289 #define PCNET32_DWIO_RAP 0x14
290 #define PCNET32_DWIO_RESET 0x18
291 #define PCNET32_DWIO_BDP 0x1C
292
293 #define PCNET32_TOTAL_SIZE 0x20
294
295 /* The PCNET32 Rx and Tx ring descriptors. */
296 struct pcnet32_rx_head {
297 u32 base;
298 s16 buf_length;
299 s16 status;
300 u32 msg_length;
301 u32 reserved;
302 };
303
304 struct pcnet32_tx_head {
305 u32 base;
306 s16 length;
307 s16 status;
308 u32 misc;
309 u32 reserved;
310 };
311
312 /* The PCNET32 32-Bit initialization block, described in databook. */
313 struct pcnet32_init_block {
314 u16 mode;
315 u16 tlen_rlen;
316 u8 phys_addr[6];
317 u16 reserved;
318 u32 filter[2];
319 /* Receive and transmit ring base, along with extra bits. */
320 u32 rx_ring;
321 u32 tx_ring;
322 };
323
324 /* PCnet32 access functions */
325 struct pcnet32_access {
326 u16 (*read_csr)(unsigned long, int);
327 void (*write_csr)(unsigned long, int, u16);
328 u16 (*read_bcr)(unsigned long, int);
329 void (*write_bcr)(unsigned long, int, u16);
330 u16 (*read_rap)(unsigned long);
331 void (*write_rap)(unsigned long, u16);
332 void (*reset)(unsigned long);
333 };
334
335 /*
336 * The first three fields of pcnet32_private are read by the ethernet device
337 * so we allocate the structure should be allocated by pci_alloc_consistent().
338 */
339 struct pcnet32_private {
340 /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */
341 struct pcnet32_rx_head rx_ring[RX_RING_SIZE];
342 struct pcnet32_tx_head tx_ring[TX_RING_SIZE];
343 struct pcnet32_init_block init_block;
344 dma_addr_t dma_addr; /* DMA address of beginning of this
345 object, returned by
346 pci_alloc_consistent */
347 struct pci_dev *pci_dev; /* Pointer to the associated pci device
348 structure */
349 const char *name;
350 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
351 struct sk_buff *tx_skbuff[TX_RING_SIZE];
352 struct sk_buff *rx_skbuff[RX_RING_SIZE];
353 dma_addr_t tx_dma_addr[TX_RING_SIZE];
354 dma_addr_t rx_dma_addr[RX_RING_SIZE];
355 struct pcnet32_access a;
356 spinlock_t lock; /* Guard lock */
357 unsigned int cur_rx, cur_tx; /* The next free ring entry */
358 unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */
359 struct net_device_stats stats;
360 char tx_full;
361 int options;
362 unsigned int shared_irq:1, /* shared irq possible */
363 dxsuflo:1, /* disable transmit stop on uflo */
364 mii:1; /* mii port available */
365 struct net_device *next;
366 struct mii_if_info mii_if;
367 struct timer_list watchdog_timer;
368 struct timer_list blink_timer;
369 u32 msg_enable; /* debug message level */
370 };
371
372 static void pcnet32_probe_vlbus(void);
373 static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *);
374 static int pcnet32_probe1(unsigned long, int, struct pci_dev *);
375 static int pcnet32_open(struct net_device *);
376 static int pcnet32_init_ring(struct net_device *);
377 static int pcnet32_start_xmit(struct sk_buff *, struct net_device *);
378 static int pcnet32_rx(struct net_device *);
379 static void pcnet32_tx_timeout (struct net_device *dev);
380 static irqreturn_t pcnet32_interrupt(int, void *, struct pt_regs *);
381 static int pcnet32_close(struct net_device *);
382 static struct net_device_stats *pcnet32_get_stats(struct net_device *);
383 static void pcnet32_load_multicast(struct net_device *dev);
384 static void pcnet32_set_multicast_list(struct net_device *);
385 static int pcnet32_ioctl(struct net_device *, struct ifreq *, int);
386 static void pcnet32_watchdog(struct net_device *);
387 static int mdio_read(struct net_device *dev, int phy_id, int reg_num);
388 static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val);
389 static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits);
390 static void pcnet32_ethtool_test(struct net_device *dev,
391 struct ethtool_test *eth_test, u64 *data);
392 static int pcnet32_loopback_test(struct net_device *dev, uint64_t *data1);
393 static int pcnet32_phys_id(struct net_device *dev, u32 data);
394 static void pcnet32_led_blink_callback(struct net_device *dev);
395 static int pcnet32_get_regs_len(struct net_device *dev);
396 static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
397 void *ptr);
398
399 enum pci_flags_bit {
400 PCI_USES_IO=1, PCI_USES_MEM=2, PCI_USES_MASTER=4,
401 PCI_ADDR0=0x10<<0, PCI_ADDR1=0x10<<1, PCI_ADDR2=0x10<<2, PCI_ADDR3=0x10<<3,
402 };
403
404
405 static u16 pcnet32_wio_read_csr (unsigned long addr, int index)
406 {
407 outw (index, addr+PCNET32_WIO_RAP);
408 return inw (addr+PCNET32_WIO_RDP);
409 }
410
411 static void pcnet32_wio_write_csr (unsigned long addr, int index, u16 val)
412 {
413 outw (index, addr+PCNET32_WIO_RAP);
414 outw (val, addr+PCNET32_WIO_RDP);
415 }
416
417 static u16 pcnet32_wio_read_bcr (unsigned long addr, int index)
418 {
419 outw (index, addr+PCNET32_WIO_RAP);
420 return inw (addr+PCNET32_WIO_BDP);
421 }
422
423 static void pcnet32_wio_write_bcr (unsigned long addr, int index, u16 val)
424 {
425 outw (index, addr+PCNET32_WIO_RAP);
426 outw (val, addr+PCNET32_WIO_BDP);
427 }
428
429 static u16 pcnet32_wio_read_rap (unsigned long addr)
430 {
431 return inw (addr+PCNET32_WIO_RAP);
432 }
433
434 static void pcnet32_wio_write_rap (unsigned long addr, u16 val)
435 {
436 outw (val, addr+PCNET32_WIO_RAP);
437 }
438
439 static void pcnet32_wio_reset (unsigned long addr)
440 {
441 inw (addr+PCNET32_WIO_RESET);
442 }
443
444 static int pcnet32_wio_check (unsigned long addr)
445 {
446 outw (88, addr+PCNET32_WIO_RAP);
447 return (inw (addr+PCNET32_WIO_RAP) == 88);
448 }
449
450 static struct pcnet32_access pcnet32_wio = {
451 .read_csr = pcnet32_wio_read_csr,
452 .write_csr = pcnet32_wio_write_csr,
453 .read_bcr = pcnet32_wio_read_bcr,
454 .write_bcr = pcnet32_wio_write_bcr,
455 .read_rap = pcnet32_wio_read_rap,
456 .write_rap = pcnet32_wio_write_rap,
457 .reset = pcnet32_wio_reset
458 };
459
460 static u16 pcnet32_dwio_read_csr (unsigned long addr, int index)
461 {
462 outl (index, addr+PCNET32_DWIO_RAP);
463 return (inl (addr+PCNET32_DWIO_RDP) & 0xffff);
464 }
465
466 static void pcnet32_dwio_write_csr (unsigned long addr, int index, u16 val)
467 {
468 outl (index, addr+PCNET32_DWIO_RAP);
469 outl (val, addr+PCNET32_DWIO_RDP);
470 }
471
472 static u16 pcnet32_dwio_read_bcr (unsigned long addr, int index)
473 {
474 outl (index, addr+PCNET32_DWIO_RAP);
475 return (inl (addr+PCNET32_DWIO_BDP) & 0xffff);
476 }
477
478 static void pcnet32_dwio_write_bcr (unsigned long addr, int index, u16 val)
479 {
480 outl (index, addr+PCNET32_DWIO_RAP);
481 outl (val, addr+PCNET32_DWIO_BDP);
482 }
483
484 static u16 pcnet32_dwio_read_rap (unsigned long addr)
485 {
486 return (inl (addr+PCNET32_DWIO_RAP) & 0xffff);
487 }
488
489 static void pcnet32_dwio_write_rap (unsigned long addr, u16 val)
490 {
491 outl (val, addr+PCNET32_DWIO_RAP);
492 }
493
494 static void pcnet32_dwio_reset (unsigned long addr)
495 {
496 inl (addr+PCNET32_DWIO_RESET);
497 }
498
499 static int pcnet32_dwio_check (unsigned long addr)
500 {
501 outl (88, addr+PCNET32_DWIO_RAP);
502 return ((inl (addr+PCNET32_DWIO_RAP) & 0xffff) == 88);
503 }
504
505 static struct pcnet32_access pcnet32_dwio = {
506 .read_csr = pcnet32_dwio_read_csr,
507 .write_csr = pcnet32_dwio_write_csr,
508 .read_bcr = pcnet32_dwio_read_bcr,
509 .write_bcr = pcnet32_dwio_write_bcr,
510 .read_rap = pcnet32_dwio_read_rap,
511 .write_rap = pcnet32_dwio_write_rap,
512 .reset = pcnet32_dwio_reset
513 };
514
515 #ifdef CONFIG_NET_POLL_CONTROLLER
516 static void pcnet32_poll_controller(struct net_device *dev)
517 {
518 disable_irq(dev->irq);
519 pcnet32_interrupt(0, dev, NULL);
520 enable_irq(dev->irq);
521 }
522 #endif
523
524
525 static int pcnet32_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
526 {
527 struct pcnet32_private *lp = dev->priv;
528 unsigned long flags;
529 int r = -EOPNOTSUPP;
530
531 if (lp->mii) {
532 spin_lock_irqsave(&lp->lock, flags);
533 mii_ethtool_gset(&lp->mii_if, cmd);
534 spin_unlock_irqrestore(&lp->lock, flags);
535 r = 0;
536 }
537 return r;
538 }
539
540 static int pcnet32_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
541 {
542 struct pcnet32_private *lp = dev->priv;
543 unsigned long flags;
544 int r = -EOPNOTSUPP;
545
546 if (lp->mii) {
547 spin_lock_irqsave(&lp->lock, flags);
548 r = mii_ethtool_sset(&lp->mii_if, cmd);
549 spin_unlock_irqrestore(&lp->lock, flags);
550 }
551 return r;
552 }
553
554 static void pcnet32_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
555 {
556 struct pcnet32_private *lp = dev->priv;
557
558 strcpy (info->driver, DRV_NAME);
559 strcpy (info->version, DRV_VERSION);
560 if (lp->pci_dev)
561 strcpy (info->bus_info, pci_name(lp->pci_dev));
562 else
563 sprintf(info->bus_info, "VLB 0x%lx", dev->base_addr);
564 }
565
566 static u32 pcnet32_get_link(struct net_device *dev)
567 {
568 struct pcnet32_private *lp = dev->priv;
569 unsigned long flags;
570 int r;
571
572 spin_lock_irqsave(&lp->lock, flags);
573 if (lp->mii) {
574 r = mii_link_ok(&lp->mii_if);
575 } else {
576 ulong ioaddr = dev->base_addr; /* card base I/O address */
577 r = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
578 }
579 spin_unlock_irqrestore(&lp->lock, flags);
580
581 return r;
582 }
583
584 static u32 pcnet32_get_msglevel(struct net_device *dev)
585 {
586 struct pcnet32_private *lp = dev->priv;
587 return lp->msg_enable;
588 }
589
590 static void pcnet32_set_msglevel(struct net_device *dev, u32 value)
591 {
592 struct pcnet32_private *lp = dev->priv;
593 lp->msg_enable = value;
594 }
595
596 static int pcnet32_nway_reset(struct net_device *dev)
597 {
598 struct pcnet32_private *lp = dev->priv;
599 unsigned long flags;
600 int r = -EOPNOTSUPP;
601
602 if (lp->mii) {
603 spin_lock_irqsave(&lp->lock, flags);
604 r = mii_nway_restart(&lp->mii_if);
605 spin_unlock_irqrestore(&lp->lock, flags);
606 }
607 return r;
608 }
609
610 static void pcnet32_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
611 {
612 struct pcnet32_private *lp = dev->priv;
613
614 ering->tx_max_pending = TX_RING_SIZE - 1;
615 ering->tx_pending = lp->cur_tx - lp->dirty_tx;
616 ering->rx_max_pending = RX_RING_SIZE - 1;
617 ering->rx_pending = lp->cur_rx & RX_RING_MOD_MASK;
618 }
619
620 static void pcnet32_get_strings(struct net_device *dev, u32 stringset, u8 *data)
621 {
622 memcpy(data, pcnet32_gstrings_test, sizeof(pcnet32_gstrings_test));
623 }
624
625 static int pcnet32_self_test_count(struct net_device *dev)
626 {
627 return PCNET32_TEST_LEN;
628 }
629
630 static void pcnet32_ethtool_test(struct net_device *dev,
631 struct ethtool_test *test, u64 *data)
632 {
633 struct pcnet32_private *lp = dev->priv;
634 int rc;
635
636 if (test->flags == ETH_TEST_FL_OFFLINE) {
637 rc = pcnet32_loopback_test(dev, data);
638 if (rc) {
639 if (netif_msg_hw(lp))
640 printk(KERN_DEBUG "%s: Loopback test failed.\n", dev->name);
641 test->flags |= ETH_TEST_FL_FAILED;
642 } else if (netif_msg_hw(lp))
643 printk(KERN_DEBUG "%s: Loopback test passed.\n", dev->name);
644 } else if (netif_msg_hw(lp))
645 printk(KERN_DEBUG "%s: No tests to run (specify 'Offline' on ethtool).", dev->name);
646 } /* end pcnet32_ethtool_test */
647
648 static int pcnet32_loopback_test(struct net_device *dev, uint64_t *data1)
649 {
650 struct pcnet32_private *lp = dev->priv;
651 struct pcnet32_access *a = &lp->a; /* access to registers */
652 ulong ioaddr = dev->base_addr; /* card base I/O address */
653 struct sk_buff *skb; /* sk buff */
654 int x, i; /* counters */
655 int numbuffs = 4; /* number of TX/RX buffers and descs */
656 u16 status = 0x8300; /* TX ring status */
657 u16 teststatus; /* test of ring status */
658 int rc; /* return code */
659 int size; /* size of packets */
660 unsigned char *packet; /* source packet data */
661 static int data_len = 60; /* length of source packets */
662 unsigned long flags;
663 unsigned long ticks;
664
665 *data1 = 1; /* status of test, default to fail */
666 rc = 1; /* default to fail */
667
668 if (netif_running(dev))
669 pcnet32_close(dev);
670
671 spin_lock_irqsave(&lp->lock, flags);
672
673 /* Reset the PCNET32 */
674 lp->a.reset (ioaddr);
675
676 /* switch pcnet32 to 32bit mode */
677 lp->a.write_bcr (ioaddr, 20, 2);
678
679 lp->init_block.mode = le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7);
680 lp->init_block.filter[0] = 0;
681 lp->init_block.filter[1] = 0;
682
683 /* purge & init rings but don't actually restart */
684 pcnet32_restart(dev, 0x0000);
685
686 lp->a.write_csr(ioaddr, 0, 0x0004); /* Set STOP bit */
687
688 /* Initialize Transmit buffers. */
689 size = data_len + 15;
690 for (x=0; x<numbuffs; x++) {
691 if (!(skb = dev_alloc_skb(size))) {
692 if (netif_msg_hw(lp))
693 printk(KERN_DEBUG "%s: Cannot allocate skb at line: %d!\n",
694 dev->name, __LINE__);
695 goto clean_up;
696 } else {
697 packet = skb->data;
698 skb_put(skb, size); /* create space for data */
699 lp->tx_skbuff[x] = skb;
700 lp->tx_ring[x].length = le16_to_cpu(-skb->len);
701 lp->tx_ring[x].misc = 0;
702
703 /* put DA and SA into the skb */
704 for (i=0; i<6; i++)
705 *packet++ = dev->dev_addr[i];
706 for (i=0; i<6; i++)
707 *packet++ = dev->dev_addr[i];
708 /* type */
709 *packet++ = 0x08;
710 *packet++ = 0x06;
711 /* packet number */
712 *packet++ = x;
713 /* fill packet with data */
714 for (i=0; i<data_len; i++)
715 *packet++ = i;
716
717 lp->tx_dma_addr[x] = pci_map_single(lp->pci_dev, skb->data,
718 skb->len, PCI_DMA_TODEVICE);
719 lp->tx_ring[x].base = (u32)le32_to_cpu(lp->tx_dma_addr[x]);
720 wmb(); /* Make sure owner changes after all others are visible */
721 lp->tx_ring[x].status = le16_to_cpu(status);
722 }
723 }
724
725 x = a->read_bcr(ioaddr, 32); /* set internal loopback in BSR32 */
726 x = x | 0x0002;
727 a->write_bcr(ioaddr, 32, x);
728
729 lp->a.write_csr (ioaddr, 15, 0x0044); /* set int loopback in CSR15 */
730
731 teststatus = le16_to_cpu(0x8000);
732 lp->a.write_csr(ioaddr, 0, 0x0002); /* Set STRT bit */
733
734 /* Check status of descriptors */
735 for (x=0; x<numbuffs; x++) {
736 ticks = 0;
737 rmb();
738 while ((lp->rx_ring[x].status & teststatus) && (ticks < 200)) {
739 spin_unlock_irqrestore(&lp->lock, flags);
740 mdelay(1);
741 spin_lock_irqsave(&lp->lock, flags);
742 rmb();
743 ticks++;
744 }
745 if (ticks == 200) {
746 if (netif_msg_hw(lp))
747 printk("%s: Desc %d failed to reset!\n",dev->name,x);
748 break;
749 }
750 }
751
752 lp->a.write_csr(ioaddr, 0, 0x0004); /* Set STOP bit */
753 wmb();
754 if (netif_msg_hw(lp) && netif_msg_pktdata(lp)) {
755 printk(KERN_DEBUG "%s: RX loopback packets:\n", dev->name);
756
757 for (x=0; x<numbuffs; x++) {
758 printk(KERN_DEBUG "%s: Packet %d:\n", dev->name, x);
759 skb = lp->rx_skbuff[x];
760 for (i=0; i<size; i++) {
761 printk("%02x ", *(skb->data+i));
762 }
763 printk("\n");
764 }
765 }
766
767 x = 0;
768 rc = 0;
769 while (x<numbuffs && !rc) {
770 skb = lp->rx_skbuff[x];
771 packet = lp->tx_skbuff[x]->data;
772 for (i=0; i<size; i++) {
773 if (*(skb->data+i) != packet[i]) {
774 if (netif_msg_hw(lp))
775 printk(KERN_DEBUG "%s: Error in compare! %2x - %02x %02x\n",
776 dev->name, i, *(skb->data+i), packet[i]);
777 rc = 1;
778 break;
779 }
780 }
781 x++;
782 }
783 if (!rc) {
784 *data1 = 0;
785 }
786
787 clean_up:
788 x = a->read_csr(ioaddr, 15) & 0xFFFF;
789 a->write_csr(ioaddr, 15, (x & ~0x0044)); /* reset bits 6 and 2 */
790
791 x = a->read_bcr(ioaddr, 32); /* reset internal loopback */
792 x = x & ~0x0002;
793 a->write_bcr(ioaddr, 32, x);
794
795 spin_unlock_irqrestore(&lp->lock, flags);
796
797 if (netif_running(dev)) {
798 pcnet32_open(dev);
799 } else {
800 lp->a.write_bcr (ioaddr, 20, 4); /* return to 16bit mode */
801 }
802
803 return(rc);
804 } /* end pcnet32_loopback_test */
805
806 static void pcnet32_led_blink_callback(struct net_device *dev)
807 {
808 struct pcnet32_private *lp = dev->priv;
809 struct pcnet32_access *a = &lp->a;
810 ulong ioaddr = dev->base_addr;
811 unsigned long flags;
812 int i;
813
814 spin_lock_irqsave(&lp->lock, flags);
815 for (i=4; i<8; i++) {
816 a->write_bcr(ioaddr, i, a->read_bcr(ioaddr, i) ^ 0x4000);
817 }
818 spin_unlock_irqrestore(&lp->lock, flags);
819
820 mod_timer(&lp->blink_timer, PCNET32_BLINK_TIMEOUT);
821 }
822
823 static int pcnet32_phys_id(struct net_device *dev, u32 data)
824 {
825 struct pcnet32_private *lp = dev->priv;
826 struct pcnet32_access *a = &lp->a;
827 ulong ioaddr = dev->base_addr;
828 unsigned long flags;
829 int i, regs[4];
830
831 if (!lp->blink_timer.function) {
832 init_timer(&lp->blink_timer);
833 lp->blink_timer.function = (void *) pcnet32_led_blink_callback;
834 lp->blink_timer.data = (unsigned long) dev;
835 }
836
837 /* Save the current value of the bcrs */
838 spin_lock_irqsave(&lp->lock, flags);
839 for (i=4; i<8; i++) {
840 regs[i-4] = a->read_bcr(ioaddr, i);
841 }
842 spin_unlock_irqrestore(&lp->lock, flags);
843
844 mod_timer(&lp->blink_timer, jiffies);
845 set_current_state(TASK_INTERRUPTIBLE);
846
847 if ((!data) || (data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ)))
848 data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
849
850 schedule_timeout(data * HZ);
851 del_timer_sync(&lp->blink_timer);
852
853 /* Restore the original value of the bcrs */
854 spin_lock_irqsave(&lp->lock, flags);
855 for (i=4; i<8; i++) {
856 a->write_bcr(ioaddr, i, regs[i-4]);
857 }
858 spin_unlock_irqrestore(&lp->lock, flags);
859
860 return 0;
861 }
862
863 static int pcnet32_get_regs_len(struct net_device *dev)
864 {
865 return(PCNET32_NUM_REGS * sizeof(u16));
866 }
867
868 static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
869 void *ptr)
870 {
871 int i, csr0;
872 u16 *buff = ptr;
873 struct pcnet32_private *lp = dev->priv;
874 struct pcnet32_access *a = &lp->a;
875 ulong ioaddr = dev->base_addr;
876 int ticks;
877 unsigned long flags;
878
879 spin_lock_irqsave(&lp->lock, flags);
880
881 csr0 = a->read_csr(ioaddr, 0);
882 if (!(csr0 & 0x0004)) { /* If not stopped */
883 /* set SUSPEND (SPND) - CSR5 bit 0 */
884 a->write_csr(ioaddr, 5, 0x0001);
885
886 /* poll waiting for bit to be set */
887 ticks = 0;
888 while (!(a->read_csr(ioaddr, 5) & 0x0001)) {
889 spin_unlock_irqrestore(&lp->lock, flags);
890 mdelay(1);
891 spin_lock_irqsave(&lp->lock, flags);
892 ticks++;
893 if (ticks > 200) {
894 if (netif_msg_hw(lp))
895 printk(KERN_DEBUG "%s: Error getting into suspend!\n",
896 dev->name);
897 break;
898 }
899 }
900 }
901
902 /* read address PROM */
903 for (i=0; i<16; i += 2)
904 *buff++ = inw(ioaddr + i);
905
906 /* read control and status registers */
907 for (i=0; i<90; i++) {
908 *buff++ = a->read_csr(ioaddr, i);
909 }
910
911 *buff++ = a->read_csr(ioaddr, 112);
912 *buff++ = a->read_csr(ioaddr, 114);
913
914 /* read bus configuration registers */
915 for (i=0; i<36; i++) {
916 *buff++ = a->read_bcr(ioaddr, i);
917 }
918
919 /* read mii phy registers */
920 if (lp->mii) {
921 for (i=0; i<32; i++) {
922 lp->a.write_bcr(ioaddr, 33, ((lp->mii_if.phy_id) << 5) | i);
923 *buff++ = lp->a.read_bcr(ioaddr, 34);
924 }
925 }
926
927 if (!(csr0 & 0x0004)) { /* If not stopped */
928 /* clear SUSPEND (SPND) - CSR5 bit 0 */
929 a->write_csr(ioaddr, 5, 0x0000);
930 }
931
932 i = buff - (u16 *)ptr;
933 for (; i < PCNET32_NUM_REGS; i++)
934 *buff++ = 0;
935
936 spin_unlock_irqrestore(&lp->lock, flags);
937 }
938
939 static struct ethtool_ops pcnet32_ethtool_ops = {
940 .get_settings = pcnet32_get_settings,
941 .set_settings = pcnet32_set_settings,
942 .get_drvinfo = pcnet32_get_drvinfo,
943 .get_msglevel = pcnet32_get_msglevel,
944 .set_msglevel = pcnet32_set_msglevel,
945 .nway_reset = pcnet32_nway_reset,
946 .get_link = pcnet32_get_link,
947 .get_ringparam = pcnet32_get_ringparam,
948 .get_tx_csum = ethtool_op_get_tx_csum,
949 .get_sg = ethtool_op_get_sg,
950 .get_tso = ethtool_op_get_tso,
951 .get_strings = pcnet32_get_strings,
952 .self_test_count = pcnet32_self_test_count,
953 .self_test = pcnet32_ethtool_test,
954 .phys_id = pcnet32_phys_id,
955 .get_regs_len = pcnet32_get_regs_len,
956 .get_regs = pcnet32_get_regs,
957 };
958
959 /* only probes for non-PCI devices, the rest are handled by
960 * pci_register_driver via pcnet32_probe_pci */
961
962 static void __devinit
963 pcnet32_probe_vlbus(void)
964 {
965 unsigned int *port, ioaddr;
966
967 /* search for PCnet32 VLB cards at known addresses */
968 for (port = pcnet32_portlist; (ioaddr = *port); port++) {
969 if (request_region(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_vlbus")) {
970 /* check if there is really a pcnet chip on that ioaddr */
971 if ((inb(ioaddr + 14) == 0x57) && (inb(ioaddr + 15) == 0x57)) {
972 pcnet32_probe1(ioaddr, 0, NULL);
973 } else {
974 release_region(ioaddr, PCNET32_TOTAL_SIZE);
975 }
976 }
977 }
978 }
979
980
981 static int __devinit
982 pcnet32_probe_pci(struct pci_dev *pdev, const struct pci_device_id *ent)
983 {
984 unsigned long ioaddr;
985 int err;
986
987 err = pci_enable_device(pdev);
988 if (err < 0) {
989 if (pcnet32_debug & NETIF_MSG_PROBE)
990 printk(KERN_ERR PFX "failed to enable device -- err=%d\n", err);
991 return err;
992 }
993 pci_set_master(pdev);
994
995 ioaddr = pci_resource_start (pdev, 0);
996 if (!ioaddr) {
997 if (pcnet32_debug & NETIF_MSG_PROBE)
998 printk (KERN_ERR PFX "card has no PCI IO resources, aborting\n");
999 return -ENODEV;
1000 }
1001
1002 if (!pci_dma_supported(pdev, PCNET32_DMA_MASK)) {
1003 if (pcnet32_debug & NETIF_MSG_PROBE)
1004 printk(KERN_ERR PFX "architecture does not support 32bit PCI busmaster DMA\n");
1005 return -ENODEV;
1006 }
1007 if (request_region(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_pci") == NULL) {
1008 if (pcnet32_debug & NETIF_MSG_PROBE)
1009 printk(KERN_ERR PFX "io address range already allocated\n");
1010 return -EBUSY;
1011 }
1012
1013 err = pcnet32_probe1(ioaddr, 1, pdev);
1014 if (err < 0) {
1015 pci_disable_device(pdev);
1016 }
1017 return err;
1018 }
1019
1020
1021 /* pcnet32_probe1
1022 * Called from both pcnet32_probe_vlbus and pcnet_probe_pci.
1023 * pdev will be NULL when called from pcnet32_probe_vlbus.
1024 */
1025 static int __devinit
1026 pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev)
1027 {
1028 struct pcnet32_private *lp;
1029 dma_addr_t lp_dma_addr;
1030 int i, media;
1031 int fdx, mii, fset, dxsuflo;
1032 int chip_version;
1033 char *chipname;
1034 struct net_device *dev;
1035 struct pcnet32_access *a = NULL;
1036 u8 promaddr[6];
1037 int ret = -ENODEV;
1038
1039 /* reset the chip */
1040 pcnet32_wio_reset(ioaddr);
1041
1042 /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */
1043 if (pcnet32_wio_read_csr(ioaddr, 0) == 4 && pcnet32_wio_check(ioaddr)) {
1044 a = &pcnet32_wio;
1045 } else {
1046 pcnet32_dwio_reset(ioaddr);
1047 if (pcnet32_dwio_read_csr(ioaddr, 0) == 4 && pcnet32_dwio_check(ioaddr)) {
1048 a = &pcnet32_dwio;
1049 } else
1050 goto err_release_region;
1051 }
1052
1053 chip_version = a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr,89) << 16);
1054 if ((pcnet32_debug & NETIF_MSG_PROBE) && (pcnet32_debug & NETIF_MSG_HW))
1055 printk(KERN_INFO " PCnet chip version is %#x.\n", chip_version);
1056 if ((chip_version & 0xfff) != 0x003) {
1057 if (pcnet32_debug & NETIF_MSG_PROBE)
1058 printk(KERN_INFO PFX "Unsupported chip version.\n");
1059 goto err_release_region;
1060 }
1061
1062 /* initialize variables */
1063 fdx = mii = fset = dxsuflo = 0;
1064 chip_version = (chip_version >> 12) & 0xffff;
1065
1066 switch (chip_version) {
1067 case 0x2420:
1068 chipname = "PCnet/PCI 79C970"; /* PCI */
1069 break;
1070 case 0x2430:
1071 if (shared)
1072 chipname = "PCnet/PCI 79C970"; /* 970 gives the wrong chip id back */
1073 else
1074 chipname = "PCnet/32 79C965"; /* 486/VL bus */
1075 break;
1076 case 0x2621:
1077 chipname = "PCnet/PCI II 79C970A"; /* PCI */
1078 fdx = 1;
1079 break;
1080 case 0x2623:
1081 chipname = "PCnet/FAST 79C971"; /* PCI */
1082 fdx = 1; mii = 1; fset = 1;
1083 break;
1084 case 0x2624:
1085 chipname = "PCnet/FAST+ 79C972"; /* PCI */
1086 fdx = 1; mii = 1; fset = 1;
1087 break;
1088 case 0x2625:
1089 chipname = "PCnet/FAST III 79C973"; /* PCI */
1090 fdx = 1; mii = 1;
1091 break;
1092 case 0x2626:
1093 chipname = "PCnet/Home 79C978"; /* PCI */
1094 fdx = 1;
1095 /*
1096 * This is based on specs published at www.amd.com. This section
1097 * assumes that a card with a 79C978 wants to go into standard
1098 * ethernet mode. The 79C978 can also go into 1Mb HomePNA mode,
1099 * and the module option homepna=1 can select this instead.
1100 */
1101 media = a->read_bcr(ioaddr, 49);
1102 media &= ~3; /* default to 10Mb ethernet */
1103 if (cards_found < MAX_UNITS && homepna[cards_found])
1104 media |= 1; /* switch to home wiring mode */
1105 if (pcnet32_debug & NETIF_MSG_PROBE)
1106 printk(KERN_DEBUG PFX "media set to %sMbit mode.\n",
1107 (media & 1) ? "1" : "10");
1108 a->write_bcr(ioaddr, 49, media);
1109 break;
1110 case 0x2627:
1111 chipname = "PCnet/FAST III 79C975"; /* PCI */
1112 fdx = 1; mii = 1;
1113 break;
1114 case 0x2628:
1115 chipname = "PCnet/PRO 79C976";
1116 fdx = 1; mii = 1;
1117 break;
1118 default:
1119 if (pcnet32_debug & NETIF_MSG_PROBE)
1120 printk(KERN_INFO PFX "PCnet version %#x, no PCnet32 chip.\n",
1121 chip_version);
1122 goto err_release_region;
1123 }
1124
1125 /*
1126 * On selected chips turn on the BCR18:NOUFLO bit. This stops transmit
1127 * starting until the packet is loaded. Strike one for reliability, lose
1128 * one for latency - although on PCI this isnt a big loss. Older chips
1129 * have FIFO's smaller than a packet, so you can't do this.
1130 * Turn on BCR18:BurstRdEn and BCR18:BurstWrEn.
1131 */
1132
1133 if (fset) {
1134 a->write_bcr(ioaddr, 18, (a->read_bcr(ioaddr, 18) | 0x0860));
1135 a->write_csr(ioaddr, 80, (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00);
1136 dxsuflo = 1;
1137 }
1138
1139 dev = alloc_etherdev(0);
1140 if (!dev) {
1141 if (pcnet32_debug & NETIF_MSG_PROBE)
1142 printk(KERN_ERR PFX "Memory allocation failed.\n");
1143 ret = -ENOMEM;
1144 goto err_release_region;
1145 }
1146 SET_NETDEV_DEV(dev, &pdev->dev);
1147
1148 if (pcnet32_debug & NETIF_MSG_PROBE)
1149 printk(KERN_INFO PFX "%s at %#3lx,", chipname, ioaddr);
1150
1151 /* In most chips, after a chip reset, the ethernet address is read from the
1152 * station address PROM at the base address and programmed into the
1153 * "Physical Address Registers" CSR12-14.
1154 * As a precautionary measure, we read the PROM values and complain if
1155 * they disagree with the CSRs. Either way, we use the CSR values, and
1156 * double check that they are valid.
1157 */
1158 for (i = 0; i < 3; i++) {
1159 unsigned int val;
1160 val = a->read_csr(ioaddr, i+12) & 0x0ffff;
1161 /* There may be endianness issues here. */
1162 dev->dev_addr[2*i] = val & 0x0ff;
1163 dev->dev_addr[2*i+1] = (val >> 8) & 0x0ff;
1164 }
1165
1166 /* read PROM address and compare with CSR address */
1167 for (i = 0; i < 6; i++)
1168 promaddr[i] = inb(ioaddr + i);
1169
1170 if (memcmp(promaddr, dev->dev_addr, 6)
1171 || !is_valid_ether_addr(dev->dev_addr)) {
1172 #ifndef __powerpc__
1173 if (is_valid_ether_addr(promaddr)) {
1174 #else
1175 if (!is_valid_ether_addr(dev->dev_addr)
1176 && is_valid_ether_addr(promaddr)) {
1177 #endif
1178 if (pcnet32_debug & NETIF_MSG_PROBE) {
1179 printk(" warning: CSR address invalid,\n");
1180 printk(KERN_INFO " using instead PROM address of");
1181 }
1182 memcpy(dev->dev_addr, promaddr, 6);
1183 }
1184 }
1185
1186 /* if the ethernet address is not valid, force to 00:00:00:00:00:00 */
1187 if (!is_valid_ether_addr(dev->dev_addr))
1188 memset(dev->dev_addr, 0, sizeof(dev->dev_addr));
1189
1190 if (pcnet32_debug & NETIF_MSG_PROBE) {
1191 for (i = 0; i < 6; i++)
1192 printk(" %2.2x", dev->dev_addr[i]);
1193
1194 /* Version 0x2623 and 0x2624 */
1195 if (((chip_version + 1) & 0xfffe) == 0x2624) {
1196 i = a->read_csr(ioaddr, 80) & 0x0C00; /* Check tx_start_pt */
1197 printk("\n" KERN_INFO " tx_start_pt(0x%04x):",i);
1198 switch(i>>10) {
1199 case 0: printk(" 20 bytes,"); break;
1200 case 1: printk(" 64 bytes,"); break;
1201 case 2: printk(" 128 bytes,"); break;
1202 case 3: printk("~220 bytes,"); break;
1203 }
1204 i = a->read_bcr(ioaddr, 18); /* Check Burst/Bus control */
1205 printk(" BCR18(%x):",i&0xffff);
1206 if (i & (1<<5)) printk("BurstWrEn ");
1207 if (i & (1<<6)) printk("BurstRdEn ");
1208 if (i & (1<<7)) printk("DWordIO ");
1209 if (i & (1<<11)) printk("NoUFlow ");
1210 i = a->read_bcr(ioaddr, 25);
1211 printk("\n" KERN_INFO " SRAMSIZE=0x%04x,",i<<8);
1212 i = a->read_bcr(ioaddr, 26);
1213 printk(" SRAM_BND=0x%04x,",i<<8);
1214 i = a->read_bcr(ioaddr, 27);
1215 if (i & (1<<14)) printk("LowLatRx");
1216 }
1217 }
1218
1219 dev->base_addr = ioaddr;
1220 /* pci_alloc_consistent returns page-aligned memory, so we do not have to check the alignment */
1221 if ((lp = pci_alloc_consistent(pdev, sizeof(*lp), &lp_dma_addr)) == NULL) {
1222 if (pcnet32_debug & NETIF_MSG_PROBE)
1223 printk(KERN_ERR PFX "Consistent memory allocation failed.\n");
1224 ret = -ENOMEM;
1225 goto err_free_netdev;
1226 }
1227
1228 memset(lp, 0, sizeof(*lp));
1229 lp->dma_addr = lp_dma_addr;
1230 lp->pci_dev = pdev;
1231
1232 spin_lock_init(&lp->lock);
1233
1234 SET_MODULE_OWNER(dev);
1235 SET_NETDEV_DEV(dev, &pdev->dev);
1236 dev->priv = lp;
1237 lp->name = chipname;
1238 lp->shared_irq = shared;
1239 lp->mii_if.full_duplex = fdx;
1240 lp->mii_if.phy_id_mask = 0x1f;
1241 lp->mii_if.reg_num_mask = 0x1f;
1242 lp->dxsuflo = dxsuflo;
1243 lp->mii = mii;
1244 lp->msg_enable = pcnet32_debug;
1245 if ((cards_found >= MAX_UNITS) || (options[cards_found] > sizeof(options_mapping)))
1246 lp->options = PCNET32_PORT_ASEL;
1247 else
1248 lp->options = options_mapping[options[cards_found]];
1249 lp->mii_if.dev = dev;
1250 lp->mii_if.mdio_read = mdio_read;
1251 lp->mii_if.mdio_write = mdio_write;
1252
1253 if (fdx && !(lp->options & PCNET32_PORT_ASEL) &&
1254 ((cards_found>=MAX_UNITS) || full_duplex[cards_found]))
1255 lp->options |= PCNET32_PORT_FD;
1256
1257 if (!a) {
1258 if (pcnet32_debug & NETIF_MSG_PROBE)
1259 printk(KERN_ERR PFX "No access methods\n");
1260 ret = -ENODEV;
1261 goto err_free_consistent;
1262 }
1263 lp->a = *a;
1264
1265 /* detect special T1/E1 WAN card by checking for MAC address */
1266 if (dev->dev_addr[0] == 0x00 && dev->dev_addr[1] == 0xe0
1267 && dev->dev_addr[2] == 0x75)
1268 lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI;
1269
1270 lp->init_block.mode = le16_to_cpu(0x0003); /* Disable Rx and Tx. */
1271 lp->init_block.tlen_rlen = le16_to_cpu(TX_RING_LEN_BITS | RX_RING_LEN_BITS);
1272 for (i = 0; i < 6; i++)
1273 lp->init_block.phys_addr[i] = dev->dev_addr[i];
1274 lp->init_block.filter[0] = 0x00000000;
1275 lp->init_block.filter[1] = 0x00000000;
1276 lp->init_block.rx_ring = (u32)le32_to_cpu(lp->dma_addr +
1277 offsetof(struct pcnet32_private, rx_ring));
1278 lp->init_block.tx_ring = (u32)le32_to_cpu(lp->dma_addr +
1279 offsetof(struct pcnet32_private, tx_ring));
1280
1281 /* switch pcnet32 to 32bit mode */
1282 a->write_bcr(ioaddr, 20, 2);
1283
1284 a->write_csr(ioaddr, 1, (lp->dma_addr + offsetof(struct pcnet32_private,
1285 init_block)) & 0xffff);
1286 a->write_csr(ioaddr, 2, (lp->dma_addr + offsetof(struct pcnet32_private,
1287 init_block)) >> 16);
1288
1289 if (pdev) { /* use the IRQ provided by PCI */
1290 dev->irq = pdev->irq;
1291 if (pcnet32_debug & NETIF_MSG_PROBE)
1292 printk(" assigned IRQ %d.\n", dev->irq);
1293 } else {
1294 unsigned long irq_mask = probe_irq_on();
1295
1296 /*
1297 * To auto-IRQ we enable the initialization-done and DMA error
1298 * interrupts. For ISA boards we get a DMA error, but VLB and PCI
1299 * boards will work.
1300 */
1301 /* Trigger an initialization just for the interrupt. */
1302 a->write_csr (ioaddr, 0, 0x41);
1303 mdelay (1);
1304
1305 dev->irq = probe_irq_off (irq_mask);
1306 if (!dev->irq) {
1307 if (pcnet32_debug & NETIF_MSG_PROBE)
1308 printk(", failed to detect IRQ line.\n");
1309 ret = -ENODEV;
1310 goto err_free_consistent;
1311 }
1312 if (pcnet32_debug & NETIF_MSG_PROBE)
1313 printk(", probed IRQ %d.\n", dev->irq);
1314 }
1315
1316 /* Set the mii phy_id so that we can query the link state */
1317 if (lp->mii)
1318 lp->mii_if.phy_id = ((lp->a.read_bcr (ioaddr, 33)) >> 5) & 0x1f;
1319
1320 init_timer (&lp->watchdog_timer);
1321 lp->watchdog_timer.data = (unsigned long) dev;
1322 lp->watchdog_timer.function = (void *) &pcnet32_watchdog;
1323
1324 /* The PCNET32-specific entries in the device structure. */
1325 dev->open = &pcnet32_open;
1326 dev->hard_start_xmit = &pcnet32_start_xmit;
1327 dev->stop = &pcnet32_close;
1328 dev->get_stats = &pcnet32_get_stats;
1329 dev->set_multicast_list = &pcnet32_set_multicast_list;
1330 dev->do_ioctl = &pcnet32_ioctl;
1331 dev->ethtool_ops = &pcnet32_ethtool_ops;
1332 dev->tx_timeout = pcnet32_tx_timeout;
1333 dev->watchdog_timeo = (5*HZ);
1334
1335 #ifdef CONFIG_NET_POLL_CONTROLLER
1336 dev->poll_controller = pcnet32_poll_controller;
1337 #endif
1338
1339 /* Fill in the generic fields of the device structure. */
1340 if (register_netdev(dev))
1341 goto err_free_consistent;
1342
1343 if (pdev) {
1344 pci_set_drvdata(pdev, dev);
1345 } else {
1346 lp->next = pcnet32_dev;
1347 pcnet32_dev = dev;
1348 }
1349
1350 if (pcnet32_debug & NETIF_MSG_PROBE)
1351 printk(KERN_INFO "%s: registered as %s\n", dev->name, lp->name);
1352 cards_found++;
1353
1354 /* enable LED writes */
1355 a->write_bcr(ioaddr, 2, a->read_bcr(ioaddr, 2) | 0x1000);
1356
1357 return 0;
1358
1359 err_free_consistent:
1360 pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr);
1361 err_free_netdev:
1362 free_netdev(dev);
1363 err_release_region:
1364 release_region(ioaddr, PCNET32_TOTAL_SIZE);
1365 return ret;
1366 }
1367
1368
1369 static int
1370 pcnet32_open(struct net_device *dev)
1371 {
1372 struct pcnet32_private *lp = dev->priv;
1373 unsigned long ioaddr = dev->base_addr;
1374 u16 val;
1375 int i;
1376 int rc;
1377 unsigned long flags;
1378
1379 if (request_irq(dev->irq, &pcnet32_interrupt,
1380 lp->shared_irq ? SA_SHIRQ : 0, dev->name, (void *)dev)) {
1381 return -EAGAIN;
1382 }
1383
1384 spin_lock_irqsave(&lp->lock, flags);
1385 /* Check for a valid station address */
1386 if (!is_valid_ether_addr(dev->dev_addr)) {
1387 rc = -EINVAL;
1388 goto err_free_irq;
1389 }
1390
1391 /* Reset the PCNET32 */
1392 lp->a.reset (ioaddr);
1393
1394 /* switch pcnet32 to 32bit mode */
1395 lp->a.write_bcr (ioaddr, 20, 2);
1396
1397 if (netif_msg_ifup(lp))
1398 printk(KERN_DEBUG "%s: pcnet32_open() irq %d tx/rx rings %#x/%#x init %#x.\n",
1399 dev->name, dev->irq,
1400 (u32) (lp->dma_addr + offsetof(struct pcnet32_private, tx_ring)),
1401 (u32) (lp->dma_addr + offsetof(struct pcnet32_private, rx_ring)),
1402 (u32) (lp->dma_addr + offsetof(struct pcnet32_private, init_block)));
1403
1404 /* set/reset autoselect bit */
1405 val = lp->a.read_bcr (ioaddr, 2) & ~2;
1406 if (lp->options & PCNET32_PORT_ASEL)
1407 val |= 2;
1408 lp->a.write_bcr (ioaddr, 2, val);
1409
1410 /* handle full duplex setting */
1411 if (lp->mii_if.full_duplex) {
1412 val = lp->a.read_bcr (ioaddr, 9) & ~3;
1413 if (lp->options & PCNET32_PORT_FD) {
1414 val |= 1;
1415 if (lp->options == (PCNET32_PORT_FD | PCNET32_PORT_AUI))
1416 val |= 2;
1417 } else if (lp->options & PCNET32_PORT_ASEL) {
1418 /* workaround of xSeries250, turn on for 79C975 only */
1419 i = ((lp->a.read_csr(ioaddr, 88) |
1420 (lp->a.read_csr(ioaddr,89) << 16)) >> 12) & 0xffff;
1421 if (i == 0x2627)
1422 val |= 3;
1423 }
1424 lp->a.write_bcr (ioaddr, 9, val);
1425 }
1426
1427 /* set/reset GPSI bit in test register */
1428 val = lp->a.read_csr (ioaddr, 124) & ~0x10;
1429 if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI)
1430 val |= 0x10;
1431 lp->a.write_csr (ioaddr, 124, val);
1432
1433 /* Allied Telesyn AT 2700/2701 FX looses the link, so skip that */
1434 if (lp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_AT &&
1435 (lp->pci_dev->subsystem_device == PCI_SUBDEVICE_ID_AT_2700FX ||
1436 lp->pci_dev->subsystem_device == PCI_SUBDEVICE_ID_AT_2701FX)) {
1437 printk(KERN_DEBUG "%s: Skipping PHY selection.\n", dev->name);
1438 } else {
1439 /*
1440 * 24 Jun 2004 according AMD, in order to change the PHY,
1441 * DANAS (or DISPM for 79C976) must be set; then select the speed,
1442 * duplex, and/or enable auto negotiation, and clear DANAS
1443 */
1444 if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) {
1445 lp->a.write_bcr(ioaddr, 32,
1446 lp->a.read_bcr(ioaddr, 32) | 0x0080);
1447 /* disable Auto Negotiation, set 10Mpbs, HD */
1448 val = lp->a.read_bcr(ioaddr, 32) & ~0xb8;
1449 if (lp->options & PCNET32_PORT_FD)
1450 val |= 0x10;
1451 if (lp->options & PCNET32_PORT_100)
1452 val |= 0x08;
1453 lp->a.write_bcr (ioaddr, 32, val);
1454 } else {
1455 if (lp->options & PCNET32_PORT_ASEL) {
1456 lp->a.write_bcr(ioaddr, 32,
1457 lp->a.read_bcr(ioaddr, 32) | 0x0080);
1458 /* enable auto negotiate, setup, disable fd */
1459 val = lp->a.read_bcr(ioaddr, 32) & ~0x98;
1460 val |= 0x20;
1461 lp->a.write_bcr(ioaddr, 32, val);
1462 }
1463 }
1464 }
1465
1466 #ifdef DO_DXSUFLO
1467 if (lp->dxsuflo) { /* Disable transmit stop on underflow */
1468 val = lp->a.read_csr (ioaddr, 3);
1469 val |= 0x40;
1470 lp->a.write_csr (ioaddr, 3, val);
1471 }
1472 #endif
1473
1474 lp->init_block.mode = le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7);
1475 pcnet32_load_multicast(dev);
1476
1477 if (pcnet32_init_ring(dev)) {
1478 rc = -ENOMEM;
1479 goto err_free_ring;
1480 }
1481
1482 /* Re-initialize the PCNET32, and start it when done. */
1483 lp->a.write_csr (ioaddr, 1, (lp->dma_addr +
1484 offsetof(struct pcnet32_private, init_block)) & 0xffff);
1485 lp->a.write_csr (ioaddr, 2, (lp->dma_addr +
1486 offsetof(struct pcnet32_private, init_block)) >> 16);
1487
1488 lp->a.write_csr (ioaddr, 4, 0x0915);
1489 lp->a.write_csr (ioaddr, 0, 0x0001);
1490
1491 netif_start_queue(dev);
1492
1493 /* If we have mii, print the link status and start the watchdog */
1494 if (lp->mii) {
1495 mii_check_media (&lp->mii_if, netif_msg_link(lp), 1);
1496 mod_timer (&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT);
1497 }
1498
1499 i = 0;
1500 while (i++ < 100)
1501 if (lp->a.read_csr (ioaddr, 0) & 0x0100)
1502 break;
1503 /*
1504 * We used to clear the InitDone bit, 0x0100, here but Mark Stockton
1505 * reports that doing so triggers a bug in the '974.
1506 */
1507 lp->a.write_csr (ioaddr, 0, 0x0042);
1508
1509 if (netif_msg_ifup(lp))
1510 printk(KERN_DEBUG "%s: pcnet32 open after %d ticks, init block %#x csr0 %4.4x.\n",
1511 dev->name, i, (u32) (lp->dma_addr +
1512 offsetof(struct pcnet32_private, init_block)),
1513 lp->a.read_csr(ioaddr, 0));
1514
1515 spin_unlock_irqrestore(&lp->lock, flags);
1516
1517 return 0; /* Always succeed */
1518
1519 err_free_ring:
1520 /* free any allocated skbuffs */
1521 for (i = 0; i < RX_RING_SIZE; i++) {
1522 lp->rx_ring[i].status = 0;
1523 if (lp->rx_skbuff[i]) {
1524 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[i], PKT_BUF_SZ-2,
1525 PCI_DMA_FROMDEVICE);
1526 dev_kfree_skb(lp->rx_skbuff[i]);
1527 }
1528 lp->rx_skbuff[i] = NULL;
1529 lp->rx_dma_addr[i] = 0;
1530 }
1531 /*
1532 * Switch back to 16bit mode to avoid problems with dumb
1533 * DOS packet driver after a warm reboot
1534 */
1535 lp->a.write_bcr (ioaddr, 20, 4);
1536
1537 err_free_irq:
1538 spin_unlock_irqrestore(&lp->lock, flags);
1539 free_irq(dev->irq, dev);
1540 return rc;
1541 }
1542
1543 /*
1544 * The LANCE has been halted for one reason or another (busmaster memory
1545 * arbitration error, Tx FIFO underflow, driver stopped it to reconfigure,
1546 * etc.). Modern LANCE variants always reload their ring-buffer
1547 * configuration when restarted, so we must reinitialize our ring
1548 * context before restarting. As part of this reinitialization,
1549 * find all packets still on the Tx ring and pretend that they had been
1550 * sent (in effect, drop the packets on the floor) - the higher-level
1551 * protocols will time out and retransmit. It'd be better to shuffle
1552 * these skbs to a temp list and then actually re-Tx them after
1553 * restarting the chip, but I'm too lazy to do so right now. dplatt@3do.com
1554 */
1555
1556 static void
1557 pcnet32_purge_tx_ring(struct net_device *dev)
1558 {
1559 struct pcnet32_private *lp = dev->priv;
1560 int i;
1561
1562 for (i = 0; i < TX_RING_SIZE; i++) {
1563 lp->tx_ring[i].status = 0; /* CPU owns buffer */
1564 wmb(); /* Make sure adapter sees owner change */
1565 if (lp->tx_skbuff[i]) {
1566 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i],
1567 lp->tx_skbuff[i]->len, PCI_DMA_TODEVICE);
1568 dev_kfree_skb_any(lp->tx_skbuff[i]);
1569 }
1570 lp->tx_skbuff[i] = NULL;
1571 lp->tx_dma_addr[i] = 0;
1572 }
1573 }
1574
1575
1576 /* Initialize the PCNET32 Rx and Tx rings. */
1577 static int
1578 pcnet32_init_ring(struct net_device *dev)
1579 {
1580 struct pcnet32_private *lp = dev->priv;
1581 int i;
1582
1583 lp->tx_full = 0;
1584 lp->cur_rx = lp->cur_tx = 0;
1585 lp->dirty_rx = lp->dirty_tx = 0;
1586
1587 for (i = 0; i < RX_RING_SIZE; i++) {
1588 struct sk_buff *rx_skbuff = lp->rx_skbuff[i];
1589 if (rx_skbuff == NULL) {
1590 if (!(rx_skbuff = lp->rx_skbuff[i] = dev_alloc_skb (PKT_BUF_SZ))) {
1591 /* there is not much, we can do at this point */
1592 if (pcnet32_debug & NETIF_MSG_DRV)
1593 printk(KERN_ERR "%s: pcnet32_init_ring dev_alloc_skb failed.\n",
1594 dev->name);
1595 return -1;
1596 }
1597 skb_reserve (rx_skbuff, 2);
1598 }
1599
1600 rmb();
1601 if (lp->rx_dma_addr[i] == 0)
1602 lp->rx_dma_addr[i] = pci_map_single(lp->pci_dev, rx_skbuff->tail,
1603 PKT_BUF_SZ-2, PCI_DMA_FROMDEVICE);
1604 lp->rx_ring[i].base = (u32)le32_to_cpu(lp->rx_dma_addr[i]);
1605 lp->rx_ring[i].buf_length = le16_to_cpu(2-PKT_BUF_SZ);
1606 wmb(); /* Make sure owner changes after all others are visible */
1607 lp->rx_ring[i].status = le16_to_cpu(0x8000);
1608 }
1609 /* The Tx buffer address is filled in as needed, but we do need to clear
1610 * the upper ownership bit. */
1611 for (i = 0; i < TX_RING_SIZE; i++) {
1612 lp->tx_ring[i].status = 0; /* CPU owns buffer */
1613 wmb(); /* Make sure adapter sees owner change */
1614 lp->tx_ring[i].base = 0;
1615 lp->tx_dma_addr[i] = 0;
1616 }
1617
1618 lp->init_block.tlen_rlen = le16_to_cpu(TX_RING_LEN_BITS | RX_RING_LEN_BITS);
1619 for (i = 0; i < 6; i++)
1620 lp->init_block.phys_addr[i] = dev->dev_addr[i];
1621 lp->init_block.rx_ring = (u32)le32_to_cpu(lp->dma_addr +
1622 offsetof(struct pcnet32_private, rx_ring));
1623 lp->init_block.tx_ring = (u32)le32_to_cpu(lp->dma_addr +
1624 offsetof(struct pcnet32_private, tx_ring));
1625 wmb(); /* Make sure all changes are visible */
1626 return 0;
1627 }
1628
1629 /* the pcnet32 has been issued a stop or reset. Wait for the stop bit
1630 * then flush the pending transmit operations, re-initialize the ring,
1631 * and tell the chip to initialize.
1632 */
1633 static void
1634 pcnet32_restart(struct net_device *dev, unsigned int csr0_bits)
1635 {
1636 struct pcnet32_private *lp = dev->priv;
1637 unsigned long ioaddr = dev->base_addr;
1638 int i;
1639
1640 /* wait for stop */
1641 for (i=0; i<100; i++)
1642 if (lp->a.read_csr(ioaddr, 0) & 0x0004)
1643 break;
1644
1645 if (i >= 100 && netif_msg_drv(lp))
1646 printk(KERN_ERR "%s: pcnet32_restart timed out waiting for stop.\n",
1647 dev->name);
1648
1649 pcnet32_purge_tx_ring(dev);
1650 if (pcnet32_init_ring(dev))
1651 return;
1652
1653 /* ReInit Ring */
1654 lp->a.write_csr (ioaddr, 0, 1);
1655 i = 0;
1656 while (i++ < 1000)
1657 if (lp->a.read_csr (ioaddr, 0) & 0x0100)
1658 break;
1659
1660 lp->a.write_csr (ioaddr, 0, csr0_bits);
1661 }
1662
1663
1664 static void
1665 pcnet32_tx_timeout (struct net_device *dev)
1666 {
1667 struct pcnet32_private *lp = dev->priv;
1668 unsigned long ioaddr = dev->base_addr, flags;
1669
1670 spin_lock_irqsave(&lp->lock, flags);
1671 /* Transmitter timeout, serious problems. */
1672 if (pcnet32_debug & NETIF_MSG_DRV)
1673 printk(KERN_ERR "%s: transmit timed out, status %4.4x, resetting.\n",
1674 dev->name, lp->a.read_csr(ioaddr, 0));
1675 lp->a.write_csr (ioaddr, 0, 0x0004);
1676 lp->stats.tx_errors++;
1677 if (netif_msg_tx_err(lp)) {
1678 int i;
1679 printk(KERN_DEBUG " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.",
1680 lp->dirty_tx, lp->cur_tx, lp->tx_full ? " (full)" : "",
1681 lp->cur_rx);
1682 for (i = 0 ; i < RX_RING_SIZE; i++)
1683 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
1684 le32_to_cpu(lp->rx_ring[i].base),
1685 (-le16_to_cpu(lp->rx_ring[i].buf_length)) & 0xffff,
1686 le32_to_cpu(lp->rx_ring[i].msg_length),
1687 le16_to_cpu(lp->rx_ring[i].status));
1688 for (i = 0 ; i < TX_RING_SIZE; i++)
1689 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
1690 le32_to_cpu(lp->tx_ring[i].base),
1691 (-le16_to_cpu(lp->tx_ring[i].length)) & 0xffff,
1692 le32_to_cpu(lp->tx_ring[i].misc),
1693 le16_to_cpu(lp->tx_ring[i].status));
1694 printk("\n");
1695 }
1696 pcnet32_restart(dev, 0x0042);
1697
1698 dev->trans_start = jiffies;
1699 netif_wake_queue(dev);
1700
1701 spin_unlock_irqrestore(&lp->lock, flags);
1702 }
1703
1704
1705 static int
1706 pcnet32_start_xmit(struct sk_buff *skb, struct net_device *dev)
1707 {
1708 struct pcnet32_private *lp = dev->priv;
1709 unsigned long ioaddr = dev->base_addr;
1710 u16 status;
1711 int entry;
1712 unsigned long flags;
1713
1714 spin_lock_irqsave(&lp->lock, flags);
1715
1716 if (netif_msg_tx_queued(lp)) {
1717 printk(KERN_DEBUG "%s: pcnet32_start_xmit() called, csr0 %4.4x.\n",
1718 dev->name, lp->a.read_csr(ioaddr, 0));
1719 }
1720
1721 /* Default status -- will not enable Successful-TxDone
1722 * interrupt when that option is available to us.
1723 */
1724 status = 0x8300;
1725
1726 /* Fill in a Tx ring entry */
1727
1728 /* Mask to ring buffer boundary. */
1729 entry = lp->cur_tx & TX_RING_MOD_MASK;
1730
1731 /* Caution: the write order is important here, set the status
1732 * with the "ownership" bits last. */
1733
1734 lp->tx_ring[entry].length = le16_to_cpu(-skb->len);
1735
1736 lp->tx_ring[entry].misc = 0x00000000;
1737
1738 lp->tx_skbuff[entry] = skb;
1739 lp->tx_dma_addr[entry] = pci_map_single(lp->pci_dev, skb->data, skb->len,
1740 PCI_DMA_TODEVICE);
1741 lp->tx_ring[entry].base = (u32)le32_to_cpu(lp->tx_dma_addr[entry]);
1742 wmb(); /* Make sure owner changes after all others are visible */
1743 lp->tx_ring[entry].status = le16_to_cpu(status);
1744
1745 lp->cur_tx++;
1746 lp->stats.tx_bytes += skb->len;
1747
1748 /* Trigger an immediate send poll. */
1749 lp->a.write_csr (ioaddr, 0, 0x0048);
1750
1751 dev->trans_start = jiffies;
1752
1753 if (lp->tx_ring[(entry+1) & TX_RING_MOD_MASK].base != 0) {
1754 lp->tx_full = 1;
1755 netif_stop_queue(dev);
1756 }
1757 spin_unlock_irqrestore(&lp->lock, flags);
1758 return 0;
1759 }
1760
1761 /* The PCNET32 interrupt handler. */
1762 static irqreturn_t
1763 pcnet32_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1764 {
1765 struct net_device *dev = dev_id;
1766 struct pcnet32_private *lp;
1767 unsigned long ioaddr;
1768 u16 csr0,rap;
1769 int boguscnt = max_interrupt_work;
1770 int must_restart;
1771
1772 if (!dev) {
1773 if (pcnet32_debug & NETIF_MSG_INTR)
1774 printk (KERN_DEBUG "%s(): irq %d for unknown device\n",
1775 __FUNCTION__, irq);
1776 return IRQ_NONE;
1777 }
1778
1779 ioaddr = dev->base_addr;
1780 lp = dev->priv;
1781
1782 spin_lock(&lp->lock);
1783
1784 rap = lp->a.read_rap(ioaddr);
1785 while ((csr0 = lp->a.read_csr (ioaddr, 0)) & 0x8f00 && --boguscnt >= 0) {
1786 if (csr0 == 0xffff) {
1787 break; /* PCMCIA remove happened */
1788 }
1789 /* Acknowledge all of the current interrupt sources ASAP. */
1790 lp->a.write_csr (ioaddr, 0, csr0 & ~0x004f);
1791
1792 must_restart = 0;
1793
1794 if (netif_msg_intr(lp))
1795 printk(KERN_DEBUG "%s: interrupt csr0=%#2.2x new csr=%#2.2x.\n",
1796 dev->name, csr0, lp->a.read_csr (ioaddr, 0));
1797
1798 if (csr0 & 0x0400) /* Rx interrupt */
1799 pcnet32_rx(dev);
1800
1801 if (csr0 & 0x0200) { /* Tx-done interrupt */
1802 unsigned int dirty_tx = lp->dirty_tx;
1803 int delta;
1804
1805 while (dirty_tx != lp->cur_tx) {
1806 int entry = dirty_tx & TX_RING_MOD_MASK;
1807 int status = (short)le16_to_cpu(lp->tx_ring[entry].status);
1808
1809 if (status < 0)
1810 break; /* It still hasn't been Txed */
1811
1812 lp->tx_ring[entry].base = 0;
1813
1814 if (status & 0x4000) {
1815 /* There was an major error, log it. */
1816 int err_status = le32_to_cpu(lp->tx_ring[entry].misc);
1817 lp->stats.tx_errors++;
1818 if (netif_msg_tx_err(lp))
1819 printk(KERN_ERR "%s: Tx error status=%04x err_status=%08x\n",
1820 dev->name, status, err_status);
1821 if (err_status & 0x04000000) lp->stats.tx_aborted_errors++;
1822 if (err_status & 0x08000000) lp->stats.tx_carrier_errors++;
1823 if (err_status & 0x10000000) lp->stats.tx_window_errors++;
1824 #ifndef DO_DXSUFLO
1825 if (err_status & 0x40000000) {
1826 lp->stats.tx_fifo_errors++;
1827 /* Ackk! On FIFO errors the Tx unit is turned off! */
1828 /* Remove this verbosity later! */
1829 if (netif_msg_tx_err(lp))
1830 printk(KERN_ERR "%s: Tx FIFO error! CSR0=%4.4x\n",
1831 dev->name, csr0);
1832 must_restart = 1;
1833 }
1834 #else
1835 if (err_status & 0x40000000) {
1836 lp->stats.tx_fifo_errors++;
1837 if (! lp->dxsuflo) { /* If controller doesn't recover ... */
1838 /* Ackk! On FIFO errors the Tx unit is turned off! */
1839 /* Remove this verbosity later! */
1840 if (netif_msg_tx_err(lp))
1841 printk(KERN_ERR "%s: Tx FIFO error! CSR0=%4.4x\n",
1842 dev->name, csr0);
1843 must_restart = 1;
1844 }
1845 }
1846 #endif
1847 } else {
1848 if (status & 0x1800)
1849 lp->stats.collisions++;
1850 lp->stats.tx_packets++;
1851 }
1852
1853 /* We must free the original skb */
1854 if (lp->tx_skbuff[entry]) {
1855 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[entry],
1856 lp->tx_skbuff[entry]->len, PCI_DMA_TODEVICE);
1857 dev_kfree_skb_irq(lp->tx_skbuff[entry]);
1858 lp->tx_skbuff[entry] = NULL;
1859 lp->tx_dma_addr[entry] = 0;
1860 }
1861 dirty_tx++;
1862 }
1863
1864 delta = (lp->cur_tx - dirty_tx) & (TX_RING_MOD_MASK + TX_RING_SIZE);
1865 if (delta > TX_RING_SIZE) {
1866 if (netif_msg_drv(lp))
1867 printk(KERN_ERR "%s: out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
1868 dev->name, dirty_tx, lp->cur_tx, lp->tx_full);
1869 dirty_tx += TX_RING_SIZE;
1870 delta -= TX_RING_SIZE;
1871 }
1872
1873 if (lp->tx_full &&
1874 netif_queue_stopped(dev) &&
1875 delta < TX_RING_SIZE - 2) {
1876 /* The ring is no longer full, clear tbusy. */
1877 lp->tx_full = 0;
1878 netif_wake_queue (dev);
1879 }
1880 lp->dirty_tx = dirty_tx;
1881 }
1882
1883 /* Log misc errors. */
1884 if (csr0 & 0x4000) lp->stats.tx_errors++; /* Tx babble. */
1885 if (csr0 & 0x1000) {
1886 /*
1887 * this happens when our receive ring is full. This shouldn't
1888 * be a problem as we will see normal rx interrupts for the frames
1889 * in the receive ring. But there are some PCI chipsets (I can
1890 * reproduce this on SP3G with Intel saturn chipset) which have
1891 * sometimes problems and will fill up the receive ring with
1892 * error descriptors. In this situation we don't get a rx
1893 * interrupt, but a missed frame interrupt sooner or later.
1894 * So we try to clean up our receive ring here.
1895 */
1896 pcnet32_rx(dev);
1897 lp->stats.rx_errors++; /* Missed a Rx frame. */
1898 }
1899 if (csr0 & 0x0800) {
1900 if (netif_msg_drv(lp))
1901 printk(KERN_ERR "%s: Bus master arbitration failure, status %4.4x.\n",
1902 dev->name, csr0);
1903 /* unlike for the lance, there is no restart needed */
1904 }
1905
1906 if (must_restart) {
1907 /* reset the chip to clear the error condition, then restart */
1908 lp->a.reset(ioaddr);
1909 lp->a.write_csr(ioaddr, 4, 0x0915);
1910 pcnet32_restart(dev, 0x0002);
1911 netif_wake_queue(dev);
1912 }
1913 }
1914
1915 /* Set interrupt enable. */
1916 lp->a.write_csr (ioaddr, 0, 0x0040);
1917 lp->a.write_rap (ioaddr,rap);
1918
1919 if (netif_msg_intr(lp))
1920 printk(KERN_DEBUG "%s: exiting interrupt, csr0=%#4.4x.\n",
1921 dev->name, lp->a.read_csr (ioaddr, 0));
1922
1923 spin_unlock(&lp->lock);
1924
1925 return IRQ_HANDLED;
1926 }
1927
1928 static int
1929 pcnet32_rx(struct net_device *dev)
1930 {
1931 struct pcnet32_private *lp = dev->priv;
1932 int entry = lp->cur_rx & RX_RING_MOD_MASK;
1933 int boguscnt = RX_RING_SIZE / 2;
1934
1935 /* If we own the next entry, it's a new packet. Send it up. */
1936 while ((short)le16_to_cpu(lp->rx_ring[entry].status) >= 0) {
1937 int status = (short)le16_to_cpu(lp->rx_ring[entry].status) >> 8;
1938
1939 if (status != 0x03) { /* There was an error. */
1940 /*
1941 * There is a tricky error noted by John Murphy,
1942 * <murf@perftech.com> to Russ Nelson: Even with full-sized
1943 * buffers it's possible for a jabber packet to use two
1944 * buffers, with only the last correctly noting the error.
1945 */
1946 if (status & 0x01) /* Only count a general error at the */
1947 lp->stats.rx_errors++; /* end of a packet.*/
1948 if (status & 0x20) lp->stats.rx_frame_errors++;
1949 if (status & 0x10) lp->stats.rx_over_errors++;
1950 if (status & 0x08) lp->stats.rx_crc_errors++;
1951 if (status & 0x04) lp->stats.rx_fifo_errors++;
1952 lp->rx_ring[entry].status &= le16_to_cpu(0x03ff);
1953 } else {
1954 /* Malloc up new buffer, compatible with net-2e. */
1955 short pkt_len = (le32_to_cpu(lp->rx_ring[entry].msg_length) & 0xfff)-4;
1956 struct sk_buff *skb;
1957
1958 /* Discard oversize frames. */
1959 if (unlikely(pkt_len > PKT_BUF_SZ - 2)) {
1960 if (netif_msg_drv(lp))
1961 printk(KERN_ERR "%s: Impossible packet size %d!\n",
1962 dev->name, pkt_len);
1963 lp->stats.rx_errors++;
1964 } else if (pkt_len < 60) {
1965 if (netif_msg_rx_err(lp))
1966 printk(KERN_ERR "%s: Runt packet!\n", dev->name);
1967 lp->stats.rx_errors++;
1968 } else {
1969 int rx_in_place = 0;
1970
1971 if (pkt_len > rx_copybreak) {
1972 struct sk_buff *newskb;
1973
1974 if ((newskb = dev_alloc_skb(PKT_BUF_SZ))) {
1975 skb_reserve (newskb, 2);
1976 skb = lp->rx_skbuff[entry];
1977 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[entry],
1978 PKT_BUF_SZ-2, PCI_DMA_FROMDEVICE);
1979 skb_put (skb, pkt_len);
1980 lp->rx_skbuff[entry] = newskb;
1981 newskb->dev = dev;
1982 lp->rx_dma_addr[entry] =
1983 pci_map_single(lp->pci_dev, newskb->tail,
1984 PKT_BUF_SZ-2, PCI_DMA_FROMDEVICE);
1985 lp->rx_ring[entry].base = le32_to_cpu(lp->rx_dma_addr[entry]);
1986 rx_in_place = 1;
1987 } else
1988 skb = NULL;
1989 } else {
1990 skb = dev_alloc_skb(pkt_len+2);
1991 }
1992
1993 if (skb == NULL) {
1994 int i;
1995 if (netif_msg_drv(lp))
1996 printk(KERN_ERR "%s: Memory squeeze, deferring packet.\n",
1997 dev->name);
1998 for (i = 0; i < RX_RING_SIZE; i++)
1999 if ((short)le16_to_cpu(lp->rx_ring[(entry+i)
2000 & RX_RING_MOD_MASK].status) < 0)
2001 break;
2002
2003 if (i > RX_RING_SIZE -2) {
2004 lp->stats.rx_dropped++;
2005 lp->rx_ring[entry].status |= le16_to_cpu(0x8000);
2006 wmb(); /* Make sure adapter sees owner change */
2007 lp->cur_rx++;
2008 }
2009 break;
2010 }
2011 skb->dev = dev;
2012 if (!rx_in_place) {
2013 skb_reserve(skb,2); /* 16 byte align */
2014 skb_put(skb,pkt_len); /* Make room */
2015 pci_dma_sync_single_for_cpu(lp->pci_dev,
2016 lp->rx_dma_addr[entry],
2017 PKT_BUF_SZ-2,
2018 PCI_DMA_FROMDEVICE);
2019 eth_copy_and_sum(skb,
2020 (unsigned char *)(lp->rx_skbuff[entry]->tail),
2021 pkt_len,0);
2022 pci_dma_sync_single_for_device(lp->pci_dev,
2023 lp->rx_dma_addr[entry],
2024 PKT_BUF_SZ-2,
2025 PCI_DMA_FROMDEVICE);
2026 }
2027 lp->stats.rx_bytes += skb->len;
2028 skb->protocol=eth_type_trans(skb,dev);
2029 netif_rx(skb);
2030 dev->last_rx = jiffies;
2031 lp->stats.rx_packets++;
2032 }
2033 }
2034 /*
2035 * The docs say that the buffer length isn't touched, but Andrew Boyd
2036 * of QNX reports that some revs of the 79C965 clear it.
2037 */
2038 lp->rx_ring[entry].buf_length = le16_to_cpu(2-PKT_BUF_SZ);
2039 wmb(); /* Make sure owner changes after all others are visible */
2040 lp->rx_ring[entry].status |= le16_to_cpu(0x8000);
2041 entry = (++lp->cur_rx) & RX_RING_MOD_MASK;
2042 if (--boguscnt <= 0) break; /* don't stay in loop forever */
2043 }
2044
2045 return 0;
2046 }
2047
2048 static int
2049 pcnet32_close(struct net_device *dev)
2050 {
2051 unsigned long ioaddr = dev->base_addr;
2052 struct pcnet32_private *lp = dev->priv;
2053 int i;
2054 unsigned long flags;
2055
2056 del_timer_sync(&lp->watchdog_timer);
2057
2058 netif_stop_queue(dev);
2059
2060 spin_lock_irqsave(&lp->lock, flags);
2061
2062 lp->stats.rx_missed_errors = lp->a.read_csr (ioaddr, 112);
2063
2064 if (netif_msg_ifdown(lp))
2065 printk(KERN_DEBUG "%s: Shutting down ethercard, status was %2.2x.\n",
2066 dev->name, lp->a.read_csr (ioaddr, 0));
2067
2068 /* We stop the PCNET32 here -- it occasionally polls memory if we don't. */
2069 lp->a.write_csr (ioaddr, 0, 0x0004);
2070
2071 /*
2072 * Switch back to 16bit mode to avoid problems with dumb
2073 * DOS packet driver after a warm reboot
2074 */
2075 lp->a.write_bcr (ioaddr, 20, 4);
2076
2077 spin_unlock_irqrestore(&lp->lock, flags);
2078
2079 free_irq(dev->irq, dev);
2080
2081 spin_lock_irqsave(&lp->lock, flags);
2082
2083 /* free all allocated skbuffs */
2084 for (i = 0; i < RX_RING_SIZE; i++) {
2085 lp->rx_ring[i].status = 0;
2086 wmb(); /* Make sure adapter sees owner change */
2087 if (lp->rx_skbuff[i]) {
2088 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[i], PKT_BUF_SZ-2,
2089 PCI_DMA_FROMDEVICE);
2090 dev_kfree_skb(lp->rx_skbuff[i]);
2091 }
2092 lp->rx_skbuff[i] = NULL;
2093 lp->rx_dma_addr[i] = 0;
2094 }
2095
2096 for (i = 0; i < TX_RING_SIZE; i++) {
2097 lp->tx_ring[i].status = 0; /* CPU owns buffer */
2098 wmb(); /* Make sure adapter sees owner change */
2099 if (lp->tx_skbuff[i]) {
2100 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i],
2101 lp->tx_skbuff[i]->len, PCI_DMA_TODEVICE);
2102 dev_kfree_skb(lp->tx_skbuff[i]);
2103 }
2104 lp->tx_skbuff[i] = NULL;
2105 lp->tx_dma_addr[i] = 0;
2106 }
2107
2108 spin_unlock_irqrestore(&lp->lock, flags);
2109
2110 return 0;
2111 }
2112
2113 static struct net_device_stats *
2114 pcnet32_get_stats(struct net_device *dev)
2115 {
2116 struct pcnet32_private *lp = dev->priv;
2117 unsigned long ioaddr = dev->base_addr;
2118 u16 saved_addr;
2119 unsigned long flags;
2120
2121 spin_lock_irqsave(&lp->lock, flags);
2122 saved_addr = lp->a.read_rap(ioaddr);
2123 lp->stats.rx_missed_errors = lp->a.read_csr (ioaddr, 112);
2124 lp->a.write_rap(ioaddr, saved_addr);
2125 spin_unlock_irqrestore(&lp->lock, flags);
2126
2127 return &lp->stats;
2128 }
2129
2130 /* taken from the sunlance driver, which it took from the depca driver */
2131 static void pcnet32_load_multicast (struct net_device *dev)
2132 {
2133 struct pcnet32_private *lp = dev->priv;
2134 volatile struct pcnet32_init_block *ib = &lp->init_block;
2135 volatile u16 *mcast_table = (u16 *)&ib->filter;
2136 struct dev_mc_list *dmi=dev->mc_list;
2137 char *addrs;
2138 int i;
2139 u32 crc;
2140
2141 /* set all multicast bits */
2142 if (dev->flags & IFF_ALLMULTI) {
2143 ib->filter[0] = 0xffffffff;
2144 ib->filter[1] = 0xffffffff;
2145 return;
2146 }
2147 /* clear the multicast filter */
2148 ib->filter[0] = 0;
2149 ib->filter[1] = 0;
2150
2151 /* Add addresses */
2152 for (i = 0; i < dev->mc_count; i++) {
2153 addrs = dmi->dmi_addr;
2154 dmi = dmi->next;
2155
2156 /* multicast address? */
2157 if (!(*addrs & 1))
2158 continue;
2159
2160 crc = ether_crc_le(6, addrs);
2161 crc = crc >> 26;
2162 mcast_table [crc >> 4] = le16_to_cpu(
2163 le16_to_cpu(mcast_table [crc >> 4]) | (1 << (crc & 0xf)));
2164 }
2165 return;
2166 }
2167
2168
2169 /*
2170 * Set or clear the multicast filter for this adaptor.
2171 */
2172 static void pcnet32_set_multicast_list(struct net_device *dev)
2173 {
2174 unsigned long ioaddr = dev->base_addr, flags;
2175 struct pcnet32_private *lp = dev->priv;
2176
2177 spin_lock_irqsave(&lp->lock, flags);
2178 if (dev->flags&IFF_PROMISC) {
2179 /* Log any net taps. */
2180 if (netif_msg_hw(lp))
2181 printk(KERN_INFO "%s: Promiscuous mode enabled.\n", dev->name);
2182 lp->init_block.mode = le16_to_cpu(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) << 7);
2183 } else {
2184 lp->init_block.mode = le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7);
2185 pcnet32_load_multicast (dev);
2186 }
2187
2188 lp->a.write_csr (ioaddr, 0, 0x0004); /* Temporarily stop the lance. */
2189 pcnet32_restart(dev, 0x0042); /* Resume normal operation */
2190 netif_wake_queue(dev);
2191
2192 spin_unlock_irqrestore(&lp->lock, flags);
2193 }
2194
2195 /* This routine assumes that the lp->lock is held */
2196 static int mdio_read(struct net_device *dev, int phy_id, int reg_num)
2197 {
2198 struct pcnet32_private *lp = dev->priv;
2199 unsigned long ioaddr = dev->base_addr;
2200 u16 val_out;
2201
2202 if (!lp->mii)
2203 return 0;
2204
2205 lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2206 val_out = lp->a.read_bcr(ioaddr, 34);
2207
2208 return val_out;
2209 }
2210
2211 /* This routine assumes that the lp->lock is held */
2212 static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val)
2213 {
2214 struct pcnet32_private *lp = dev->priv;
2215 unsigned long ioaddr = dev->base_addr;
2216
2217 if (!lp->mii)
2218 return;
2219
2220 lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2221 lp->a.write_bcr(ioaddr, 34, val);
2222 }
2223
2224 static int pcnet32_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2225 {
2226 struct pcnet32_private *lp = dev->priv;
2227 int rc;
2228 unsigned long flags;
2229
2230 /* SIOC[GS]MIIxxx ioctls */
2231 if (lp->mii) {
2232 spin_lock_irqsave(&lp->lock, flags);
2233 rc = generic_mii_ioctl(&lp->mii_if, if_mii(rq), cmd, NULL);
2234 spin_unlock_irqrestore(&lp->lock, flags);
2235 } else {
2236 rc = -EOPNOTSUPP;
2237 }
2238
2239 return rc;
2240 }
2241
2242 static void pcnet32_watchdog(struct net_device *dev)
2243 {
2244 struct pcnet32_private *lp = dev->priv;
2245 unsigned long flags;
2246
2247 /* Print the link status if it has changed */
2248 if (lp->mii) {
2249 spin_lock_irqsave(&lp->lock, flags);
2250 mii_check_media (&lp->mii_if, netif_msg_link(lp), 0);
2251 spin_unlock_irqrestore(&lp->lock, flags);
2252 }
2253
2254 mod_timer (&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT);
2255 }
2256
2257 static void __devexit pcnet32_remove_one(struct pci_dev *pdev)
2258 {
2259 struct net_device *dev = pci_get_drvdata(pdev);
2260
2261 if (dev) {
2262 struct pcnet32_private *lp = dev->priv;
2263
2264 unregister_netdev(dev);
2265 release_region(dev->base_addr, PCNET32_TOTAL_SIZE);
2266 pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr);
2267 free_netdev(dev);
2268 pci_disable_device(pdev);
2269 pci_set_drvdata(pdev, NULL);
2270 }
2271 }
2272
2273 static struct pci_driver pcnet32_driver = {
2274 .name = DRV_NAME,
2275 .probe = pcnet32_probe_pci,
2276 .remove = __devexit_p(pcnet32_remove_one),
2277 .id_table = pcnet32_pci_tbl,
2278 };
2279
2280 /* An additional parameter that may be passed in... */
2281 static int debug = -1;
2282 static int tx_start_pt = -1;
2283 static int pcnet32_have_pci;
2284
2285 module_param(debug, int, 0);
2286 MODULE_PARM_DESC(debug, DRV_NAME " debug level");
2287 module_param(max_interrupt_work, int, 0);
2288 MODULE_PARM_DESC(max_interrupt_work, DRV_NAME " maximum events handled per interrupt");
2289 module_param(rx_copybreak, int, 0);
2290 MODULE_PARM_DESC(rx_copybreak, DRV_NAME " copy breakpoint for copy-only-tiny-frames");
2291 module_param(tx_start_pt, int, 0);
2292 MODULE_PARM_DESC(tx_start_pt, DRV_NAME " transmit start point (0-3)");
2293 module_param(pcnet32vlb, int, 0);
2294 MODULE_PARM_DESC(pcnet32vlb, DRV_NAME " Vesa local bus (VLB) support (0/1)");
2295 module_param_array(options, int, NULL, 0);
2296 MODULE_PARM_DESC(options, DRV_NAME " initial option setting(s) (0-15)");
2297 module_param_array(full_duplex, int, NULL, 0);
2298 MODULE_PARM_DESC(full_duplex, DRV_NAME " full duplex setting(s) (1)");
2299 /* Module Parameter for HomePNA cards added by Patrick Simmons, 2004 */
2300 module_param_array(homepna, int, NULL, 0);
2301 MODULE_PARM_DESC(homepna, DRV_NAME " mode for 79C978 cards (1 for HomePNA, 0 for Ethernet, default Ethernet");
2302
2303 MODULE_AUTHOR("Thomas Bogendoerfer");
2304 MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards");
2305 MODULE_LICENSE("GPL");
2306
2307 #define PCNET32_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
2308
2309 static int __init pcnet32_init_module(void)
2310 {
2311 printk(KERN_INFO "%s", version);
2312
2313 pcnet32_debug = netif_msg_init(debug, PCNET32_MSG_DEFAULT);
2314
2315 if ((tx_start_pt >= 0) && (tx_start_pt <= 3))
2316 tx_start = tx_start_pt;
2317
2318 /* find the PCI devices */
2319 if (!pci_module_init(&pcnet32_driver))
2320 pcnet32_have_pci = 1;
2321
2322 /* should we find any remaining VLbus devices ? */
2323 if (pcnet32vlb)
2324 pcnet32_probe_vlbus();
2325
2326 if (cards_found && (pcnet32_debug & NETIF_MSG_PROBE))
2327 printk(KERN_INFO PFX "%d cards_found.\n", cards_found);
2328
2329 return (pcnet32_have_pci + cards_found) ? 0 : -ENODEV;
2330 }
2331
2332 static void __exit pcnet32_cleanup_module(void)
2333 {
2334 struct net_device *next_dev;
2335
2336 while (pcnet32_dev) {
2337 struct pcnet32_private *lp = pcnet32_dev->priv;
2338 next_dev = lp->next;
2339 unregister_netdev(pcnet32_dev);
2340 release_region(pcnet32_dev->base_addr, PCNET32_TOTAL_SIZE);
2341 pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr);
2342 free_netdev(pcnet32_dev);
2343 pcnet32_dev = next_dev;
2344 }
2345
2346 if (pcnet32_have_pci)
2347 pci_unregister_driver(&pcnet32_driver);
2348 }
2349
2350 module_init(pcnet32_init_module);
2351 module_exit(pcnet32_cleanup_module);
2352
2353 /*
2354 * Local variables:
2355 * c-indent-level: 4
2356 * tab-width: 8
2357 * End:
2358 */
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