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[TG3]: Add tagged status support.
[linux-2.6/verdex.git] / drivers / serial / ioc4_serial.c
blobba4e13a22a50951484dd23df491942d7109eb7a9
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003-2005 Silicon Graphics, Inc. All Rights Reserved.
7 */
8
9
10 /*
11 * This file contains a module version of the ioc4 serial driver. This
12 * includes all the support functions needed (support functions, etc.)
13 * and the serial driver itself.
14 */
15 #include <linux/errno.h>
16 #include <linux/tty.h>
17 #include <linux/serial.h>
18 #include <linux/serialP.h>
19 #include <linux/circ_buf.h>
20 #include <linux/serial_reg.h>
21 #include <linux/module.h>
22 #include <linux/pci.h>
23 #include <linux/ioc4_common.h>
24 #include <linux/serial_core.h>
25
26 /*
27 * interesting things about the ioc4
28 */
29
30 #define IOC4_NUM_SERIAL_PORTS 4 /* max ports per card */
31 #define IOC4_NUM_CARDS 8 /* max cards per partition */
32
33 #define GET_SIO_IR(_n) (_n == 0) ? (IOC4_SIO_IR_S0) : \
34 (_n == 1) ? (IOC4_SIO_IR_S1) : \
35 (_n == 2) ? (IOC4_SIO_IR_S2) : \
36 (IOC4_SIO_IR_S3)
37
38 #define GET_OTHER_IR(_n) (_n == 0) ? (IOC4_OTHER_IR_S0_MEMERR) : \
39 (_n == 1) ? (IOC4_OTHER_IR_S1_MEMERR) : \
40 (_n == 2) ? (IOC4_OTHER_IR_S2_MEMERR) : \
41 (IOC4_OTHER_IR_S3_MEMERR)
42
43
44 /*
45 * All IOC4 registers are 32 bits wide.
46 */
47
48 /*
49 * PCI Memory Space Map
50 */
51 #define IOC4_PCI_ERR_ADDR_L 0x000 /* Low Error Address */
52 #define IOC4_PCI_ERR_ADDR_VLD (0x1 << 0)
53 #define IOC4_PCI_ERR_ADDR_MST_ID_MSK (0xf << 1)
54 #define IOC4_PCI_ERR_ADDR_MST_NUM_MSK (0xe << 1)
55 #define IOC4_PCI_ERR_ADDR_MST_TYP_MSK (0x1 << 1)
56 #define IOC4_PCI_ERR_ADDR_MUL_ERR (0x1 << 5)
57 #define IOC4_PCI_ERR_ADDR_ADDR_MSK (0x3ffffff << 6)
58
59 /* Interrupt types */
60 #define IOC4_SIO_INTR_TYPE 0
61 #define IOC4_OTHER_INTR_TYPE 1
62 #define IOC4_NUM_INTR_TYPES 2
63
64 /* Bitmasks for IOC4_SIO_IR, IOC4_SIO_IEC, and IOC4_SIO_IES */
65 #define IOC4_SIO_IR_S0_TX_MT 0x00000001 /* Serial port 0 TX empty */
66 #define IOC4_SIO_IR_S0_RX_FULL 0x00000002 /* Port 0 RX buf full */
67 #define IOC4_SIO_IR_S0_RX_HIGH 0x00000004 /* Port 0 RX hiwat */
68 #define IOC4_SIO_IR_S0_RX_TIMER 0x00000008 /* Port 0 RX timeout */
69 #define IOC4_SIO_IR_S0_DELTA_DCD 0x00000010 /* Port 0 delta DCD */
70 #define IOC4_SIO_IR_S0_DELTA_CTS 0x00000020 /* Port 0 delta CTS */
71 #define IOC4_SIO_IR_S0_INT 0x00000040 /* Port 0 pass-thru intr */
72 #define IOC4_SIO_IR_S0_TX_EXPLICIT 0x00000080 /* Port 0 explicit TX thru */
73 #define IOC4_SIO_IR_S1_TX_MT 0x00000100 /* Serial port 1 */
74 #define IOC4_SIO_IR_S1_RX_FULL 0x00000200 /* */
75 #define IOC4_SIO_IR_S1_RX_HIGH 0x00000400 /* */
76 #define IOC4_SIO_IR_S1_RX_TIMER 0x00000800 /* */
77 #define IOC4_SIO_IR_S1_DELTA_DCD 0x00001000 /* */
78 #define IOC4_SIO_IR_S1_DELTA_CTS 0x00002000 /* */
79 #define IOC4_SIO_IR_S1_INT 0x00004000 /* */
80 #define IOC4_SIO_IR_S1_TX_EXPLICIT 0x00008000 /* */
81 #define IOC4_SIO_IR_S2_TX_MT 0x00010000 /* Serial port 2 */
82 #define IOC4_SIO_IR_S2_RX_FULL 0x00020000 /* */
83 #define IOC4_SIO_IR_S2_RX_HIGH 0x00040000 /* */
84 #define IOC4_SIO_IR_S2_RX_TIMER 0x00080000 /* */
85 #define IOC4_SIO_IR_S2_DELTA_DCD 0x00100000 /* */
86 #define IOC4_SIO_IR_S2_DELTA_CTS 0x00200000 /* */
87 #define IOC4_SIO_IR_S2_INT 0x00400000 /* */
88 #define IOC4_SIO_IR_S2_TX_EXPLICIT 0x00800000 /* */
89 #define IOC4_SIO_IR_S3_TX_MT 0x01000000 /* Serial port 3 */
90 #define IOC4_SIO_IR_S3_RX_FULL 0x02000000 /* */
91 #define IOC4_SIO_IR_S3_RX_HIGH 0x04000000 /* */
92 #define IOC4_SIO_IR_S3_RX_TIMER 0x08000000 /* */
93 #define IOC4_SIO_IR_S3_DELTA_DCD 0x10000000 /* */
94 #define IOC4_SIO_IR_S3_DELTA_CTS 0x20000000 /* */
95 #define IOC4_SIO_IR_S3_INT 0x40000000 /* */
96 #define IOC4_SIO_IR_S3_TX_EXPLICIT 0x80000000 /* */
97
98 /* Per device interrupt masks */
99 #define IOC4_SIO_IR_S0 (IOC4_SIO_IR_S0_TX_MT | \
100 IOC4_SIO_IR_S0_RX_FULL | \
101 IOC4_SIO_IR_S0_RX_HIGH | \
102 IOC4_SIO_IR_S0_RX_TIMER | \
103 IOC4_SIO_IR_S0_DELTA_DCD | \
104 IOC4_SIO_IR_S0_DELTA_CTS | \
105 IOC4_SIO_IR_S0_INT | \
106 IOC4_SIO_IR_S0_TX_EXPLICIT)
107 #define IOC4_SIO_IR_S1 (IOC4_SIO_IR_S1_TX_MT | \
108 IOC4_SIO_IR_S1_RX_FULL | \
109 IOC4_SIO_IR_S1_RX_HIGH | \
110 IOC4_SIO_IR_S1_RX_TIMER | \
111 IOC4_SIO_IR_S1_DELTA_DCD | \
112 IOC4_SIO_IR_S1_DELTA_CTS | \
113 IOC4_SIO_IR_S1_INT | \
114 IOC4_SIO_IR_S1_TX_EXPLICIT)
115 #define IOC4_SIO_IR_S2 (IOC4_SIO_IR_S2_TX_MT | \
116 IOC4_SIO_IR_S2_RX_FULL | \
117 IOC4_SIO_IR_S2_RX_HIGH | \
118 IOC4_SIO_IR_S2_RX_TIMER | \
119 IOC4_SIO_IR_S2_DELTA_DCD | \
120 IOC4_SIO_IR_S2_DELTA_CTS | \
121 IOC4_SIO_IR_S2_INT | \
122 IOC4_SIO_IR_S2_TX_EXPLICIT)
123 #define IOC4_SIO_IR_S3 (IOC4_SIO_IR_S3_TX_MT | \
124 IOC4_SIO_IR_S3_RX_FULL | \
125 IOC4_SIO_IR_S3_RX_HIGH | \
126 IOC4_SIO_IR_S3_RX_TIMER | \
127 IOC4_SIO_IR_S3_DELTA_DCD | \
128 IOC4_SIO_IR_S3_DELTA_CTS | \
129 IOC4_SIO_IR_S3_INT | \
130 IOC4_SIO_IR_S3_TX_EXPLICIT)
131
132 /* Bitmasks for IOC4_OTHER_IR, IOC4_OTHER_IEC, and IOC4_OTHER_IES */
133 #define IOC4_OTHER_IR_ATA_INT 0x00000001 /* ATAPI intr pass-thru */
134 #define IOC4_OTHER_IR_ATA_MEMERR 0x00000002 /* ATAPI DMA PCI error */
135 #define IOC4_OTHER_IR_S0_MEMERR 0x00000004 /* Port 0 PCI error */
136 #define IOC4_OTHER_IR_S1_MEMERR 0x00000008 /* Port 1 PCI error */
137 #define IOC4_OTHER_IR_S2_MEMERR 0x00000010 /* Port 2 PCI error */
138 #define IOC4_OTHER_IR_S3_MEMERR 0x00000020 /* Port 3 PCI error */
139
140 /* Bitmasks for IOC4_SIO_CR */
141 #define IOC4_SIO_CR_CMD_PULSE_SHIFT 0 /* byte bus strobe shift */
142 #define IOC4_SIO_CR_ARB_DIAG_TX0 0x00000000
143 #define IOC4_SIO_CR_ARB_DIAG_RX0 0x00000010
144 #define IOC4_SIO_CR_ARB_DIAG_TX1 0x00000020
145 #define IOC4_SIO_CR_ARB_DIAG_RX1 0x00000030
146 #define IOC4_SIO_CR_ARB_DIAG_TX2 0x00000040
147 #define IOC4_SIO_CR_ARB_DIAG_RX2 0x00000050
148 #define IOC4_SIO_CR_ARB_DIAG_TX3 0x00000060
149 #define IOC4_SIO_CR_ARB_DIAG_RX3 0x00000070
150 #define IOC4_SIO_CR_SIO_DIAG_IDLE 0x00000080 /* 0 -> active request among
151 serial ports (ro) */
152 /* Defs for some of the generic I/O pins */
153 #define IOC4_GPCR_UART0_MODESEL 0x10 /* Pin is output to port 0
154 mode sel */
155 #define IOC4_GPCR_UART1_MODESEL 0x20 /* Pin is output to port 1
156 mode sel */
157 #define IOC4_GPCR_UART2_MODESEL 0x40 /* Pin is output to port 2
158 mode sel */
159 #define IOC4_GPCR_UART3_MODESEL 0x80 /* Pin is output to port 3
160 mode sel */
161
162 #define IOC4_GPPR_UART0_MODESEL_PIN 4 /* GIO pin controlling
163 uart 0 mode select */
164 #define IOC4_GPPR_UART1_MODESEL_PIN 5 /* GIO pin controlling
165 uart 1 mode select */
166 #define IOC4_GPPR_UART2_MODESEL_PIN 6 /* GIO pin controlling
167 uart 2 mode select */
168 #define IOC4_GPPR_UART3_MODESEL_PIN 7 /* GIO pin controlling
169 uart 3 mode select */
170
171 /* Bitmasks for serial RX status byte */
172 #define IOC4_RXSB_OVERRUN 0x01 /* Char(s) lost */
173 #define IOC4_RXSB_PAR_ERR 0x02 /* Parity error */
174 #define IOC4_RXSB_FRAME_ERR 0x04 /* Framing error */
175 #define IOC4_RXSB_BREAK 0x08 /* Break character */
176 #define IOC4_RXSB_CTS 0x10 /* State of CTS */
177 #define IOC4_RXSB_DCD 0x20 /* State of DCD */
178 #define IOC4_RXSB_MODEM_VALID 0x40 /* DCD, CTS, and OVERRUN are valid */
179 #define IOC4_RXSB_DATA_VALID 0x80 /* Data byte, FRAME_ERR PAR_ERR
180 * & BREAK valid */
181
182 /* Bitmasks for serial TX control byte */
183 #define IOC4_TXCB_INT_WHEN_DONE 0x20 /* Interrupt after this byte is sent */
184 #define IOC4_TXCB_INVALID 0x00 /* Byte is invalid */
185 #define IOC4_TXCB_VALID 0x40 /* Byte is valid */
186 #define IOC4_TXCB_MCR 0x80 /* Data<7:0> to modem control reg */
187 #define IOC4_TXCB_DELAY 0xc0 /* Delay data<7:0> mSec */
188
189 /* Bitmasks for IOC4_SBBR_L */
190 #define IOC4_SBBR_L_SIZE 0x00000001 /* 0 == 1KB rings, 1 == 4KB rings */
191
192 /* Bitmasks for IOC4_SSCR_<3:0> */
193 #define IOC4_SSCR_RX_THRESHOLD 0x000001ff /* Hiwater mark */
194 #define IOC4_SSCR_TX_TIMER_BUSY 0x00010000 /* TX timer in progress */
195 #define IOC4_SSCR_HFC_EN 0x00020000 /* Hardware flow control enabled */
196 #define IOC4_SSCR_RX_RING_DCD 0x00040000 /* Post RX record on delta-DCD */
197 #define IOC4_SSCR_RX_RING_CTS 0x00080000 /* Post RX record on delta-CTS */
198 #define IOC4_SSCR_DIAG 0x00200000 /* Bypass clock divider for sim */
199 #define IOC4_SSCR_RX_DRAIN 0x08000000 /* Drain RX buffer to memory */
200 #define IOC4_SSCR_DMA_EN 0x10000000 /* Enable ring buffer DMA */
201 #define IOC4_SSCR_DMA_PAUSE 0x20000000 /* Pause DMA */
202 #define IOC4_SSCR_PAUSE_STATE 0x40000000 /* Sets when PAUSE takes effect */
203 #define IOC4_SSCR_RESET 0x80000000 /* Reset DMA channels */
204
205 /* All producer/comsumer pointers are the same bitfield */
206 #define IOC4_PROD_CONS_PTR_4K 0x00000ff8 /* For 4K buffers */
207 #define IOC4_PROD_CONS_PTR_1K 0x000003f8 /* For 1K buffers */
208 #define IOC4_PROD_CONS_PTR_OFF 3
209
210 /* Bitmasks for IOC4_SRCIR_<3:0> */
211 #define IOC4_SRCIR_ARM 0x80000000 /* Arm RX timer */
212
213 /* Bitmasks for IOC4_SHADOW_<3:0> */
214 #define IOC4_SHADOW_DR 0x00000001 /* Data ready */
215 #define IOC4_SHADOW_OE 0x00000002 /* Overrun error */
216 #define IOC4_SHADOW_PE 0x00000004 /* Parity error */
217 #define IOC4_SHADOW_FE 0x00000008 /* Framing error */
218 #define IOC4_SHADOW_BI 0x00000010 /* Break interrupt */
219 #define IOC4_SHADOW_THRE 0x00000020 /* Xmit holding register empty */
220 #define IOC4_SHADOW_TEMT 0x00000040 /* Xmit shift register empty */
221 #define IOC4_SHADOW_RFCE 0x00000080 /* Char in RX fifo has an error */
222 #define IOC4_SHADOW_DCTS 0x00010000 /* Delta clear to send */
223 #define IOC4_SHADOW_DDCD 0x00080000 /* Delta data carrier detect */
224 #define IOC4_SHADOW_CTS 0x00100000 /* Clear to send */
225 #define IOC4_SHADOW_DCD 0x00800000 /* Data carrier detect */
226 #define IOC4_SHADOW_DTR 0x01000000 /* Data terminal ready */
227 #define IOC4_SHADOW_RTS 0x02000000 /* Request to send */
228 #define IOC4_SHADOW_OUT1 0x04000000 /* 16550 OUT1 bit */
229 #define IOC4_SHADOW_OUT2 0x08000000 /* 16550 OUT2 bit */
230 #define IOC4_SHADOW_LOOP 0x10000000 /* Loopback enabled */
231
232 /* Bitmasks for IOC4_SRTR_<3:0> */
233 #define IOC4_SRTR_CNT 0x00000fff /* Reload value for RX timer */
234 #define IOC4_SRTR_CNT_VAL 0x0fff0000 /* Current value of RX timer */
235 #define IOC4_SRTR_CNT_VAL_SHIFT 16
236 #define IOC4_SRTR_HZ 16000 /* SRTR clock frequency */
237
238 /* Serial port register map used for DMA and PIO serial I/O */
239 struct ioc4_serialregs {
240 uint32_t sscr;
241 uint32_t stpir;
242 uint32_t stcir;
243 uint32_t srpir;
244 uint32_t srcir;
245 uint32_t srtr;
246 uint32_t shadow;
247 };
248
249 /* IOC4 UART register map */
250 struct ioc4_uartregs {
251 char i4u_lcr;
252 union {
253 char iir; /* read only */
254 char fcr; /* write only */
255 } u3;
256 union {
257 char ier; /* DLAB == 0 */
258 char dlm; /* DLAB == 1 */
259 } u2;
260 union {
261 char rbr; /* read only, DLAB == 0 */
262 char thr; /* write only, DLAB == 0 */
263 char dll; /* DLAB == 1 */
264 } u1;
265 char i4u_scr;
266 char i4u_msr;
267 char i4u_lsr;
268 char i4u_mcr;
269 };
270
271 /* short names */
272 #define i4u_dll u1.dll
273 #define i4u_ier u2.ier
274 #define i4u_dlm u2.dlm
275 #define i4u_fcr u3.fcr
276
277 /* PCI memory space register map addressed using pci_bar0 */
278 struct ioc4_memregs {
279 struct ioc4_mem {
280 /* Miscellaneous IOC4 registers */
281 uint32_t pci_err_addr_l;
282 uint32_t pci_err_addr_h;
283 uint32_t sio_ir;
284 uint32_t other_ir;
285
286 /* These registers are read-only for general kernel code. */
287 uint32_t sio_ies_ro;
288 uint32_t other_ies_ro;
289 uint32_t sio_iec_ro;
290 uint32_t other_iec_ro;
291 uint32_t sio_cr;
292 uint32_t misc_fill1;
293 uint32_t int_out;
294 uint32_t misc_fill2;
295 uint32_t gpcr_s;
296 uint32_t gpcr_c;
297 uint32_t gpdr;
298 uint32_t misc_fill3;
299 uint32_t gppr_0;
300 uint32_t gppr_1;
301 uint32_t gppr_2;
302 uint32_t gppr_3;
303 uint32_t gppr_4;
304 uint32_t gppr_5;
305 uint32_t gppr_6;
306 uint32_t gppr_7;
307 } ioc4_mem;
308
309 char misc_fill4[0x100 - 0x5C - 4];
310
311 /* ATA/ATAP registers */
312 uint32_t ata_notused[9];
313 char ata_fill1[0x140 - 0x120 - 4];
314 uint32_t ata_notused1[8];
315 char ata_fill2[0x200 - 0x15C - 4];
316
317 /* Keyboard and mouse registers */
318 uint32_t km_notused[5];;
319 char km_fill1[0x300 - 0x210 - 4];
320
321 /* Serial port registers used for DMA serial I/O */
322 struct ioc4_serial {
323 uint32_t sbbr01_l;
324 uint32_t sbbr01_h;
325 uint32_t sbbr23_l;
326 uint32_t sbbr23_h;
327
328 struct ioc4_serialregs port_0;
329 struct ioc4_serialregs port_1;
330 struct ioc4_serialregs port_2;
331 struct ioc4_serialregs port_3;
332 struct ioc4_uartregs uart_0;
333 struct ioc4_uartregs uart_1;
334 struct ioc4_uartregs uart_2;
335 struct ioc4_uartregs uart_3;
336 } ioc4_serial;
337 };
338
339 /* UART clock speed */
340 #define IOC4_SER_XIN_CLK IOC4_SER_XIN_CLK_66
341 #define IOC4_SER_XIN_CLK_66 66666667
342 #define IOC4_SER_XIN_CLK_33 33333333
343
344 #define IOC4_W_IES 0
345 #define IOC4_W_IEC 1
346
347 typedef void ioc4_intr_func_f(void *, uint32_t);
348 typedef ioc4_intr_func_f *ioc4_intr_func_t;
349
350 /* defining this will get you LOTS of great debug info */
351 //#define DEBUG_INTERRUPTS
352 #define DPRINT_CONFIG(_x...) ;
353 //#define DPRINT_CONFIG(_x...) printk _x
354
355 /* number of characters left in xmit buffer before we ask for more */
356 #define WAKEUP_CHARS 256
357
358 /* number of characters we want to transmit to the lower level at a time */
359 #define IOC4_MAX_CHARS 128
360
361 /* Device name we're using */
362 #define DEVICE_NAME "ttyIOC"
363 #define DEVICE_MAJOR 204
364 #define DEVICE_MINOR 50
365
366 /* register offsets */
367 #define IOC4_SERIAL_OFFSET 0x300
368
369 /* flags for next_char_state */
370 #define NCS_BREAK 0x1
371 #define NCS_PARITY 0x2
372 #define NCS_FRAMING 0x4
373 #define NCS_OVERRUN 0x8
374
375 /* cause we need SOME parameters ... */
376 #define MIN_BAUD_SUPPORTED 1200
377 #define MAX_BAUD_SUPPORTED 115200
378
379 /* protocol types supported */
380 enum sio_proto {
381 PROTO_RS232,
382 PROTO_RS422
383 };
384
385 /* Notification types */
386 #define N_DATA_READY 0x01
387 #define N_OUTPUT_LOWAT 0x02
388 #define N_BREAK 0x04
389 #define N_PARITY_ERROR 0x08
390 #define N_FRAMING_ERROR 0x10
391 #define N_OVERRUN_ERROR 0x20
392 #define N_DDCD 0x40
393 #define N_DCTS 0x80
394
395 #define N_ALL_INPUT (N_DATA_READY | N_BREAK | \
396 N_PARITY_ERROR | N_FRAMING_ERROR | \
397 N_OVERRUN_ERROR | N_DDCD | N_DCTS)
398
399 #define N_ALL_OUTPUT N_OUTPUT_LOWAT
400
401 #define N_ALL_ERRORS (N_PARITY_ERROR | N_FRAMING_ERROR | N_OVERRUN_ERROR)
402
403 #define N_ALL (N_DATA_READY | N_OUTPUT_LOWAT | N_BREAK | \
404 N_PARITY_ERROR | N_FRAMING_ERROR | \
405 N_OVERRUN_ERROR | N_DDCD | N_DCTS)
406
407 #define SER_DIVISOR(_x, clk) (((clk) + (_x) * 8) / ((_x) * 16))
408 #define DIVISOR_TO_BAUD(div, clk) ((clk) / 16 / (div))
409
410 /* Some masks */
411 #define LCR_MASK_BITS_CHAR (UART_LCR_WLEN5 | UART_LCR_WLEN6 \
412 | UART_LCR_WLEN7 | UART_LCR_WLEN8)
413 #define LCR_MASK_STOP_BITS (UART_LCR_STOP)
414
415 #define PENDING(_p) (readl(&(_p)->ip_mem->sio_ir) & _p->ip_ienb)
416 #define READ_SIO_IR(_p) readl(&(_p)->ip_mem->sio_ir)
417
418 /* Default to 4k buffers */
419 #ifdef IOC4_1K_BUFFERS
420 #define RING_BUF_SIZE 1024
421 #define IOC4_BUF_SIZE_BIT 0
422 #define PROD_CONS_MASK IOC4_PROD_CONS_PTR_1K
423 #else
424 #define RING_BUF_SIZE 4096
425 #define IOC4_BUF_SIZE_BIT IOC4_SBBR_L_SIZE
426 #define PROD_CONS_MASK IOC4_PROD_CONS_PTR_4K
427 #endif
428
429 #define TOTAL_RING_BUF_SIZE (RING_BUF_SIZE * 4)
430
431 /*
432 * This is the entry saved by the driver - one per card
433 */
434 struct ioc4_control {
435 int ic_irq;
436 struct {
437 /* uart ports are allocated here */
438 struct uart_port icp_uart_port;
439 /* Handy reference material */
440 struct ioc4_port *icp_port;
441 } ic_port[IOC4_NUM_SERIAL_PORTS];
442 struct ioc4_soft *ic_soft;
443 };
444
445 /*
446 * per-IOC4 data structure
447 */
448 #define MAX_IOC4_INTR_ENTS (8 * sizeof(uint32_t))
449 struct ioc4_soft {
450 struct ioc4_mem __iomem *is_ioc4_mem_addr;
451 struct ioc4_serial __iomem *is_ioc4_serial_addr;
452
453 /* Each interrupt type has an entry in the array */
454 struct ioc4_intr_type {
455
456 /*
457 * Each in-use entry in this array contains at least
458 * one nonzero bit in sd_bits; no two entries in this
459 * array have overlapping sd_bits values.
460 */
461 struct ioc4_intr_info {
462 uint32_t sd_bits;
463 ioc4_intr_func_f *sd_intr;
464 void *sd_info;
465 } is_intr_info[MAX_IOC4_INTR_ENTS];
466
467 /* Number of entries active in the above array */
468 atomic_t is_num_intrs;
469 } is_intr_type[IOC4_NUM_INTR_TYPES];
470
471 /* is_ir_lock must be held while
472 * modifying sio_ie values, so
473 * we can be sure that sio_ie is
474 * not changing when we read it
475 * along with sio_ir.
476 */
477 spinlock_t is_ir_lock; /* SIO_IE[SC] mod lock */
478 };
479
480 /* Local port info for each IOC4 serial ports */
481 struct ioc4_port {
482 struct uart_port *ip_port;
483 /* Back ptrs for this port */
484 struct ioc4_control *ip_control;
485 struct pci_dev *ip_pdev;
486 struct ioc4_soft *ip_ioc4_soft;
487
488 /* pci mem addresses */
489 struct ioc4_mem __iomem *ip_mem;
490 struct ioc4_serial __iomem *ip_serial;
491 struct ioc4_serialregs __iomem *ip_serial_regs;
492 struct ioc4_uartregs __iomem *ip_uart_regs;
493
494 /* Ring buffer page for this port */
495 dma_addr_t ip_dma_ringbuf;
496 /* vaddr of ring buffer */
497 struct ring_buffer *ip_cpu_ringbuf;
498
499 /* Rings for this port */
500 struct ring *ip_inring;
501 struct ring *ip_outring;
502
503 /* Hook to port specific values */
504 struct hooks *ip_hooks;
505
506 spinlock_t ip_lock;
507
508 /* Various rx/tx parameters */
509 int ip_baud;
510 int ip_tx_lowat;
511 int ip_rx_timeout;
512
513 /* Copy of notification bits */
514 int ip_notify;
515
516 /* Shadow copies of various registers so we don't need to PIO
517 * read them constantly
518 */
519 uint32_t ip_ienb; /* Enabled interrupts */
520 uint32_t ip_sscr;
521 uint32_t ip_tx_prod;
522 uint32_t ip_rx_cons;
523 int ip_pci_bus_speed;
524 unsigned char ip_flags;
525 };
526
527 /* tx low water mark. We need to notify the driver whenever tx is getting
528 * close to empty so it can refill the tx buffer and keep things going.
529 * Let's assume that if we interrupt 1 ms before the tx goes idle, we'll
530 * have no trouble getting in more chars in time (I certainly hope so).
531 */
532 #define TX_LOWAT_LATENCY 1000
533 #define TX_LOWAT_HZ (1000000 / TX_LOWAT_LATENCY)
534 #define TX_LOWAT_CHARS(baud) (baud / 10 / TX_LOWAT_HZ)
535
536 /* Flags per port */
537 #define INPUT_HIGH 0x01
538 #define DCD_ON 0x02
539 #define LOWAT_WRITTEN 0x04
540 #define READ_ABORTED 0x08
541
542 /* Since each port has different register offsets and bitmasks
543 * for everything, we'll store those that we need in tables so we
544 * don't have to be constantly checking the port we are dealing with.
545 */
546 struct hooks {
547 uint32_t intr_delta_dcd;
548 uint32_t intr_delta_cts;
549 uint32_t intr_tx_mt;
550 uint32_t intr_rx_timer;
551 uint32_t intr_rx_high;
552 uint32_t intr_tx_explicit;
553 uint32_t intr_dma_error;
554 uint32_t intr_clear;
555 uint32_t intr_all;
556 char rs422_select_pin;
557 };
558
559 static struct hooks hooks_array[IOC4_NUM_SERIAL_PORTS] = {
560 /* Values for port 0 */
561 {
562 IOC4_SIO_IR_S0_DELTA_DCD, IOC4_SIO_IR_S0_DELTA_CTS,
563 IOC4_SIO_IR_S0_TX_MT, IOC4_SIO_IR_S0_RX_TIMER,
564 IOC4_SIO_IR_S0_RX_HIGH, IOC4_SIO_IR_S0_TX_EXPLICIT,
565 IOC4_OTHER_IR_S0_MEMERR,
566 (IOC4_SIO_IR_S0_TX_MT | IOC4_SIO_IR_S0_RX_FULL |
567 IOC4_SIO_IR_S0_RX_HIGH | IOC4_SIO_IR_S0_RX_TIMER |
568 IOC4_SIO_IR_S0_DELTA_DCD | IOC4_SIO_IR_S0_DELTA_CTS |
569 IOC4_SIO_IR_S0_INT | IOC4_SIO_IR_S0_TX_EXPLICIT),
570 IOC4_SIO_IR_S0, IOC4_GPPR_UART0_MODESEL_PIN,
571 },
572
573 /* Values for port 1 */
574 {
575 IOC4_SIO_IR_S1_DELTA_DCD, IOC4_SIO_IR_S1_DELTA_CTS,
576 IOC4_SIO_IR_S1_TX_MT, IOC4_SIO_IR_S1_RX_TIMER,
577 IOC4_SIO_IR_S1_RX_HIGH, IOC4_SIO_IR_S1_TX_EXPLICIT,
578 IOC4_OTHER_IR_S1_MEMERR,
579 (IOC4_SIO_IR_S1_TX_MT | IOC4_SIO_IR_S1_RX_FULL |
580 IOC4_SIO_IR_S1_RX_HIGH | IOC4_SIO_IR_S1_RX_TIMER |
581 IOC4_SIO_IR_S1_DELTA_DCD | IOC4_SIO_IR_S1_DELTA_CTS |
582 IOC4_SIO_IR_S1_INT | IOC4_SIO_IR_S1_TX_EXPLICIT),
583 IOC4_SIO_IR_S1, IOC4_GPPR_UART1_MODESEL_PIN,
584 },
585
586 /* Values for port 2 */
587 {
588 IOC4_SIO_IR_S2_DELTA_DCD, IOC4_SIO_IR_S2_DELTA_CTS,
589 IOC4_SIO_IR_S2_TX_MT, IOC4_SIO_IR_S2_RX_TIMER,
590 IOC4_SIO_IR_S2_RX_HIGH, IOC4_SIO_IR_S2_TX_EXPLICIT,
591 IOC4_OTHER_IR_S2_MEMERR,
592 (IOC4_SIO_IR_S2_TX_MT | IOC4_SIO_IR_S2_RX_FULL |
593 IOC4_SIO_IR_S2_RX_HIGH | IOC4_SIO_IR_S2_RX_TIMER |
594 IOC4_SIO_IR_S2_DELTA_DCD | IOC4_SIO_IR_S2_DELTA_CTS |
595 IOC4_SIO_IR_S2_INT | IOC4_SIO_IR_S2_TX_EXPLICIT),
596 IOC4_SIO_IR_S2, IOC4_GPPR_UART2_MODESEL_PIN,
597 },
598
599 /* Values for port 3 */
600 {
601 IOC4_SIO_IR_S3_DELTA_DCD, IOC4_SIO_IR_S3_DELTA_CTS,
602 IOC4_SIO_IR_S3_TX_MT, IOC4_SIO_IR_S3_RX_TIMER,
603 IOC4_SIO_IR_S3_RX_HIGH, IOC4_SIO_IR_S3_TX_EXPLICIT,
604 IOC4_OTHER_IR_S3_MEMERR,
605 (IOC4_SIO_IR_S3_TX_MT | IOC4_SIO_IR_S3_RX_FULL |
606 IOC4_SIO_IR_S3_RX_HIGH | IOC4_SIO_IR_S3_RX_TIMER |
607 IOC4_SIO_IR_S3_DELTA_DCD | IOC4_SIO_IR_S3_DELTA_CTS |
608 IOC4_SIO_IR_S3_INT | IOC4_SIO_IR_S3_TX_EXPLICIT),
609 IOC4_SIO_IR_S3, IOC4_GPPR_UART3_MODESEL_PIN,
610 }
611 };
612
613 /* A ring buffer entry */
614 struct ring_entry {
615 union {
616 struct {
617 uint32_t alldata;
618 uint32_t allsc;
619 } all;
620 struct {
621 char data[4]; /* data bytes */
622 char sc[4]; /* status/control */
623 } s;
624 } u;
625 };
626
627 /* Test the valid bits in any of the 4 sc chars using "allsc" member */
628 #define RING_ANY_VALID \
629 ((uint32_t)(IOC4_RXSB_MODEM_VALID | IOC4_RXSB_DATA_VALID) * 0x01010101)
630
631 #define ring_sc u.s.sc
632 #define ring_data u.s.data
633 #define ring_allsc u.all.allsc
634
635 /* Number of entries per ring buffer. */
636 #define ENTRIES_PER_RING (RING_BUF_SIZE / (int) sizeof(struct ring_entry))
637
638 /* An individual ring */
639 struct ring {
640 struct ring_entry entries[ENTRIES_PER_RING];
641 };
642
643 /* The whole enchilada */
644 struct ring_buffer {
645 struct ring TX_0_OR_2;
646 struct ring RX_0_OR_2;
647 struct ring TX_1_OR_3;
648 struct ring RX_1_OR_3;
649 };
650
651 /* Get a ring from a port struct */
652 #define RING(_p, _wh) &(((struct ring_buffer *)((_p)->ip_cpu_ringbuf))->_wh)
653
654 /* Infinite loop detection.
655 */
656 #define MAXITER 10000000
657
658 /* Prototypes */
659 static void receive_chars(struct uart_port *);
660 static void handle_intr(void *arg, uint32_t sio_ir);
661
662 /**
663 * write_ireg - write the interrupt regs
664 * @ioc4_soft: ptr to soft struct for this port
665 * @val: value to write
666 * @which: which register
667 * @type: which ireg set
668 */
669 static inline void
670 write_ireg(struct ioc4_soft *ioc4_soft, uint32_t val, int which, int type)
671 {
672 struct ioc4_mem __iomem *mem = ioc4_soft->is_ioc4_mem_addr;
673 unsigned long flags;
674
675 spin_lock_irqsave(&ioc4_soft->is_ir_lock, flags);
676
677 switch (type) {
678 case IOC4_SIO_INTR_TYPE:
679 switch (which) {
680 case IOC4_W_IES:
681 writel(val, &mem->sio_ies_ro);
682 break;
683
684 case IOC4_W_IEC:
685 writel(val, &mem->sio_iec_ro);
686 break;
687 }
688 break;
689
690 case IOC4_OTHER_INTR_TYPE:
691 switch (which) {
692 case IOC4_W_IES:
693 writel(val, &mem->other_ies_ro);
694 break;
695
696 case IOC4_W_IEC:
697 writel(val, &mem->other_iec_ro);
698 break;
699 }
700 break;
701
702 default:
703 break;
704 }
705 spin_unlock_irqrestore(&ioc4_soft->is_ir_lock, flags);
706 }
707
708 /**
709 * set_baud - Baud rate setting code
710 * @port: port to set
711 * @baud: baud rate to use
712 */
713 static int set_baud(struct ioc4_port *port, int baud)
714 {
715 int actual_baud;
716 int diff;
717 int lcr;
718 unsigned short divisor;
719 struct ioc4_uartregs __iomem *uart;
720
721 divisor = SER_DIVISOR(baud, port->ip_pci_bus_speed);
722 if (!divisor)
723 return 1;
724 actual_baud = DIVISOR_TO_BAUD(divisor, port->ip_pci_bus_speed);
725
726 diff = actual_baud - baud;
727 if (diff < 0)
728 diff = -diff;
729
730 /* If we're within 1%, we've found a match */
731 if (diff * 100 > actual_baud)
732 return 1;
733
734 uart = port->ip_uart_regs;
735 lcr = readb(&uart->i4u_lcr);
736 writeb(lcr | UART_LCR_DLAB, &uart->i4u_lcr);
737 writeb((unsigned char)divisor, &uart->i4u_dll);
738 writeb((unsigned char)(divisor >> 8), &uart->i4u_dlm);
739 writeb(lcr, &uart->i4u_lcr);
740 return 0;
741 }
742
743
744 /**
745 * get_ioc4_port - given a uart port, return the control structure
746 * @port: uart port
747 */
748 static struct ioc4_port *get_ioc4_port(struct uart_port *the_port)
749 {
750 struct ioc4_control *control = dev_get_drvdata(the_port->dev);
751 int ii;
752
753 if (control) {
754 for ( ii = 0; ii < IOC4_NUM_SERIAL_PORTS; ii++ ) {
755 if (!control->ic_port[ii].icp_port)
756 continue;
757 if (the_port == control->ic_port[ii].icp_port->ip_port)
758 return control->ic_port[ii].icp_port;
759 }
760 }
761 return NULL;
762 }
763
764 /* The IOC4 hardware provides no atomic way to determine if interrupts
765 * are pending since two reads are required to do so. The handler must
766 * read the SIO_IR and the SIO_IES, and take the logical and of the
767 * two. When this value is zero, all interrupts have been serviced and
768 * the handler may return.
769 *
770 * This has the unfortunate "hole" that, if some other CPU or
771 * some other thread or some higher level interrupt manages to
772 * modify SIO_IE between our reads of SIO_IR and SIO_IE, we may
773 * think we have observed SIO_IR&SIO_IE==0 when in fact this
774 * condition never really occurred.
775 *
776 * To solve this, we use a simple spinlock that must be held
777 * whenever modifying SIO_IE; holding this lock while observing
778 * both SIO_IR and SIO_IE guarantees that we do not falsely
779 * conclude that no enabled interrupts are pending.
780 */
781
782 static inline uint32_t
783 pending_intrs(struct ioc4_soft *soft, int type)
784 {
785 struct ioc4_mem __iomem *mem = soft->is_ioc4_mem_addr;
786 unsigned long flag;
787 uint32_t intrs = 0;
788
789 BUG_ON(!((type == IOC4_SIO_INTR_TYPE)
790 || (type == IOC4_OTHER_INTR_TYPE)));
791
792 spin_lock_irqsave(&soft->is_ir_lock, flag);
793
794 switch (type) {
795 case IOC4_SIO_INTR_TYPE:
796 intrs = readl(&mem->sio_ir) & readl(&mem->sio_ies_ro);
797 break;
798
799 case IOC4_OTHER_INTR_TYPE:
800 intrs = readl(&mem->other_ir) & readl(&mem->other_ies_ro);
801
802 /* Don't process any ATA interrupte */
803 intrs &= ~(IOC4_OTHER_IR_ATA_INT | IOC4_OTHER_IR_ATA_MEMERR);
804 break;
805
806 default:
807 break;
808 }
809 spin_unlock_irqrestore(&soft->is_ir_lock, flag);
810 return intrs;
811 }
812
813 /**
814 * port_init - Initialize the sio and ioc4 hardware for a given port
815 * called per port from attach...
816 * @port: port to initialize
817 */
818 static int inline port_init(struct ioc4_port *port)
819 {
820 uint32_t sio_cr;
821 struct hooks *hooks = port->ip_hooks;
822 struct ioc4_uartregs __iomem *uart;
823
824 /* Idle the IOC4 serial interface */
825 writel(IOC4_SSCR_RESET, &port->ip_serial_regs->sscr);
826
827 /* Wait until any pending bus activity for this port has ceased */
828 do
829 sio_cr = readl(&port->ip_mem->sio_cr);
830 while (!(sio_cr & IOC4_SIO_CR_SIO_DIAG_IDLE));
831
832 /* Finish reset sequence */
833 writel(0, &port->ip_serial_regs->sscr);
834
835 /* Once RESET is done, reload cached tx_prod and rx_cons values
836 * and set rings to empty by making prod == cons
837 */
838 port->ip_tx_prod = readl(&port->ip_serial_regs->stcir) & PROD_CONS_MASK;
839 writel(port->ip_tx_prod, &port->ip_serial_regs->stpir);
840 port->ip_rx_cons = readl(&port->ip_serial_regs->srpir) & PROD_CONS_MASK;
841 writel(port->ip_rx_cons | IOC4_SRCIR_ARM, &port->ip_serial_regs->srcir);
842
843 /* Disable interrupts for this 16550 */
844 uart = port->ip_uart_regs;
845 writeb(0, &uart->i4u_lcr);
846 writeb(0, &uart->i4u_ier);
847
848 /* Set the default baud */
849 set_baud(port, port->ip_baud);
850
851 /* Set line control to 8 bits no parity */
852 writeb(UART_LCR_WLEN8 | 0, &uart->i4u_lcr);
853 /* UART_LCR_STOP == 1 stop */
854
855 /* Enable the FIFOs */
856 writeb(UART_FCR_ENABLE_FIFO, &uart->i4u_fcr);
857 /* then reset 16550 FIFOs */
858 writeb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
859 &uart->i4u_fcr);
860
861 /* Clear modem control register */
862 writeb(0, &uart->i4u_mcr);
863
864 /* Clear deltas in modem status register */
865 readb(&uart->i4u_msr);
866
867 /* Only do this once per port pair */
868 if (port->ip_hooks == &hooks_array[0]
869 || port->ip_hooks == &hooks_array[2]) {
870 unsigned long ring_pci_addr;
871 uint32_t __iomem *sbbr_l;
872 uint32_t __iomem *sbbr_h;
873
874 if (port->ip_hooks == &hooks_array[0]) {
875 sbbr_l = &port->ip_serial->sbbr01_l;
876 sbbr_h = &port->ip_serial->sbbr01_h;
877 } else {
878 sbbr_l = &port->ip_serial->sbbr23_l;
879 sbbr_h = &port->ip_serial->sbbr23_h;
880 }
881
882 ring_pci_addr = (unsigned long __iomem)port->ip_dma_ringbuf;
883 DPRINT_CONFIG(("%s: ring_pci_addr 0x%lx\n",
884 __FUNCTION__, ring_pci_addr));
885
886 writel((unsigned int)((uint64_t)ring_pci_addr >> 32), sbbr_h);
887 writel((unsigned int)ring_pci_addr | IOC4_BUF_SIZE_BIT, sbbr_l);
888 }
889
890 /* Set the receive timeout value to 10 msec */
891 writel(IOC4_SRTR_HZ / 100, &port->ip_serial_regs->srtr);
892
893 /* Set rx threshold, enable DMA */
894 /* Set high water mark at 3/4 of full ring */
895 port->ip_sscr = (ENTRIES_PER_RING * 3 / 4);
896 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
897
898 /* Disable and clear all serial related interrupt bits */
899 write_ireg(port->ip_ioc4_soft, hooks->intr_clear,
900 IOC4_W_IEC, IOC4_SIO_INTR_TYPE);
901 port->ip_ienb &= ~hooks->intr_clear;
902 writel(hooks->intr_clear, &port->ip_mem->sio_ir);
903 return 0;
904 }
905
906 /**
907 * handle_dma_error_intr - service any pending DMA error interrupts for the
908 * given port - 2nd level called via sd_intr
909 * @arg: handler arg
910 * @other_ir: ioc4regs
911 */
912 static void handle_dma_error_intr(void *arg, uint32_t other_ir)
913 {
914 struct ioc4_port *port = (struct ioc4_port *)arg;
915 struct hooks *hooks = port->ip_hooks;
916 unsigned int flags;
917
918 spin_lock_irqsave(&port->ip_lock, flags);
919
920 /* ACK the interrupt */
921 writel(hooks->intr_dma_error, &port->ip_mem->other_ir);
922
923 if (readl(&port->ip_mem->pci_err_addr_l) & IOC4_PCI_ERR_ADDR_VLD) {
924 printk(KERN_ERR
925 "PCI error address is 0x%lx, "
926 "master is serial port %c %s\n",
927 (((uint64_t)readl(&port->ip_mem->pci_err_addr_h)
928 << 32)
929 | readl(&port->ip_mem->pci_err_addr_l))
930 & IOC4_PCI_ERR_ADDR_ADDR_MSK, '1' +
931 ((char)(readl(&port->ip_mem-> pci_err_addr_l) &
932 IOC4_PCI_ERR_ADDR_MST_NUM_MSK) >> 1),
933 (readl(&port->ip_mem->pci_err_addr_l)
934 & IOC4_PCI_ERR_ADDR_MST_TYP_MSK)
935 ? "RX" : "TX");
936
937 if (readl(&port->ip_mem->pci_err_addr_l)
938 & IOC4_PCI_ERR_ADDR_MUL_ERR) {
939 printk(KERN_ERR
940 "Multiple errors occurred\n");
941 }
942 }
943 spin_unlock_irqrestore(&port->ip_lock, flags);
944
945 /* Re-enable DMA error interrupts */
946 write_ireg(port->ip_ioc4_soft, hooks->intr_dma_error, IOC4_W_IES,
947 IOC4_OTHER_INTR_TYPE);
948 }
949
950 /**
951 * intr_connect - interrupt connect function
952 * @soft: soft struct for this card
953 * @type: interrupt type
954 * @intrbits: bit pattern to set
955 * @intr: handler function
956 * @info: handler arg
957 */
958 static void
959 intr_connect(struct ioc4_soft *soft, int type,
960 uint32_t intrbits, ioc4_intr_func_f * intr, void *info)
961 {
962 int i;
963 struct ioc4_intr_info *intr_ptr;
964
965 BUG_ON(!((type == IOC4_SIO_INTR_TYPE)
966 || (type == IOC4_OTHER_INTR_TYPE)));
967
968 i = atomic_inc(&soft-> is_intr_type[type].is_num_intrs) - 1;
969 BUG_ON(!(i < MAX_IOC4_INTR_ENTS || (printk("i %d\n", i), 0)));
970
971 /* Save off the lower level interrupt handler */
972 intr_ptr = &soft->is_intr_type[type].is_intr_info[i];
973 intr_ptr->sd_bits = intrbits;
974 intr_ptr->sd_intr = intr;
975 intr_ptr->sd_info = info;
976 }
977
978 /**
979 * ioc4_intr - Top level IOC4 interrupt handler.
980 * @irq: irq value
981 * @arg: handler arg
982 * @regs: registers
983 */
984 static irqreturn_t ioc4_intr(int irq, void *arg, struct pt_regs *regs)
985 {
986 struct ioc4_soft *soft;
987 uint32_t this_ir, this_mir;
988 int xx, num_intrs = 0;
989 int intr_type;
990 int handled = 0;
991 struct ioc4_intr_info *ii;
992
993 soft = arg;
994 for (intr_type = 0; intr_type < IOC4_NUM_INTR_TYPES; intr_type++) {
995 num_intrs = (int)atomic_read(
996 &soft->is_intr_type[intr_type].is_num_intrs);
997
998 this_mir = this_ir = pending_intrs(soft, intr_type);
999
1000 /* Farm out the interrupt to the various drivers depending on
1001 * which interrupt bits are set.
1002 */
1003 for (xx = 0; xx < num_intrs; xx++) {
1004 ii = &soft->is_intr_type[intr_type].is_intr_info[xx];
1005 if ((this_mir = this_ir & ii->sd_bits)) {
1006 /* Disable owned interrupts, call handler */
1007 handled++;
1008 write_ireg(soft, ii->sd_bits, IOC4_W_IEC,
1009 intr_type);
1010 ii->sd_intr(ii->sd_info, this_mir);
1011 this_ir &= ~this_mir;
1012 }
1013 }
1014 if (this_ir) {
1015 printk(KERN_ERR
1016 "unknown IOC4 %s interrupt 0x%x, sio_ir = 0x%x,"
1017 " sio_ies = 0x%x, other_ir = 0x%x :"
1018 "other_ies = 0x%x\n",
1019 (intr_type == IOC4_SIO_INTR_TYPE) ? "sio" :
1020 "other", this_ir,
1021 readl(&soft->is_ioc4_mem_addr->sio_ir),
1022 readl(&soft->is_ioc4_mem_addr->sio_ies_ro),
1023 readl(&soft->is_ioc4_mem_addr->other_ir),
1024 readl(&soft->is_ioc4_mem_addr->other_ies_ro));
1025 }
1026 }
1027 #ifdef DEBUG_INTERRUPTS
1028 {
1029 struct ioc4_mem __iomem *mem = soft->is_ioc4_mem_addr;
1030 spinlock_t *lp = &soft->is_ir_lock;
1031 unsigned long flag;
1032
1033 spin_lock_irqsave(&soft->is_ir_lock, flag);
1034 printk ("%s : %d : mem 0x%p sio_ir 0x%x sio_ies_ro 0x%x "
1035 "other_ir 0x%x other_ies_ro 0x%x mask 0x%x\n",
1036 __FUNCTION__, __LINE__,
1037 (void *)mem, readl(&mem->sio_ir),
1038 readl(&mem->sio_ies_ro),
1039 readl(&mem->other_ir),
1040 readl(&mem->other_ies_ro),
1041 IOC4_OTHER_IR_ATA_INT | IOC4_OTHER_IR_ATA_MEMERR);
1042 spin_unlock_irqrestore(&soft->is_ir_lock, flag);
1043 }
1044 #endif
1045 return handled ? IRQ_HANDLED : IRQ_NONE;
1046 }
1047
1048 /**
1049 * ioc4_attach_local - Device initialization.
1050 * Called at *_attach() time for each
1051 * IOC4 with serial ports in the system.
1052 * @control: ioc4_control ptr
1053 * @pdev: PCI handle for this device
1054 * @soft: soft struct for this device
1055 * @ioc4: ioc4 mem space
1056 */
1057 static int inline ioc4_attach_local(struct pci_dev *pdev,
1058 struct ioc4_control *control,
1059 struct ioc4_soft *soft, void __iomem *ioc4_mem,
1060 void __iomem *ioc4_serial)
1061 {
1062 struct ioc4_port *port;
1063 struct ioc4_port *ports[IOC4_NUM_SERIAL_PORTS];
1064 int port_number;
1065 uint16_t ioc4_revid_min = 62;
1066 uint16_t ioc4_revid;
1067
1068 /* IOC4 firmware must be at least rev 62 */
1069 pci_read_config_word(pdev, PCI_COMMAND_SPECIAL, &ioc4_revid);
1070
1071 printk(KERN_INFO "IOC4 firmware revision %d\n", ioc4_revid);
1072 if (ioc4_revid < ioc4_revid_min) {
1073 printk(KERN_WARNING
1074 "IOC4 serial not supported on firmware rev %d, "
1075 "please upgrade to rev %d or higher\n",
1076 ioc4_revid, ioc4_revid_min);
1077 return -EPERM;
1078 }
1079 BUG_ON(ioc4_mem == NULL);
1080 BUG_ON(ioc4_serial == NULL);
1081
1082 /* Create port structures for each port */
1083 for (port_number = 0; port_number < IOC4_NUM_SERIAL_PORTS;
1084 port_number++) {
1085 port = kmalloc(sizeof(struct ioc4_port), GFP_KERNEL);
1086 if (!port) {
1087 printk(KERN_WARNING
1088 "IOC4 serial memory not available for port\n");
1089 return -ENOMEM;
1090 }
1091 memset(port, 0, sizeof(struct ioc4_port));
1092
1093 /* we need to remember the previous ones, to point back to
1094 * them farther down - setting up the ring buffers.
1095 */
1096 ports[port_number] = port;
1097
1098 /* Allocate buffers and jumpstart the hardware. */
1099 control->ic_port[port_number].icp_port = port;
1100 port->ip_ioc4_soft = soft;
1101 port->ip_pdev = pdev;
1102 port->ip_ienb = 0;
1103 port->ip_pci_bus_speed = IOC4_SER_XIN_CLK;
1104 port->ip_baud = 9600;
1105 port->ip_control = control;
1106 port->ip_mem = ioc4_mem;
1107 port->ip_serial = ioc4_serial;
1108
1109 /* point to the right hook */
1110 port->ip_hooks = &hooks_array[port_number];
1111
1112 /* Get direct hooks to the serial regs and uart regs
1113 * for this port
1114 */
1115 switch (port_number) {
1116 case 0:
1117 port->ip_serial_regs = &(port->ip_serial->port_0);
1118 port->ip_uart_regs = &(port->ip_serial->uart_0);
1119 break;
1120 case 1:
1121 port->ip_serial_regs = &(port->ip_serial->port_1);
1122 port->ip_uart_regs = &(port->ip_serial->uart_1);
1123 break;
1124 case 2:
1125 port->ip_serial_regs = &(port->ip_serial->port_2);
1126 port->ip_uart_regs = &(port->ip_serial->uart_2);
1127 break;
1128 default:
1129 case 3:
1130 port->ip_serial_regs = &(port->ip_serial->port_3);
1131 port->ip_uart_regs = &(port->ip_serial->uart_3);
1132 break;
1133 }
1134
1135 /* ring buffers are 1 to a pair of ports */
1136 if (port_number && (port_number & 1)) {
1137 /* odd use the evens buffer */
1138 port->ip_dma_ringbuf =
1139 ports[port_number - 1]->ip_dma_ringbuf;
1140 port->ip_cpu_ringbuf =
1141 ports[port_number - 1]->ip_cpu_ringbuf;
1142 port->ip_inring = RING(port, RX_1_OR_3);
1143 port->ip_outring = RING(port, TX_1_OR_3);
1144
1145 } else {
1146 if (port->ip_dma_ringbuf == 0) {
1147 port->ip_cpu_ringbuf = pci_alloc_consistent
1148 (pdev, TOTAL_RING_BUF_SIZE,
1149 &port->ip_dma_ringbuf);
1150
1151 }
1152 BUG_ON(!((((int64_t)port->ip_dma_ringbuf) &
1153 (TOTAL_RING_BUF_SIZE - 1)) == 0));
1154 DPRINT_CONFIG(("%s : ip_cpu_ringbuf 0x%p "
1155 "ip_dma_ringbuf 0x%p\n",
1156 __FUNCTION__,
1157 (void *)port->ip_cpu_ringbuf,
1158 (void *)port->ip_dma_ringbuf));
1159 port->ip_inring = RING(port, RX_0_OR_2);
1160 port->ip_outring = RING(port, TX_0_OR_2);
1161 }
1162 DPRINT_CONFIG(("%s : port %d [addr 0x%p] control 0x%p",
1163 __FUNCTION__,
1164 port_number, (void *)port, (void *)control));
1165 DPRINT_CONFIG((" ip_serial_regs 0x%p ip_uart_regs 0x%p\n",
1166 (void *)port->ip_serial_regs,
1167 (void *)port->ip_uart_regs));
1168
1169 /* Initialize the hardware for IOC4 */
1170 port_init(port);
1171
1172 DPRINT_CONFIG(("%s: port_number %d port 0x%p inring 0x%p "
1173 "outring 0x%p\n",
1174 __FUNCTION__,
1175 port_number, (void *)port,
1176 (void *)port->ip_inring,
1177 (void *)port->ip_outring));
1178
1179 /* Attach interrupt handlers */
1180 intr_connect(soft, IOC4_SIO_INTR_TYPE,
1181 GET_SIO_IR(port_number),
1182 handle_intr, port);
1183
1184 intr_connect(soft, IOC4_OTHER_INTR_TYPE,
1185 GET_OTHER_IR(port_number),
1186 handle_dma_error_intr, port);
1187 }
1188 return 0;
1189 }
1190
1191 /**
1192 * enable_intrs - enable interrupts
1193 * @port: port to enable
1194 * @mask: mask to use
1195 */
1196 static void enable_intrs(struct ioc4_port *port, uint32_t mask)
1197 {
1198 struct hooks *hooks = port->ip_hooks;
1199
1200 if ((port->ip_ienb & mask) != mask) {
1201 write_ireg(port->ip_ioc4_soft, mask, IOC4_W_IES,
1202 IOC4_SIO_INTR_TYPE);
1203 port->ip_ienb |= mask;
1204 }
1205
1206 if (port->ip_ienb)
1207 write_ireg(port->ip_ioc4_soft, hooks->intr_dma_error,
1208 IOC4_W_IES, IOC4_OTHER_INTR_TYPE);
1209 }
1210
1211 /**
1212 * local_open - local open a port
1213 * @port: port to open
1214 */
1215 static inline int local_open(struct ioc4_port *port)
1216 {
1217 int spiniter = 0;
1218
1219 port->ip_flags = 0;
1220
1221 /* Pause the DMA interface if necessary */
1222 if (port->ip_sscr & IOC4_SSCR_DMA_EN) {
1223 writel(port->ip_sscr | IOC4_SSCR_DMA_PAUSE,
1224 &port->ip_serial_regs->sscr);
1225 while((readl(&port->ip_serial_regs-> sscr)
1226 & IOC4_SSCR_PAUSE_STATE) == 0) {
1227 spiniter++;
1228 if (spiniter > MAXITER) {
1229 return -1;
1230 }
1231 }
1232 }
1233
1234 /* Reset the input fifo. If the uart received chars while the port
1235 * was closed and DMA is not enabled, the uart may have a bunch of
1236 * chars hanging around in its rx fifo which will not be discarded
1237 * by rclr in the upper layer. We must get rid of them here.
1238 */
1239 writeb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR,
1240 &port->ip_uart_regs->i4u_fcr);
1241
1242 writeb(UART_LCR_WLEN8, &port->ip_uart_regs->i4u_lcr);
1243 /* UART_LCR_STOP == 1 stop */
1244
1245 /* Re-enable DMA, set default threshold to intr whenever there is
1246 * data available.
1247 */
1248 port->ip_sscr &= ~IOC4_SSCR_RX_THRESHOLD;
1249 port->ip_sscr |= 1; /* default threshold */
1250
1251 /* Plug in the new sscr. This implicitly clears the DMA_PAUSE
1252 * flag if it was set above
1253 */
1254 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1255 port->ip_tx_lowat = 1;
1256 return 0;
1257 }
1258
1259 /**
1260 * set_rx_timeout - Set rx timeout and threshold values.
1261 * @port: port to use
1262 * @timeout: timeout value in ticks
1263 */
1264 static inline int set_rx_timeout(struct ioc4_port *port, int timeout)
1265 {
1266 int threshold;
1267
1268 port->ip_rx_timeout = timeout;
1269
1270 /* Timeout is in ticks. Let's figure out how many chars we
1271 * can receive at the current baud rate in that interval
1272 * and set the rx threshold to that amount. There are 4 chars
1273 * per ring entry, so we'll divide the number of chars that will
1274 * arrive in timeout by 4.
1275 * So .... timeout * baud / 10 / HZ / 4, with HZ = 100.
1276 */
1277 threshold = timeout * port->ip_baud / 4000;
1278 if (threshold == 0)
1279 threshold = 1; /* otherwise we'll intr all the time! */
1280
1281 if ((unsigned)threshold > (unsigned)IOC4_SSCR_RX_THRESHOLD)
1282 return 1;
1283
1284 port->ip_sscr &= ~IOC4_SSCR_RX_THRESHOLD;
1285 port->ip_sscr |= threshold;
1286
1287 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1288
1289 /* Now set the rx timeout to the given value
1290 * again timeout * IOC4_SRTR_HZ / HZ
1291 */
1292 timeout = timeout * IOC4_SRTR_HZ / 100;
1293 if (timeout > IOC4_SRTR_CNT)
1294 timeout = IOC4_SRTR_CNT;
1295
1296 writel(timeout, &port->ip_serial_regs->srtr);
1297 return 0;
1298 }
1299
1300 /**
1301 * config_port - config the hardware
1302 * @port: port to config
1303 * @baud: baud rate for the port
1304 * @byte_size: data size
1305 * @stop_bits: number of stop bits
1306 * @parenb: parity enable ?
1307 * @parodd: odd parity ?
1308 */
1309 static inline int
1310 config_port(struct ioc4_port *port,
1311 int baud, int byte_size, int stop_bits, int parenb, int parodd)
1312 {
1313 char lcr, sizebits;
1314 int spiniter = 0;
1315
1316 DPRINT_CONFIG(("%s: baud %d byte_size %d stop %d parenb %d parodd %d\n",
1317 __FUNCTION__, baud, byte_size, stop_bits, parenb, parodd));
1318
1319 if (set_baud(port, baud))
1320 return 1;
1321
1322 switch (byte_size) {
1323 case 5:
1324 sizebits = UART_LCR_WLEN5;
1325 break;
1326 case 6:
1327 sizebits = UART_LCR_WLEN6;
1328 break;
1329 case 7:
1330 sizebits = UART_LCR_WLEN7;
1331 break;
1332 case 8:
1333 sizebits = UART_LCR_WLEN8;
1334 break;
1335 default:
1336 return 1;
1337 }
1338
1339 /* Pause the DMA interface if necessary */
1340 if (port->ip_sscr & IOC4_SSCR_DMA_EN) {
1341 writel(port->ip_sscr | IOC4_SSCR_DMA_PAUSE,
1342 &port->ip_serial_regs->sscr);
1343 while((readl(&port->ip_serial_regs->sscr)
1344 & IOC4_SSCR_PAUSE_STATE) == 0) {
1345 spiniter++;
1346 if (spiniter > MAXITER)
1347 return -1;
1348 }
1349 }
1350
1351 /* Clear relevant fields in lcr */
1352 lcr = readb(&port->ip_uart_regs->i4u_lcr);
1353 lcr &= ~(LCR_MASK_BITS_CHAR | UART_LCR_EPAR |
1354 UART_LCR_PARITY | LCR_MASK_STOP_BITS);
1355
1356 /* Set byte size in lcr */
1357 lcr |= sizebits;
1358
1359 /* Set parity */
1360 if (parenb) {
1361 lcr |= UART_LCR_PARITY;
1362 if (!parodd)
1363 lcr |= UART_LCR_EPAR;
1364 }
1365
1366 /* Set stop bits */
1367 if (stop_bits)
1368 lcr |= UART_LCR_STOP /* 2 stop bits */ ;
1369
1370 writeb(lcr, &port->ip_uart_regs->i4u_lcr);
1371
1372 /* Re-enable the DMA interface if necessary */
1373 if (port->ip_sscr & IOC4_SSCR_DMA_EN) {
1374 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1375 }
1376 port->ip_baud = baud;
1377
1378 /* When we get within this number of ring entries of filling the
1379 * entire ring on tx, place an EXPLICIT intr to generate a lowat
1380 * notification when output has drained.
1381 */
1382 port->ip_tx_lowat = (TX_LOWAT_CHARS(baud) + 3) / 4;
1383 if (port->ip_tx_lowat == 0)
1384 port->ip_tx_lowat = 1;
1385
1386 set_rx_timeout(port, 2);
1387
1388 return 0;
1389 }
1390
1391 /**
1392 * do_write - Write bytes to the port. Returns the number of bytes
1393 * actually written. Called from transmit_chars
1394 * @port: port to use
1395 * @buf: the stuff to write
1396 * @len: how many bytes in 'buf'
1397 */
1398 static inline int do_write(struct ioc4_port *port, char *buf, int len)
1399 {
1400 int prod_ptr, cons_ptr, total = 0;
1401 struct ring *outring;
1402 struct ring_entry *entry;
1403 struct hooks *hooks = port->ip_hooks;
1404
1405 BUG_ON(!(len >= 0));
1406
1407 prod_ptr = port->ip_tx_prod;
1408 cons_ptr = readl(&port->ip_serial_regs->stcir) & PROD_CONS_MASK;
1409 outring = port->ip_outring;
1410
1411 /* Maintain a 1-entry red-zone. The ring buffer is full when
1412 * (cons - prod) % ring_size is 1. Rather than do this subtraction
1413 * in the body of the loop, I'll do it now.
1414 */
1415 cons_ptr = (cons_ptr - (int)sizeof(struct ring_entry)) & PROD_CONS_MASK;
1416
1417 /* Stuff the bytes into the output */
1418 while ((prod_ptr != cons_ptr) && (len > 0)) {
1419 int xx;
1420
1421 /* Get 4 bytes (one ring entry) at a time */
1422 entry = (struct ring_entry *)((caddr_t) outring + prod_ptr);
1423
1424 /* Invalidate all entries */
1425 entry->ring_allsc = 0;
1426
1427 /* Copy in some bytes */
1428 for (xx = 0; (xx < 4) && (len > 0); xx++) {
1429 entry->ring_data[xx] = *buf++;
1430 entry->ring_sc[xx] = IOC4_TXCB_VALID;
1431 len--;
1432 total++;
1433 }
1434
1435 /* If we are within some small threshold of filling up the
1436 * entire ring buffer, we must place an EXPLICIT intr here
1437 * to generate a lowat interrupt in case we subsequently
1438 * really do fill up the ring and the caller goes to sleep.
1439 * No need to place more than one though.
1440 */
1441 if (!(port->ip_flags & LOWAT_WRITTEN) &&
1442 ((cons_ptr - prod_ptr) & PROD_CONS_MASK)
1443 <= port->ip_tx_lowat
1444 * (int)sizeof(struct ring_entry)) {
1445 port->ip_flags |= LOWAT_WRITTEN;
1446 entry->ring_sc[0] |= IOC4_TXCB_INT_WHEN_DONE;
1447 }
1448
1449 /* Go on to next entry */
1450 prod_ptr += sizeof(struct ring_entry);
1451 prod_ptr &= PROD_CONS_MASK;
1452 }
1453
1454 /* If we sent something, start DMA if necessary */
1455 if (total > 0 && !(port->ip_sscr & IOC4_SSCR_DMA_EN)) {
1456 port->ip_sscr |= IOC4_SSCR_DMA_EN;
1457 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1458 }
1459
1460 /* Store the new producer pointer. If tx is disabled, we stuff the
1461 * data into the ring buffer, but we don't actually start tx.
1462 */
1463 if (!uart_tx_stopped(port->ip_port)) {
1464 writel(prod_ptr, &port->ip_serial_regs->stpir);
1465
1466 /* If we are now transmitting, enable tx_mt interrupt so we
1467 * can disable DMA if necessary when the tx finishes.
1468 */
1469 if (total > 0)
1470 enable_intrs(port, hooks->intr_tx_mt);
1471 }
1472 port->ip_tx_prod = prod_ptr;
1473 return total;
1474 }
1475
1476 /**
1477 * disable_intrs - disable interrupts
1478 * @port: port to enable
1479 * @mask: mask to use
1480 */
1481 static void disable_intrs(struct ioc4_port *port, uint32_t mask)
1482 {
1483 struct hooks *hooks = port->ip_hooks;
1484
1485 if (port->ip_ienb & mask) {
1486 write_ireg(port->ip_ioc4_soft, mask, IOC4_W_IEC,
1487 IOC4_SIO_INTR_TYPE);
1488 port->ip_ienb &= ~mask;
1489 }
1490
1491 if (!port->ip_ienb)
1492 write_ireg(port->ip_ioc4_soft, hooks->intr_dma_error,
1493 IOC4_W_IEC, IOC4_OTHER_INTR_TYPE);
1494 }
1495
1496 /**
1497 * set_notification - Modify event notification
1498 * @port: port to use
1499 * @mask: events mask
1500 * @set_on: set ?
1501 */
1502 static int set_notification(struct ioc4_port *port, int mask, int set_on)
1503 {
1504 struct hooks *hooks = port->ip_hooks;
1505 uint32_t intrbits, sscrbits;
1506
1507 BUG_ON(!mask);
1508
1509 intrbits = sscrbits = 0;
1510
1511 if (mask & N_DATA_READY)
1512 intrbits |= (hooks->intr_rx_timer | hooks->intr_rx_high);
1513 if (mask & N_OUTPUT_LOWAT)
1514 intrbits |= hooks->intr_tx_explicit;
1515 if (mask & N_DDCD) {
1516 intrbits |= hooks->intr_delta_dcd;
1517 sscrbits |= IOC4_SSCR_RX_RING_DCD;
1518 }
1519 if (mask & N_DCTS)
1520 intrbits |= hooks->intr_delta_cts;
1521
1522 if (set_on) {
1523 enable_intrs(port, intrbits);
1524 port->ip_notify |= mask;
1525 port->ip_sscr |= sscrbits;
1526 } else {
1527 disable_intrs(port, intrbits);
1528 port->ip_notify &= ~mask;
1529 port->ip_sscr &= ~sscrbits;
1530 }
1531
1532 /* We require DMA if either DATA_READY or DDCD notification is
1533 * currently requested. If neither of these is requested and
1534 * there is currently no tx in progress, DMA may be disabled.
1535 */
1536 if (port->ip_notify & (N_DATA_READY | N_DDCD))
1537 port->ip_sscr |= IOC4_SSCR_DMA_EN;
1538 else if (!(port->ip_ienb & hooks->intr_tx_mt))
1539 port->ip_sscr &= ~IOC4_SSCR_DMA_EN;
1540
1541 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1542 return 0;
1543 }
1544
1545 /**
1546 * set_mcr - set the master control reg
1547 * @the_port: port to use
1548 * @set: set ?
1549 * @mask1: mcr mask
1550 * @mask2: shadow mask
1551 */
1552 static inline int set_mcr(struct uart_port *the_port, int set,
1553 int mask1, int mask2)
1554 {
1555 struct ioc4_port *port = get_ioc4_port(the_port);
1556 uint32_t shadow;
1557 int spiniter = 0;
1558 char mcr;
1559
1560 if (!port)
1561 return -1;
1562
1563 /* Pause the DMA interface if necessary */
1564 if (port->ip_sscr & IOC4_SSCR_DMA_EN) {
1565 writel(port->ip_sscr | IOC4_SSCR_DMA_PAUSE,
1566 &port->ip_serial_regs->sscr);
1567 while ((readl(&port->ip_serial_regs->sscr)
1568 & IOC4_SSCR_PAUSE_STATE) == 0) {
1569 spiniter++;
1570 if (spiniter > MAXITER)
1571 return -1;
1572 }
1573 }
1574 shadow = readl(&port->ip_serial_regs->shadow);
1575 mcr = (shadow & 0xff000000) >> 24;
1576
1577 /* Set new value */
1578 if (set) {
1579 mcr |= mask1;
1580 shadow |= mask2;
1581 } else {
1582 mcr &= ~mask1;
1583 shadow &= ~mask2;
1584 }
1585 writeb(mcr, &port->ip_uart_regs->i4u_mcr);
1586 writel(shadow, &port->ip_serial_regs->shadow);
1587
1588 /* Re-enable the DMA interface if necessary */
1589 if (port->ip_sscr & IOC4_SSCR_DMA_EN) {
1590 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1591 }
1592 return 0;
1593 }
1594
1595 /**
1596 * ioc4_set_proto - set the protocol for the port
1597 * @port: port to use
1598 * @proto: protocol to use
1599 */
1600 static int ioc4_set_proto(struct ioc4_port *port, enum sio_proto proto)
1601 {
1602 struct hooks *hooks = port->ip_hooks;
1603
1604 switch (proto) {
1605 case PROTO_RS232:
1606 /* Clear the appropriate GIO pin */
1607 writel(0, (&port->ip_mem->gppr_0 +
1608 hooks->rs422_select_pin));
1609 break;
1610
1611 case PROTO_RS422:
1612 /* Set the appropriate GIO pin */
1613 writel(1, (&port->ip_mem->gppr_0 +
1614 hooks->rs422_select_pin));
1615 break;
1616
1617 default:
1618 return 1;
1619 }
1620 return 0;
1621 }
1622
1623 /**
1624 * transmit_chars - upper level write, called with ip_lock
1625 * @the_port: port to write
1626 */
1627 static void transmit_chars(struct uart_port *the_port)
1628 {
1629 int xmit_count, tail, head;
1630 int result;
1631 char *start;
1632 struct tty_struct *tty;
1633 struct ioc4_port *port = get_ioc4_port(the_port);
1634 struct uart_info *info;
1635
1636 if (!the_port)
1637 return;
1638 if (!port)
1639 return;
1640
1641 info = the_port->info;
1642 tty = info->tty;
1643
1644 if (uart_circ_empty(&info->xmit) || uart_tx_stopped(the_port)) {
1645 /* Nothing to do or hw stopped */
1646 set_notification(port, N_ALL_OUTPUT, 0);
1647 return;
1648 }
1649
1650 head = info->xmit.head;
1651 tail = info->xmit.tail;
1652 start = (char *)&info->xmit.buf[tail];
1653
1654 /* write out all the data or until the end of the buffer */
1655 xmit_count = (head < tail) ? (UART_XMIT_SIZE - tail) : (head - tail);
1656 if (xmit_count > 0) {
1657 result = do_write(port, start, xmit_count);
1658 if (result > 0) {
1659 /* booking */
1660 xmit_count -= result;
1661 the_port->icount.tx += result;
1662 /* advance the pointers */
1663 tail += result;
1664 tail &= UART_XMIT_SIZE - 1;
1665 info->xmit.tail = tail;
1666 start = (char *)&info->xmit.buf[tail];
1667 }
1668 }
1669 if (uart_circ_chars_pending(&info->xmit) < WAKEUP_CHARS)
1670 uart_write_wakeup(the_port);
1671
1672 if (uart_circ_empty(&info->xmit)) {
1673 set_notification(port, N_OUTPUT_LOWAT, 0);
1674 } else {
1675 set_notification(port, N_OUTPUT_LOWAT, 1);
1676 }
1677 }
1678
1679 /**
1680 * ioc4_change_speed - change the speed of the port
1681 * @the_port: port to change
1682 * @new_termios: new termios settings
1683 * @old_termios: old termios settings
1684 */
1685 static void
1686 ioc4_change_speed(struct uart_port *the_port,
1687 struct termios *new_termios, struct termios *old_termios)
1688 {
1689 struct ioc4_port *port = get_ioc4_port(the_port);
1690 int baud, bits;
1691 unsigned cflag;
1692 int new_parity = 0, new_parity_enable = 0, new_stop = 0, new_data = 8;
1693 struct uart_info *info = the_port->info;
1694
1695 cflag = new_termios->c_cflag;
1696
1697 switch (cflag & CSIZE) {
1698 case CS5:
1699 new_data = 5;
1700 bits = 7;
1701 break;
1702 case CS6:
1703 new_data = 6;
1704 bits = 8;
1705 break;
1706 case CS7:
1707 new_data = 7;
1708 bits = 9;
1709 break;
1710 case CS8:
1711 new_data = 8;
1712 bits = 10;
1713 break;
1714 default:
1715 /* cuz we always need a default ... */
1716 new_data = 5;
1717 bits = 7;
1718 break;
1719 }
1720 if (cflag & CSTOPB) {
1721 bits++;
1722 new_stop = 1;
1723 }
1724 if (cflag & PARENB) {
1725 bits++;
1726 new_parity_enable = 1;
1727 if (cflag & PARODD)
1728 new_parity = 1;
1729 }
1730 baud = uart_get_baud_rate(the_port, new_termios, old_termios,
1731 MIN_BAUD_SUPPORTED, MAX_BAUD_SUPPORTED);
1732 DPRINT_CONFIG(("%s: returned baud %d\n", __FUNCTION__, baud));
1733
1734 /* default is 9600 */
1735 if (!baud)
1736 baud = 9600;
1737
1738 if (!the_port->fifosize)
1739 the_port->fifosize = IOC4_MAX_CHARS;
1740 the_port->timeout = ((the_port->fifosize * HZ * bits) / (baud / 10));
1741 the_port->timeout += HZ / 50; /* Add .02 seconds of slop */
1742
1743 the_port->ignore_status_mask = N_ALL_INPUT;
1744
1745 if (I_IGNPAR(info->tty))
1746 the_port->ignore_status_mask &= ~(N_PARITY_ERROR
1747 | N_FRAMING_ERROR);
1748 if (I_IGNBRK(info->tty)) {
1749 the_port->ignore_status_mask &= ~N_BREAK;
1750 if (I_IGNPAR(info->tty))
1751 the_port->ignore_status_mask &= ~N_OVERRUN_ERROR;
1752 }
1753 if (!(cflag & CREAD)) {
1754 /* ignore everything */
1755 the_port->ignore_status_mask &= ~N_DATA_READY;
1756 }
1757
1758 if (cflag & CRTSCTS) {
1759 info->flags |= ASYNC_CTS_FLOW;
1760 port->ip_sscr |= IOC4_SSCR_HFC_EN;
1761 }
1762 else {
1763 info->flags &= ~ASYNC_CTS_FLOW;
1764 port->ip_sscr &= ~IOC4_SSCR_HFC_EN;
1765 }
1766 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1767
1768 /* Set the configuration and proper notification call */
1769 DPRINT_CONFIG(("%s : port 0x%p cflag 0%o "
1770 "config_port(baud %d data %d stop %d p enable %d parity %d),"
1771 " notification 0x%x\n",
1772 __FUNCTION__, (void *)port, cflag, baud, new_data, new_stop,
1773 new_parity_enable, new_parity, the_port->ignore_status_mask));
1774
1775 if ((config_port(port, baud, /* baud */
1776 new_data, /* byte size */
1777 new_stop, /* stop bits */
1778 new_parity_enable, /* set parity */
1779 new_parity)) >= 0) { /* parity 1==odd */
1780 set_notification(port, the_port->ignore_status_mask, 1);
1781 }
1782 }
1783
1784 /**
1785 * ic4_startup_local - Start up the serial port - returns >= 0 if no errors
1786 * @the_port: Port to operate on
1787 */
1788 static inline int ic4_startup_local(struct uart_port *the_port)
1789 {
1790 int retval = 0;
1791 struct ioc4_port *port;
1792 struct uart_info *info;
1793
1794 if (!the_port)
1795 return -1;
1796
1797 port = get_ioc4_port(the_port);
1798 if (!port)
1799 return -1;
1800
1801 info = the_port->info;
1802 if (info->flags & UIF_INITIALIZED) {
1803 return retval;
1804 }
1805
1806 if (info->tty) {
1807 set_bit(TTY_IO_ERROR, &info->tty->flags);
1808 clear_bit(TTY_IO_ERROR, &info->tty->flags);
1809 if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_HI)
1810 info->tty->alt_speed = 57600;
1811 if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_VHI)
1812 info->tty->alt_speed = 115200;
1813 if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_SHI)
1814 info->tty->alt_speed = 230400;
1815 if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_WARP)
1816 info->tty->alt_speed = 460800;
1817 }
1818 local_open(port);
1819
1820 /* set the speed of the serial port */
1821 ioc4_change_speed(the_port, info->tty->termios, (struct termios *)0);
1822
1823 info->flags |= UIF_INITIALIZED;
1824 return 0;
1825 }
1826
1827 /*
1828 * ioc4_cb_output_lowat - called when the output low water mark is hit
1829 * @port: port to output
1830 */
1831 static void ioc4_cb_output_lowat(struct ioc4_port *port)
1832 {
1833 /* ip_lock is set on the call here */
1834 if (port->ip_port) {
1835 transmit_chars(port->ip_port);
1836 }
1837 }
1838
1839 /**
1840 * handle_intr - service any interrupts for the given port - 2nd level
1841 * called via sd_intr
1842 * @arg: handler arg
1843 * @sio_ir: ioc4regs
1844 */
1845 static void handle_intr(void *arg, uint32_t sio_ir)
1846 {
1847 struct ioc4_port *port = (struct ioc4_port *)arg;
1848 struct hooks *hooks = port->ip_hooks;
1849 unsigned int rx_high_rd_aborted = 0;
1850 unsigned int flags;
1851 struct uart_port *the_port;
1852 int loop_counter;
1853
1854 /* Possible race condition here: The tx_mt interrupt bit may be
1855 * cleared without the intervention of the interrupt handler,
1856 * e.g. by a write. If the top level interrupt handler reads a
1857 * tx_mt, then some other processor does a write, starting up
1858 * output, then we come in here, see the tx_mt and stop DMA, the
1859 * output started by the other processor will hang. Thus we can
1860 * only rely on tx_mt being legitimate if it is read while the
1861 * port lock is held. Therefore this bit must be ignored in the
1862 * passed in interrupt mask which was read by the top level
1863 * interrupt handler since the port lock was not held at the time
1864 * it was read. We can only rely on this bit being accurate if it
1865 * is read while the port lock is held. So we'll clear it for now,
1866 * and reload it later once we have the port lock.
1867 */
1868 sio_ir &= ~(hooks->intr_tx_mt);
1869
1870 spin_lock_irqsave(&port->ip_lock, flags);
1871
1872 loop_counter = MAXITER; /* to avoid hangs */
1873
1874 do {
1875 uint32_t shadow;
1876
1877 if ( loop_counter-- <= 0 ) {
1878 printk(KERN_WARNING "IOC4 serial: "
1879 "possible hang condition/"
1880 "port stuck on interrupt.\n");
1881 break;
1882 }
1883
1884 /* Handle a DCD change */
1885 if (sio_ir & hooks->intr_delta_dcd) {
1886 /* ACK the interrupt */
1887 writel(hooks->intr_delta_dcd,
1888 &port->ip_mem->sio_ir);
1889
1890 shadow = readl(&port->ip_serial_regs->shadow);
1891
1892 if ((port->ip_notify & N_DDCD)
1893 && (shadow & IOC4_SHADOW_DCD)
1894 && (port->ip_port)) {
1895 the_port = port->ip_port;
1896 the_port->icount.dcd = 1;
1897 wake_up_interruptible
1898 (&the_port-> info->delta_msr_wait);
1899 } else if ((port->ip_notify & N_DDCD)
1900 && !(shadow & IOC4_SHADOW_DCD)) {
1901 /* Flag delta DCD/no DCD */
1902 port->ip_flags |= DCD_ON;
1903 }
1904 }
1905
1906 /* Handle a CTS change */
1907 if (sio_ir & hooks->intr_delta_cts) {
1908 /* ACK the interrupt */
1909 writel(hooks->intr_delta_cts,
1910 &port->ip_mem->sio_ir);
1911
1912 shadow = readl(&port->ip_serial_regs->shadow);
1913
1914 if ((port->ip_notify & N_DCTS)
1915 && (port->ip_port)) {
1916 the_port = port->ip_port;
1917 the_port->icount.cts =
1918 (shadow & IOC4_SHADOW_CTS) ? 1 : 0;
1919 wake_up_interruptible
1920 (&the_port->info->delta_msr_wait);
1921 }
1922 }
1923
1924 /* rx timeout interrupt. Must be some data available. Put this
1925 * before the check for rx_high since servicing this condition
1926 * may cause that condition to clear.
1927 */
1928 if (sio_ir & hooks->intr_rx_timer) {
1929 /* ACK the interrupt */
1930 writel(hooks->intr_rx_timer,
1931 &port->ip_mem->sio_ir);
1932
1933 if ((port->ip_notify & N_DATA_READY)
1934 && (port->ip_port)) {
1935 /* ip_lock is set on call here */
1936 receive_chars(port->ip_port);
1937 }
1938 }
1939
1940 /* rx high interrupt. Must be after rx_timer. */
1941 else if (sio_ir & hooks->intr_rx_high) {
1942 /* Data available, notify upper layer */
1943 if ((port->ip_notify & N_DATA_READY)
1944 && port->ip_port) {
1945 /* ip_lock is set on call here */
1946 receive_chars(port->ip_port);
1947 }
1948
1949 /* We can't ACK this interrupt. If receive_chars didn't
1950 * cause the condition to clear, we'll have to disable
1951 * the interrupt until the data is drained.
1952 * If the read was aborted, don't disable the interrupt
1953 * as this may cause us to hang indefinitely. An
1954 * aborted read generally means that this interrupt
1955 * hasn't been delivered to the cpu yet anyway, even
1956 * though we see it as asserted when we read the sio_ir.
1957 */
1958 if ((sio_ir = PENDING(port)) & hooks->intr_rx_high) {
1959 if ((port->ip_flags & READ_ABORTED) == 0) {
1960 port->ip_ienb &= ~hooks->intr_rx_high;
1961 port->ip_flags |= INPUT_HIGH;
1962 } else {
1963 rx_high_rd_aborted++;
1964 }
1965 }
1966 }
1967
1968 /* We got a low water interrupt: notify upper layer to
1969 * send more data. Must come before tx_mt since servicing
1970 * this condition may cause that condition to clear.
1971 */
1972 if (sio_ir & hooks->intr_tx_explicit) {
1973 port->ip_flags &= ~LOWAT_WRITTEN;
1974
1975 /* ACK the interrupt */
1976 writel(hooks->intr_tx_explicit,
1977 &port->ip_mem->sio_ir);
1978
1979 if (port->ip_notify & N_OUTPUT_LOWAT)
1980 ioc4_cb_output_lowat(port);
1981 }
1982
1983 /* Handle tx_mt. Must come after tx_explicit. */
1984 else if (sio_ir & hooks->intr_tx_mt) {
1985 /* If we are expecting a lowat notification
1986 * and we get to this point it probably means that for
1987 * some reason the tx_explicit didn't work as expected
1988 * (that can legitimately happen if the output buffer is
1989 * filled up in just the right way).
1990 * So send the notification now.
1991 */
1992 if (port->ip_notify & N_OUTPUT_LOWAT) {
1993 ioc4_cb_output_lowat(port);
1994
1995 /* We need to reload the sio_ir since the lowat
1996 * call may have caused another write to occur,
1997 * clearing the tx_mt condition.
1998 */
1999 sio_ir = PENDING(port);
2000 }
2001
2002 /* If the tx_mt condition still persists even after the
2003 * lowat call, we've got some work to do.
2004 */
2005 if (sio_ir & hooks->intr_tx_mt) {
2006
2007 /* If we are not currently expecting DMA input,
2008 * and the transmitter has just gone idle,
2009 * there is no longer any reason for DMA, so
2010 * disable it.
2011 */
2012 if (!(port->ip_notify
2013 & (N_DATA_READY | N_DDCD))) {
2014 BUG_ON(!(port->ip_sscr
2015 & IOC4_SSCR_DMA_EN));
2016 port->ip_sscr &= ~IOC4_SSCR_DMA_EN;
2017 writel(port->ip_sscr,
2018 &port->ip_serial_regs->sscr);
2019 }
2020
2021 /* Prevent infinite tx_mt interrupt */
2022 port->ip_ienb &= ~hooks->intr_tx_mt;
2023 }
2024 }
2025 sio_ir = PENDING(port);
2026
2027 /* if the read was aborted and only hooks->intr_rx_high,
2028 * clear hooks->intr_rx_high, so we do not loop forever.
2029 */
2030
2031 if (rx_high_rd_aborted && (sio_ir == hooks->intr_rx_high)) {
2032 sio_ir &= ~hooks->intr_rx_high;
2033 }
2034 } while (sio_ir & hooks->intr_all);
2035
2036 spin_unlock_irqrestore(&port->ip_lock, flags);
2037
2038 /* Re-enable interrupts before returning from interrupt handler.
2039 * Getting interrupted here is okay. It'll just v() our semaphore, and
2040 * we'll come through the loop again.
2041 */
2042
2043 write_ireg(port->ip_ioc4_soft, port->ip_ienb, IOC4_W_IES,
2044 IOC4_SIO_INTR_TYPE);
2045 }
2046
2047 /*
2048 * ioc4_cb_post_ncs - called for some basic errors
2049 * @port: port to use
2050 * @ncs: event
2051 */
2052 static void ioc4_cb_post_ncs(struct uart_port *the_port, int ncs)
2053 {
2054 struct uart_icount *icount;
2055
2056 icount = &the_port->icount;
2057
2058 if (ncs & NCS_BREAK)
2059 icount->brk++;
2060 if (ncs & NCS_FRAMING)
2061 icount->frame++;
2062 if (ncs & NCS_OVERRUN)
2063 icount->overrun++;
2064 if (ncs & NCS_PARITY)
2065 icount->parity++;
2066 }
2067
2068 /**
2069 * do_read - Read in bytes from the port. Return the number of bytes
2070 * actually read.
2071 * @the_port: port to use
2072 * @buf: place to put the stuff we read
2073 * @len: how big 'buf' is
2074 */
2075
2076 static inline int do_read(struct uart_port *the_port, unsigned char *buf,
2077 int len)
2078 {
2079 int prod_ptr, cons_ptr, total;
2080 struct ioc4_port *port = get_ioc4_port(the_port);
2081 struct ring *inring;
2082 struct ring_entry *entry;
2083 struct hooks *hooks = port->ip_hooks;
2084 int byte_num;
2085 char *sc;
2086 int loop_counter;
2087
2088 BUG_ON(!(len >= 0));
2089 BUG_ON(!port);
2090
2091 /* There is a nasty timing issue in the IOC4. When the rx_timer
2092 * expires or the rx_high condition arises, we take an interrupt.
2093 * At some point while servicing the interrupt, we read bytes from
2094 * the ring buffer and re-arm the rx_timer. However the rx_timer is
2095 * not started until the first byte is received *after* it is armed,
2096 * and any bytes pending in the rx construction buffers are not drained
2097 * to memory until either there are 4 bytes available or the rx_timer
2098 * expires. This leads to a potential situation where data is left
2099 * in the construction buffers forever - 1 to 3 bytes were received
2100 * after the interrupt was generated but before the rx_timer was
2101 * re-armed. At that point as long as no subsequent bytes are received
2102 * the timer will never be started and the bytes will remain in the
2103 * construction buffer forever. The solution is to execute a DRAIN
2104 * command after rearming the timer. This way any bytes received before
2105 * the DRAIN will be drained to memory, and any bytes received after
2106 * the DRAIN will start the TIMER and be drained when it expires.
2107 * Luckily, this only needs to be done when the DMA buffer is empty
2108 * since there is no requirement that this function return all
2109 * available data as long as it returns some.
2110 */
2111 /* Re-arm the timer */
2112 writel(port->ip_rx_cons | IOC4_SRCIR_ARM,
2113 &port->ip_serial_regs->srcir);
2114
2115 prod_ptr = readl(&port->ip_serial_regs->srpir) & PROD_CONS_MASK;
2116 cons_ptr = port->ip_rx_cons;
2117
2118 if (prod_ptr == cons_ptr) {
2119 int reset_dma = 0;
2120
2121 /* Input buffer appears empty, do a flush. */
2122
2123 /* DMA must be enabled for this to work. */
2124 if (!(port->ip_sscr & IOC4_SSCR_DMA_EN)) {
2125 port->ip_sscr |= IOC4_SSCR_DMA_EN;
2126 reset_dma = 1;
2127 }
2128
2129 /* Potential race condition: we must reload the srpir after
2130 * issuing the drain command, otherwise we could think the rx
2131 * buffer is empty, then take a very long interrupt, and when
2132 * we come back it's full and we wait forever for the drain to
2133 * complete.
2134 */
2135 writel(port->ip_sscr | IOC4_SSCR_RX_DRAIN,
2136 &port->ip_serial_regs->sscr);
2137 prod_ptr = readl(&port->ip_serial_regs->srpir)
2138 & PROD_CONS_MASK;
2139
2140 /* We must not wait for the DRAIN to complete unless there are
2141 * at least 8 bytes (2 ring entries) available to receive the
2142 * data otherwise the DRAIN will never complete and we'll
2143 * deadlock here.
2144 * In fact, to make things easier, I'll just ignore the flush if
2145 * there is any data at all now available.
2146 */
2147 if (prod_ptr == cons_ptr) {
2148 loop_counter = 0;
2149 while (readl(&port->ip_serial_regs->sscr) &
2150 IOC4_SSCR_RX_DRAIN) {
2151 loop_counter++;
2152 if (loop_counter > MAXITER)
2153 return -1;
2154 }
2155
2156 /* SIGH. We have to reload the prod_ptr *again* since
2157 * the drain may have caused it to change
2158 */
2159 prod_ptr = readl(&port->ip_serial_regs->srpir)
2160 & PROD_CONS_MASK;
2161 }
2162 if (reset_dma) {
2163 port->ip_sscr &= ~IOC4_SSCR_DMA_EN;
2164 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
2165 }
2166 }
2167 inring = port->ip_inring;
2168 port->ip_flags &= ~READ_ABORTED;
2169
2170 total = 0;
2171 loop_counter = 0xfffff; /* to avoid hangs */
2172
2173 /* Grab bytes from the hardware */
2174 while ((prod_ptr != cons_ptr) && (len > 0)) {
2175 entry = (struct ring_entry *)((caddr_t)inring + cons_ptr);
2176
2177 if ( loop_counter-- <= 0 ) {
2178 printk(KERN_WARNING "IOC4 serial: "
2179 "possible hang condition/"
2180 "port stuck on read.\n");
2181 break;
2182 }
2183
2184 /* According to the producer pointer, this ring entry
2185 * must contain some data. But if the PIO happened faster
2186 * than the DMA, the data may not be available yet, so let's
2187 * wait until it arrives.
2188 */
2189 if ((entry->ring_allsc & RING_ANY_VALID) == 0) {
2190 /* Indicate the read is aborted so we don't disable
2191 * the interrupt thinking that the consumer is
2192 * congested.
2193 */
2194 port->ip_flags |= READ_ABORTED;
2195 len = 0;
2196 break;
2197 }
2198
2199 /* Load the bytes/status out of the ring entry */
2200 for (byte_num = 0; byte_num < 4 && len > 0; byte_num++) {
2201 sc = &(entry->ring_sc[byte_num]);
2202
2203 /* Check for change in modem state or overrun */
2204 if ((*sc & IOC4_RXSB_MODEM_VALID)
2205 && (port->ip_notify & N_DDCD)) {
2206 /* Notify upper layer if DCD dropped */
2207
2208 if ((port->ip_flags & DCD_ON)
2209 && !(*sc & IOC4_RXSB_DCD)) {
2210
2211 /* If we have already copied some data,
2212 * return it. We'll pick up the carrier
2213 * drop on the next pass. That way we
2214 * don't throw away the data that has
2215 * already been copied back to
2216 * the caller's buffer.
2217 */
2218 if (total > 0) {
2219 len = 0;
2220 break;
2221 }
2222 port->ip_flags &= ~DCD_ON;
2223
2224 /* Turn off this notification so the
2225 * carrier drop protocol won't see it
2226 * again when it does a read.
2227 */
2228 *sc &= ~IOC4_RXSB_MODEM_VALID;
2229
2230 /* To keep things consistent, we need
2231 * to update the consumer pointer so
2232 * the next reader won't come in and
2233 * try to read the same ring entries
2234 * again. This must be done here before
2235 * the dcd change.
2236 */
2237
2238 if ((entry->ring_allsc & RING_ANY_VALID)
2239 == 0) {
2240 cons_ptr += (int)sizeof
2241 (struct ring_entry);
2242 cons_ptr &= PROD_CONS_MASK;
2243 }
2244 writel(cons_ptr,
2245 &port->ip_serial_regs->srcir);
2246 port->ip_rx_cons = cons_ptr;
2247
2248 /* Notify upper layer of carrier drop */
2249 if ((port->ip_notify & N_DDCD)
2250 && port->ip_port) {
2251 the_port->icount.dcd = 0;
2252 wake_up_interruptible
2253 (&the_port->info->
2254 delta_msr_wait);
2255 }
2256
2257 /* If we had any data to return, we
2258 * would have returned it above.
2259 */
2260 return 0;
2261 }
2262 }
2263 if (*sc & IOC4_RXSB_MODEM_VALID) {
2264 /* Notify that an input overrun occurred */
2265 if ((*sc & IOC4_RXSB_OVERRUN)
2266 && (port->ip_notify & N_OVERRUN_ERROR)) {
2267 ioc4_cb_post_ncs(the_port, NCS_OVERRUN);
2268 }
2269 /* Don't look at this byte again */
2270 *sc &= ~IOC4_RXSB_MODEM_VALID;
2271 }
2272
2273 /* Check for valid data or RX errors */
2274 if ((*sc & IOC4_RXSB_DATA_VALID) &&
2275 ((*sc & (IOC4_RXSB_PAR_ERR
2276 | IOC4_RXSB_FRAME_ERR
2277 | IOC4_RXSB_BREAK))
2278 && (port->ip_notify & (N_PARITY_ERROR
2279 | N_FRAMING_ERROR
2280 | N_BREAK)))) {
2281 /* There is an error condition on the next byte.
2282 * If we have already transferred some bytes,
2283 * we'll stop here. Otherwise if this is the
2284 * first byte to be read, we'll just transfer
2285 * it alone after notifying the
2286 * upper layer of its status.
2287 */
2288 if (total > 0) {
2289 len = 0;
2290 break;
2291 } else {
2292 if ((*sc & IOC4_RXSB_PAR_ERR) &&
2293 (port->ip_notify & N_PARITY_ERROR)) {
2294 ioc4_cb_post_ncs(the_port,
2295 NCS_PARITY);
2296 }
2297 if ((*sc & IOC4_RXSB_FRAME_ERR) &&
2298 (port->ip_notify & N_FRAMING_ERROR)){
2299 ioc4_cb_post_ncs(the_port,
2300 NCS_FRAMING);
2301 }
2302 if ((*sc & IOC4_RXSB_BREAK)
2303 && (port->ip_notify & N_BREAK)) {
2304 ioc4_cb_post_ncs
2305 (the_port,
2306 NCS_BREAK);
2307 }
2308 len = 1;
2309 }
2310 }
2311 if (*sc & IOC4_RXSB_DATA_VALID) {
2312 *sc &= ~IOC4_RXSB_DATA_VALID;
2313 *buf = entry->ring_data[byte_num];
2314 buf++;
2315 len--;
2316 total++;
2317 }
2318 }
2319
2320 /* If we used up this entry entirely, go on to the next one,
2321 * otherwise we must have run out of buffer space, so
2322 * leave the consumer pointer here for the next read in case
2323 * there are still unread bytes in this entry.
2324 */
2325 if ((entry->ring_allsc & RING_ANY_VALID) == 0) {
2326 cons_ptr += (int)sizeof(struct ring_entry);
2327 cons_ptr &= PROD_CONS_MASK;
2328 }
2329 }
2330
2331 /* Update consumer pointer and re-arm rx timer interrupt */
2332 writel(cons_ptr, &port->ip_serial_regs->srcir);
2333 port->ip_rx_cons = cons_ptr;
2334
2335 /* If we have now dipped below the rx high water mark and we have
2336 * rx_high interrupt turned off, we can now turn it back on again.
2337 */
2338 if ((port->ip_flags & INPUT_HIGH) && (((prod_ptr - cons_ptr)
2339 & PROD_CONS_MASK) < ((port->ip_sscr &
2340 IOC4_SSCR_RX_THRESHOLD)
2341 << IOC4_PROD_CONS_PTR_OFF))) {
2342 port->ip_flags &= ~INPUT_HIGH;
2343 enable_intrs(port, hooks->intr_rx_high);
2344 }
2345 return total;
2346 }
2347 /**
2348 * receive_chars - upper level read. Called with ip_lock.
2349 * @the_port: port to read from
2350 */
2351 static void receive_chars(struct uart_port *the_port)
2352 {
2353 struct tty_struct *tty;
2354 unsigned char ch[IOC4_MAX_CHARS];
2355 int read_count, request_count;
2356 struct uart_icount *icount;
2357 struct uart_info *info = the_port->info;
2358
2359 /* Make sure all the pointers are "good" ones */
2360 if (!info)
2361 return;
2362 if (!info->tty)
2363 return;
2364
2365 tty = info->tty;
2366
2367 request_count = TTY_FLIPBUF_SIZE - tty->flip.count - 1;
2368
2369 if (request_count > 0) {
2370 if (request_count > IOC4_MAX_CHARS - 2)
2371 request_count = IOC4_MAX_CHARS - 2;
2372 icount = &the_port->icount;
2373 read_count = do_read(the_port, ch, request_count);
2374 if (read_count > 0) {
2375 memcpy(tty->flip.char_buf_ptr, ch, read_count);
2376 memset(tty->flip.flag_buf_ptr, TTY_NORMAL, read_count);
2377 tty->flip.char_buf_ptr += read_count;
2378 tty->flip.flag_buf_ptr += read_count;
2379 tty->flip.count += read_count;
2380 icount->rx += read_count;
2381 }
2382 }
2383 tty_flip_buffer_push(tty);
2384 }
2385
2386 /**
2387 * ic4_type - What type of console are we?
2388 * @port: Port to operate with (we ignore since we only have one port)
2389 *
2390 */
2391 static const char *ic4_type(struct uart_port *the_port)
2392 {
2393 return "SGI IOC4 Serial";
2394 }
2395
2396 /**
2397 * ic4_tx_empty - Is the transmitter empty? We pretend we're always empty
2398 * @port: Port to operate on (we ignore since we always return 1)
2399 *
2400 */
2401 static unsigned int ic4_tx_empty(struct uart_port *the_port)
2402 {
2403 return 1;
2404 }
2405
2406 /**
2407 * ic4_stop_tx - stop the transmitter
2408 * @port: Port to operate on
2409 * @tty_stop: Set to 1 if called via uart_stop
2410 *
2411 */
2412 static void ic4_stop_tx(struct uart_port *the_port, unsigned int tty_stop)
2413 {
2414 }
2415
2416 /**
2417 * null_void_function -
2418 * @port: Port to operate on
2419 *
2420 */
2421 static void null_void_function(struct uart_port *the_port)
2422 {
2423 }
2424
2425 /**
2426 * ic4_shutdown - shut down the port - free irq and disable
2427 * @port: Port to shut down
2428 *
2429 */
2430 static void ic4_shutdown(struct uart_port *the_port)
2431 {
2432 unsigned long port_flags;
2433 struct ioc4_port *port;
2434 struct uart_info *info;
2435
2436 port = get_ioc4_port(the_port);
2437 if (!port)
2438 return;
2439
2440 info = the_port->info;
2441
2442 if (!(info->flags & UIF_INITIALIZED))
2443 return;
2444
2445 wake_up_interruptible(&info->delta_msr_wait);
2446
2447 if (info->tty)
2448 set_bit(TTY_IO_ERROR, &info->tty->flags);
2449
2450 spin_lock_irqsave(&port->ip_lock, port_flags);
2451 set_notification(port, N_ALL, 0);
2452 info->flags &= ~UIF_INITIALIZED;
2453 spin_unlock_irqrestore(&port->ip_lock, port_flags);
2454 }
2455
2456 /**
2457 * ic4_set_mctrl - set control lines (dtr, rts, etc)
2458 * @port: Port to operate on
2459 * @mctrl: Lines to set/unset
2460 *
2461 */
2462 static void ic4_set_mctrl(struct uart_port *the_port, unsigned int mctrl)
2463 {
2464 unsigned char mcr = 0;
2465
2466 if (mctrl & TIOCM_RTS)
2467 mcr |= UART_MCR_RTS;
2468 if (mctrl & TIOCM_DTR)
2469 mcr |= UART_MCR_DTR;
2470 if (mctrl & TIOCM_OUT1)
2471 mcr |= UART_MCR_OUT1;
2472 if (mctrl & TIOCM_OUT2)
2473 mcr |= UART_MCR_OUT2;
2474 if (mctrl & TIOCM_LOOP)
2475 mcr |= UART_MCR_LOOP;
2476
2477 set_mcr(the_port, 1, mcr, IOC4_SHADOW_DTR);
2478 }
2479
2480 /**
2481 * ic4_get_mctrl - get control line info
2482 * @port: port to operate on
2483 *
2484 */
2485 static unsigned int ic4_get_mctrl(struct uart_port *the_port)
2486 {
2487 struct ioc4_port *port = get_ioc4_port(the_port);
2488 uint32_t shadow;
2489 unsigned int ret = 0;
2490
2491 if (!port)
2492 return 0;
2493
2494 shadow = readl(&port->ip_serial_regs->shadow);
2495 if (shadow & IOC4_SHADOW_DCD)
2496 ret |= TIOCM_CAR;
2497 if (shadow & IOC4_SHADOW_DR)
2498 ret |= TIOCM_DSR;
2499 if (shadow & IOC4_SHADOW_CTS)
2500 ret |= TIOCM_CTS;
2501 return ret;
2502 }
2503
2504 /**
2505 * ic4_start_tx - Start transmitter, flush any output
2506 * @port: Port to operate on
2507 * @tty_stop: Set to 1 if called via uart_start
2508 *
2509 */
2510 static void ic4_start_tx(struct uart_port *the_port, unsigned int tty_stop)
2511 {
2512 struct ioc4_port *port = get_ioc4_port(the_port);
2513 unsigned long flags;
2514
2515 if (port) {
2516 spin_lock_irqsave(&port->ip_lock, flags);
2517 transmit_chars(the_port);
2518 spin_unlock_irqrestore(&port->ip_lock, flags);
2519 }
2520 }
2521
2522 /**
2523 * ic4_break_ctl - handle breaks
2524 * @port: Port to operate on
2525 * @break_state: Break state
2526 *
2527 */
2528 static void ic4_break_ctl(struct uart_port *the_port, int break_state)
2529 {
2530 }
2531
2532 /**
2533 * ic4_startup - Start up the serial port - always return 0 (We're always on)
2534 * @port: Port to operate on
2535 *
2536 */
2537 static int ic4_startup(struct uart_port *the_port)
2538 {
2539 int retval;
2540 struct ioc4_port *port;
2541 struct ioc4_control *control;
2542 struct uart_info *info;
2543 unsigned long port_flags;
2544
2545 if (!the_port) {
2546 return -ENODEV;
2547 }
2548 port = get_ioc4_port(the_port);
2549 if (!port) {
2550 return -ENODEV;
2551 }
2552 info = the_port->info;
2553
2554 control = port->ip_control;
2555 if (!control) {
2556 return -ENODEV;
2557 }
2558
2559 /* Start up the serial port */
2560 spin_lock_irqsave(&port->ip_lock, port_flags);
2561 retval = ic4_startup_local(the_port);
2562 spin_unlock_irqrestore(&port->ip_lock, port_flags);
2563 return retval;
2564 }
2565
2566 /**
2567 * ic4_set_termios - set termios stuff
2568 * @port: port to operate on
2569 * @termios: New settings
2570 * @termios: Old
2571 *
2572 */
2573 static void
2574 ic4_set_termios(struct uart_port *the_port,
2575 struct termios *termios, struct termios *old_termios)
2576 {
2577 struct ioc4_port *port = get_ioc4_port(the_port);
2578 unsigned long port_flags;
2579
2580 spin_lock_irqsave(&port->ip_lock, port_flags);
2581 ioc4_change_speed(the_port, termios, old_termios);
2582 spin_unlock_irqrestore(&port->ip_lock, port_flags);
2583 }
2584
2585 /**
2586 * ic4_request_port - allocate resources for port - no op....
2587 * @port: port to operate on
2588 *
2589 */
2590 static int ic4_request_port(struct uart_port *port)
2591 {
2592 return 0;
2593 }
2594
2595 /* Associate the uart functions above - given to serial core */
2596
2597 static struct uart_ops ioc4_ops = {
2598 .tx_empty = ic4_tx_empty,
2599 .set_mctrl = ic4_set_mctrl,
2600 .get_mctrl = ic4_get_mctrl,
2601 .stop_tx = ic4_stop_tx,
2602 .start_tx = ic4_start_tx,
2603 .stop_rx = null_void_function,
2604 .enable_ms = null_void_function,
2605 .break_ctl = ic4_break_ctl,
2606 .startup = ic4_startup,
2607 .shutdown = ic4_shutdown,
2608 .set_termios = ic4_set_termios,
2609 .type = ic4_type,
2610 .release_port = null_void_function,
2611 .request_port = ic4_request_port,
2612 };
2613
2614 /*
2615 * Boot-time initialization code
2616 */
2617
2618 static struct uart_driver ioc4_uart = {
2619 .owner = THIS_MODULE,
2620 .driver_name = "ioc4_serial",
2621 .dev_name = DEVICE_NAME,
2622 .major = DEVICE_MAJOR,
2623 .minor = DEVICE_MINOR,
2624 .nr = IOC4_NUM_CARDS * IOC4_NUM_SERIAL_PORTS,
2625 };
2626
2627 /**
2628 * ioc4_serial_core_attach - register with serial core
2629 * This is done during pci probing
2630 * @pdev: handle for this card
2631 */
2632 static inline int
2633 ioc4_serial_core_attach(struct pci_dev *pdev)
2634 {
2635 struct ioc4_port *port;
2636 struct uart_port *the_port;
2637 struct ioc4_control *control = pci_get_drvdata(pdev);
2638 int ii;
2639
2640 DPRINT_CONFIG(("%s: attach pdev 0x%p - control 0x%p\n",
2641 __FUNCTION__, pdev, (void *)control));
2642
2643 if (!control)
2644 return -ENODEV;
2645
2646 /* once around for each port on this card */
2647 for (ii = 0; ii < IOC4_NUM_SERIAL_PORTS; ii++) {
2648 the_port = &control->ic_port[ii].icp_uart_port;
2649 port = control->ic_port[ii].icp_port;
2650 port->ip_port = the_port;
2651
2652 DPRINT_CONFIG(("%s: attach the_port 0x%p / port 0x%p\n",
2653 __FUNCTION__, (void *)the_port,
2654 (void *)port));
2655
2656 spin_lock_init(&the_port->lock);
2657 /* membase, iobase and mapbase just need to be non-0 */
2658 the_port->membase = (unsigned char __iomem *)1;
2659 the_port->line = the_port->iobase = ii;
2660 the_port->mapbase = 1;
2661 the_port->type = PORT_16550A;
2662 the_port->fifosize = IOC4_MAX_CHARS;
2663 the_port->ops = &ioc4_ops;
2664 the_port->irq = control->ic_irq;
2665 the_port->dev = &pdev->dev;
2666 if (uart_add_one_port(&ioc4_uart, the_port) < 0) {
2667 printk(KERN_WARNING
2668 "%s: unable to add port %d\n",
2669 __FUNCTION__, the_port->line);
2670 } else {
2671 DPRINT_CONFIG(
2672 ("IOC4 serial driver port %d irq = %d\n",
2673 the_port->line, the_port->irq));
2674 }
2675 /* all ports are rs232 for now */
2676 ioc4_set_proto(port, PROTO_RS232);
2677 }
2678 return 0;
2679 }
2680
2681 /**
2682 * ioc4_serial_attach_one - register attach function
2683 * called per card found from ioc4_serial_detect as part
2684 * of module_init().
2685 * @pdev: handle for this card
2686 * @pci_id: pci id for this card
2687 */
2688 int
2689 ioc4_serial_attach_one(struct pci_dev *pdev, const struct pci_device_id *pci_id)
2690 {
2691 struct ioc4_mem __iomem *mem;
2692 unsigned long tmp_addr, tmp_addr1;
2693 struct ioc4_serial __iomem *serial;
2694 struct ioc4_soft *soft;
2695 struct ioc4_control *control;
2696 int tmp, ret = 0;
2697
2698
2699 DPRINT_CONFIG(("%s (0x%p, 0x%p)\n", __FUNCTION__, pdev, pci_id));
2700
2701 /* Map in the ioc4 memory */
2702 tmp_addr = pci_resource_start(pdev, 0);
2703 if (!tmp_addr) {
2704 printk(KERN_WARNING
2705 "ioc4 (%p) : unable to get PIO mapping for "
2706 "MEM space\n", (void *)pdev);
2707 return -ENODEV;
2708 }
2709 if (!request_region(tmp_addr, sizeof(struct ioc4_mem), "sioc4_mem")) {
2710 printk(KERN_ALERT
2711 "ioc4 (%p): unable to get request region for "
2712 "MEM space\n", (void *)pdev);
2713 return -ENODEV;
2714 }
2715 mem = ioremap(tmp_addr, sizeof(struct ioc4_mem));
2716 if (!mem) {
2717 printk(KERN_WARNING
2718 "ioc4 (%p) : unable to remap ioc4 memory\n",
2719 (void *)pdev);
2720 ret = -ENODEV;
2721 goto out1;
2722 }
2723
2724 /* request serial registers */
2725 tmp_addr1 = pci_resource_start(pdev, 0) + IOC4_SERIAL_OFFSET;
2726
2727 if (!request_region(tmp_addr1, sizeof(struct ioc4_serial),
2728 "sioc4_uart")) {
2729 printk(KERN_WARNING
2730 "ioc4 (%p): unable to get request region for "
2731 "uart space\n", (void *)pdev);
2732 ret = -ENODEV;
2733 goto out1;
2734 }
2735 serial = ioremap(tmp_addr1, sizeof(struct ioc4_serial));
2736 if (!serial) {
2737 printk(KERN_WARNING
2738 "ioc4 (%p) : unable to remap ioc4 serial register\n",
2739 (void *)pdev);
2740 ret = -ENODEV;
2741 goto out2;
2742 }
2743 DPRINT_CONFIG(("%s : mem 0x%p, serial 0x%p\n",
2744 __FUNCTION__, (void *)mem, (void *)serial));
2745
2746 /* Get memory for the new card */
2747 control = kmalloc(sizeof(struct ioc4_control) * IOC4_NUM_SERIAL_PORTS,
2748 GFP_KERNEL);
2749
2750 if (!control) {
2751 printk(KERN_WARNING "ioc4_attach_one"
2752 ": unable to get memory for the IOC4\n");
2753 ret = -ENOMEM;
2754 goto out2;
2755 }
2756 memset(control, 0, sizeof(struct ioc4_control));
2757 pci_set_drvdata(pdev, control);
2758
2759 /* Allocate the soft structure */
2760 soft = kmalloc(sizeof(struct ioc4_soft), GFP_KERNEL);
2761 if (!soft) {
2762 printk(KERN_WARNING
2763 "ioc4 (%p): unable to get memory for the soft struct\n",
2764 (void *)pdev);
2765 ret = -ENOMEM;
2766 goto out3;
2767 }
2768 memset(soft, 0, sizeof(struct ioc4_soft));
2769
2770 spin_lock_init(&soft->is_ir_lock);
2771 soft->is_ioc4_mem_addr = mem;
2772 soft->is_ioc4_serial_addr = serial;
2773
2774 /* Init the IOC4 */
2775 pci_read_config_dword(pdev, PCI_COMMAND, &tmp);
2776 pci_write_config_dword(pdev, PCI_COMMAND,
2777 tmp | PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
2778
2779 writel(0xf << IOC4_SIO_CR_CMD_PULSE_SHIFT, &mem->sio_cr);
2780
2781 /* Enable serial port mode select generic PIO pins as outputs */
2782 writel(IOC4_GPCR_UART0_MODESEL | IOC4_GPCR_UART1_MODESEL
2783 | IOC4_GPCR_UART2_MODESEL | IOC4_GPCR_UART3_MODESEL,
2784 &mem->gpcr_s);
2785
2786 /* Clear and disable all interrupts */
2787 write_ireg(soft, ~0, IOC4_W_IEC, IOC4_SIO_INTR_TYPE);
2788 writel(~0, &mem->sio_ir);
2789 write_ireg(soft, ~(IOC4_OTHER_IR_ATA_INT | IOC4_OTHER_IR_ATA_MEMERR),
2790 IOC4_W_IEC, IOC4_OTHER_INTR_TYPE);
2791 writel(~(IOC4_OTHER_IR_ATA_MEMERR | IOC4_OTHER_IR_ATA_MEMERR),
2792 &mem->other_ir);
2793 control->ic_soft = soft;
2794 if (!request_irq(pdev->irq, ioc4_intr, SA_SHIRQ,
2795 "sgi-ioc4serial", (void *)soft)) {
2796 control->ic_irq = pdev->irq;
2797 } else {
2798 printk(KERN_WARNING
2799 "%s : request_irq fails for IRQ 0x%x\n ",
2800 __FUNCTION__, pdev->irq);
2801 }
2802 if ((ret = ioc4_attach_local(pdev, control, soft,
2803 soft->is_ioc4_mem_addr,
2804 soft->is_ioc4_serial_addr)))
2805 goto out4;
2806
2807 /* register port with the serial core */
2808
2809 if ((ret = ioc4_serial_core_attach(pdev)))
2810 goto out4;
2811
2812 return ret;
2813
2814 /* error exits that give back resources */
2815 out4:
2816 kfree(soft);
2817 out3:
2818 kfree(control);
2819 out2:
2820 release_region(tmp_addr1, sizeof(struct ioc4_serial));
2821 out1:
2822 release_region(tmp_addr, sizeof(struct ioc4_mem));
2823
2824 return ret;
2825 }
2826
2827
2828 /**
2829 * ioc4_serial_remove_one - detach function
2830 *
2831 * @pdev: handle for this card
2832 */
2833
2834 #if 0
2835 void ioc4_serial_remove_one(struct pci_dev *pdev)
2836 {
2837 int ii;
2838 struct ioc4_control *control;
2839 struct uart_port *the_port;
2840 struct ioc4_port *port;
2841 struct ioc4_soft *soft;
2842
2843 control = pci_get_drvdata(pdev);
2844
2845 for (ii = 0; ii < IOC4_NUM_SERIAL_PORTS; ii++) {
2846 the_port = &control->ic_port[ii].icp_uart_port;
2847 if (the_port) {
2848 uart_remove_one_port(&ioc4_uart, the_port);
2849 }
2850 port = control->ic_port[ii].icp_port;
2851 if (!(ii & 1) && port) {
2852 pci_free_consistent(port->ip_pdev,
2853 TOTAL_RING_BUF_SIZE,
2854 (void *)port->ip_cpu_ringbuf,
2855 port->ip_dma_ringbuf);
2856 kfree(port);
2857 }
2858 }
2859 soft = control->ic_soft;
2860 if (soft) {
2861 free_irq(control->ic_irq, (void *)soft);
2862 if (soft->is_ioc4_serial_addr) {
2863 release_region((unsigned long)
2864 soft->is_ioc4_serial_addr,
2865 sizeof(struct ioc4_serial));
2866 }
2867 kfree(soft);
2868 }
2869 kfree(control);
2870 pci_set_drvdata(pdev, NULL);
2871 uart_unregister_driver(&ioc4_uart);
2872 }
2873 #endif
2874
2875 /**
2876 * ioc4_serial_init - module init
2877 */
2878 int ioc4_serial_init(void)
2879 {
2880 int ret;
2881
2882 /* register with serial core */
2883 if ((ret = uart_register_driver(&ioc4_uart)) < 0) {
2884 printk(KERN_WARNING
2885 "%s: Couldn't register IOC4 serial driver\n",
2886 __FUNCTION__);
2887 return ret;
2888 }
2889 return 0;
2890 }
2891
2892 MODULE_AUTHOR("Pat Gefre - Silicon Graphics Inc. (SGI) <pfg@sgi.com>");
2893 MODULE_DESCRIPTION("Serial PCI driver module for SGI IOC4 Base-IO Card");
2894 MODULE_LICENSE("GPL");
2895
2896 EXPORT_SYMBOL(ioc4_serial_init);
2897 EXPORT_SYMBOL(ioc4_serial_attach_one);
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