2 * drivers/video/aty/radeon_pm.c
4 * Copyright 2003,2004 Ben. Herrenschmidt <benh@kernel.crashing.org>
5 * Copyright 2004 Paul Mackerras <paulus@samba.org>
7 * This is the power management code for ATI radeon chipsets. It contains
8 * some dynamic clock PM enable/disable code similar to what X.org does,
9 * some D2-state (APM-style) sleep/wakeup code for use on some PowerMacs,
10 * and the necessary bits to re-initialize from scratch a few chips found
11 * on PowerMacs as well. The later could be extended to more platforms
12 * provided the memory controller configuration code be made more generic,
13 * and you can get the proper mode register commands for your RAMs.
14 * Those things may be found in the BIOS image...
19 #include <linux/console.h>
20 #include <linux/agp_backend.h>
22 #ifdef CONFIG_PPC_PMAC
23 #include <asm/processor.h>
25 #include <asm/pmac_feature.h>
30 static void radeon_pm_disable_dynamic_mode(struct radeonfb_info
*rinfo
)
35 if ((rinfo
->family
== CHIP_FAMILY_RV100
) && (!rinfo
->is_mobility
)) {
36 if (rinfo
->has_CRTC2
) {
37 tmp
= INPLL(pllSCLK_CNTL
);
38 tmp
&= ~SCLK_CNTL__DYN_STOP_LAT_MASK
;
39 tmp
|= SCLK_CNTL__CP_MAX_DYN_STOP_LAT
| SCLK_CNTL__FORCEON_MASK
;
40 OUTPLL(pllSCLK_CNTL
, tmp
);
42 tmp
= INPLL(pllMCLK_CNTL
);
43 tmp
|= (MCLK_CNTL__FORCE_MCLKA
|
44 MCLK_CNTL__FORCE_MCLKB
|
45 MCLK_CNTL__FORCE_YCLKA
|
46 MCLK_CNTL__FORCE_YCLKB
|
47 MCLK_CNTL__FORCE_AIC
|
49 OUTPLL(pllMCLK_CNTL
, tmp
);
53 if (!rinfo
->has_CRTC2
) {
54 tmp
= INPLL(pllSCLK_CNTL
);
55 tmp
|= (SCLK_CNTL__FORCE_CP
| SCLK_CNTL__FORCE_HDP
|
56 SCLK_CNTL__FORCE_DISP1
| SCLK_CNTL__FORCE_TOP
|
57 SCLK_CNTL__FORCE_E2
| SCLK_CNTL__FORCE_SE
|
58 SCLK_CNTL__FORCE_IDCT
| SCLK_CNTL__FORCE_VIP
|
59 SCLK_CNTL__FORCE_RE
| SCLK_CNTL__FORCE_PB
|
60 SCLK_CNTL__FORCE_TAM
| SCLK_CNTL__FORCE_TDM
|
62 OUTPLL(pllSCLK_CNTL
, tmp
);
66 if (rinfo
->family
== CHIP_FAMILY_RV350
) {
67 /* for RV350/M10, no delays are required. */
68 tmp
= INPLL(pllSCLK_CNTL2
);
69 tmp
|= (SCLK_CNTL2__R300_FORCE_TCL
|
70 SCLK_CNTL2__R300_FORCE_GA
|
71 SCLK_CNTL2__R300_FORCE_CBA
);
72 OUTPLL(pllSCLK_CNTL2
, tmp
);
74 tmp
= INPLL(pllSCLK_CNTL
);
75 tmp
|= (SCLK_CNTL__FORCE_DISP2
| SCLK_CNTL__FORCE_CP
|
76 SCLK_CNTL__FORCE_HDP
| SCLK_CNTL__FORCE_DISP1
|
77 SCLK_CNTL__FORCE_TOP
| SCLK_CNTL__FORCE_E2
|
78 SCLK_CNTL__R300_FORCE_VAP
| SCLK_CNTL__FORCE_IDCT
|
79 SCLK_CNTL__FORCE_VIP
| SCLK_CNTL__R300_FORCE_SR
|
80 SCLK_CNTL__R300_FORCE_PX
| SCLK_CNTL__R300_FORCE_TX
|
81 SCLK_CNTL__R300_FORCE_US
| SCLK_CNTL__FORCE_TV_SCLK
|
82 SCLK_CNTL__R300_FORCE_SU
| SCLK_CNTL__FORCE_OV0
);
83 OUTPLL(pllSCLK_CNTL
, tmp
);
85 tmp
= INPLL(pllSCLK_MORE_CNTL
);
86 tmp
|= (SCLK_MORE_CNTL__FORCE_DISPREGS
| SCLK_MORE_CNTL__FORCE_MC_GUI
|
87 SCLK_MORE_CNTL__FORCE_MC_HOST
);
88 OUTPLL(pllSCLK_MORE_CNTL
, tmp
);
90 tmp
= INPLL(pllMCLK_CNTL
);
91 tmp
|= (MCLK_CNTL__FORCE_MCLKA
|
92 MCLK_CNTL__FORCE_MCLKB
|
93 MCLK_CNTL__FORCE_YCLKA
|
94 MCLK_CNTL__FORCE_YCLKB
|
96 OUTPLL(pllMCLK_CNTL
, tmp
);
98 tmp
= INPLL(pllVCLK_ECP_CNTL
);
99 tmp
&= ~(VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb
|
100 VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb
|
101 VCLK_ECP_CNTL__R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF
);
102 OUTPLL(pllVCLK_ECP_CNTL
, tmp
);
104 tmp
= INPLL(pllPIXCLKS_CNTL
);
105 tmp
&= ~(PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb
|
106 PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb
|
107 PIXCLKS_CNTL__DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb
|
108 PIXCLKS_CNTL__R300_DVOCLK_ALWAYS_ONb
|
109 PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb
|
110 PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb
|
111 PIXCLKS_CNTL__R300_PIXCLK_DVO_ALWAYS_ONb
|
112 PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb
|
113 PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb
|
114 PIXCLKS_CNTL__R300_PIXCLK_TRANS_ALWAYS_ONb
|
115 PIXCLKS_CNTL__R300_PIXCLK_TVO_ALWAYS_ONb
|
116 PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb
|
117 PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb
|
118 PIXCLKS_CNTL__R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF
);
119 OUTPLL(pllPIXCLKS_CNTL
, tmp
);
126 /* Force Core Clocks */
127 tmp
= INPLL(pllSCLK_CNTL
);
128 tmp
|= (SCLK_CNTL__FORCE_CP
| SCLK_CNTL__FORCE_E2
);
130 /* XFree doesn't do that case, but we had this code from Apple and it
131 * seem necessary for proper suspend/resume operations
133 if (rinfo
->is_mobility
) {
134 tmp
|= SCLK_CNTL__FORCE_HDP
|
135 SCLK_CNTL__FORCE_DISP1
|
136 SCLK_CNTL__FORCE_DISP2
|
137 SCLK_CNTL__FORCE_TOP
|
139 SCLK_CNTL__FORCE_IDCT
|
140 SCLK_CNTL__FORCE_VIP
|
143 SCLK_CNTL__FORCE_TAM
|
144 SCLK_CNTL__FORCE_TDM
|
146 SCLK_CNTL__FORCE_TV_SCLK
|
147 SCLK_CNTL__FORCE_SUBPIC
|
148 SCLK_CNTL__FORCE_OV0
;
150 else if (rinfo
->family
== CHIP_FAMILY_R300
||
151 rinfo
->family
== CHIP_FAMILY_R350
) {
152 tmp
|= SCLK_CNTL__FORCE_HDP
|
153 SCLK_CNTL__FORCE_DISP1
|
154 SCLK_CNTL__FORCE_DISP2
|
155 SCLK_CNTL__FORCE_TOP
|
156 SCLK_CNTL__FORCE_IDCT
|
157 SCLK_CNTL__FORCE_VIP
;
159 OUTPLL(pllSCLK_CNTL
, tmp
);
162 if (rinfo
->family
== CHIP_FAMILY_R300
|| rinfo
->family
== CHIP_FAMILY_R350
) {
163 tmp
= INPLL(pllSCLK_CNTL2
);
164 tmp
|= SCLK_CNTL2__R300_FORCE_TCL
|
165 SCLK_CNTL2__R300_FORCE_GA
|
166 SCLK_CNTL2__R300_FORCE_CBA
;
167 OUTPLL(pllSCLK_CNTL2
, tmp
);
171 tmp
= INPLL(pllCLK_PIN_CNTL
);
172 tmp
&= ~CLK_PIN_CNTL__SCLK_DYN_START_CNTL
;
173 OUTPLL(pllCLK_PIN_CNTL
, tmp
);
177 /* Weird ... X is _un_ forcing clocks here, I think it's
178 * doing backward. Imitate it for now...
180 tmp
= INPLL(pllMCLK_CNTL
);
181 tmp
&= ~(MCLK_CNTL__FORCE_MCLKA
|
182 MCLK_CNTL__FORCE_YCLKA
);
183 OUTPLL(pllMCLK_CNTL
, tmp
);
186 /* Hrm... same shit, X doesn't do that but I have to */
187 else if (rinfo
->is_mobility
) {
188 tmp
= INPLL(pllMCLK_CNTL
);
189 tmp
|= (MCLK_CNTL__FORCE_MCLKA
|
190 MCLK_CNTL__FORCE_MCLKB
|
191 MCLK_CNTL__FORCE_YCLKA
|
192 MCLK_CNTL__FORCE_YCLKB
);
193 OUTPLL(pllMCLK_CNTL
, tmp
);
196 tmp
= INPLL(pllMCLK_MISC
);
197 tmp
&= ~(MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT
|
198 MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT
|
199 MCLK_MISC__MC_MCLK_DYN_ENABLE
|
200 MCLK_MISC__IO_MCLK_DYN_ENABLE
);
201 OUTPLL(pllMCLK_MISC
, tmp
);
205 if (rinfo
->is_mobility
) {
206 tmp
= INPLL(pllSCLK_MORE_CNTL
);
207 tmp
|= SCLK_MORE_CNTL__FORCE_DISPREGS
|
208 SCLK_MORE_CNTL__FORCE_MC_GUI
|
209 SCLK_MORE_CNTL__FORCE_MC_HOST
;
210 OUTPLL(pllSCLK_MORE_CNTL
, tmp
);
214 tmp
= INPLL(pllPIXCLKS_CNTL
);
215 tmp
&= ~(PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb
|
216 PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb
|
217 PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb
|
218 PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb
|
219 PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb
|
220 PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb
|
221 PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb
);
222 OUTPLL(pllPIXCLKS_CNTL
, tmp
);
225 tmp
= INPLL( pllVCLK_ECP_CNTL
);
226 tmp
&= ~(VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb
|
227 VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb
);
228 OUTPLL( pllVCLK_ECP_CNTL
, tmp
);
232 static void radeon_pm_enable_dynamic_mode(struct radeonfb_info
*rinfo
)
237 if (!rinfo
->has_CRTC2
) {
238 tmp
= INPLL(pllSCLK_CNTL
);
240 if ((INREG(CONFIG_CNTL
) & CFG_ATI_REV_ID_MASK
) > CFG_ATI_REV_A13
)
241 tmp
&= ~(SCLK_CNTL__FORCE_CP
| SCLK_CNTL__FORCE_RB
);
242 tmp
&= ~(SCLK_CNTL__FORCE_HDP
| SCLK_CNTL__FORCE_DISP1
|
243 SCLK_CNTL__FORCE_TOP
| SCLK_CNTL__FORCE_SE
|
244 SCLK_CNTL__FORCE_IDCT
| SCLK_CNTL__FORCE_RE
|
245 SCLK_CNTL__FORCE_PB
| SCLK_CNTL__FORCE_TAM
|
246 SCLK_CNTL__FORCE_TDM
);
247 OUTPLL(pllSCLK_CNTL
, tmp
);
252 if (rinfo
->family
== CHIP_FAMILY_RV350
) {
253 tmp
= INPLL(pllSCLK_CNTL2
);
254 tmp
&= ~(SCLK_CNTL2__R300_FORCE_TCL
|
255 SCLK_CNTL2__R300_FORCE_GA
|
256 SCLK_CNTL2__R300_FORCE_CBA
);
257 tmp
|= (SCLK_CNTL2__R300_TCL_MAX_DYN_STOP_LAT
|
258 SCLK_CNTL2__R300_GA_MAX_DYN_STOP_LAT
|
259 SCLK_CNTL2__R300_CBA_MAX_DYN_STOP_LAT
);
260 OUTPLL(pllSCLK_CNTL2
, tmp
);
262 tmp
= INPLL(pllSCLK_CNTL
);
263 tmp
&= ~(SCLK_CNTL__FORCE_DISP2
| SCLK_CNTL__FORCE_CP
|
264 SCLK_CNTL__FORCE_HDP
| SCLK_CNTL__FORCE_DISP1
|
265 SCLK_CNTL__FORCE_TOP
| SCLK_CNTL__FORCE_E2
|
266 SCLK_CNTL__R300_FORCE_VAP
| SCLK_CNTL__FORCE_IDCT
|
267 SCLK_CNTL__FORCE_VIP
| SCLK_CNTL__R300_FORCE_SR
|
268 SCLK_CNTL__R300_FORCE_PX
| SCLK_CNTL__R300_FORCE_TX
|
269 SCLK_CNTL__R300_FORCE_US
| SCLK_CNTL__FORCE_TV_SCLK
|
270 SCLK_CNTL__R300_FORCE_SU
| SCLK_CNTL__FORCE_OV0
);
271 tmp
|= SCLK_CNTL__DYN_STOP_LAT_MASK
;
272 OUTPLL(pllSCLK_CNTL
, tmp
);
274 tmp
= INPLL(pllSCLK_MORE_CNTL
);
275 tmp
&= ~SCLK_MORE_CNTL__FORCEON
;
276 tmp
|= SCLK_MORE_CNTL__DISPREGS_MAX_DYN_STOP_LAT
|
277 SCLK_MORE_CNTL__MC_GUI_MAX_DYN_STOP_LAT
|
278 SCLK_MORE_CNTL__MC_HOST_MAX_DYN_STOP_LAT
;
279 OUTPLL(pllSCLK_MORE_CNTL
, tmp
);
281 tmp
= INPLL(pllVCLK_ECP_CNTL
);
282 tmp
|= (VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb
|
283 VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb
);
284 OUTPLL(pllVCLK_ECP_CNTL
, tmp
);
286 tmp
= INPLL(pllPIXCLKS_CNTL
);
287 tmp
|= (PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb
|
288 PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb
|
289 PIXCLKS_CNTL__DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb
|
290 PIXCLKS_CNTL__R300_DVOCLK_ALWAYS_ONb
|
291 PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb
|
292 PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb
|
293 PIXCLKS_CNTL__R300_PIXCLK_DVO_ALWAYS_ONb
|
294 PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb
|
295 PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb
|
296 PIXCLKS_CNTL__R300_PIXCLK_TRANS_ALWAYS_ONb
|
297 PIXCLKS_CNTL__R300_PIXCLK_TVO_ALWAYS_ONb
|
298 PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb
|
299 PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb
);
300 OUTPLL(pllPIXCLKS_CNTL
, tmp
);
302 tmp
= INPLL(pllMCLK_MISC
);
303 tmp
|= (MCLK_MISC__MC_MCLK_DYN_ENABLE
|
304 MCLK_MISC__IO_MCLK_DYN_ENABLE
);
305 OUTPLL(pllMCLK_MISC
, tmp
);
307 tmp
= INPLL(pllMCLK_CNTL
);
308 tmp
|= (MCLK_CNTL__FORCE_MCLKA
| MCLK_CNTL__FORCE_MCLKB
);
309 tmp
&= ~(MCLK_CNTL__FORCE_YCLKA
|
310 MCLK_CNTL__FORCE_YCLKB
|
311 MCLK_CNTL__FORCE_MC
);
313 /* Some releases of vbios have set DISABLE_MC_MCLKA
314 * and DISABLE_MC_MCLKB bits in the vbios table. Setting these
315 * bits will cause H/W hang when reading video memory with dynamic
318 if ((tmp
& MCLK_CNTL__R300_DISABLE_MC_MCLKA
) &&
319 (tmp
& MCLK_CNTL__R300_DISABLE_MC_MCLKB
)) {
320 /* If both bits are set, then check the active channels */
321 tmp
= INPLL(pllMCLK_CNTL
);
322 if (rinfo
->vram_width
== 64) {
323 if (INREG(MEM_CNTL
) & R300_MEM_USE_CD_CH_ONLY
)
324 tmp
&= ~MCLK_CNTL__R300_DISABLE_MC_MCLKB
;
326 tmp
&= ~MCLK_CNTL__R300_DISABLE_MC_MCLKA
;
328 tmp
&= ~(MCLK_CNTL__R300_DISABLE_MC_MCLKA
|
329 MCLK_CNTL__R300_DISABLE_MC_MCLKB
);
332 OUTPLL(pllMCLK_CNTL
, tmp
);
337 if (rinfo
->family
== CHIP_FAMILY_R300
|| rinfo
->family
== CHIP_FAMILY_R350
) {
338 tmp
= INPLL(pllSCLK_CNTL
);
339 tmp
&= ~(SCLK_CNTL__R300_FORCE_VAP
);
340 tmp
|= SCLK_CNTL__FORCE_CP
;
341 OUTPLL(pllSCLK_CNTL
, tmp
);
344 tmp
= INPLL(pllSCLK_CNTL2
);
345 tmp
&= ~(SCLK_CNTL2__R300_FORCE_TCL
|
346 SCLK_CNTL2__R300_FORCE_GA
|
347 SCLK_CNTL2__R300_FORCE_CBA
);
348 OUTPLL(pllSCLK_CNTL2
, tmp
);
353 tmp
= INPLL( pllCLK_PWRMGT_CNTL
);
354 tmp
&= ~(CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK
|
355 CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT_MASK
|
356 CLK_PWRMGT_CNTL__DYN_STOP_MODE_MASK
);
357 tmp
|= CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE_MASK
|
358 (0x01 << CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT__SHIFT
);
359 OUTPLL( pllCLK_PWRMGT_CNTL
, tmp
);
362 tmp
= INPLL(pllCLK_PIN_CNTL
);
363 tmp
|= CLK_PIN_CNTL__SCLK_DYN_START_CNTL
;
364 OUTPLL(pllCLK_PIN_CNTL
, tmp
);
367 /* When DRI is enabled, setting DYN_STOP_LAT to zero can cause some R200
368 * to lockup randomly, leave them as set by BIOS.
370 tmp
= INPLL(pllSCLK_CNTL
);
371 tmp
&= ~SCLK_CNTL__FORCEON_MASK
;
373 /*RAGE_6::A11 A12 A12N1 A13, RV250::A11 A12, R300*/
374 if ((rinfo
->family
== CHIP_FAMILY_RV250
&&
375 ((INREG(CONFIG_CNTL
) & CFG_ATI_REV_ID_MASK
) < CFG_ATI_REV_A13
)) ||
376 ((rinfo
->family
== CHIP_FAMILY_RV100
) &&
377 ((INREG(CONFIG_CNTL
) & CFG_ATI_REV_ID_MASK
) <= CFG_ATI_REV_A13
))) {
378 tmp
|= SCLK_CNTL__FORCE_CP
;
379 tmp
|= SCLK_CNTL__FORCE_VIP
;
381 OUTPLL(pllSCLK_CNTL
, tmp
);
384 if ((rinfo
->family
== CHIP_FAMILY_RV200
) ||
385 (rinfo
->family
== CHIP_FAMILY_RV250
) ||
386 (rinfo
->family
== CHIP_FAMILY_RV280
)) {
387 tmp
= INPLL(pllSCLK_MORE_CNTL
);
388 tmp
&= ~SCLK_MORE_CNTL__FORCEON
;
390 /* RV200::A11 A12 RV250::A11 A12 */
391 if (((rinfo
->family
== CHIP_FAMILY_RV200
) ||
392 (rinfo
->family
== CHIP_FAMILY_RV250
)) &&
393 ((INREG(CONFIG_CNTL
) & CFG_ATI_REV_ID_MASK
) < CFG_ATI_REV_A13
))
394 tmp
|= SCLK_MORE_CNTL__FORCEON
;
396 OUTPLL(pllSCLK_MORE_CNTL
, tmp
);
401 /* RV200::A11 A12, RV250::A11 A12 */
402 if (((rinfo
->family
== CHIP_FAMILY_RV200
) ||
403 (rinfo
->family
== CHIP_FAMILY_RV250
)) &&
404 ((INREG(CONFIG_CNTL
) & CFG_ATI_REV_ID_MASK
) < CFG_ATI_REV_A13
)) {
405 tmp
= INPLL(pllPLL_PWRMGT_CNTL
);
406 tmp
|= PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE
;
407 OUTPLL(pllPLL_PWRMGT_CNTL
, tmp
);
411 tmp
= INPLL(pllPIXCLKS_CNTL
);
412 tmp
|= PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb
|
413 PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb
|
414 PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb
|
415 PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb
|
416 PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb
|
417 PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb
|
418 PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb
;
419 OUTPLL(pllPIXCLKS_CNTL
, tmp
);
422 tmp
= INPLL(pllVCLK_ECP_CNTL
);
423 tmp
|= VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb
|
424 VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb
;
425 OUTPLL(pllVCLK_ECP_CNTL
, tmp
);
427 /* X doesn't do that ... hrm, we do on mobility && Macs */
429 if (rinfo
->is_mobility
) {
430 tmp
= INPLL(pllMCLK_CNTL
);
431 tmp
&= ~(MCLK_CNTL__FORCE_MCLKA
|
432 MCLK_CNTL__FORCE_MCLKB
|
433 MCLK_CNTL__FORCE_YCLKA
|
434 MCLK_CNTL__FORCE_YCLKB
);
435 OUTPLL(pllMCLK_CNTL
, tmp
);
438 tmp
= INPLL(pllMCLK_MISC
);
439 tmp
|= MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT
|
440 MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT
|
441 MCLK_MISC__MC_MCLK_DYN_ENABLE
|
442 MCLK_MISC__IO_MCLK_DYN_ENABLE
;
443 OUTPLL(pllMCLK_MISC
, tmp
);
446 #endif /* CONFIG_PPC_OF */
451 static void OUTMC( struct radeonfb_info
*rinfo
, u8 indx
, u32 value
)
453 OUTREG( MC_IND_INDEX
, indx
| MC_IND_INDEX__MC_IND_WR_EN
);
454 OUTREG( MC_IND_DATA
, value
);
457 static u32
INMC(struct radeonfb_info
*rinfo
, u8 indx
)
459 OUTREG( MC_IND_INDEX
, indx
);
460 return INREG( MC_IND_DATA
);
463 static void radeon_pm_save_regs(struct radeonfb_info
*rinfo
, int saving_for_d3
)
465 rinfo
->save_regs
[0] = INPLL(PLL_PWRMGT_CNTL
);
466 rinfo
->save_regs
[1] = INPLL(CLK_PWRMGT_CNTL
);
467 rinfo
->save_regs
[2] = INPLL(MCLK_CNTL
);
468 rinfo
->save_regs
[3] = INPLL(SCLK_CNTL
);
469 rinfo
->save_regs
[4] = INPLL(CLK_PIN_CNTL
);
470 rinfo
->save_regs
[5] = INPLL(VCLK_ECP_CNTL
);
471 rinfo
->save_regs
[6] = INPLL(PIXCLKS_CNTL
);
472 rinfo
->save_regs
[7] = INPLL(MCLK_MISC
);
473 rinfo
->save_regs
[8] = INPLL(P2PLL_CNTL
);
475 rinfo
->save_regs
[9] = INREG(DISP_MISC_CNTL
);
476 rinfo
->save_regs
[10] = INREG(DISP_PWR_MAN
);
477 rinfo
->save_regs
[11] = INREG(LVDS_GEN_CNTL
);
478 rinfo
->save_regs
[13] = INREG(TV_DAC_CNTL
);
479 rinfo
->save_regs
[14] = INREG(BUS_CNTL1
);
480 rinfo
->save_regs
[15] = INREG(CRTC_OFFSET_CNTL
);
481 rinfo
->save_regs
[16] = INREG(AGP_CNTL
);
482 rinfo
->save_regs
[17] = (INREG(CRTC_GEN_CNTL
) & 0xfdffffff) | 0x04000000;
483 rinfo
->save_regs
[18] = (INREG(CRTC2_GEN_CNTL
) & 0xfdffffff) | 0x04000000;
484 rinfo
->save_regs
[19] = INREG(GPIOPAD_A
);
485 rinfo
->save_regs
[20] = INREG(GPIOPAD_EN
);
486 rinfo
->save_regs
[21] = INREG(GPIOPAD_MASK
);
487 rinfo
->save_regs
[22] = INREG(ZV_LCDPAD_A
);
488 rinfo
->save_regs
[23] = INREG(ZV_LCDPAD_EN
);
489 rinfo
->save_regs
[24] = INREG(ZV_LCDPAD_MASK
);
490 rinfo
->save_regs
[25] = INREG(GPIO_VGA_DDC
);
491 rinfo
->save_regs
[26] = INREG(GPIO_DVI_DDC
);
492 rinfo
->save_regs
[27] = INREG(GPIO_MONID
);
493 rinfo
->save_regs
[28] = INREG(GPIO_CRT2_DDC
);
495 rinfo
->save_regs
[29] = INREG(SURFACE_CNTL
);
496 rinfo
->save_regs
[30] = INREG(MC_FB_LOCATION
);
497 rinfo
->save_regs
[31] = INREG(DISPLAY_BASE_ADDR
);
498 rinfo
->save_regs
[32] = INREG(MC_AGP_LOCATION
);
499 rinfo
->save_regs
[33] = INREG(CRTC2_DISPLAY_BASE_ADDR
);
501 rinfo
->save_regs
[34] = INPLL(SCLK_MORE_CNTL
);
502 rinfo
->save_regs
[35] = INREG(MEM_SDRAM_MODE_REG
);
503 rinfo
->save_regs
[36] = INREG(BUS_CNTL
);
504 rinfo
->save_regs
[39] = INREG(RBBM_CNTL
);
505 rinfo
->save_regs
[40] = INREG(DAC_CNTL
);
506 rinfo
->save_regs
[41] = INREG(HOST_PATH_CNTL
);
507 rinfo
->save_regs
[37] = INREG(MPP_TB_CONFIG
);
508 rinfo
->save_regs
[38] = INREG(FCP_CNTL
);
510 if (rinfo
->is_mobility
) {
511 rinfo
->save_regs
[12] = INREG(LVDS_PLL_CNTL
);
512 rinfo
->save_regs
[43] = INPLL(pllSSPLL_CNTL
);
513 rinfo
->save_regs
[44] = INPLL(pllSSPLL_REF_DIV
);
514 rinfo
->save_regs
[45] = INPLL(pllSSPLL_DIV_0
);
515 rinfo
->save_regs
[90] = INPLL(pllSS_INT_CNTL
);
516 rinfo
->save_regs
[91] = INPLL(pllSS_TST_CNTL
);
517 rinfo
->save_regs
[81] = INREG(LVDS_GEN_CNTL
);
520 if (rinfo
->family
>= CHIP_FAMILY_RV200
) {
521 rinfo
->save_regs
[42] = INREG(MEM_REFRESH_CNTL
);
522 rinfo
->save_regs
[46] = INREG(MC_CNTL
);
523 rinfo
->save_regs
[47] = INREG(MC_INIT_GFX_LAT_TIMER
);
524 rinfo
->save_regs
[48] = INREG(MC_INIT_MISC_LAT_TIMER
);
525 rinfo
->save_regs
[49] = INREG(MC_TIMING_CNTL
);
526 rinfo
->save_regs
[50] = INREG(MC_READ_CNTL_AB
);
527 rinfo
->save_regs
[51] = INREG(MC_IOPAD_CNTL
);
528 rinfo
->save_regs
[52] = INREG(MC_CHIP_IO_OE_CNTL_AB
);
529 rinfo
->save_regs
[53] = INREG(MC_DEBUG
);
531 rinfo
->save_regs
[54] = INREG(PAMAC0_DLY_CNTL
);
532 rinfo
->save_regs
[55] = INREG(PAMAC1_DLY_CNTL
);
533 rinfo
->save_regs
[56] = INREG(PAD_CTLR_MISC
);
534 rinfo
->save_regs
[57] = INREG(FW_CNTL
);
536 if (rinfo
->family
>= CHIP_FAMILY_R300
) {
537 rinfo
->save_regs
[58] = INMC(rinfo
, ixR300_MC_MC_INIT_WR_LAT_TIMER
);
538 rinfo
->save_regs
[59] = INMC(rinfo
, ixR300_MC_IMP_CNTL
);
539 rinfo
->save_regs
[60] = INMC(rinfo
, ixR300_MC_CHP_IO_CNTL_C0
);
540 rinfo
->save_regs
[61] = INMC(rinfo
, ixR300_MC_CHP_IO_CNTL_C1
);
541 rinfo
->save_regs
[62] = INMC(rinfo
, ixR300_MC_CHP_IO_CNTL_D0
);
542 rinfo
->save_regs
[63] = INMC(rinfo
, ixR300_MC_CHP_IO_CNTL_D1
);
543 rinfo
->save_regs
[64] = INMC(rinfo
, ixR300_MC_BIST_CNTL_3
);
544 rinfo
->save_regs
[65] = INMC(rinfo
, ixR300_MC_CHP_IO_CNTL_A0
);
545 rinfo
->save_regs
[66] = INMC(rinfo
, ixR300_MC_CHP_IO_CNTL_A1
);
546 rinfo
->save_regs
[67] = INMC(rinfo
, ixR300_MC_CHP_IO_CNTL_B0
);
547 rinfo
->save_regs
[68] = INMC(rinfo
, ixR300_MC_CHP_IO_CNTL_B1
);
548 rinfo
->save_regs
[69] = INMC(rinfo
, ixR300_MC_DEBUG_CNTL
);
549 rinfo
->save_regs
[70] = INMC(rinfo
, ixR300_MC_DLL_CNTL
);
550 rinfo
->save_regs
[71] = INMC(rinfo
, ixR300_MC_IMP_CNTL_0
);
551 rinfo
->save_regs
[72] = INMC(rinfo
, ixR300_MC_ELPIDA_CNTL
);
552 rinfo
->save_regs
[96] = INMC(rinfo
, ixR300_MC_READ_CNTL_CD
);
554 rinfo
->save_regs
[59] = INMC(rinfo
, ixMC_IMP_CNTL
);
555 rinfo
->save_regs
[65] = INMC(rinfo
, ixMC_CHP_IO_CNTL_A0
);
556 rinfo
->save_regs
[66] = INMC(rinfo
, ixMC_CHP_IO_CNTL_A1
);
557 rinfo
->save_regs
[67] = INMC(rinfo
, ixMC_CHP_IO_CNTL_B0
);
558 rinfo
->save_regs
[68] = INMC(rinfo
, ixMC_CHP_IO_CNTL_B1
);
559 rinfo
->save_regs
[71] = INMC(rinfo
, ixMC_IMP_CNTL_0
);
562 rinfo
->save_regs
[73] = INPLL(pllMPLL_CNTL
);
563 rinfo
->save_regs
[74] = INPLL(pllSPLL_CNTL
);
564 rinfo
->save_regs
[75] = INPLL(pllMPLL_AUX_CNTL
);
565 rinfo
->save_regs
[76] = INPLL(pllSPLL_AUX_CNTL
);
566 rinfo
->save_regs
[77] = INPLL(pllM_SPLL_REF_FB_DIV
);
567 rinfo
->save_regs
[78] = INPLL(pllAGP_PLL_CNTL
);
568 rinfo
->save_regs
[79] = INREG(PAMAC2_DLY_CNTL
);
570 rinfo
->save_regs
[80] = INREG(OV0_BASE_ADDR
);
571 rinfo
->save_regs
[82] = INREG(FP_GEN_CNTL
);
572 rinfo
->save_regs
[83] = INREG(FP2_GEN_CNTL
);
573 rinfo
->save_regs
[84] = INREG(TMDS_CNTL
);
574 rinfo
->save_regs
[85] = INREG(TMDS_TRANSMITTER_CNTL
);
575 rinfo
->save_regs
[86] = INREG(DISP_OUTPUT_CNTL
);
576 rinfo
->save_regs
[87] = INREG(DISP_HW_DEBUG
);
577 rinfo
->save_regs
[88] = INREG(TV_MASTER_CNTL
);
578 rinfo
->save_regs
[89] = INPLL(pllP2PLL_REF_DIV
);
579 rinfo
->save_regs
[92] = INPLL(pllPPLL_DIV_0
);
580 rinfo
->save_regs
[93] = INPLL(pllPPLL_CNTL
);
581 rinfo
->save_regs
[94] = INREG(GRPH_BUFFER_CNTL
);
582 rinfo
->save_regs
[95] = INREG(GRPH2_BUFFER_CNTL
);
583 rinfo
->save_regs
[96] = INREG(HDP_DEBUG
);
584 rinfo
->save_regs
[97] = INPLL(pllMDLL_CKO
);
585 rinfo
->save_regs
[98] = INPLL(pllMDLL_RDCKA
);
586 rinfo
->save_regs
[99] = INPLL(pllMDLL_RDCKB
);
589 static void radeon_pm_restore_regs(struct radeonfb_info
*rinfo
)
591 OUTPLL(P2PLL_CNTL
, rinfo
->save_regs
[8] & 0xFFFFFFFE); /* First */
593 OUTPLL(PLL_PWRMGT_CNTL
, rinfo
->save_regs
[0]);
594 OUTPLL(CLK_PWRMGT_CNTL
, rinfo
->save_regs
[1]);
595 OUTPLL(MCLK_CNTL
, rinfo
->save_regs
[2]);
596 OUTPLL(SCLK_CNTL
, rinfo
->save_regs
[3]);
597 OUTPLL(CLK_PIN_CNTL
, rinfo
->save_regs
[4]);
598 OUTPLL(VCLK_ECP_CNTL
, rinfo
->save_regs
[5]);
599 OUTPLL(PIXCLKS_CNTL
, rinfo
->save_regs
[6]);
600 OUTPLL(MCLK_MISC
, rinfo
->save_regs
[7]);
601 if (rinfo
->family
== CHIP_FAMILY_RV350
)
602 OUTPLL(SCLK_MORE_CNTL
, rinfo
->save_regs
[34]);
604 OUTREG(SURFACE_CNTL
, rinfo
->save_regs
[29]);
605 OUTREG(MC_FB_LOCATION
, rinfo
->save_regs
[30]);
606 OUTREG(DISPLAY_BASE_ADDR
, rinfo
->save_regs
[31]);
607 OUTREG(MC_AGP_LOCATION
, rinfo
->save_regs
[32]);
608 OUTREG(CRTC2_DISPLAY_BASE_ADDR
, rinfo
->save_regs
[33]);
609 OUTREG(CONFIG_MEMSIZE
, rinfo
->video_ram
);
611 OUTREG(DISP_MISC_CNTL
, rinfo
->save_regs
[9]);
612 OUTREG(DISP_PWR_MAN
, rinfo
->save_regs
[10]);
613 OUTREG(LVDS_GEN_CNTL
, rinfo
->save_regs
[11]);
614 OUTREG(LVDS_PLL_CNTL
,rinfo
->save_regs
[12]);
615 OUTREG(TV_DAC_CNTL
, rinfo
->save_regs
[13]);
616 OUTREG(BUS_CNTL1
, rinfo
->save_regs
[14]);
617 OUTREG(CRTC_OFFSET_CNTL
, rinfo
->save_regs
[15]);
618 OUTREG(AGP_CNTL
, rinfo
->save_regs
[16]);
619 OUTREG(CRTC_GEN_CNTL
, rinfo
->save_regs
[17]);
620 OUTREG(CRTC2_GEN_CNTL
, rinfo
->save_regs
[18]);
621 OUTPLL(P2PLL_CNTL
, rinfo
->save_regs
[8]);
623 OUTREG(GPIOPAD_A
, rinfo
->save_regs
[19]);
624 OUTREG(GPIOPAD_EN
, rinfo
->save_regs
[20]);
625 OUTREG(GPIOPAD_MASK
, rinfo
->save_regs
[21]);
626 OUTREG(ZV_LCDPAD_A
, rinfo
->save_regs
[22]);
627 OUTREG(ZV_LCDPAD_EN
, rinfo
->save_regs
[23]);
628 OUTREG(ZV_LCDPAD_MASK
, rinfo
->save_regs
[24]);
629 OUTREG(GPIO_VGA_DDC
, rinfo
->save_regs
[25]);
630 OUTREG(GPIO_DVI_DDC
, rinfo
->save_regs
[26]);
631 OUTREG(GPIO_MONID
, rinfo
->save_regs
[27]);
632 OUTREG(GPIO_CRT2_DDC
, rinfo
->save_regs
[28]);
635 static void radeon_pm_disable_iopad(struct radeonfb_info
*rinfo
)
637 OUTREG(GPIOPAD_MASK
, 0x0001ffff);
638 OUTREG(GPIOPAD_EN
, 0x00000400);
639 OUTREG(GPIOPAD_A
, 0x00000000);
640 OUTREG(ZV_LCDPAD_MASK
, 0x00000000);
641 OUTREG(ZV_LCDPAD_EN
, 0x00000000);
642 OUTREG(ZV_LCDPAD_A
, 0x00000000);
643 OUTREG(GPIO_VGA_DDC
, 0x00030000);
644 OUTREG(GPIO_DVI_DDC
, 0x00000000);
645 OUTREG(GPIO_MONID
, 0x00030000);
646 OUTREG(GPIO_CRT2_DDC
, 0x00000000);
649 static void radeon_pm_program_v2clk(struct radeonfb_info
*rinfo
)
651 /* Set v2clk to 65MHz */
652 if (rinfo
->family
<= CHIP_FAMILY_RV280
) {
653 OUTPLL(pllPIXCLKS_CNTL
,
654 __INPLL(rinfo
, pllPIXCLKS_CNTL
)
655 & ~PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK
);
657 OUTPLL(pllP2PLL_REF_DIV
, 0x0000000c);
658 OUTPLL(pllP2PLL_CNTL
, 0x0000bf00);
660 OUTPLL(pllP2PLL_REF_DIV
, 0x0000000c);
661 INPLL(pllP2PLL_REF_DIV
);
662 OUTPLL(pllP2PLL_CNTL
, 0x0000a700);
665 OUTPLL(pllP2PLL_DIV_0
, 0x00020074 | P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W
);
667 OUTPLL(pllP2PLL_CNTL
, INPLL(pllP2PLL_CNTL
) & ~P2PLL_CNTL__P2PLL_SLEEP
);
670 OUTPLL(pllP2PLL_CNTL
, INPLL(pllP2PLL_CNTL
) & ~P2PLL_CNTL__P2PLL_RESET
);
673 OUTPLL(pllPIXCLKS_CNTL
,
674 (INPLL(pllPIXCLKS_CNTL
) & ~PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK
)
675 | (0x03 << PIXCLKS_CNTL__PIX2CLK_SRC_SEL__SHIFT
));
679 static void radeon_pm_low_current(struct radeonfb_info
*rinfo
)
683 reg
= INREG(BUS_CNTL1
);
684 if (rinfo
->family
<= CHIP_FAMILY_RV280
) {
685 reg
&= ~BUS_CNTL1_MOBILE_PLATFORM_SEL_MASK
;
686 reg
|= BUS_CNTL1_AGPCLK_VALID
| (1<<BUS_CNTL1_MOBILE_PLATFORM_SEL_SHIFT
);
690 OUTREG(BUS_CNTL1
, reg
);
692 reg
= INPLL(PLL_PWRMGT_CNTL
);
693 reg
|= PLL_PWRMGT_CNTL_SPLL_TURNOFF
| PLL_PWRMGT_CNTL_PPLL_TURNOFF
|
694 PLL_PWRMGT_CNTL_P2PLL_TURNOFF
| PLL_PWRMGT_CNTL_TVPLL_TURNOFF
;
695 reg
&= ~PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK
;
696 reg
&= ~PLL_PWRMGT_CNTL_MOBILE_SU
;
697 OUTPLL(PLL_PWRMGT_CNTL
, reg
);
699 reg
= INREG(TV_DAC_CNTL
);
700 reg
&= ~(TV_DAC_CNTL_BGADJ_MASK
|TV_DAC_CNTL_DACADJ_MASK
);
701 reg
|=TV_DAC_CNTL_BGSLEEP
| TV_DAC_CNTL_RDACPD
| TV_DAC_CNTL_GDACPD
|
703 (8<<TV_DAC_CNTL_BGADJ__SHIFT
) | (8<<TV_DAC_CNTL_DACADJ__SHIFT
);
704 OUTREG(TV_DAC_CNTL
, reg
);
706 reg
= INREG(TMDS_TRANSMITTER_CNTL
);
707 reg
&= ~(TMDS_PLL_EN
| TMDS_PLLRST
);
708 OUTREG(TMDS_TRANSMITTER_CNTL
, reg
);
710 reg
= INREG(DAC_CNTL
);
712 OUTREG(DAC_CNTL
, reg
);
714 reg
= INREG(DAC_CNTL2
);
716 OUTREG(DAC_CNTL2
, reg
);
718 reg
= INREG(TV_DAC_CNTL
);
719 reg
&= ~TV_DAC_CNTL_DETECT
;
720 OUTREG(TV_DAC_CNTL
, reg
);
723 static void radeon_pm_setup_for_suspend(struct radeonfb_info
*rinfo
)
726 u32 sclk_cntl
, mclk_cntl
, sclk_more_cntl
;
737 /* Force Core Clocks */
738 sclk_cntl
= INPLL( pllSCLK_CNTL
);
739 sclk_cntl
|= SCLK_CNTL__IDCT_MAX_DYN_STOP_LAT
|
740 SCLK_CNTL__VIP_MAX_DYN_STOP_LAT
|
741 SCLK_CNTL__RE_MAX_DYN_STOP_LAT
|
742 SCLK_CNTL__PB_MAX_DYN_STOP_LAT
|
743 SCLK_CNTL__TAM_MAX_DYN_STOP_LAT
|
744 SCLK_CNTL__TDM_MAX_DYN_STOP_LAT
|
745 SCLK_CNTL__RB_MAX_DYN_STOP_LAT
|
747 SCLK_CNTL__FORCE_DISP2
|
749 SCLK_CNTL__FORCE_HDP
|
750 SCLK_CNTL__FORCE_DISP1
|
751 SCLK_CNTL__FORCE_TOP
|
754 SCLK_CNTL__FORCE_IDCT
|
755 SCLK_CNTL__FORCE_VIP
|
758 SCLK_CNTL__FORCE_TAM
|
759 SCLK_CNTL__FORCE_TDM
|
761 SCLK_CNTL__FORCE_TV_SCLK
|
762 SCLK_CNTL__FORCE_SUBPIC
|
763 SCLK_CNTL__FORCE_OV0
;
764 if (rinfo
->family
<= CHIP_FAMILY_RV280
)
765 sclk_cntl
|= SCLK_CNTL__FORCE_RE
;
767 sclk_cntl
|= SCLK_CNTL__SE_MAX_DYN_STOP_LAT
|
768 SCLK_CNTL__E2_MAX_DYN_STOP_LAT
|
769 SCLK_CNTL__TV_MAX_DYN_STOP_LAT
|
770 SCLK_CNTL__HDP_MAX_DYN_STOP_LAT
|
771 SCLK_CNTL__CP_MAX_DYN_STOP_LAT
;
773 OUTPLL( pllSCLK_CNTL
, sclk_cntl
);
775 sclk_more_cntl
= INPLL(pllSCLK_MORE_CNTL
);
776 sclk_more_cntl
|= SCLK_MORE_CNTL__FORCE_DISPREGS
|
777 SCLK_MORE_CNTL__FORCE_MC_GUI
|
778 SCLK_MORE_CNTL__FORCE_MC_HOST
;
780 OUTPLL(pllSCLK_MORE_CNTL
, sclk_more_cntl
);
783 mclk_cntl
= INPLL( pllMCLK_CNTL
);
784 mclk_cntl
&= ~( MCLK_CNTL__FORCE_MCLKA
|
785 MCLK_CNTL__FORCE_MCLKB
|
786 MCLK_CNTL__FORCE_YCLKA
|
787 MCLK_CNTL__FORCE_YCLKB
|
790 OUTPLL( pllMCLK_CNTL
, mclk_cntl
);
792 /* Force Display clocks */
793 vclk_ecp_cntl
= INPLL( pllVCLK_ECP_CNTL
);
794 vclk_ecp_cntl
&= ~(VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb
795 | VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb
);
796 vclk_ecp_cntl
|= VCLK_ECP_CNTL__ECP_FORCE_ON
;
797 OUTPLL( pllVCLK_ECP_CNTL
, vclk_ecp_cntl
);
800 pixclks_cntl
= INPLL( pllPIXCLKS_CNTL
);
801 pixclks_cntl
&= ~( PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb
|
802 PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb
|
803 PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb
|
804 PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb
|
805 PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb
|
806 PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb
|
807 PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb
);
809 OUTPLL( pllPIXCLKS_CNTL
, pixclks_cntl
);
811 /* Switch off LVDS interface */
812 OUTREG(LVDS_GEN_CNTL
, INREG(LVDS_GEN_CNTL
) &
813 ~(LVDS_BLON
| LVDS_EN
| LVDS_ON
| LVDS_DIGON
));
815 /* Enable System power management */
816 pll_pwrmgt_cntl
= INPLL( pllPLL_PWRMGT_CNTL
);
818 pll_pwrmgt_cntl
|= PLL_PWRMGT_CNTL__SPLL_TURNOFF
|
819 PLL_PWRMGT_CNTL__MPLL_TURNOFF
|
820 PLL_PWRMGT_CNTL__PPLL_TURNOFF
|
821 PLL_PWRMGT_CNTL__P2PLL_TURNOFF
|
822 PLL_PWRMGT_CNTL__TVPLL_TURNOFF
;
824 OUTPLL( pllPLL_PWRMGT_CNTL
, pll_pwrmgt_cntl
);
826 clk_pwrmgt_cntl
= INPLL( pllCLK_PWRMGT_CNTL
);
828 clk_pwrmgt_cntl
&= ~( CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF
|
829 CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF
|
830 CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF
|
831 CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF
|
832 CLK_PWRMGT_CNTL__MCLK_TURNOFF
|
833 CLK_PWRMGT_CNTL__SCLK_TURNOFF
|
834 CLK_PWRMGT_CNTL__PCLK_TURNOFF
|
835 CLK_PWRMGT_CNTL__P2CLK_TURNOFF
|
836 CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF
|
837 CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN
|
838 CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE
|
839 CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK
|
840 CLK_PWRMGT_CNTL__CG_NO1_DEBUG_MASK
843 clk_pwrmgt_cntl
|= CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN
844 | CLK_PWRMGT_CNTL__DISP_PM
;
846 OUTPLL( pllCLK_PWRMGT_CNTL
, clk_pwrmgt_cntl
);
848 clk_pin_cntl
= INPLL( pllCLK_PIN_CNTL
);
850 clk_pin_cntl
&= ~CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND
;
852 /* because both INPLL and OUTPLL take the same lock, that's why. */
853 tmp
= INPLL( pllMCLK_MISC
) | MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND
;
854 OUTPLL( pllMCLK_MISC
, tmp
);
856 /* AGP PLL control */
857 if (rinfo
->family
<= CHIP_FAMILY_RV280
) {
858 OUTREG(BUS_CNTL1
, INREG(BUS_CNTL1
) | BUS_CNTL1__AGPCLK_VALID
);
861 (INREG(BUS_CNTL1
) & ~BUS_CNTL1__MOBILE_PLATFORM_SEL_MASK
)
862 | (2<<BUS_CNTL1__MOBILE_PLATFORM_SEL__SHIFT
)); // 440BX
864 OUTREG(BUS_CNTL1
, INREG(BUS_CNTL1
));
865 OUTREG(BUS_CNTL1
, (INREG(BUS_CNTL1
) & ~0x4000) | 0x8000);
868 OUTREG(CRTC_OFFSET_CNTL
, (INREG(CRTC_OFFSET_CNTL
)
869 & ~CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN
));
871 clk_pin_cntl
&= ~CLK_PIN_CNTL__CG_CLK_TO_OUTPIN
;
872 clk_pin_cntl
|= CLK_PIN_CNTL__XTALIN_ALWAYS_ONb
;
873 OUTPLL( pllCLK_PIN_CNTL
, clk_pin_cntl
);
877 (INREG(AGP_CNTL
) & ~(AGP_CNTL__MAX_IDLE_CLK_MASK
))
878 | (0x20<<AGP_CNTL__MAX_IDLE_CLK__SHIFT
));
881 /* because both INPLL and OUTPLL take the same lock, that's why. */
882 tmp
= INPLL( pllPLL_PWRMGT_CNTL
) & ~PLL_PWRMGT_CNTL__PM_MODE_SEL
;
883 OUTPLL( pllPLL_PWRMGT_CNTL
, tmp
);
886 disp_mis_cntl
= INREG(DISP_MISC_CNTL
);
888 disp_mis_cntl
&= ~( DISP_MISC_CNTL__SOFT_RESET_GRPH_PP
|
889 DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP
|
890 DISP_MISC_CNTL__SOFT_RESET_OV0_PP
|
891 DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK
|
892 DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK
|
893 DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK
|
894 DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP
|
895 DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK
|
896 DISP_MISC_CNTL__SOFT_RESET_LVDS
|
897 DISP_MISC_CNTL__SOFT_RESET_TMDS
|
898 DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS
|
899 DISP_MISC_CNTL__SOFT_RESET_TV
);
901 OUTREG(DISP_MISC_CNTL
, disp_mis_cntl
);
903 disp_pwr_man
= INREG(DISP_PWR_MAN
);
905 disp_pwr_man
&= ~( DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN
|
906 DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN
|
907 DISP_PWR_MAN__DISP_PWR_MAN_DPMS_MASK
|
908 DISP_PWR_MAN__DISP_D3_RST
|
909 DISP_PWR_MAN__DISP_D3_REG_RST
912 disp_pwr_man
|= DISP_PWR_MAN__DISP_D3_GRPH_RST
|
913 DISP_PWR_MAN__DISP_D3_SUBPIC_RST
|
914 DISP_PWR_MAN__DISP_D3_OV0_RST
|
915 DISP_PWR_MAN__DISP_D1D2_GRPH_RST
|
916 DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST
|
917 DISP_PWR_MAN__DISP_D1D2_OV0_RST
|
918 DISP_PWR_MAN__DIG_TMDS_ENABLE_RST
|
919 DISP_PWR_MAN__TV_ENABLE_RST
|
920 // DISP_PWR_MAN__AUTO_PWRUP_EN|
923 OUTREG(DISP_PWR_MAN
, disp_pwr_man
);
925 clk_pwrmgt_cntl
= INPLL( pllCLK_PWRMGT_CNTL
);
926 pll_pwrmgt_cntl
= INPLL( pllPLL_PWRMGT_CNTL
) ;
927 clk_pin_cntl
= INPLL( pllCLK_PIN_CNTL
);
928 disp_pwr_man
= INREG(DISP_PWR_MAN
);
932 clk_pwrmgt_cntl
|= CLK_PWRMGT_CNTL__DISP_PM
;
933 pll_pwrmgt_cntl
|= PLL_PWRMGT_CNTL__MOBILE_SU
| PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK
;
934 clk_pin_cntl
|= CLK_PIN_CNTL__XTALIN_ALWAYS_ONb
;
935 disp_pwr_man
&= ~(DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN_MASK
936 | DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN_MASK
);
938 OUTPLL( pllCLK_PWRMGT_CNTL
, clk_pwrmgt_cntl
);
939 OUTPLL( pllPLL_PWRMGT_CNTL
, pll_pwrmgt_cntl
);
940 OUTPLL( pllCLK_PIN_CNTL
, clk_pin_cntl
);
941 OUTREG(DISP_PWR_MAN
, disp_pwr_man
);
943 /* disable display request & disable display */
944 OUTREG( CRTC_GEN_CNTL
, (INREG( CRTC_GEN_CNTL
) & ~CRTC_GEN_CNTL__CRTC_EN
)
945 | CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B
);
946 OUTREG( CRTC2_GEN_CNTL
, (INREG( CRTC2_GEN_CNTL
) & ~CRTC2_GEN_CNTL__CRTC2_EN
)
947 | CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B
);
953 static void radeon_pm_yclk_mclk_sync(struct radeonfb_info
*rinfo
)
955 u32 mc_chp_io_cntl_a1
, mc_chp_io_cntl_b1
;
957 mc_chp_io_cntl_a1
= INMC( rinfo
, ixMC_CHP_IO_CNTL_A1
)
958 & ~MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA_MASK
;
959 mc_chp_io_cntl_b1
= INMC( rinfo
, ixMC_CHP_IO_CNTL_B1
)
960 & ~MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB_MASK
;
962 OUTMC( rinfo
, ixMC_CHP_IO_CNTL_A1
, mc_chp_io_cntl_a1
963 | (1<<MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA__SHIFT
));
964 OUTMC( rinfo
, ixMC_CHP_IO_CNTL_B1
, mc_chp_io_cntl_b1
965 | (1<<MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB__SHIFT
));
967 OUTMC( rinfo
, ixMC_CHP_IO_CNTL_A1
, mc_chp_io_cntl_a1
);
968 OUTMC( rinfo
, ixMC_CHP_IO_CNTL_B1
, mc_chp_io_cntl_b1
);
973 static void radeon_pm_yclk_mclk_sync_m10(struct radeonfb_info
*rinfo
)
975 u32 mc_chp_io_cntl_a1
, mc_chp_io_cntl_b1
;
977 mc_chp_io_cntl_a1
= INMC(rinfo
, ixR300_MC_CHP_IO_CNTL_A1
)
978 & ~MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA_MASK
;
979 mc_chp_io_cntl_b1
= INMC(rinfo
, ixR300_MC_CHP_IO_CNTL_B1
)
980 & ~MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB_MASK
;
982 OUTMC( rinfo
, ixR300_MC_CHP_IO_CNTL_A1
,
983 mc_chp_io_cntl_a1
| (1<<MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA__SHIFT
));
984 OUTMC( rinfo
, ixR300_MC_CHP_IO_CNTL_B1
,
985 mc_chp_io_cntl_b1
| (1<<MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB__SHIFT
));
987 OUTMC( rinfo
, ixR300_MC_CHP_IO_CNTL_A1
, mc_chp_io_cntl_a1
);
988 OUTMC( rinfo
, ixR300_MC_CHP_IO_CNTL_B1
, mc_chp_io_cntl_b1
);
993 static void radeon_pm_program_mode_reg(struct radeonfb_info
*rinfo
, u16 value
,
998 mem_sdram_mode
= INREG( MEM_SDRAM_MODE_REG
);
1000 mem_sdram_mode
&= ~MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK
;
1001 mem_sdram_mode
|= (value
<<MEM_SDRAM_MODE_REG__MEM_MODE_REG__SHIFT
)
1002 | MEM_SDRAM_MODE_REG__MEM_CFG_TYPE
;
1003 OUTREG( MEM_SDRAM_MODE_REG
, mem_sdram_mode
);
1004 if (delay_required
>= 2)
1007 mem_sdram_mode
|= MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET
;
1008 OUTREG( MEM_SDRAM_MODE_REG
, mem_sdram_mode
);
1009 if (delay_required
>= 2)
1012 mem_sdram_mode
&= ~MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET
;
1013 OUTREG( MEM_SDRAM_MODE_REG
, mem_sdram_mode
);
1014 if (delay_required
>= 2)
1017 if (delay_required
) {
1019 if (delay_required
>= 2)
1021 } while ((INREG(MC_STATUS
)
1022 & (MC_STATUS__MEM_PWRUP_COMPL_A
|
1023 MC_STATUS__MEM_PWRUP_COMPL_B
)) == 0);
1027 static void radeon_pm_m10_program_mode_wait(struct radeonfb_info
*rinfo
)
1031 for (cnt
= 0; cnt
< 100; ++cnt
) {
1033 if (INREG(MC_STATUS
) & (MC_STATUS__MEM_PWRUP_COMPL_A
1034 | MC_STATUS__MEM_PWRUP_COMPL_B
))
1040 static void radeon_pm_enable_dll(struct radeonfb_info
*rinfo
)
1042 #define DLL_RESET_DELAY 5
1043 #define DLL_SLEEP_DELAY 1
1045 u32 cko
= INPLL(pllMDLL_CKO
) | MDLL_CKO__MCKOA_SLEEP
1046 | MDLL_CKO__MCKOA_RESET
;
1047 u32 cka
= INPLL(pllMDLL_RDCKA
) | MDLL_RDCKA__MRDCKA0_SLEEP
1048 | MDLL_RDCKA__MRDCKA1_SLEEP
| MDLL_RDCKA__MRDCKA0_RESET
1049 | MDLL_RDCKA__MRDCKA1_RESET
;
1050 u32 ckb
= INPLL(pllMDLL_RDCKB
) | MDLL_RDCKB__MRDCKB0_SLEEP
1051 | MDLL_RDCKB__MRDCKB1_SLEEP
| MDLL_RDCKB__MRDCKB0_RESET
1052 | MDLL_RDCKB__MRDCKB1_RESET
;
1054 /* Setting up the DLL range for write */
1055 OUTPLL(pllMDLL_CKO
, cko
);
1056 OUTPLL(pllMDLL_RDCKA
, cka
);
1057 OUTPLL(pllMDLL_RDCKB
, ckb
);
1059 mdelay(DLL_RESET_DELAY
*2);
1061 cko
&= ~(MDLL_CKO__MCKOA_SLEEP
| MDLL_CKO__MCKOB_SLEEP
);
1062 OUTPLL(pllMDLL_CKO
, cko
);
1063 mdelay(DLL_SLEEP_DELAY
);
1064 cko
&= ~(MDLL_CKO__MCKOA_RESET
| MDLL_CKO__MCKOB_RESET
);
1065 OUTPLL(pllMDLL_CKO
, cko
);
1066 mdelay(DLL_RESET_DELAY
);
1068 cka
&= ~(MDLL_RDCKA__MRDCKA0_SLEEP
| MDLL_RDCKA__MRDCKA1_SLEEP
);
1069 OUTPLL(pllMDLL_RDCKA
, cka
);
1070 mdelay(DLL_SLEEP_DELAY
);
1071 cka
&= ~(MDLL_RDCKA__MRDCKA0_RESET
| MDLL_RDCKA__MRDCKA1_RESET
);
1072 OUTPLL(pllMDLL_RDCKA
, cka
);
1073 mdelay(DLL_RESET_DELAY
);
1075 ckb
&= ~(MDLL_RDCKB__MRDCKB0_SLEEP
| MDLL_RDCKB__MRDCKB1_SLEEP
);
1076 OUTPLL(pllMDLL_RDCKB
, ckb
);
1077 mdelay(DLL_SLEEP_DELAY
);
1078 ckb
&= ~(MDLL_RDCKB__MRDCKB0_RESET
| MDLL_RDCKB__MRDCKB1_RESET
);
1079 OUTPLL(pllMDLL_RDCKB
, ckb
);
1080 mdelay(DLL_RESET_DELAY
);
1083 #undef DLL_RESET_DELAY
1084 #undef DLL_SLEEP_DELAY
1087 static void radeon_pm_enable_dll_m10(struct radeonfb_info
*rinfo
)
1090 u32 dll_sleep_mask
= 0;
1091 u32 dll_reset_mask
= 0;
1094 #define DLL_RESET_DELAY 5
1095 #define DLL_SLEEP_DELAY 1
1097 OUTMC(rinfo
, ixR300_MC_DLL_CNTL
, rinfo
->save_regs
[70]);
1098 mc
= INREG(MC_CNTL
);
1099 /* Check which channels are enabled */
1105 dll_sleep_mask
|= MDLL_R300_RDCK__MRDCKB_SLEEP
;
1106 dll_reset_mask
|= MDLL_R300_RDCK__MRDCKB_RESET
;
1108 dll_sleep_mask
|= MDLL_R300_RDCK__MRDCKA_SLEEP
;
1109 dll_reset_mask
|= MDLL_R300_RDCK__MRDCKA_RESET
;
1116 dll_sleep_mask
|= MDLL_R300_RDCK__MRDCKD_SLEEP
;
1117 dll_reset_mask
|= MDLL_R300_RDCK__MRDCKD_RESET
;
1118 dll_sleep_mask
|= MDLL_R300_RDCK__MRDCKC_SLEEP
;
1119 dll_reset_mask
|= MDLL_R300_RDCK__MRDCKC_RESET
;
1122 dll_value
= INPLL(pllMDLL_RDCKA
);
1125 dll_value
&= ~(dll_sleep_mask
);
1126 OUTPLL(pllMDLL_RDCKA
, dll_value
);
1127 mdelay( DLL_SLEEP_DELAY
);
1129 dll_value
&= ~(dll_reset_mask
);
1130 OUTPLL(pllMDLL_RDCKA
, dll_value
);
1131 mdelay( DLL_RESET_DELAY
);
1133 #undef DLL_RESET_DELAY
1134 #undef DLL_SLEEP_DELAY
1138 static void radeon_pm_full_reset_sdram(struct radeonfb_info
*rinfo
)
1140 u32 crtcGenCntl
, crtcGenCntl2
, memRefreshCntl
, crtc_more_cntl
,
1141 fp_gen_cntl
, fp2_gen_cntl
;
1143 crtcGenCntl
= INREG( CRTC_GEN_CNTL
);
1144 crtcGenCntl2
= INREG( CRTC2_GEN_CNTL
);
1146 crtc_more_cntl
= INREG( CRTC_MORE_CNTL
);
1147 fp_gen_cntl
= INREG( FP_GEN_CNTL
);
1148 fp2_gen_cntl
= INREG( FP2_GEN_CNTL
);
1151 OUTREG( CRTC_MORE_CNTL
, 0);
1152 OUTREG( FP_GEN_CNTL
, 0);
1153 OUTREG( FP2_GEN_CNTL
,0);
1155 OUTREG( CRTC_GEN_CNTL
, (crtcGenCntl
| CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B
) );
1156 OUTREG( CRTC2_GEN_CNTL
, (crtcGenCntl2
| CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B
) );
1158 /* This is the code for the Aluminium PowerBooks M10 */
1159 if (rinfo
->family
== CHIP_FAMILY_RV350
) {
1160 u32 sdram_mode_reg
= rinfo
->save_regs
[35];
1161 static u32 default_mrtable
[] =
1163 0x21321000, 0xa1321000, 0x21321000, 0xffffffff,
1164 0x21320032, 0xa1320032, 0x21320032, 0xffffffff,
1165 0x21321002, 0xa1321002, 0x21321002, 0xffffffff,
1166 0x21320132, 0xa1320132, 0x21320132, 0xffffffff,
1167 0x21320032, 0xa1320032, 0x21320032, 0xffffffff,
1170 u32
*mrtable
= default_mrtable
;
1171 int i
, mrtable_size
= ARRAY_SIZE(default_mrtable
);
1175 /* Disable refresh */
1176 memRefreshCntl
= INREG( MEM_REFRESH_CNTL
)
1177 & ~MEM_REFRESH_CNTL__MEM_REFRESH_DIS
;
1178 OUTREG( MEM_REFRESH_CNTL
, memRefreshCntl
1179 | MEM_REFRESH_CNTL__MEM_REFRESH_DIS
);
1181 /* Configure and enable M & SPLLs */
1182 radeon_pm_enable_dll_m10(rinfo
);
1183 radeon_pm_yclk_mclk_sync_m10(rinfo
);
1185 #ifdef CONFIG_PPC_OF
1186 if (rinfo
->of_node
!= NULL
) {
1189 mrtable
= (u32
*)get_property(rinfo
->of_node
, "ATY,MRT", &size
);
1191 mrtable_size
= size
>> 2;
1193 mrtable
= default_mrtable
;
1195 #endif /* CONFIG_PPC_OF */
1197 /* Program the SDRAM */
1198 sdram_mode_reg
= mrtable
[0];
1199 OUTREG(MEM_SDRAM_MODE_REG
, sdram_mode_reg
);
1200 for (i
= 0; i
< mrtable_size
; i
++) {
1201 if (mrtable
[i
] == 0xffffffffu
)
1202 radeon_pm_m10_program_mode_wait(rinfo
);
1204 sdram_mode_reg
&= ~(MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK
1205 | MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE
1206 | MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET
);
1207 sdram_mode_reg
|= mrtable
[i
];
1209 OUTREG(MEM_SDRAM_MODE_REG
, sdram_mode_reg
);
1214 /* Restore memory refresh */
1215 OUTREG(MEM_REFRESH_CNTL
, memRefreshCntl
);
1219 /* Here come the desktop RV200 "QW" card */
1220 else if (!rinfo
->is_mobility
&& rinfo
->family
== CHIP_FAMILY_RV200
) {
1221 /* Disable refresh */
1222 memRefreshCntl
= INREG( MEM_REFRESH_CNTL
)
1223 & ~MEM_REFRESH_CNTL__MEM_REFRESH_DIS
;
1224 OUTREG(MEM_REFRESH_CNTL
, memRefreshCntl
1225 | MEM_REFRESH_CNTL__MEM_REFRESH_DIS
);
1229 OUTREG(MEM_SDRAM_MODE_REG
,
1230 INREG( MEM_SDRAM_MODE_REG
) & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE
);
1232 radeon_pm_program_mode_reg(rinfo
, 0x2002, 2);
1233 radeon_pm_program_mode_reg(rinfo
, 0x0132, 2);
1234 radeon_pm_program_mode_reg(rinfo
, 0x0032, 2);
1236 OUTREG(MEM_SDRAM_MODE_REG
,
1237 INREG(MEM_SDRAM_MODE_REG
) | MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE
);
1239 OUTREG( MEM_REFRESH_CNTL
, memRefreshCntl
);
1243 else if (rinfo
->is_mobility
&& rinfo
->family
== CHIP_FAMILY_RV100
) {
1244 /* Disable refresh */
1245 memRefreshCntl
= INREG(EXT_MEM_CNTL
) & ~(1 << 20);
1246 OUTREG( EXT_MEM_CNTL
, memRefreshCntl
| (1 << 20));
1249 OUTREG( MEM_SDRAM_MODE_REG
,
1250 INREG( MEM_SDRAM_MODE_REG
)
1251 & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE
);
1254 radeon_pm_enable_dll(rinfo
);
1256 /* MLCK / YCLK sync */
1257 radeon_pm_yclk_mclk_sync(rinfo
);
1259 /* Program Mode Register */
1260 radeon_pm_program_mode_reg(rinfo
, 0x2000, 1);
1261 radeon_pm_program_mode_reg(rinfo
, 0x2001, 1);
1262 radeon_pm_program_mode_reg(rinfo
, 0x2002, 1);
1263 radeon_pm_program_mode_reg(rinfo
, 0x0132, 1);
1264 radeon_pm_program_mode_reg(rinfo
, 0x0032, 1);
1266 /* Complete & re-enable refresh */
1267 OUTREG( MEM_SDRAM_MODE_REG
,
1268 INREG( MEM_SDRAM_MODE_REG
) | MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE
);
1270 OUTREG(EXT_MEM_CNTL
, memRefreshCntl
);
1272 /* And finally, the M7..M9 models, including M9+ (RV280) */
1273 else if (rinfo
->is_mobility
) {
1275 /* Disable refresh */
1276 memRefreshCntl
= INREG( MEM_REFRESH_CNTL
)
1277 & ~MEM_REFRESH_CNTL__MEM_REFRESH_DIS
;
1278 OUTREG( MEM_REFRESH_CNTL
, memRefreshCntl
1279 | MEM_REFRESH_CNTL__MEM_REFRESH_DIS
);
1282 OUTREG( MEM_SDRAM_MODE_REG
,
1283 INREG( MEM_SDRAM_MODE_REG
)
1284 & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE
);
1287 radeon_pm_enable_dll(rinfo
);
1289 /* MLCK / YCLK sync */
1290 radeon_pm_yclk_mclk_sync(rinfo
);
1292 /* M6, M7 and M9 so far ... */
1293 if (rinfo
->family
<= CHIP_FAMILY_RV250
) {
1294 radeon_pm_program_mode_reg(rinfo
, 0x2000, 1);
1295 radeon_pm_program_mode_reg(rinfo
, 0x2001, 1);
1296 radeon_pm_program_mode_reg(rinfo
, 0x2002, 1);
1297 radeon_pm_program_mode_reg(rinfo
, 0x0132, 1);
1298 radeon_pm_program_mode_reg(rinfo
, 0x0032, 1);
1300 /* M9+ (iBook G4) */
1301 else if (rinfo
->family
== CHIP_FAMILY_RV280
) {
1302 radeon_pm_program_mode_reg(rinfo
, 0x2000, 1);
1303 radeon_pm_program_mode_reg(rinfo
, 0x0132, 1);
1304 radeon_pm_program_mode_reg(rinfo
, 0x0032, 1);
1307 /* Complete & re-enable refresh */
1308 OUTREG( MEM_SDRAM_MODE_REG
,
1309 INREG( MEM_SDRAM_MODE_REG
) | MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE
);
1311 OUTREG( MEM_REFRESH_CNTL
, memRefreshCntl
);
1314 OUTREG( CRTC_GEN_CNTL
, crtcGenCntl
);
1315 OUTREG( CRTC2_GEN_CNTL
, crtcGenCntl2
);
1316 OUTREG( FP_GEN_CNTL
, fp_gen_cntl
);
1317 OUTREG( FP2_GEN_CNTL
, fp2_gen_cntl
);
1319 OUTREG( CRTC_MORE_CNTL
, crtc_more_cntl
);
1324 #ifdef CONFIG_PPC_OF
1326 static void radeon_pm_reset_pad_ctlr_strength(struct radeonfb_info
*rinfo
)
1331 /* Reset the PAD_CTLR_STRENGTH & wait for it to be stable */
1332 INREG(PAD_CTLR_STRENGTH
);
1333 OUTREG(PAD_CTLR_STRENGTH
, INREG(PAD_CTLR_STRENGTH
) & ~PAD_MANUAL_OVERRIDE
);
1334 tmp
= INREG(PAD_CTLR_STRENGTH
);
1335 for (i
= j
= 0; i
< 65; ++i
) {
1337 tmp2
= INREG(PAD_CTLR_STRENGTH
);
1343 printk(KERN_WARNING
"radeon: PAD_CTLR_STRENGTH doesn't "
1351 static void radeon_pm_all_ppls_off(struct radeonfb_info
*rinfo
)
1355 tmp
= INPLL(pllPPLL_CNTL
);
1356 OUTPLL(pllPPLL_CNTL
, tmp
| 0x3);
1357 tmp
= INPLL(pllP2PLL_CNTL
);
1358 OUTPLL(pllP2PLL_CNTL
, tmp
| 0x3);
1359 tmp
= INPLL(pllSPLL_CNTL
);
1360 OUTPLL(pllSPLL_CNTL
, tmp
| 0x3);
1361 tmp
= INPLL(pllMPLL_CNTL
);
1362 OUTPLL(pllMPLL_CNTL
, tmp
| 0x3);
1365 static void radeon_pm_start_mclk_sclk(struct radeonfb_info
*rinfo
)
1369 /* Switch SPLL to PCI source */
1370 tmp
= INPLL(pllSCLK_CNTL
);
1371 OUTPLL(pllSCLK_CNTL
, tmp
& ~SCLK_CNTL__SCLK_SRC_SEL_MASK
);
1373 /* Reconfigure SPLL charge pump, VCO gain, duty cycle */
1374 tmp
= INPLL(pllSPLL_CNTL
);
1375 OUTREG8(CLOCK_CNTL_INDEX
, pllSPLL_CNTL
+ PLL_WR_EN
);
1376 radeon_pll_errata_after_index(rinfo
);
1377 OUTREG8(CLOCK_CNTL_DATA
+ 1, (tmp
>> 8) & 0xff);
1378 radeon_pll_errata_after_data(rinfo
);
1380 /* Set SPLL feedback divider */
1381 tmp
= INPLL(pllM_SPLL_REF_FB_DIV
);
1382 tmp
= (tmp
& 0xff00fffful
) | (rinfo
->save_regs
[77] & 0x00ff0000ul
);
1383 OUTPLL(pllM_SPLL_REF_FB_DIV
, tmp
);
1386 tmp
= INPLL(pllSPLL_CNTL
);
1387 OUTPLL(pllSPLL_CNTL
, tmp
& ~1);
1388 (void)INPLL(pllSPLL_CNTL
);
1392 /* Release SPLL reset */
1393 tmp
= INPLL(pllSPLL_CNTL
);
1394 OUTPLL(pllSPLL_CNTL
, tmp
& ~0x2);
1395 (void)INPLL(pllSPLL_CNTL
);
1399 /* Select SCLK source */
1400 tmp
= INPLL(pllSCLK_CNTL
);
1401 tmp
&= ~SCLK_CNTL__SCLK_SRC_SEL_MASK
;
1402 tmp
|= rinfo
->save_regs
[3] & SCLK_CNTL__SCLK_SRC_SEL_MASK
;
1403 OUTPLL(pllSCLK_CNTL
, tmp
);
1404 (void)INPLL(pllSCLK_CNTL
);
1408 /* Reconfigure MPLL charge pump, VCO gain, duty cycle */
1409 tmp
= INPLL(pllMPLL_CNTL
);
1410 OUTREG8(CLOCK_CNTL_INDEX
, pllMPLL_CNTL
+ PLL_WR_EN
);
1411 radeon_pll_errata_after_index(rinfo
);
1412 OUTREG8(CLOCK_CNTL_DATA
+ 1, (tmp
>> 8) & 0xff);
1413 radeon_pll_errata_after_data(rinfo
);
1415 /* Set MPLL feedback divider */
1416 tmp
= INPLL(pllM_SPLL_REF_FB_DIV
);
1417 tmp
= (tmp
& 0xffff00fful
) | (rinfo
->save_regs
[77] & 0x0000ff00ul
);
1419 OUTPLL(pllM_SPLL_REF_FB_DIV
, tmp
);
1421 tmp
= INPLL(pllMPLL_CNTL
);
1422 OUTPLL(pllMPLL_CNTL
, tmp
& ~0x2);
1423 (void)INPLL(pllMPLL_CNTL
);
1428 tmp
= INPLL(pllMPLL_CNTL
);
1429 OUTPLL(pllMPLL_CNTL
, tmp
& ~0x1);
1430 (void)INPLL(pllMPLL_CNTL
);
1434 /* Select source for MCLK */
1435 tmp
= INPLL(pllMCLK_CNTL
);
1436 tmp
|= rinfo
->save_regs
[2] & 0xffff;
1437 OUTPLL(pllMCLK_CNTL
, tmp
);
1438 (void)INPLL(pllMCLK_CNTL
);
1443 static void radeon_pm_m10_disable_spread_spectrum(struct radeonfb_info
*rinfo
)
1447 /* GACK ! I though we didn't have a DDA on Radeon's anymore
1448 * here we rewrite with the same value, ... I suppose we clear
1449 * some bits that are already clear ? Or maybe this 0x2ec
1450 * register is something new ?
1453 r2ec
= INREG(VGA_DDA_ON_OFF
);
1454 OUTREG(VGA_DDA_ON_OFF
, r2ec
);
1457 /* Spread spectrum PLLL off */
1458 OUTPLL(pllSSPLL_CNTL
, 0xbf03);
1460 /* Spread spectrum disabled */
1461 OUTPLL(pllSS_INT_CNTL
, rinfo
->save_regs
[90] & ~3);
1463 /* The trace shows read & rewrite of LVDS_PLL_CNTL here with same
1464 * value, not sure what for...
1468 OUTREG(VGA_DDA_ON_OFF
, r2ec
);
1472 static void radeon_pm_m10_enable_lvds_spread_spectrum(struct radeonfb_info
*rinfo
)
1476 /* GACK (bis) ! I though we didn't have a DDA on Radeon's anymore
1477 * here we rewrite with the same value, ... I suppose we clear/set
1478 * some bits that are already clear/set ?
1480 r2ec
= INREG(VGA_DDA_ON_OFF
);
1481 OUTREG(VGA_DDA_ON_OFF
, r2ec
);
1484 /* Enable spread spectrum */
1485 OUTPLL(pllSSPLL_CNTL
, rinfo
->save_regs
[43] | 3);
1488 OUTPLL(pllSSPLL_REF_DIV
, rinfo
->save_regs
[44]);
1489 OUTPLL(pllSSPLL_DIV_0
, rinfo
->save_regs
[45]);
1490 tmp
= INPLL(pllSSPLL_CNTL
);
1491 OUTPLL(pllSSPLL_CNTL
, tmp
& ~0x2);
1493 tmp
= INPLL(pllSSPLL_CNTL
);
1494 OUTPLL(pllSSPLL_CNTL
, tmp
& ~0x1);
1497 OUTPLL(pllSS_INT_CNTL
, rinfo
->save_regs
[90]);
1500 OUTREG(VGA_DDA_ON_OFF
, r2ec
);
1503 /* Enable LVDS interface */
1504 tmp
= INREG(LVDS_GEN_CNTL
);
1505 OUTREG(LVDS_GEN_CNTL
, tmp
| LVDS_EN
);
1507 /* Enable LVDS_PLL */
1508 tmp
= INREG(LVDS_PLL_CNTL
);
1511 OUTREG(LVDS_PLL_CNTL
, tmp
);
1513 OUTPLL(pllSCLK_MORE_CNTL
, rinfo
->save_regs
[34]);
1514 OUTPLL(pllSS_TST_CNTL
, rinfo
->save_regs
[91]);
1516 /* The trace reads that one here, waiting for something to settle down ? */
1519 /* Ugh ? SS_TST_DEC is supposed to be a read register in the
1520 * R300 register spec at least...
1522 tmp
= INPLL(pllSS_TST_CNTL
);
1524 OUTPLL(pllSS_TST_CNTL
, tmp
);
1527 static void radeon_pm_restore_pixel_pll(struct radeonfb_info
*rinfo
)
1531 OUTREG8(CLOCK_CNTL_INDEX
, pllHTOTAL_CNTL
+ PLL_WR_EN
);
1532 radeon_pll_errata_after_index(rinfo
);
1533 OUTREG8(CLOCK_CNTL_DATA
, 0);
1534 radeon_pll_errata_after_data(rinfo
);
1536 tmp
= INPLL(pllVCLK_ECP_CNTL
);
1537 OUTPLL(pllVCLK_ECP_CNTL
, tmp
| 0x80);
1540 tmp
= INPLL(pllPPLL_REF_DIV
);
1541 tmp
= (tmp
& ~PPLL_REF_DIV_MASK
) | rinfo
->pll
.ref_div
;
1542 OUTPLL(pllPPLL_REF_DIV
, tmp
);
1543 INPLL(pllPPLL_REF_DIV
);
1545 /* Reconfigure SPLL charge pump, VCO gain, duty cycle,
1546 * probably useless since we already did it ...
1548 tmp
= INPLL(pllPPLL_CNTL
);
1549 OUTREG8(CLOCK_CNTL_INDEX
, pllSPLL_CNTL
+ PLL_WR_EN
);
1550 radeon_pll_errata_after_index(rinfo
);
1551 OUTREG8(CLOCK_CNTL_DATA
+ 1, (tmp
>> 8) & 0xff);
1552 radeon_pll_errata_after_data(rinfo
);
1554 /* Restore our "reference" PPLL divider set by firmware
1555 * according to proper spread spectrum calculations
1557 OUTPLL(pllPPLL_DIV_0
, rinfo
->save_regs
[92]);
1559 tmp
= INPLL(pllPPLL_CNTL
);
1560 OUTPLL(pllPPLL_CNTL
, tmp
& ~0x2);
1563 tmp
= INPLL(pllPPLL_CNTL
);
1564 OUTPLL(pllPPLL_CNTL
, tmp
& ~0x1);
1567 tmp
= INPLL(pllVCLK_ECP_CNTL
);
1568 OUTPLL(pllVCLK_ECP_CNTL
, tmp
| 3);
1571 tmp
= INPLL(pllVCLK_ECP_CNTL
);
1572 OUTPLL(pllVCLK_ECP_CNTL
, tmp
| 3);
1575 /* Switch pixel clock to firmware default div 0 */
1576 OUTREG8(CLOCK_CNTL_INDEX
+1, 0);
1577 radeon_pll_errata_after_index(rinfo
);
1578 radeon_pll_errata_after_data(rinfo
);
1581 static void radeon_pm_m10_reconfigure_mc(struct radeonfb_info
*rinfo
)
1583 OUTREG(MC_CNTL
, rinfo
->save_regs
[46]);
1584 OUTREG(MC_INIT_GFX_LAT_TIMER
, rinfo
->save_regs
[47]);
1585 OUTREG(MC_INIT_MISC_LAT_TIMER
, rinfo
->save_regs
[48]);
1586 OUTREG(MEM_SDRAM_MODE_REG
,
1587 rinfo
->save_regs
[35] & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE
);
1588 OUTREG(MC_TIMING_CNTL
, rinfo
->save_regs
[49]);
1589 OUTREG(MEM_REFRESH_CNTL
, rinfo
->save_regs
[42]);
1590 OUTREG(MC_READ_CNTL_AB
, rinfo
->save_regs
[50]);
1591 OUTREG(MC_CHIP_IO_OE_CNTL_AB
, rinfo
->save_regs
[52]);
1592 OUTREG(MC_IOPAD_CNTL
, rinfo
->save_regs
[51]);
1593 OUTREG(MC_DEBUG
, rinfo
->save_regs
[53]);
1595 OUTMC(rinfo
, ixR300_MC_MC_INIT_WR_LAT_TIMER
, rinfo
->save_regs
[58]);
1596 OUTMC(rinfo
, ixR300_MC_IMP_CNTL
, rinfo
->save_regs
[59]);
1597 OUTMC(rinfo
, ixR300_MC_CHP_IO_CNTL_C0
, rinfo
->save_regs
[60]);
1598 OUTMC(rinfo
, ixR300_MC_CHP_IO_CNTL_C1
, rinfo
->save_regs
[61]);
1599 OUTMC(rinfo
, ixR300_MC_CHP_IO_CNTL_D0
, rinfo
->save_regs
[62]);
1600 OUTMC(rinfo
, ixR300_MC_CHP_IO_CNTL_D1
, rinfo
->save_regs
[63]);
1601 OUTMC(rinfo
, ixR300_MC_BIST_CNTL_3
, rinfo
->save_regs
[64]);
1602 OUTMC(rinfo
, ixR300_MC_CHP_IO_CNTL_A0
, rinfo
->save_regs
[65]);
1603 OUTMC(rinfo
, ixR300_MC_CHP_IO_CNTL_A1
, rinfo
->save_regs
[66]);
1604 OUTMC(rinfo
, ixR300_MC_CHP_IO_CNTL_B0
, rinfo
->save_regs
[67]);
1605 OUTMC(rinfo
, ixR300_MC_CHP_IO_CNTL_B1
, rinfo
->save_regs
[68]);
1606 OUTMC(rinfo
, ixR300_MC_DEBUG_CNTL
, rinfo
->save_regs
[69]);
1607 OUTMC(rinfo
, ixR300_MC_DLL_CNTL
, rinfo
->save_regs
[70]);
1608 OUTMC(rinfo
, ixR300_MC_IMP_CNTL_0
, rinfo
->save_regs
[71]);
1609 OUTMC(rinfo
, ixR300_MC_ELPIDA_CNTL
, rinfo
->save_regs
[72]);
1610 OUTMC(rinfo
, ixR300_MC_READ_CNTL_CD
, rinfo
->save_regs
[96]);
1611 OUTREG(MC_IND_INDEX
, 0);
1614 static void radeon_reinitialize_M10(struct radeonfb_info
*rinfo
)
1618 /* Restore a bunch of registers first */
1619 OUTREG(MC_AGP_LOCATION
, rinfo
->save_regs
[32]);
1620 OUTREG(DISPLAY_BASE_ADDR
, rinfo
->save_regs
[31]);
1621 OUTREG(CRTC2_DISPLAY_BASE_ADDR
, rinfo
->save_regs
[33]);
1622 OUTREG(MC_FB_LOCATION
, rinfo
->save_regs
[30]);
1623 OUTREG(OV0_BASE_ADDR
, rinfo
->save_regs
[80]);
1624 OUTREG(CONFIG_MEMSIZE
, rinfo
->video_ram
);
1625 OUTREG(BUS_CNTL
, rinfo
->save_regs
[36]);
1626 OUTREG(BUS_CNTL1
, rinfo
->save_regs
[14]);
1627 OUTREG(MPP_TB_CONFIG
, rinfo
->save_regs
[37]);
1628 OUTREG(FCP_CNTL
, rinfo
->save_regs
[38]);
1629 OUTREG(RBBM_CNTL
, rinfo
->save_regs
[39]);
1630 OUTREG(DAC_CNTL
, rinfo
->save_regs
[40]);
1631 OUTREG(DAC_MACRO_CNTL
, (INREG(DAC_MACRO_CNTL
) & ~0x6) | 8);
1632 OUTREG(DAC_MACRO_CNTL
, (INREG(DAC_MACRO_CNTL
) & ~0x6) | 8);
1635 OUTREG(DAC_CNTL2
, INREG(DAC_CNTL2
) | DAC2_EXPAND_MODE
);
1637 /* Reset the PAD CTLR */
1638 radeon_pm_reset_pad_ctlr_strength(rinfo
);
1640 /* Some PLLs are Read & written identically in the trace here...
1641 * I suppose it's actually to switch them all off & reset,
1642 * let's assume off is what we want. I'm just doing that for all major PLLs now.
1644 radeon_pm_all_ppls_off(rinfo
);
1646 /* Clear tiling, reset swappers */
1647 INREG(SURFACE_CNTL
);
1648 OUTREG(SURFACE_CNTL
, 0);
1650 /* Some black magic with TV_DAC_CNTL, we should restore those from backups
1651 * rather than hard coding...
1653 tmp
= INREG(TV_DAC_CNTL
) & ~TV_DAC_CNTL_BGADJ_MASK
;
1654 tmp
|= 8 << TV_DAC_CNTL_BGADJ__SHIFT
;
1655 OUTREG(TV_DAC_CNTL
, tmp
);
1657 tmp
= INREG(TV_DAC_CNTL
) & ~TV_DAC_CNTL_DACADJ_MASK
;
1658 tmp
|= 7 << TV_DAC_CNTL_DACADJ__SHIFT
;
1659 OUTREG(TV_DAC_CNTL
, tmp
);
1661 /* More registers restored */
1662 OUTREG(AGP_CNTL
, rinfo
->save_regs
[16]);
1663 OUTREG(HOST_PATH_CNTL
, rinfo
->save_regs
[41]);
1664 OUTREG(DISP_MISC_CNTL
, rinfo
->save_regs
[9]);
1666 /* Hrmmm ... What is that ? */
1667 tmp
= rinfo
->save_regs
[1]
1668 & ~(CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK
|
1669 CLK_PWRMGT_CNTL__MC_BUSY
);
1670 OUTPLL(pllCLK_PWRMGT_CNTL
, tmp
);
1672 OUTREG(PAD_CTLR_MISC
, rinfo
->save_regs
[56]);
1673 OUTREG(FW_CNTL
, rinfo
->save_regs
[57]);
1674 OUTREG(HDP_DEBUG
, rinfo
->save_regs
[96]);
1675 OUTREG(PAMAC0_DLY_CNTL
, rinfo
->save_regs
[54]);
1676 OUTREG(PAMAC1_DLY_CNTL
, rinfo
->save_regs
[55]);
1677 OUTREG(PAMAC2_DLY_CNTL
, rinfo
->save_regs
[79]);
1679 /* Restore Memory Controller configuration */
1680 radeon_pm_m10_reconfigure_mc(rinfo
);
1682 /* Make sure CRTC's dont touch memory */
1683 OUTREG(CRTC_GEN_CNTL
, INREG(CRTC_GEN_CNTL
)
1684 | CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B
);
1685 OUTREG(CRTC2_GEN_CNTL
, INREG(CRTC2_GEN_CNTL
)
1686 | CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B
);
1689 /* Disable SDRAM refresh */
1690 OUTREG(MEM_REFRESH_CNTL
, INREG(MEM_REFRESH_CNTL
)
1691 | MEM_REFRESH_CNTL__MEM_REFRESH_DIS
);
1693 /* Restore XTALIN routing (CLK_PIN_CNTL) */
1694 OUTPLL(pllCLK_PIN_CNTL
, rinfo
->save_regs
[4]);
1696 /* Switch MCLK, YCLK and SCLK PLLs to PCI source & force them ON */
1697 tmp
= rinfo
->save_regs
[2] & 0xff000000;
1698 tmp
|= MCLK_CNTL__FORCE_MCLKA
|
1699 MCLK_CNTL__FORCE_MCLKB
|
1700 MCLK_CNTL__FORCE_YCLKA
|
1701 MCLK_CNTL__FORCE_YCLKB
|
1702 MCLK_CNTL__FORCE_MC
;
1703 OUTPLL(pllMCLK_CNTL
, tmp
);
1705 /* Force all clocks on in SCLK */
1706 tmp
= INPLL(pllSCLK_CNTL
);
1707 tmp
|= SCLK_CNTL__FORCE_DISP2
|
1708 SCLK_CNTL__FORCE_CP
|
1709 SCLK_CNTL__FORCE_HDP
|
1710 SCLK_CNTL__FORCE_DISP1
|
1711 SCLK_CNTL__FORCE_TOP
|
1712 SCLK_CNTL__FORCE_E2
|
1713 SCLK_CNTL__FORCE_SE
|
1714 SCLK_CNTL__FORCE_IDCT
|
1715 SCLK_CNTL__FORCE_VIP
|
1716 SCLK_CNTL__FORCE_PB
|
1717 SCLK_CNTL__FORCE_TAM
|
1718 SCLK_CNTL__FORCE_TDM
|
1719 SCLK_CNTL__FORCE_RB
|
1720 SCLK_CNTL__FORCE_TV_SCLK
|
1721 SCLK_CNTL__FORCE_SUBPIC
|
1722 SCLK_CNTL__FORCE_OV0
;
1723 tmp
|= SCLK_CNTL__CP_MAX_DYN_STOP_LAT
|
1724 SCLK_CNTL__HDP_MAX_DYN_STOP_LAT
|
1725 SCLK_CNTL__TV_MAX_DYN_STOP_LAT
|
1726 SCLK_CNTL__E2_MAX_DYN_STOP_LAT
|
1727 SCLK_CNTL__SE_MAX_DYN_STOP_LAT
|
1728 SCLK_CNTL__IDCT_MAX_DYN_STOP_LAT
|
1729 SCLK_CNTL__VIP_MAX_DYN_STOP_LAT
|
1730 SCLK_CNTL__RE_MAX_DYN_STOP_LAT
|
1731 SCLK_CNTL__PB_MAX_DYN_STOP_LAT
|
1732 SCLK_CNTL__TAM_MAX_DYN_STOP_LAT
|
1733 SCLK_CNTL__TDM_MAX_DYN_STOP_LAT
|
1734 SCLK_CNTL__RB_MAX_DYN_STOP_LAT
;
1735 OUTPLL(pllSCLK_CNTL
, tmp
);
1737 OUTPLL(pllVCLK_ECP_CNTL
, 0);
1738 OUTPLL(pllPIXCLKS_CNTL
, 0);
1739 OUTPLL(pllMCLK_MISC
,
1740 MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT
|
1741 MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT
);
1745 /* Restore the M_SPLL_REF_FB_DIV, MPLL_AUX_CNTL and SPLL_AUX_CNTL values */
1746 OUTPLL(pllM_SPLL_REF_FB_DIV
, rinfo
->save_regs
[77]);
1747 OUTPLL(pllMPLL_AUX_CNTL
, rinfo
->save_regs
[75]);
1748 OUTPLL(pllSPLL_AUX_CNTL
, rinfo
->save_regs
[76]);
1750 /* Now restore the major PLLs settings, keeping them off & reset though */
1751 OUTPLL(pllPPLL_CNTL
, rinfo
->save_regs
[93] | 0x3);
1752 OUTPLL(pllP2PLL_CNTL
, rinfo
->save_regs
[8] | 0x3);
1753 OUTPLL(pllMPLL_CNTL
, rinfo
->save_regs
[73] | 0x03);
1754 OUTPLL(pllSPLL_CNTL
, rinfo
->save_regs
[74] | 0x03);
1756 /* Restore MC DLL state and switch it off/reset too */
1757 OUTMC(rinfo
, ixR300_MC_DLL_CNTL
, rinfo
->save_regs
[70]);
1759 /* Switch MDLL off & reset */
1760 OUTPLL(pllMDLL_RDCKA
, rinfo
->save_regs
[98] | 0xff);
1763 /* Setup some black magic bits in PLL_PWRMGT_CNTL. Hrm... we saved
1764 * 0xa1100007... and MacOS writes 0xa1000007 ..
1766 OUTPLL(pllPLL_PWRMGT_CNTL
, rinfo
->save_regs
[0]);
1768 /* Restore more stuffs */
1769 OUTPLL(pllHTOTAL_CNTL
, 0);
1770 OUTPLL(pllHTOTAL2_CNTL
, 0);
1772 /* More PLL initial configuration */
1773 tmp
= INPLL(pllSCLK_CNTL2
); /* What for ? */
1774 OUTPLL(pllSCLK_CNTL2
, tmp
);
1776 tmp
= INPLL(pllSCLK_MORE_CNTL
);
1777 tmp
|= SCLK_MORE_CNTL__FORCE_DISPREGS
| /* a guess */
1778 SCLK_MORE_CNTL__FORCE_MC_GUI
|
1779 SCLK_MORE_CNTL__FORCE_MC_HOST
;
1780 OUTPLL(pllSCLK_MORE_CNTL
, tmp
);
1782 /* Now we actually start MCLK and SCLK */
1783 radeon_pm_start_mclk_sclk(rinfo
);
1785 /* Full reset sdrams, this also re-inits the MDLL */
1786 radeon_pm_full_reset_sdram(rinfo
);
1789 OUTREG(DAC_CNTL2
, INREG(DAC_CNTL2
) | 0x20);
1790 for (i
=0; i
<256; i
++)
1791 OUTREG(PALETTE_30_DATA
, 0x15555555);
1792 OUTREG(DAC_CNTL2
, INREG(DAC_CNTL2
) & ~20);
1794 for (i
=0; i
<256; i
++)
1795 OUTREG(PALETTE_30_DATA
, 0x15555555);
1797 OUTREG(DAC_CNTL2
, INREG(DAC_CNTL2
) & ~0x20);
1801 OUTREG(FP_GEN_CNTL
, rinfo
->save_regs
[82]);
1802 OUTREG(FP2_GEN_CNTL
, rinfo
->save_regs
[83]);
1804 /* Set LVDS registers but keep interface & pll down */
1805 OUTREG(LVDS_GEN_CNTL
, rinfo
->save_regs
[11] &
1806 ~(LVDS_EN
| LVDS_ON
| LVDS_DIGON
| LVDS_BLON
| LVDS_BL_MOD_EN
));
1807 OUTREG(LVDS_PLL_CNTL
, (rinfo
->save_regs
[12] & ~0xf0000) | 0x20000);
1809 OUTREG(DISP_OUTPUT_CNTL
, rinfo
->save_regs
[86]);
1811 /* Restore GPIOPAD state */
1812 OUTREG(GPIOPAD_A
, rinfo
->save_regs
[19]);
1813 OUTREG(GPIOPAD_EN
, rinfo
->save_regs
[20]);
1814 OUTREG(GPIOPAD_MASK
, rinfo
->save_regs
[21]);
1816 /* write some stuff to the framebuffer... */
1817 for (i
= 0; i
< 0x8000; ++i
)
1818 writeb(0, rinfo
->fb_base
+ i
);
1821 OUTREG(LVDS_GEN_CNTL
, INREG(LVDS_GEN_CNTL
) | LVDS_DIGON
| LVDS_ON
);
1824 /* Restore a few more things */
1825 OUTREG(GRPH_BUFFER_CNTL
, rinfo
->save_regs
[94]);
1826 OUTREG(GRPH2_BUFFER_CNTL
, rinfo
->save_regs
[95]);
1828 /* Take care of spread spectrum & PPLLs now */
1829 radeon_pm_m10_disable_spread_spectrum(rinfo
);
1830 radeon_pm_restore_pixel_pll(rinfo
);
1832 /* GRRRR... I can't figure out the proper LVDS power sequence, and the
1833 * code I have for blank/unblank doesn't quite work on some laptop models
1834 * it seems ... Hrm. What I have here works most of the time ...
1836 radeon_pm_m10_enable_lvds_spread_spectrum(rinfo
);
1839 static void radeon_pm_m9p_reconfigure_mc(struct radeonfb_info
*rinfo
)
1841 OUTREG(MC_CNTL
, rinfo
->save_regs
[46]);
1842 OUTREG(MC_INIT_GFX_LAT_TIMER
, rinfo
->save_regs
[47]);
1843 OUTREG(MC_INIT_MISC_LAT_TIMER
, rinfo
->save_regs
[48]);
1844 OUTREG(MEM_SDRAM_MODE_REG
,
1845 rinfo
->save_regs
[35] & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE
);
1846 OUTREG(MC_TIMING_CNTL
, rinfo
->save_regs
[49]);
1847 OUTREG(MC_READ_CNTL_AB
, rinfo
->save_regs
[50]);
1848 OUTREG(MEM_REFRESH_CNTL
, rinfo
->save_regs
[42]);
1849 OUTREG(MC_IOPAD_CNTL
, rinfo
->save_regs
[51]);
1850 OUTREG(MC_DEBUG
, rinfo
->save_regs
[53]);
1851 OUTREG(MC_CHIP_IO_OE_CNTL_AB
, rinfo
->save_regs
[52]);
1853 OUTMC(rinfo
, ixMC_IMP_CNTL
, rinfo
->save_regs
[59] /*0x00f460d6*/);
1854 OUTMC(rinfo
, ixMC_CHP_IO_CNTL_A0
, rinfo
->save_regs
[65] /*0xfecfa666*/);
1855 OUTMC(rinfo
, ixMC_CHP_IO_CNTL_A1
, rinfo
->save_regs
[66] /*0x141555ff*/);
1856 OUTMC(rinfo
, ixMC_CHP_IO_CNTL_B0
, rinfo
->save_regs
[67] /*0xfecfa666*/);
1857 OUTMC(rinfo
, ixMC_CHP_IO_CNTL_B1
, rinfo
->save_regs
[68] /*0x141555ff*/);
1858 OUTMC(rinfo
, ixMC_IMP_CNTL_0
, rinfo
->save_regs
[71] /*0x00009249*/);
1859 OUTREG(MC_IND_INDEX
, 0);
1860 OUTREG(CONFIG_MEMSIZE
, rinfo
->video_ram
);
1865 static void radeon_reinitialize_M9P(struct radeonfb_info
*rinfo
)
1869 /* Restore a bunch of registers first */
1870 OUTREG(SURFACE_CNTL
, rinfo
->save_regs
[29]);
1871 OUTREG(MC_AGP_LOCATION
, rinfo
->save_regs
[32]);
1872 OUTREG(DISPLAY_BASE_ADDR
, rinfo
->save_regs
[31]);
1873 OUTREG(CRTC2_DISPLAY_BASE_ADDR
, rinfo
->save_regs
[33]);
1874 OUTREG(MC_FB_LOCATION
, rinfo
->save_regs
[30]);
1875 OUTREG(OV0_BASE_ADDR
, rinfo
->save_regs
[80]);
1876 OUTREG(BUS_CNTL
, rinfo
->save_regs
[36]);
1877 OUTREG(BUS_CNTL1
, rinfo
->save_regs
[14]);
1878 OUTREG(MPP_TB_CONFIG
, rinfo
->save_regs
[37]);
1879 OUTREG(FCP_CNTL
, rinfo
->save_regs
[38]);
1880 OUTREG(RBBM_CNTL
, rinfo
->save_regs
[39]);
1882 OUTREG(DAC_CNTL
, rinfo
->save_regs
[40]);
1883 OUTREG(DAC_CNTL2
, INREG(DAC_CNTL2
) | DAC2_EXPAND_MODE
);
1885 /* Reset the PAD CTLR */
1886 radeon_pm_reset_pad_ctlr_strength(rinfo
);
1888 /* Some PLLs are Read & written identically in the trace here...
1889 * I suppose it's actually to switch them all off & reset,
1890 * let's assume off is what we want. I'm just doing that for all major PLLs now.
1892 radeon_pm_all_ppls_off(rinfo
);
1894 /* Clear tiling, reset swappers */
1895 INREG(SURFACE_CNTL
);
1896 OUTREG(SURFACE_CNTL
, 0);
1898 /* Some black magic with TV_DAC_CNTL, we should restore those from backups
1899 * rather than hard coding...
1901 tmp
= INREG(TV_DAC_CNTL
) & ~TV_DAC_CNTL_BGADJ_MASK
;
1902 tmp
|= 6 << TV_DAC_CNTL_BGADJ__SHIFT
;
1903 OUTREG(TV_DAC_CNTL
, tmp
);
1905 tmp
= INREG(TV_DAC_CNTL
) & ~TV_DAC_CNTL_DACADJ_MASK
;
1906 tmp
|= 6 << TV_DAC_CNTL_DACADJ__SHIFT
;
1907 OUTREG(TV_DAC_CNTL
, tmp
);
1909 OUTPLL(pllAGP_PLL_CNTL
, rinfo
->save_regs
[78]);
1911 OUTREG(PAMAC0_DLY_CNTL
, rinfo
->save_regs
[54]);
1912 OUTREG(PAMAC1_DLY_CNTL
, rinfo
->save_regs
[55]);
1913 OUTREG(PAMAC2_DLY_CNTL
, rinfo
->save_regs
[79]);
1915 OUTREG(AGP_CNTL
, rinfo
->save_regs
[16]);
1916 OUTREG(HOST_PATH_CNTL
, rinfo
->save_regs
[41]); /* MacOS sets that to 0 !!! */
1917 OUTREG(DISP_MISC_CNTL
, rinfo
->save_regs
[9]);
1919 tmp
= rinfo
->save_regs
[1]
1920 & ~(CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK
|
1921 CLK_PWRMGT_CNTL__MC_BUSY
);
1922 OUTPLL(pllCLK_PWRMGT_CNTL
, tmp
);
1924 OUTREG(FW_CNTL
, rinfo
->save_regs
[57]);
1926 /* Disable SDRAM refresh */
1927 OUTREG(MEM_REFRESH_CNTL
, INREG(MEM_REFRESH_CNTL
)
1928 | MEM_REFRESH_CNTL__MEM_REFRESH_DIS
);
1930 /* Restore XTALIN routing (CLK_PIN_CNTL) */
1931 OUTPLL(pllCLK_PIN_CNTL
, rinfo
->save_regs
[4]);
1933 /* Force MCLK to be PCI sourced and forced ON */
1934 tmp
= rinfo
->save_regs
[2] & 0xff000000;
1935 tmp
|= MCLK_CNTL__FORCE_MCLKA
|
1936 MCLK_CNTL__FORCE_MCLKB
|
1937 MCLK_CNTL__FORCE_YCLKA
|
1938 MCLK_CNTL__FORCE_YCLKB
|
1939 MCLK_CNTL__FORCE_MC
|
1940 MCLK_CNTL__FORCE_AIC
;
1941 OUTPLL(pllMCLK_CNTL
, tmp
);
1943 /* Force SCLK to be PCI sourced with a bunch forced */
1945 SCLK_CNTL__FORCE_DISP2
|
1946 SCLK_CNTL__FORCE_CP
|
1947 SCLK_CNTL__FORCE_HDP
|
1948 SCLK_CNTL__FORCE_DISP1
|
1949 SCLK_CNTL__FORCE_TOP
|
1950 SCLK_CNTL__FORCE_E2
|
1951 SCLK_CNTL__FORCE_SE
|
1952 SCLK_CNTL__FORCE_IDCT
|
1953 SCLK_CNTL__FORCE_VIP
|
1954 SCLK_CNTL__FORCE_RE
|
1955 SCLK_CNTL__FORCE_PB
|
1956 SCLK_CNTL__FORCE_TAM
|
1957 SCLK_CNTL__FORCE_TDM
|
1958 SCLK_CNTL__FORCE_RB
;
1959 OUTPLL(pllSCLK_CNTL
, tmp
);
1961 /* Clear VCLK_ECP_CNTL & PIXCLKS_CNTL */
1962 OUTPLL(pllVCLK_ECP_CNTL
, 0);
1963 OUTPLL(pllPIXCLKS_CNTL
, 0);
1965 /* Setup MCLK_MISC, non dynamic mode */
1966 OUTPLL(pllMCLK_MISC
,
1967 MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT
|
1968 MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT
);
1972 /* Set back the default clock dividers */
1973 OUTPLL(pllM_SPLL_REF_FB_DIV
, rinfo
->save_regs
[77]);
1974 OUTPLL(pllMPLL_AUX_CNTL
, rinfo
->save_regs
[75]);
1975 OUTPLL(pllSPLL_AUX_CNTL
, rinfo
->save_regs
[76]);
1977 /* PPLL and P2PLL default values & off */
1978 OUTPLL(pllPPLL_CNTL
, rinfo
->save_regs
[93] | 0x3);
1979 OUTPLL(pllP2PLL_CNTL
, rinfo
->save_regs
[8] | 0x3);
1981 /* S and M PLLs are reset & off, configure them */
1982 OUTPLL(pllMPLL_CNTL
, rinfo
->save_regs
[73] | 0x03);
1983 OUTPLL(pllSPLL_CNTL
, rinfo
->save_regs
[74] | 0x03);
1985 /* Default values for MDLL ... fixme */
1986 OUTPLL(pllMDLL_CKO
, 0x9c009c);
1987 OUTPLL(pllMDLL_RDCKA
, 0x08830883);
1988 OUTPLL(pllMDLL_RDCKB
, 0x08830883);
1991 /* Restore PLL_PWRMGT_CNTL */ // XXXX
1992 tmp
= rinfo
->save_regs
[0];
1993 tmp
&= ~PLL_PWRMGT_CNTL_SU_SCLK_USE_BCLK
;
1994 tmp
|= PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK
;
1995 OUTPLL(PLL_PWRMGT_CNTL
, tmp
);
1997 /* Clear HTOTAL_CNTL & HTOTAL2_CNTL */
1998 OUTPLL(pllHTOTAL_CNTL
, 0);
1999 OUTPLL(pllHTOTAL2_CNTL
, 0);
2001 /* All outputs off */
2002 OUTREG(CRTC_GEN_CNTL
, 0x04000000);
2003 OUTREG(CRTC2_GEN_CNTL
, 0x04000000);
2004 OUTREG(FP_GEN_CNTL
, 0x00004008);
2005 OUTREG(FP2_GEN_CNTL
, 0x00000008);
2006 OUTREG(LVDS_GEN_CNTL
, 0x08000008);
2008 /* Restore Memory Controller configuration */
2009 radeon_pm_m9p_reconfigure_mc(rinfo
);
2011 /* Now we actually start MCLK and SCLK */
2012 radeon_pm_start_mclk_sclk(rinfo
);
2014 /* Full reset sdrams, this also re-inits the MDLL */
2015 radeon_pm_full_reset_sdram(rinfo
);
2018 OUTREG(DAC_CNTL2
, INREG(DAC_CNTL2
) | 0x20);
2019 for (i
=0; i
<256; i
++)
2020 OUTREG(PALETTE_30_DATA
, 0x15555555);
2021 OUTREG(DAC_CNTL2
, INREG(DAC_CNTL2
) & ~20);
2023 for (i
=0; i
<256; i
++)
2024 OUTREG(PALETTE_30_DATA
, 0x15555555);
2026 OUTREG(DAC_CNTL2
, INREG(DAC_CNTL2
) & ~0x20);
2029 /* Restore TV stuff, make sure TV DAC is down */
2030 OUTREG(TV_MASTER_CNTL
, rinfo
->save_regs
[88]);
2031 OUTREG(TV_DAC_CNTL
, rinfo
->save_regs
[13] | 0x07000000);
2033 /* Restore GPIOS. MacOS does some magic here with one of the GPIO bits,
2034 * possibly related to the weird PLL related workarounds and to the
2035 * fact that CLK_PIN_CNTL is tweaked in ways I don't fully understand,
2036 * but we keep things the simple way here
2038 OUTREG(GPIOPAD_A
, rinfo
->save_regs
[19]);
2039 OUTREG(GPIOPAD_EN
, rinfo
->save_regs
[20]);
2040 OUTREG(GPIOPAD_MASK
, rinfo
->save_regs
[21]);
2042 /* Now do things with SCLK_MORE_CNTL. Force bits are already set, copy
2043 * high bits from backup
2045 tmp
= INPLL(pllSCLK_MORE_CNTL
) & 0x0000ffff;
2046 tmp
|= rinfo
->save_regs
[34] & 0xffff0000;
2047 tmp
|= SCLK_MORE_CNTL__FORCE_DISPREGS
;
2048 OUTPLL(pllSCLK_MORE_CNTL
, tmp
);
2050 tmp
= INPLL(pllSCLK_MORE_CNTL
) & 0x0000ffff;
2051 tmp
|= rinfo
->save_regs
[34] & 0xffff0000;
2052 tmp
|= SCLK_MORE_CNTL__FORCE_DISPREGS
;
2053 OUTPLL(pllSCLK_MORE_CNTL
, tmp
);
2055 OUTREG(LVDS_GEN_CNTL
, rinfo
->save_regs
[11] &
2056 ~(LVDS_EN
| LVDS_ON
| LVDS_DIGON
| LVDS_BLON
| LVDS_BL_MOD_EN
));
2057 OUTREG(LVDS_GEN_CNTL
, INREG(LVDS_GEN_CNTL
) | LVDS_BLON
);
2058 OUTREG(LVDS_PLL_CNTL
, (rinfo
->save_regs
[12] & ~0xf0000) | 0x20000);
2061 /* write some stuff to the framebuffer... */
2062 for (i
= 0; i
< 0x8000; ++i
)
2063 writeb(0, rinfo
->fb_base
+ i
);
2065 OUTREG(0x2ec, 0x6332a020);
2066 OUTPLL(pllSSPLL_REF_DIV
, rinfo
->save_regs
[44] /*0x3f */);
2067 OUTPLL(pllSSPLL_DIV_0
, rinfo
->save_regs
[45] /*0x000081bb */);
2068 tmp
= INPLL(pllSSPLL_CNTL
);
2070 OUTPLL(pllSSPLL_CNTL
, tmp
);
2073 OUTPLL(pllSSPLL_CNTL
, tmp
);
2076 OUTPLL(pllSSPLL_CNTL
, tmp
);
2079 OUTPLL(pllSS_INT_CNTL
, rinfo
->save_regs
[90] & ~3);/*0x0020300c*/
2080 OUTREG(0x2ec, 0x6332a3f0);
2083 OUTPLL(pllPPLL_REF_DIV
, rinfo
->pll
.ref_div
);;
2084 OUTPLL(pllPPLL_DIV_0
, rinfo
->save_regs
[92]);
2087 OUTREG(LVDS_GEN_CNTL
, INREG(LVDS_GEN_CNTL
) | LVDS_DIGON
| LVDS_ON
);
2090 /* Restore a few more things */
2091 OUTREG(GRPH_BUFFER_CNTL
, rinfo
->save_regs
[94]);
2092 OUTREG(GRPH2_BUFFER_CNTL
, rinfo
->save_regs
[95]);
2094 /* Restore PPLL, spread spectrum & LVDS */
2095 radeon_pm_m10_disable_spread_spectrum(rinfo
);
2096 radeon_pm_restore_pixel_pll(rinfo
);
2097 radeon_pm_m10_enable_lvds_spread_spectrum(rinfo
);
2100 #if 0 /* Not ready yet */
2101 static void radeon_reinitialize_QW(struct radeonfb_info
*rinfo
)
2108 OUTREG(MC_AGP_LOCATION
, rinfo
->save_regs
[32]);
2109 OUTREG(DISPLAY_BASE_ADDR
, rinfo
->save_regs
[31]);
2110 OUTREG(CRTC2_DISPLAY_BASE_ADDR
, rinfo
->save_regs
[33]);
2111 OUTREG(MC_FB_LOCATION
, rinfo
->save_regs
[30]);
2112 OUTREG(BUS_CNTL
, rinfo
->save_regs
[36]);
2113 OUTREG(RBBM_CNTL
, rinfo
->save_regs
[39]);
2115 INREG(PAD_CTLR_STRENGTH
);
2116 OUTREG(PAD_CTLR_STRENGTH
, INREG(PAD_CTLR_STRENGTH
) & ~0x10000);
2117 for (i
= 0; i
< 65; ++i
) {
2119 INREG(PAD_CTLR_STRENGTH
);
2122 OUTREG(DISP_TEST_DEBUG_CNTL
, INREG(DISP_TEST_DEBUG_CNTL
) | 0x10000000);
2123 OUTREG(OV0_FLAG_CNTRL
, INREG(OV0_FLAG_CNTRL
) | 0x100);
2124 OUTREG(CRTC_GEN_CNTL
, INREG(CRTC_GEN_CNTL
));
2125 OUTREG(DAC_CNTL
, 0xff00410a);
2126 OUTREG(CRTC2_GEN_CNTL
, INREG(CRTC2_GEN_CNTL
));
2127 OUTREG(DAC_CNTL2
, INREG(DAC_CNTL2
) | 0x4000);
2129 OUTREG(SURFACE_CNTL
, rinfo
->save_regs
[29]);
2130 OUTREG(AGP_CNTL
, rinfo
->save_regs
[16]);
2131 OUTREG(HOST_PATH_CNTL
, rinfo
->save_regs
[41]);
2132 OUTREG(DISP_MISC_CNTL
, rinfo
->save_regs
[9]);
2134 OUTMC(rinfo
, ixMC_CHP_IO_CNTL_A0
, 0xf7bb4433);
2135 OUTREG(MC_IND_INDEX
, 0);
2136 OUTMC(rinfo
, ixMC_CHP_IO_CNTL_B0
, 0xf7bb4433);
2137 OUTREG(MC_IND_INDEX
, 0);
2139 OUTREG(CRTC_MORE_CNTL
, INREG(CRTC_MORE_CNTL
));
2141 tmp
= INPLL(pllVCLK_ECP_CNTL
);
2142 OUTPLL(pllVCLK_ECP_CNTL
, tmp
);
2143 tmp
= INPLL(pllPIXCLKS_CNTL
);
2144 OUTPLL(pllPIXCLKS_CNTL
, tmp
);
2146 OUTPLL(MCLK_CNTL
, 0xaa3f0000);
2147 OUTPLL(SCLK_CNTL
, 0xffff0000);
2148 OUTPLL(pllMPLL_AUX_CNTL
, 6);
2149 OUTPLL(pllSPLL_AUX_CNTL
, 1);
2150 OUTPLL(MDLL_CKO
, 0x9f009f);
2151 OUTPLL(MDLL_RDCKA
, 0x830083);
2152 OUTPLL(pllMDLL_RDCKB
, 0x830083);
2153 OUTPLL(PPLL_CNTL
, 0xa433);
2154 OUTPLL(P2PLL_CNTL
, 0xa433);
2155 OUTPLL(MPLL_CNTL
, 0x0400a403);
2156 OUTPLL(SPLL_CNTL
, 0x0400a433);
2158 tmp
= INPLL(M_SPLL_REF_FB_DIV
);
2159 OUTPLL(M_SPLL_REF_FB_DIV
, tmp
);
2160 tmp
= INPLL(M_SPLL_REF_FB_DIV
);
2161 OUTPLL(M_SPLL_REF_FB_DIV
, tmp
| 0xc);
2162 INPLL(M_SPLL_REF_FB_DIV
);
2164 tmp
= INPLL(MPLL_CNTL
);
2165 OUTREG8(CLOCK_CNTL_INDEX
, MPLL_CNTL
+ PLL_WR_EN
);
2166 radeon_pll_errata_after_index(rinfo
);
2167 OUTREG8(CLOCK_CNTL_DATA
+ 1, (tmp
>> 8) & 0xff);
2168 radeon_pll_errata_after_data(rinfo
);
2170 tmp
= INPLL(M_SPLL_REF_FB_DIV
);
2171 OUTPLL(M_SPLL_REF_FB_DIV
, tmp
| 0x5900);
2173 tmp
= INPLL(MPLL_CNTL
);
2174 OUTPLL(MPLL_CNTL
, tmp
& ~0x2);
2176 tmp
= INPLL(MPLL_CNTL
);
2177 OUTPLL(MPLL_CNTL
, tmp
& ~0x1);
2180 OUTPLL(MCLK_CNTL
, 0xaa3f1212);
2183 INPLL(M_SPLL_REF_FB_DIV
);
2185 INPLL(M_SPLL_REF_FB_DIV
);
2187 tmp
= INPLL(SPLL_CNTL
);
2188 OUTREG8(CLOCK_CNTL_INDEX
, SPLL_CNTL
+ PLL_WR_EN
);
2189 radeon_pll_errata_after_index(rinfo
);
2190 OUTREG8(CLOCK_CNTL_DATA
+ 1, (tmp
>> 8) & 0xff);
2191 radeon_pll_errata_after_data(rinfo
);
2193 tmp
= INPLL(M_SPLL_REF_FB_DIV
);
2194 OUTPLL(M_SPLL_REF_FB_DIV
, tmp
| 0x780000);
2196 tmp
= INPLL(SPLL_CNTL
);
2197 OUTPLL(SPLL_CNTL
, tmp
& ~0x1);
2199 tmp
= INPLL(SPLL_CNTL
);
2200 OUTPLL(SPLL_CNTL
, tmp
& ~0x2);
2203 tmp
= INPLL(SCLK_CNTL
);
2204 OUTPLL(SCLK_CNTL
, tmp
| 2);
2207 cko
= INPLL(pllMDLL_CKO
);
2208 cka
= INPLL(pllMDLL_RDCKA
);
2209 ckb
= INPLL(pllMDLL_RDCKB
);
2211 cko
&= ~(MDLL_CKO__MCKOA_SLEEP
| MDLL_CKO__MCKOB_SLEEP
);
2212 OUTPLL(pllMDLL_CKO
, cko
);
2214 cko
&= ~(MDLL_CKO__MCKOA_RESET
| MDLL_CKO__MCKOB_RESET
);
2215 OUTPLL(pllMDLL_CKO
, cko
);
2218 cka
&= ~(MDLL_RDCKA__MRDCKA0_SLEEP
| MDLL_RDCKA__MRDCKA1_SLEEP
);
2219 OUTPLL(pllMDLL_RDCKA
, cka
);
2221 cka
&= ~(MDLL_RDCKA__MRDCKA0_RESET
| MDLL_RDCKA__MRDCKA1_RESET
);
2222 OUTPLL(pllMDLL_RDCKA
, cka
);
2225 ckb
&= ~(MDLL_RDCKB__MRDCKB0_SLEEP
| MDLL_RDCKB__MRDCKB1_SLEEP
);
2226 OUTPLL(pllMDLL_RDCKB
, ckb
);
2228 ckb
&= ~(MDLL_RDCKB__MRDCKB0_RESET
| MDLL_RDCKB__MRDCKB1_RESET
);
2229 OUTPLL(pllMDLL_RDCKB
, ckb
);
2232 OUTMC(rinfo
, ixMC_CHP_IO_CNTL_A1
, 0x151550ff);
2233 OUTREG(MC_IND_INDEX
, 0);
2234 OUTMC(rinfo
, ixMC_CHP_IO_CNTL_B1
, 0x151550ff);
2235 OUTREG(MC_IND_INDEX
, 0);
2237 OUTMC(rinfo
, ixMC_CHP_IO_CNTL_A1
, 0x141550ff);
2238 OUTREG(MC_IND_INDEX
, 0);
2239 OUTMC(rinfo
, ixMC_CHP_IO_CNTL_B1
, 0x141550ff);
2240 OUTREG(MC_IND_INDEX
, 0);
2243 OUTPLL(pllHTOTAL_CNTL
, 0);
2244 OUTPLL(pllHTOTAL2_CNTL
, 0);
2246 OUTREG(MEM_CNTL
, 0x29002901);
2247 OUTREG(MEM_SDRAM_MODE_REG
, 0x45320032); /* XXX use save_regs[35]? */
2248 OUTREG(EXT_MEM_CNTL
, 0x1a394333);
2249 OUTREG(MEM_IO_CNTL_A1
, 0x0aac0aac);
2250 OUTREG(MEM_INIT_LATENCY_TIMER
, 0x34444444);
2251 OUTREG(MEM_REFRESH_CNTL
, 0x1f1f7218); /* XXX or save_regs[42]? */
2252 OUTREG(MC_DEBUG
, 0);
2253 OUTREG(MEM_IO_OE_CNTL
, 0x04300430);
2255 OUTMC(rinfo
, ixMC_IMP_CNTL
, 0x00f460d6);
2256 OUTREG(MC_IND_INDEX
, 0);
2257 OUTMC(rinfo
, ixMC_IMP_CNTL_0
, 0x00009249);
2258 OUTREG(MC_IND_INDEX
, 0);
2260 OUTREG(CONFIG_MEMSIZE
, rinfo
->video_ram
);
2262 radeon_pm_full_reset_sdram(rinfo
);
2265 OUTREG(TMDS_CNTL
, 0x01000000); /* XXX ? */
2266 tmp
= INREG(FP_GEN_CNTL
);
2267 tmp
|= FP_CRTC_DONT_SHADOW_HEND
| FP_CRTC_DONT_SHADOW_VPAR
| 0x200;
2268 OUTREG(FP_GEN_CNTL
, tmp
);
2270 tmp
= INREG(DISP_OUTPUT_CNTL
);
2272 OUTREG(DISP_OUTPUT_CNTL
, tmp
);
2274 OUTPLL(CLK_PIN_CNTL
, rinfo
->save_regs
[4]);
2275 OUTPLL(CLK_PWRMGT_CNTL
, rinfo
->save_regs
[1]);
2276 OUTPLL(PLL_PWRMGT_CNTL
, rinfo
->save_regs
[0]);
2278 tmp
= INPLL(MCLK_MISC
);
2279 tmp
|= MCLK_MISC__MC_MCLK_DYN_ENABLE
| MCLK_MISC__IO_MCLK_DYN_ENABLE
;
2280 OUTPLL(MCLK_MISC
, tmp
);
2282 tmp
= INPLL(SCLK_CNTL
);
2283 OUTPLL(SCLK_CNTL
, tmp
);
2285 OUTREG(CRTC_MORE_CNTL
, 0);
2286 OUTREG8(CRTC_GEN_CNTL
+1, 6);
2287 OUTREG8(CRTC_GEN_CNTL
+3, 1);
2288 OUTREG(CRTC_PITCH
, 32);
2290 tmp
= INPLL(VCLK_ECP_CNTL
);
2291 OUTPLL(VCLK_ECP_CNTL
, tmp
);
2293 tmp
= INPLL(PPLL_CNTL
);
2294 OUTPLL(PPLL_CNTL
, tmp
);
2296 /* palette stuff and BIOS_1_SCRATCH... */
2298 tmp
= INREG(FP_GEN_CNTL
);
2299 tmp2
= INREG(TMDS_TRANSMITTER_CNTL
);
2301 OUTREG(FP_GEN_CNTL
, tmp
);
2303 OUTREG(FP_GEN_CNTL
, tmp
);
2305 OUTREG(TMDS_TRANSMITTER_CNTL
, tmp2
);
2306 OUTREG(CRTC_MORE_CNTL
, 0);
2309 tmp
= INREG(CRTC_MORE_CNTL
);
2310 OUTREG(CRTC_MORE_CNTL
, tmp
);
2312 cgc
= INREG(CRTC_GEN_CNTL
);
2313 cec
= INREG(CRTC_EXT_CNTL
);
2314 c2gc
= INREG(CRTC2_GEN_CNTL
);
2316 OUTREG(CRTC_H_SYNC_STRT_WID
, 0x008e0580);
2317 OUTREG(CRTC_H_TOTAL_DISP
, 0x009f00d2);
2318 OUTREG8(CLOCK_CNTL_INDEX
, HTOTAL_CNTL
+ PLL_WR_EN
);
2319 radeon_pll_errata_after_index(rinfo
);
2320 OUTREG8(CLOCK_CNTL_DATA
, 0);
2321 radeon_pll_errata_after_data(rinfo
);
2322 OUTREG(CRTC_V_SYNC_STRT_WID
, 0x00830403);
2323 OUTREG(CRTC_V_TOTAL_DISP
, 0x03ff0429);
2324 OUTREG(FP_CRTC_H_TOTAL_DISP
, 0x009f0033);
2325 OUTREG(FP_H_SYNC_STRT_WID
, 0x008e0080);
2326 OUTREG(CRT_CRTC_H_SYNC_STRT_WID
, 0x008e0080);
2327 OUTREG(FP_CRTC_V_TOTAL_DISP
, 0x03ff002a);
2328 OUTREG(FP_V_SYNC_STRT_WID
, 0x00830004);
2329 OUTREG(CRT_CRTC_V_SYNC_STRT_WID
, 0x00830004);
2330 OUTREG(FP_HORZ_VERT_ACTIVE
, 0x009f03ff);
2331 OUTREG(FP_HORZ_STRETCH
, 0);
2332 OUTREG(FP_VERT_STRETCH
, 0);
2334 OUTREG(OVR_WID_LEFT_RIGHT
, 0);
2335 OUTREG(OVR_WID_TOP_BOTTOM
, 0);
2337 tmp
= INPLL(PPLL_REF_DIV
);
2338 tmp
= (tmp
& ~PPLL_REF_DIV_MASK
) | rinfo
->pll
.ref_div
;
2339 OUTPLL(PPLL_REF_DIV
, tmp
);
2340 INPLL(PPLL_REF_DIV
);
2342 OUTREG8(CLOCK_CNTL_INDEX
, PPLL_CNTL
+ PLL_WR_EN
);
2343 radeon_pll_errata_after_index(rinfo
);
2344 OUTREG8(CLOCK_CNTL_DATA
+ 1, 0xbc);
2345 radeon_pll_errata_after_data(rinfo
);
2347 tmp
= INREG(CLOCK_CNTL_INDEX
);
2348 radeon_pll_errata_after_index(rinfo
);
2349 OUTREG(CLOCK_CNTL_INDEX
, tmp
& 0xff);
2350 radeon_pll_errata_after_index(rinfo
);
2351 radeon_pll_errata_after_data(rinfo
);
2353 OUTPLL(PPLL_DIV_0
, 0x48090);
2355 tmp
= INPLL(PPLL_CNTL
);
2356 OUTPLL(PPLL_CNTL
, tmp
& ~0x2);
2358 tmp
= INPLL(PPLL_CNTL
);
2359 OUTPLL(PPLL_CNTL
, tmp
& ~0x1);
2362 tmp
= INPLL(VCLK_ECP_CNTL
);
2363 OUTPLL(VCLK_ECP_CNTL
, tmp
| 3);
2366 tmp
= INPLL(VCLK_ECP_CNTL
);
2367 OUTPLL(VCLK_ECP_CNTL
, tmp
);
2369 c2gc
|= CRTC2_DISP_REQ_EN_B
;
2370 OUTREG(CRTC2_GEN_CNTL
, c2gc
);
2372 OUTREG(CRTC_GEN_CNTL
, cgc
);
2373 OUTREG(CRTC_EXT_CNTL
, cec
);
2374 OUTREG(CRTC_PITCH
, 0xa0);
2375 OUTREG(CRTC_OFFSET
, 0);
2376 OUTREG(CRTC_OFFSET_CNTL
, 0);
2378 OUTREG(GRPH_BUFFER_CNTL
, 0x20117c7c);
2379 OUTREG(GRPH2_BUFFER_CNTL
, 0x00205c5c);
2381 tmp2
= INREG(FP_GEN_CNTL
);
2382 tmp
= INREG(TMDS_TRANSMITTER_CNTL
);
2383 OUTREG(0x2a8, 0x0000061b);
2385 OUTREG(TMDS_TRANSMITTER_CNTL
, tmp
);
2387 tmp
&= ~TMDS_PLLRST
;
2388 OUTREG(TMDS_TRANSMITTER_CNTL
, tmp
);
2391 OUTREG(FP_GEN_CNTL
, tmp2
);
2394 OUTREG(FP_GEN_CNTL
, tmp2
);
2396 OUTREG(CUR_HORZ_VERT_OFF
, CUR_LOCK
| 1);
2397 cgc
= INREG(CRTC_GEN_CNTL
);
2398 OUTREG(CUR_HORZ_VERT_POSN
, 0xbfff0fff);
2400 OUTREG(CUR_OFFSET
, 0);
2404 #endif /* CONFIG_PPC_OF */
2406 static void radeon_set_suspend(struct radeonfb_info
*rinfo
, int suspend
)
2415 /* Set the chip into appropriate suspend mode (we use D2,
2416 * D3 would require a compete re-initialization of the chip,
2417 * including PCI config registers, clocks, AGP conf, ...)
2420 printk(KERN_DEBUG
"radeonfb (%s): switching to D2 state...\n",
2421 pci_name(rinfo
->pdev
));
2423 /* Disable dynamic power management of clocks for the
2424 * duration of the suspend/resume process
2426 radeon_pm_disable_dynamic_mode(rinfo
);
2428 /* Save some registers */
2429 radeon_pm_save_regs(rinfo
, 0);
2431 /* Prepare mobility chips for suspend.
2433 if (rinfo
->is_mobility
) {
2435 radeon_pm_program_v2clk(rinfo
);
2437 /* Disable IO PADs */
2438 radeon_pm_disable_iopad(rinfo
);
2440 /* Set low current */
2441 radeon_pm_low_current(rinfo
);
2443 /* Prepare chip for power management */
2444 radeon_pm_setup_for_suspend(rinfo
);
2446 if (rinfo
->family
<= CHIP_FAMILY_RV280
) {
2447 /* Reset the MDLL */
2448 /* because both INPLL and OUTPLL take the same
2449 * lock, that's why. */
2450 tmp
= INPLL( pllMDLL_CKO
) | MDLL_CKO__MCKOA_RESET
2451 | MDLL_CKO__MCKOB_RESET
;
2452 OUTPLL( pllMDLL_CKO
, tmp
);
2456 for (i
= 0; i
< 64; ++i
)
2457 pci_read_config_dword(rinfo
->pdev
, i
* 4,
2458 &rinfo
->cfg_save
[i
]);
2460 /* Switch PCI power managment to D2. */
2461 pci_disable_device(rinfo
->pdev
);
2463 pci_read_config_word(
2464 rinfo
->pdev
, rinfo
->pm_reg
+PCI_PM_CTRL
,
2468 pci_write_config_word(
2469 rinfo
->pdev
, rinfo
->pm_reg
+PCI_PM_CTRL
,
2470 (pwr_cmd
& ~PCI_PM_CTRL_STATE_MASK
) | 2);
2474 printk(KERN_DEBUG
"radeonfb (%s): switching to D0 state...\n",
2475 pci_name(rinfo
->pdev
));
2477 /* Switch back PCI powermanagment to D0 */
2479 pci_write_config_word(rinfo
->pdev
, rinfo
->pm_reg
+PCI_PM_CTRL
, 0);
2482 if (rinfo
->family
<= CHIP_FAMILY_RV250
) {
2483 /* Reset the SDRAM controller */
2484 radeon_pm_full_reset_sdram(rinfo
);
2486 /* Restore some registers */
2487 radeon_pm_restore_regs(rinfo
);
2489 /* Restore registers first */
2490 radeon_pm_restore_regs(rinfo
);
2491 /* init sdram controller */
2492 radeon_pm_full_reset_sdram(rinfo
);
2497 static int radeon_restore_pci_cfg(struct radeonfb_info
*rinfo
)
2500 static u32 radeon_cfg_after_resume
[64];
2502 for (i
= 0; i
< 64; ++i
)
2503 pci_read_config_dword(rinfo
->pdev
, i
* 4,
2504 &radeon_cfg_after_resume
[i
]);
2506 if (radeon_cfg_after_resume
[PCI_BASE_ADDRESS_0
/4]
2507 == rinfo
->cfg_save
[PCI_BASE_ADDRESS_0
/4])
2508 return 0; /* assume everything is ok */
2510 for (i
= PCI_BASE_ADDRESS_0
/4; i
< 64; ++i
) {
2511 if (radeon_cfg_after_resume
[i
] != rinfo
->cfg_save
[i
])
2512 pci_write_config_dword(rinfo
->pdev
, i
* 4,
2513 rinfo
->cfg_save
[i
]);
2515 pci_write_config_word(rinfo
->pdev
, PCI_CACHE_LINE_SIZE
,
2516 rinfo
->cfg_save
[PCI_CACHE_LINE_SIZE
/4]);
2517 pci_write_config_word(rinfo
->pdev
, PCI_COMMAND
,
2518 rinfo
->cfg_save
[PCI_COMMAND
/4]);
2523 int radeonfb_pci_suspend(struct pci_dev
*pdev
, pm_message_t state
)
2525 struct fb_info
*info
= pci_get_drvdata(pdev
);
2526 struct radeonfb_info
*rinfo
= info
->par
;
2529 if (state
== pdev
->dev
.power
.power_state
)
2532 printk(KERN_DEBUG
"radeonfb (%s): suspending to state: %d...\n",
2533 pci_name(pdev
), state
);
2535 /* For suspend-to-disk, we cheat here. We don't suspend anything and
2536 * let fbcon continue drawing until we are all set. That shouldn't
2537 * really cause any problem at this point, provided that the wakeup
2538 * code knows that any state in memory may not match the HW
2540 if (state
!= PM_SUSPEND_MEM
)
2543 acquire_console_sem();
2545 fb_set_suspend(info
, 1);
2547 if (!(info
->flags
& FBINFO_HWACCEL_DISABLED
)) {
2548 /* Make sure engine is reset */
2549 radeon_engine_idle();
2550 radeonfb_engine_reset(rinfo
);
2551 radeon_engine_idle();
2554 /* Blank display and LCD */
2555 radeon_screen_blank(rinfo
, FB_BLANK_POWERDOWN
, 1);
2559 rinfo
->lock_blank
= 1;
2560 del_timer_sync(&rinfo
->lvds_timer
);
2562 #ifdef CONFIG_PPC_PMAC
2563 /* On powermac, we have hooks to properly suspend/resume AGP now,
2564 * use them here. We'll ultimately need some generic support here,
2565 * but the generic code isn't quite ready for that yet
2567 pmac_suspend_agp_for_card(pdev
);
2568 #endif /* CONFIG_PPC_PMAC */
2570 /* If we support wakeup from poweroff, we save all regs we can including cfg
2573 if (rinfo
->pm_mode
& radeon_pm_off
) {
2574 /* Always disable dynamic clocks or weird things are happening when
2575 * the chip goes off (basically the panel doesn't shut down properly
2576 * and we crash on wakeup),
2577 * also, we want the saved regs context to have no dynamic clocks in
2578 * it, we'll restore the dynamic clocks state on wakeup
2580 radeon_pm_disable_dynamic_mode(rinfo
);
2582 radeon_pm_save_regs(rinfo
, 1);
2584 if (rinfo
->is_mobility
&& !(rinfo
->pm_mode
& radeon_pm_d2
)) {
2585 /* Switch off LVDS interface */
2587 OUTREG(LVDS_GEN_CNTL
, INREG(LVDS_GEN_CNTL
) & ~(LVDS_BL_MOD_EN
));
2589 OUTREG(LVDS_GEN_CNTL
, INREG(LVDS_GEN_CNTL
) & ~(LVDS_EN
| LVDS_ON
));
2590 OUTREG(LVDS_PLL_CNTL
, (INREG(LVDS_PLL_CNTL
) & ~30000) | 0x20000);
2592 OUTREG(LVDS_GEN_CNTL
, INREG(LVDS_GEN_CNTL
) & ~(LVDS_DIGON
));
2594 // FIXME: Use PCI layer
2595 for (i
= 0; i
< 64; ++i
)
2596 pci_read_config_dword(pdev
, i
* 4, &rinfo
->cfg_save
[i
]);
2597 pci_disable_device(pdev
);
2599 /* If we support D2, we go to it (should be fixed later with a flag forcing
2600 * D3 only for some laptops)
2602 if (rinfo
->pm_mode
& radeon_pm_d2
)
2603 radeon_set_suspend(rinfo
, 1);
2605 release_console_sem();
2608 pdev
->dev
.power
.power_state
= state
;
2613 int radeonfb_pci_resume(struct pci_dev
*pdev
)
2615 struct fb_info
*info
= pci_get_drvdata(pdev
);
2616 struct radeonfb_info
*rinfo
= info
->par
;
2619 if (pdev
->dev
.power
.power_state
== 0)
2622 if (rinfo
->no_schedule
) {
2623 if (try_acquire_console_sem())
2626 acquire_console_sem();
2628 printk(KERN_DEBUG
"radeonfb (%s): resuming from state: %d...\n",
2629 pci_name(pdev
), pdev
->dev
.power
.power_state
);
2632 if (pci_enable_device(pdev
)) {
2634 printk(KERN_ERR
"radeonfb (%s): can't enable PCI device !\n",
2638 pci_set_master(pdev
);
2640 if (pdev
->dev
.power
.power_state
== PM_SUSPEND_MEM
) {
2641 /* Wakeup chip. Check from config space if we were powered off
2642 * (todo: additionally, check CLK_PIN_CNTL too)
2644 if ((rinfo
->pm_mode
& radeon_pm_off
) && radeon_restore_pci_cfg(rinfo
)) {
2645 if (rinfo
->reinit_func
!= NULL
)
2646 rinfo
->reinit_func(rinfo
);
2648 printk(KERN_ERR
"radeonfb (%s): can't resume radeon from"
2649 " D3 cold, need softboot !", pci_name(pdev
));
2654 /* If we support D2, try to resume... we should check what was our
2655 * state though... (were we really in D2 state ?). Right now, this code
2656 * is only enable on Macs so it's fine.
2658 else if (rinfo
->pm_mode
& radeon_pm_d2
)
2659 radeon_set_suspend(rinfo
, 0);
2663 radeon_engine_idle();
2665 /* Restore display & engine */
2666 radeon_write_mode (rinfo
, &rinfo
->state
, 1);
2667 if (!(info
->flags
& FBINFO_HWACCEL_DISABLED
))
2668 radeonfb_engine_init (rinfo
);
2670 fb_pan_display(info
, &info
->var
);
2671 fb_set_cmap(&info
->cmap
, info
);
2674 fb_set_suspend(info
, 0);
2677 rinfo
->lock_blank
= 0;
2678 radeon_screen_blank(rinfo
, FB_BLANK_UNBLANK
, 1);
2680 #ifdef CONFIG_PPC_PMAC
2681 /* On powermac, we have hooks to properly suspend/resume AGP now,
2682 * use them here. We'll ultimately need some generic support here,
2683 * but the generic code isn't quite ready for that yet
2685 pmac_resume_agp_for_card(pdev
);
2686 #endif /* CONFIG_PPC_PMAC */
2689 /* Check status of dynclk */
2690 if (rinfo
->dynclk
== 1)
2691 radeon_pm_enable_dynamic_mode(rinfo
);
2692 else if (rinfo
->dynclk
== 0)
2693 radeon_pm_disable_dynamic_mode(rinfo
);
2695 pdev
->dev
.power
.power_state
= PMSG_ON
;
2698 release_console_sem();
2703 #ifdef CONFIG_PPC_OF
2704 static void radeonfb_early_resume(void *data
)
2706 struct radeonfb_info
*rinfo
= data
;
2708 rinfo
->no_schedule
= 1;
2709 radeonfb_pci_resume(rinfo
->pdev
);
2710 rinfo
->no_schedule
= 0;
2712 #endif /* CONFIG_PPC_OF */
2714 #endif /* CONFIG_PM */
2716 void radeonfb_pm_init(struct radeonfb_info
*rinfo
, int dynclk
)
2718 /* Find PM registers in config space if any*/
2719 rinfo
->pm_reg
= pci_find_capability(rinfo
->pdev
, PCI_CAP_ID_PM
);
2721 /* Enable/Disable dynamic clocks: TODO add sysfs access */
2722 rinfo
->dynclk
= dynclk
;
2724 radeon_pm_enable_dynamic_mode(rinfo
);
2725 printk("radeonfb: Dynamic Clock Power Management enabled\n");
2726 } else if (dynclk
== 0) {
2727 radeon_pm_disable_dynamic_mode(rinfo
);
2728 printk("radeonfb: Dynamic Clock Power Management disabled\n");
2731 /* Check if we can power manage on suspend/resume. We can do
2732 * D2 on M6, M7 and M9, and we can resume from D3 cold a few other
2733 * "Mac" cards, but that's all. We need more infos about what the
2734 * BIOS does tho. Right now, all this PM stuff is pmac-only for that
2737 #if defined(CONFIG_PM) && defined(CONFIG_PPC_OF)
2738 if (_machine
== _MACH_Pmac
&& rinfo
->of_node
) {
2739 if (rinfo
->is_mobility
&& rinfo
->pm_reg
&&
2740 rinfo
->family
<= CHIP_FAMILY_RV250
)
2741 rinfo
->pm_mode
|= radeon_pm_d2
;
2743 /* We can restart Jasper (M10 chip in albooks), BlueStone (7500 chip
2744 * in some desktop G4s), and Via (M9+ chip on iBook G4)
2746 if (!strcmp(rinfo
->of_node
->name
, "ATY,JasperParent")) {
2747 rinfo
->reinit_func
= radeon_reinitialize_M10
;
2748 rinfo
->pm_mode
|= radeon_pm_off
;
2750 #if 0 /* Not ready yet */
2751 if (!strcmp(rinfo
->of_node
->name
, "ATY,BlueStoneParent")) {
2752 rinfo
->reinit_func
= radeon_reinitialize_QW
;
2753 rinfo
->pm_mode
|= radeon_pm_off
;
2756 if (!strcmp(rinfo
->of_node
->name
, "ATY,ViaParent")) {
2757 rinfo
->reinit_func
= radeon_reinitialize_M9P
;
2758 rinfo
->pm_mode
|= radeon_pm_off
;
2761 /* If any of the above is set, we assume the machine can sleep/resume.
2762 * It's a bit of a "shortcut" but will work fine. Ideally, we need infos
2763 * from the platform about what happens to the chip...
2764 * Now we tell the platform about our capability
2766 if (rinfo
->pm_mode
!= radeon_pm_none
) {
2767 pmac_call_feature(PMAC_FTR_DEVICE_CAN_WAKE
, rinfo
->of_node
, 0, 1);
2768 pmac_set_early_video_resume(radeonfb_early_resume
, rinfo
);
2772 /* Power down TV DAC, taht saves a significant amount of power,
2773 * we'll have something better once we actually have some TVOut
2776 OUTREG(TV_DAC_CNTL
, INREG(TV_DAC_CNTL
) | 0x07000000);
2779 #endif /* defined(CONFIG_PM) && defined(CONFIG_PPC_OF) */
2782 void radeonfb_pm_exit(struct radeonfb_info
*rinfo
)
2784 #if defined(CONFIG_PM) && defined(CONFIG_PPC_OF)
2785 if (rinfo
->pm_mode
!= radeon_pm_none
)
2786 pmac_set_early_video_resume(NULL
, NULL
);