| blob | bd364f5a99bcc221f8e55bcb8f582737f977accc |
1 /*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
15 */
16 /* DO NOT EDIT!! - this file automatically generated
17 * from .s file by awk -f s2h.awk
18 */
19 /**************************************************************************
20 * * Copyright © ARM Limited 1998. All rights reserved.
21 * ***********************************************************************/
22 /* ************************************************************************
23 *
24 * Integrator address map
25 *
26 * NOTE: This is a multi-hosted header file for use with uHAL and
27 * supported debuggers.
28 *
29 * $Id: platform.s,v 1.32 2000/02/18 10:51:39 asims Exp $
30 *
31 * ***********************************************************************/
33 #ifndef __address_h
34 #define __address_h 1
36 /* ========================================================================
37 * Integrator definitions
38 * ========================================================================
39 * ------------------------------------------------------------------------
40 * Memory definitions
41 * ------------------------------------------------------------------------
42 * Integrator memory map
43 *
44 */
45 #define INTEGRATOR_BOOT_ROM_LO 0x00000000
46 #define INTEGRATOR_BOOT_ROM_HI 0x20000000
48 #define INTEGRATOR_BOOT_ROM_SIZE SZ_512K
50 /*
51 * New Core Modules have different amounts of SSRAM, the amount of SSRAM
52 * fitted can be found in HDR_STAT.
53 *
54 * The symbol INTEGRATOR_SSRAM_SIZE is kept, however this now refers to
55 * the minimum amount of SSRAM fitted on any core module.
56 *
57 * New Core Modules also alias the SSRAM.
58 *
59 */
60 #define INTEGRATOR_SSRAM_BASE 0x00000000
61 #define INTEGRATOR_SSRAM_ALIAS_BASE 0x10800000
62 #define INTEGRATOR_SSRAM_SIZE SZ_256K
64 #define INTEGRATOR_FLASH_BASE 0x24000000
65 #define INTEGRATOR_FLASH_SIZE SZ_32M
67 #define INTEGRATOR_MBRD_SSRAM_BASE 0x28000000
68 #define INTEGRATOR_MBRD_SSRAM_SIZE SZ_512K
70 /*
71 * SDRAM is a SIMM therefore the size is not known.
72 *
73 */
74 #define INTEGRATOR_SDRAM_BASE 0x00040000
76 #define INTEGRATOR_SDRAM_ALIAS_BASE 0x80000000
77 #define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000
78 #define INTEGRATOR_HDR1_SDRAM_BASE 0x90000000
79 #define INTEGRATOR_HDR2_SDRAM_BASE 0xA0000000
80 #define INTEGRATOR_HDR3_SDRAM_BASE 0xB0000000
82 /*
83 * Logic expansion modules
84 *
85 */
86 #define INTEGRATOR_LOGIC_MODULES_BASE 0xC0000000
87 #define INTEGRATOR_LOGIC_MODULE0_BASE 0xC0000000
88 #define INTEGRATOR_LOGIC_MODULE1_BASE 0xD0000000
89 #define INTEGRATOR_LOGIC_MODULE2_BASE 0xE0000000
90 #define INTEGRATOR_LOGIC_MODULE3_BASE 0xF0000000
92 /* ------------------------------------------------------------------------
93 * Integrator header card registers
94 * ------------------------------------------------------------------------
95 *
96 */
97 #define INTEGRATOR_HDR_ID_OFFSET 0x00
98 #define INTEGRATOR_HDR_PROC_OFFSET 0x04
99 #define INTEGRATOR_HDR_OSC_OFFSET 0x08
100 #define INTEGRATOR_HDR_CTRL_OFFSET 0x0C
101 #define INTEGRATOR_HDR_STAT_OFFSET 0x10
102 #define INTEGRATOR_HDR_LOCK_OFFSET 0x14
103 #define INTEGRATOR_HDR_SDRAM_OFFSET 0x20
105 #define INTEGRATOR_HDR_IC_OFFSET 0x40
106 #define INTEGRATOR_HDR_SPDBASE_OFFSET 0x100
107 #define INTEGRATOR_HDR_SPDTOP_OFFSET 0x200
109 #define INTEGRATOR_HDR_BASE 0x10000000
110 #define INTEGRATOR_HDR_ID (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_ID_OFFSET)
111 #define INTEGRATOR_HDR_PROC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_PROC_OFFSET)
112 #define INTEGRATOR_HDR_OSC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_OSC_OFFSET)
113 #define INTEGRATOR_HDR_CTRL (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_CTRL_OFFSET)
114 #define INTEGRATOR_HDR_STAT (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_STAT_OFFSET)
115 #define INTEGRATOR_HDR_LOCK (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_LOCK_OFFSET)
116 #define INTEGRATOR_HDR_SDRAM (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SDRAM_OFFSET)
117 #define INTEGRATOR_HDR_INIT (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_INIT_OFFSET)
118 #define INTEGRATOR_HDR_IC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_IC_OFFSET)
119 #define INTEGRATOR_HDR_SPDBASE (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SPDBASE_OFFSET)
120 #define INTEGRATOR_HDR_SPDTOP (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SPDTOP_OFFSET)
122 #define INTEGRATOR_HDR_CTRL_LED 0x01
123 #define INTEGRATOR_HDR_CTRL_MBRD_DETECH 0x02
124 #define INTEGRATOR_HDR_CTRL_REMAP 0x04
125 #define INTEGRATOR_HDR_CTRL_RESET 0x08
126 #define INTEGRATOR_HDR_CTRL_HIGHVECTORS 0x10
127 #define INTEGRATOR_HDR_CTRL_BIG_ENDIAN 0x20
128 #define INTEGRATOR_HDR_CTRL_FASTBUS 0x40
129 #define INTEGRATOR_HDR_CTRL_SYNC 0x80
131 #define INTEGRATOR_HDR_OSC_CORE_10MHz 0x102
132 #define INTEGRATOR_HDR_OSC_CORE_15MHz 0x107
133 #define INTEGRATOR_HDR_OSC_CORE_20MHz 0x10C
134 #define INTEGRATOR_HDR_OSC_CORE_25MHz 0x111
135 #define INTEGRATOR_HDR_OSC_CORE_30MHz 0x116
136 #define INTEGRATOR_HDR_OSC_CORE_35MHz 0x11B
137 #define INTEGRATOR_HDR_OSC_CORE_40MHz 0x120
138 #define INTEGRATOR_HDR_OSC_CORE_45MHz 0x125
139 #define INTEGRATOR_HDR_OSC_CORE_50MHz 0x12A
140 #define INTEGRATOR_HDR_OSC_CORE_55MHz 0x12F
141 #define INTEGRATOR_HDR_OSC_CORE_60MHz 0x134
142 #define INTEGRATOR_HDR_OSC_CORE_65MHz 0x139
143 #define INTEGRATOR_HDR_OSC_CORE_70MHz 0x13E
144 #define INTEGRATOR_HDR_OSC_CORE_75MHz 0x143
145 #define INTEGRATOR_HDR_OSC_CORE_80MHz 0x148
146 #define INTEGRATOR_HDR_OSC_CORE_85MHz 0x14D
147 #define INTEGRATOR_HDR_OSC_CORE_90MHz 0x152
148 #define INTEGRATOR_HDR_OSC_CORE_95MHz 0x157
149 #define INTEGRATOR_HDR_OSC_CORE_100MHz 0x15C
150 #define INTEGRATOR_HDR_OSC_CORE_105MHz 0x161
151 #define INTEGRATOR_HDR_OSC_CORE_110MHz 0x166
152 #define INTEGRATOR_HDR_OSC_CORE_115MHz 0x16B
153 #define INTEGRATOR_HDR_OSC_CORE_120MHz 0x170
154 #define INTEGRATOR_HDR_OSC_CORE_125MHz 0x175
155 #define INTEGRATOR_HDR_OSC_CORE_130MHz 0x17A
156 #define INTEGRATOR_HDR_OSC_CORE_135MHz 0x17F
157 #define INTEGRATOR_HDR_OSC_CORE_140MHz 0x184
158 #define INTEGRATOR_HDR_OSC_CORE_145MHz 0x189
159 #define INTEGRATOR_HDR_OSC_CORE_150MHz 0x18E
160 #define INTEGRATOR_HDR_OSC_CORE_155MHz 0x193
161 #define INTEGRATOR_HDR_OSC_CORE_160MHz 0x198
162 #define INTEGRATOR_HDR_OSC_CORE_MASK 0x7FF
164 #define INTEGRATOR_HDR_OSC_MEM_10MHz 0x10C000
165 #define INTEGRATOR_HDR_OSC_MEM_15MHz 0x116000
166 #define INTEGRATOR_HDR_OSC_MEM_20MHz 0x120000
167 #define INTEGRATOR_HDR_OSC_MEM_25MHz 0x12A000
168 #define INTEGRATOR_HDR_OSC_MEM_30MHz 0x134000
169 #define INTEGRATOR_HDR_OSC_MEM_33MHz 0x13A000
170 #define INTEGRATOR_HDR_OSC_MEM_40MHz 0x148000
171 #define INTEGRATOR_HDR_OSC_MEM_50MHz 0x15C000
172 #define INTEGRATOR_HDR_OSC_MEM_60MHz 0x170000
173 #define INTEGRATOR_HDR_OSC_MEM_66MHz 0x17C000
174 #define INTEGRATOR_HDR_OSC_MEM_MASK 0x7FF000
176 #define INTEGRATOR_HDR_OSC_BUS_MODE_CM7x0 0x0
177 #define INTEGRATOR_HDR_OSC_BUS_MODE_CM9x0 0x0800000
178 #define INTEGRATOR_HDR_OSC_BUS_MODE_CM9x6 0x1000000
179 #define INTEGRATOR_HDR_OSC_BUS_MODE_CM10x00 0x1800000
180 #define INTEGRATOR_HDR_OSC_BUS_MODE_MASK 0x1800000
182 #define INTEGRATOR_HDR_SDRAM_SPD_OK (1 << 5)
185 /* ------------------------------------------------------------------------
186 * Integrator system registers
187 * ------------------------------------------------------------------------
188 *
189 */
191 /*
192 * System Controller
193 *
194 */
195 #define INTEGRATOR_SC_ID_OFFSET 0x00
196 #define INTEGRATOR_SC_OSC_OFFSET 0x04
197 #define INTEGRATOR_SC_CTRLS_OFFSET 0x08
198 #define INTEGRATOR_SC_CTRLC_OFFSET 0x0C
199 #define INTEGRATOR_SC_DEC_OFFSET 0x10
200 #define INTEGRATOR_SC_ARB_OFFSET 0x14
201 #define INTEGRATOR_SC_PCIENABLE_OFFSET 0x18
202 #define INTEGRATOR_SC_LOCK_OFFSET 0x1C
204 #define INTEGRATOR_SC_BASE 0x11000000
205 #define INTEGRATOR_SC_ID (INTEGRATOR_SC_BASE + INTEGRATOR_SC_ID_OFFSET)
206 #define INTEGRATOR_SC_OSC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_OSC_OFFSET)
207 #define INTEGRATOR_SC_CTRLS (INTEGRATOR_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET)
208 #define INTEGRATOR_SC_CTRLC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET)
209 #define INTEGRATOR_SC_DEC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_DEC_OFFSET)
210 #define INTEGRATOR_SC_ARB (INTEGRATOR_SC_BASE + INTEGRATOR_SC_ARB_OFFSET)
211 #define INTEGRATOR_SC_PCIENABLE (INTEGRATOR_SC_BASE + INTEGRATOR_SC_PCIENABLE_OFFSET)
212 #define INTEGRATOR_SC_LOCK (INTEGRATOR_SC_BASE + INTEGRATOR_SC_LOCK_OFFSET)
214 #define INTEGRATOR_SC_OSC_SYS_10MHz 0x20
215 #define INTEGRATOR_SC_OSC_SYS_15MHz 0x34
216 #define INTEGRATOR_SC_OSC_SYS_20MHz 0x48
217 #define INTEGRATOR_SC_OSC_SYS_25MHz 0x5C
218 #define INTEGRATOR_SC_OSC_SYS_33MHz 0x7C
219 #define INTEGRATOR_SC_OSC_SYS_MASK 0xFF
221 #define INTEGRATOR_SC_OSC_PCI_25MHz 0x100
222 #define INTEGRATOR_SC_OSC_PCI_33MHz 0x0
223 #define INTEGRATOR_SC_OSC_PCI_MASK 0x100
225 #define INTEGRATOR_SC_CTRL_SOFTRST (1 << 0)
226 #define INTEGRATOR_SC_CTRL_nFLVPPEN (1 << 1)
227 #define INTEGRATOR_SC_CTRL_nFLWP (1 << 2)
228 #define INTEGRATOR_SC_CTRL_URTS0 (1 << 4)
229 #define INTEGRATOR_SC_CTRL_UDTR0 (1 << 5)
230 #define INTEGRATOR_SC_CTRL_URTS1 (1 << 6)
231 #define INTEGRATOR_SC_CTRL_UDTR1 (1 << 7)
233 /*
234 * External Bus Interface
235 *
236 */
237 #define INTEGRATOR_EBI_BASE 0x12000000
239 #define INTEGRATOR_EBI_CSR0_OFFSET 0x00
240 #define INTEGRATOR_EBI_CSR1_OFFSET 0x04
241 #define INTEGRATOR_EBI_CSR2_OFFSET 0x08
242 #define INTEGRATOR_EBI_CSR3_OFFSET 0x0C
243 #define INTEGRATOR_EBI_LOCK_OFFSET 0x20
245 #define INTEGRATOR_EBI_CSR0 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR0_OFFSET)
246 #define INTEGRATOR_EBI_CSR1 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
247 #define INTEGRATOR_EBI_CSR2 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR2_OFFSET)
248 #define INTEGRATOR_EBI_CSR3 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR3_OFFSET)
249 #define INTEGRATOR_EBI_LOCK (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)
251 #define INTEGRATOR_EBI_8_BIT 0x00
252 #define INTEGRATOR_EBI_16_BIT 0x01
253 #define INTEGRATOR_EBI_32_BIT 0x02
254 #define INTEGRATOR_EBI_WRITE_ENABLE 0x04
255 #define INTEGRATOR_EBI_SYNC 0x08
256 #define INTEGRATOR_EBI_WS_2 0x00
257 #define INTEGRATOR_EBI_WS_3 0x10
258 #define INTEGRATOR_EBI_WS_4 0x20
259 #define INTEGRATOR_EBI_WS_5 0x30
260 #define INTEGRATOR_EBI_WS_6 0x40
261 #define INTEGRATOR_EBI_WS_7 0x50
262 #define INTEGRATOR_EBI_WS_8 0x60
263 #define INTEGRATOR_EBI_WS_9 0x70
264 #define INTEGRATOR_EBI_WS_10 0x80
265 #define INTEGRATOR_EBI_WS_11 0x90
266 #define INTEGRATOR_EBI_WS_12 0xA0
267 #define INTEGRATOR_EBI_WS_13 0xB0
268 #define INTEGRATOR_EBI_WS_14 0xC0
269 #define INTEGRATOR_EBI_WS_15 0xD0
270 #define INTEGRATOR_EBI_WS_16 0xE0
271 #define INTEGRATOR_EBI_WS_17 0xF0
282 /*
283 * LED's & Switches
284 *
285 */
286 #define INTEGRATOR_DBG_ALPHA_OFFSET 0x00
287 #define INTEGRATOR_DBG_LEDS_OFFSET 0x04
288 #define INTEGRATOR_DBG_SWITCH_OFFSET 0x08
290 #define INTEGRATOR_DBG_BASE 0x1A000000
291 #define INTEGRATOR_DBG_ALPHA (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_ALPHA_OFFSET)
292 #define INTEGRATOR_DBG_LEDS (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_LEDS_OFFSET)
293 #define INTEGRATOR_DBG_SWITCH (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_SWITCH_OFFSET)
298 /* ------------------------------------------------------------------------
299 * KMI keyboard/mouse definitions
300 * ------------------------------------------------------------------------
301 */
302 /* PS2 Keyboard interface */
303 #define KMI0_BASE INTEGRATOR_KBD_BASE
305 /* PS2 Mouse interface */
306 #define KMI1_BASE INTEGRATOR_MOUSE_BASE
308 /* KMI definitions are now in include/asm-arm/hardware/amba_kmi.h -- rmk */
310 /* ------------------------------------------------------------------------
311 * Where in the memory map does PCI live?
312 * ------------------------------------------------------------------------
313 * This represents a fairly liberal usage of address space. Even though
314 * the V3 only has two windows (therefore we need to map stuff on the fly),
315 * we maintain the same addresses, even if they're not mapped.
316 *
317 */
319 /* unused 256M from A0000000-AFFFFFFF might be used for I2O ???
320 */
322 /* unused (128-16)M from B1000000-B7FFFFFF
323 */
325 /* unused ((128-16)M - 64K) from XXX
326 */
327 #define PHYS_PCI_V3_BASE 0x62000000
329 #define PCI_DRAMSIZE INTEGRATOR_SSRAM_SIZE
331 /* 'export' these to UHAL */
332 #define UHAL_PCI_IO PCI_IO_BASE
333 #define UHAL_PCI_MEM PCI_MEM_BASE
334 #define UHAL_PCI_ALLOC_IO_BASE 0x00004000
335 #define UHAL_PCI_ALLOC_MEM_BASE PCI_MEM_BASE
336 #define UHAL_PCI_MAX_SLOT 20
338 /* ========================================================================
339 * Start of uHAL definitions
340 * ========================================================================
341 */
343 /* ------------------------------------------------------------------------
344 * Integrator Interrupt Controllers
345 * ------------------------------------------------------------------------
346 *
347 * Offsets from interrupt controller base
348 *
349 * System Controller interrupt controller base is
350 *
351 * INTEGRATOR_IC_BASE + (header_number << 6)
352 *
353 * Core Module interrupt controller base is
354 *
355 * INTEGRATOR_HDR_IC
356 *
357 */
358 #define IRQ_STATUS 0
359 #define IRQ_RAW_STATUS 0x04
360 #define IRQ_ENABLE 0x08
361 #define IRQ_ENABLE_SET 0x08
362 #define IRQ_ENABLE_CLEAR 0x0C
364 #define INT_SOFT_SET 0x10
365 #define INT_SOFT_CLEAR 0x14
367 #define FIQ_STATUS 0x20
368 #define FIQ_RAW_STATUS 0x24
369 #define FIQ_ENABLE 0x28
370 #define FIQ_ENABLE_SET 0x28
371 #define FIQ_ENABLE_CLEAR 0x2C
374 /* ------------------------------------------------------------------------
375 * Interrupts
376 * ------------------------------------------------------------------------
377 *
378 *
379 * Each Core Module has two interrupts controllers, one on the core module
380 * itself and one in the system controller on the motherboard. The
381 * READ_INT macro in target.s reads both interrupt controllers and returns
382 * a 32 bit bitmask, bits 0 to 23 are interrupts from the system controller
383 * and bits 24 to 31 are from the core module.
384 *
385 * The following definitions relate to the bitmask returned by READ_INT.
386 *
387 */
389 /* ------------------------------------------------------------------------
390 * LED's - The header LED is not accessible via the uHAL API
391 * ------------------------------------------------------------------------
392 *
393 */
394 #define GREEN_LED 0x01
395 #define YELLOW_LED 0x02
396 #define RED_LED 0x04
397 #define GREEN_LED_2 0x08
398 #define ALL_LEDS 0x0F
400 #define LED_BANK INTEGRATOR_DBG_LEDS
402 /*
403 * Memory definitions - run uHAL out of SSRAM.
404 *
405 */
406 #define uHAL_MEMORY_SIZE INTEGRATOR_SSRAM_SIZE
408 /*
409 * Application Flash
410 *
411 */
412 #define FLASH_BASE INTEGRATOR_FLASH_BASE
413 #define FLASH_SIZE INTEGRATOR_FLASH_SIZE
414 #define FLASH_END (FLASH_BASE + FLASH_SIZE - 1)
415 #define FLASH_BLOCK_SIZE SZ_128K
417 /*
418 * Boot Flash
419 *
420 */
421 #define EPROM_BASE INTEGRATOR_BOOT_ROM_HI
422 #define EPROM_SIZE INTEGRATOR_BOOT_ROM_SIZE
423 #define EPROM_END (EPROM_BASE + EPROM_SIZE - 1)
425 /*
426 * Clean base - dummy
427 *
428 */
429 #define CLEAN_BASE EPROM_BASE
431 /*
432 * Timer definitions
433 *
434 * Only use timer 1 & 2
435 * (both run at 24MHz and will need the clock divider set to 16).
436 *
437 * Timer 0 runs at bus frequency and therefore could vary and currently
438 * uHAL can't handle that.
439 *
440 */
442 #define INTEGRATOR_TIMER0_BASE INTEGRATOR_CT_BASE
443 #define INTEGRATOR_TIMER1_BASE (INTEGRATOR_CT_BASE + 0x100)
444 #define INTEGRATOR_TIMER2_BASE (INTEGRATOR_CT_BASE + 0x200)
446 #define MAX_TIMER 2
447 #define MAX_PERIOD 699050
448 #define TICKS_PER_uSEC 24
450 /*
451 * These are useconds NOT ticks.
452 *
453 */
454 #define mSEC_1 1000
455 #define mSEC_5 (mSEC_1 * 5)
456 #define mSEC_10 (mSEC_1 * 10)
457 #define mSEC_25 (mSEC_1 * 25)
458 #define SEC_1 (mSEC_1 * 1000)
460 #define INTEGRATOR_CSR_BASE 0x10000000
461 #define INTEGRATOR_CSR_SIZE 0x10000000
463 #endif
465 /* END */