include/asm-arm/arch-omap/hardware.h

   1 /*
   2  * linux/include/asm-arm/arch-omap/hardware.h
   3  *
   4  * Hardware definitions for TI OMAP processors and boards
   5  *
   6  * NOTE: Please put device driver specific defines into a separate header
   7  *       file for each driver.
   8  *
   9  * Copyright (C) 2001 RidgeRun, Inc.
  10  * Author: RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com>
  11  *
  12  * Reorganized for Linux-2.6 by Tony Lindgren <tony@atomide.com>
  13  *                          and Dirk Behme <dirk.behme@de.bosch.com>
  14  *
  15  * This program is free software; you can redistribute it and/or modify it
  16  * under the terms of the GNU General Public License as published by the
  17  * Free Software Foundation; either version 2 of the License, or (at your
  18  * option) any later version.
  19  *
  20  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  21  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  22  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  23  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  24  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  25  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  26  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  27  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  28  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  29  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  30  *
  31  * You should have received a copy of the GNU General Public License along
  32  * with this program; if not, write to the Free Software Foundation, Inc.,
  33  * 675 Mass Ave, Cambridge, MA 02139, USA.
  34  */
  35
  36 #ifndef __ASM_ARCH_OMAP_HARDWARE_H
  37 #define __ASM_ARCH_OMAP_HARDWARE_H
  38
  39 #include <asm/sizes.h>
  40 #include <linux/config.h>
  41 #ifndef __ASSEMBLER__
  42 #include <asm/types.h>
  43 #include <asm/arch/cpu.h>
  44 #endif
  45 #include <asm/arch/io.h>
  46
  47 /*
  48  * ---------------------------------------------------------------------------
  49  * Common definitions for all OMAP processors
  50  * NOTE: Put all processor or board specific parts to the special header
  51  *       files.
  52  * ---------------------------------------------------------------------------
  53  */
  54
  55 /*
  56  * ----------------------------------------------------------------------------
  57  * Clocks
  58  * ----------------------------------------------------------------------------
  59  */
  60 #define CLKGEN_REG_BASE         (0xfffece00)
  61 #define ARM_CKCTL               (CLKGEN_REG_BASE + 0x0)
  62 #define ARM_IDLECT1             (CLKGEN_REG_BASE + 0x4)
  63 #define ARM_IDLECT2             (CLKGEN_REG_BASE + 0x8)
  64 #define ARM_EWUPCT              (CLKGEN_REG_BASE + 0xC)
  65 #define ARM_RSTCT1              (CLKGEN_REG_BASE + 0x10)
  66 #define ARM_RSTCT2              (CLKGEN_REG_BASE + 0x14)
  67 #define ARM_SYSST               (CLKGEN_REG_BASE + 0x18)
  68 #define ARM_IDLECT3             (CLKGEN_REG_BASE + 0x24)
  69
  70 #define CK_RATEF                1
  71 #define CK_IDLEF                2
  72 #define CK_ENABLEF              4
  73 #define CK_SELECTF              8
  74 #define SETARM_IDLE_SHIFT
  75
  76 /* DPLL control registers */
  77 #define DPLL_CTL                (0xfffecf00)
  78
  79 /* DSP clock control */
  80 #define DSP_CONFIG_REG_BASE     (0xe1008000)
  81 #define DSP_IDLECT1             (DSP_CONFIG_REG_BASE + 0x4)
  82 #define DSP_IDLECT2             (DSP_CONFIG_REG_BASE + 0x8)
  83
  84 /*
  85  * ---------------------------------------------------------------------------
  86  * UPLD
  87  * ---------------------------------------------------------------------------
  88  */
  89 #define ULPD_REG_BASE           (0xfffe0800)
  90 #define ULPD_IT_STATUS          (ULPD_REG_BASE + 0x14)
  91 #define ULPD_CLOCK_CTRL         (ULPD_REG_BASE + 0x30)
  92 #       define DIS_USB_PVCI_CLK         (1 << 5)        /* no USB/FAC synch */
  93 #       define USB_MCLK_EN              (1 << 4)        /* enable W4_USB_CLKO */
  94 #define ULPD_SOFT_REQ           (ULPD_REG_BASE + 0x34)
  95 #       define SOFT_UDC_REQ             (1 << 4)
  96 #       define SOFT_USB_CLK_REQ         (1 << 3)
  97 #       define SOFT_DPLL_REQ            (1 << 0)
  98 #define ULPD_DPLL_CTRL          (ULPD_REG_BASE + 0x3c)
  99 #define ULPD_STATUS_REQ         (ULPD_REG_BASE + 0x40)
 100 #define ULPD_APLL_CTRL          (ULPD_REG_BASE + 0x4c)
 101 #define ULPD_POWER_CTRL         (ULPD_REG_BASE + 0x50)
 102 #define ULPD_SOFT_DISABLE_REQ_REG       (ULPD_REG_BASE + 0x68)
 103 #       define DIS_MMC2_DPLL_REQ        (1 << 11)
 104 #       define DIS_MMC1_DPLL_REQ        (1 << 10)
 105 #       define DIS_UART3_DPLL_REQ       (1 << 9)
 106 #       define DIS_UART2_DPLL_REQ       (1 << 8)
 107 #       define DIS_UART1_DPLL_REQ       (1 << 7)
 108 #       define DIS_USB_HOST_DPLL_REQ    (1 << 6)
 109 #define ULPD_SDW_CLK_DIV_CTRL_SEL       (ULPD_REG_BASE + 0x74)
 110 #define ULPD_CAM_CLK_CTRL       (ULPD_REG_BASE + 0x7c)
 111
 112 /*
 113  * ---------------------------------------------------------------------------
 114  * Watchdog timer
 115  * ---------------------------------------------------------------------------
 116  */
 117
 118 /* Watchdog timer within the OMAP3.2 gigacell */
 119 #define OMAP_MPU_WATCHDOG_BASE  (0xfffec800)
 120 #define OMAP_WDT_TIMER          (OMAP_MPU_WATCHDOG_BASE + 0x0)
 121 #define OMAP_WDT_LOAD_TIM       (OMAP_MPU_WATCHDOG_BASE + 0x4)
 122 #define OMAP_WDT_READ_TIM       (OMAP_MPU_WATCHDOG_BASE + 0x4)
 123 #define OMAP_WDT_TIMER_MODE     (OMAP_MPU_WATCHDOG_BASE + 0x8)
 124
 125 /*
 126  * ---------------------------------------------------------------------------
 127  * Interrupts
 128  * ---------------------------------------------------------------------------
 129  */
 130 #define OMAP_IH1_BASE           0xfffecb00
 131 #define OMAP_IH2_BASE           0xfffe0000
 132
 133 #define OMAP_IH1_ITR            (OMAP_IH1_BASE + 0x00)
 134 #define OMAP_IH1_MIR            (OMAP_IH1_BASE + 0x04)
 135 #define OMAP_IH1_SIR_IRQ        (OMAP_IH1_BASE + 0x10)
 136 #define OMAP_IH1_SIR_FIQ        (OMAP_IH1_BASE + 0x14)
 137 #define OMAP_IH1_CONTROL        (OMAP_IH1_BASE + 0x18)
 138 #define OMAP_IH1_ILR0           (OMAP_IH1_BASE + 0x1c)
 139 #define OMAP_IH1_ISR            (OMAP_IH1_BASE + 0x9c)
 140
 141 #define OMAP_IH2_ITR            (OMAP_IH2_BASE + 0x00)
 142 #define OMAP_IH2_MIR            (OMAP_IH2_BASE + 0x04)
 143 #define OMAP_IH2_SIR_IRQ        (OMAP_IH2_BASE + 0x10)
 144 #define OMAP_IH2_SIR_FIQ        (OMAP_IH2_BASE + 0x14)
 145 #define OMAP_IH2_CONTROL        (OMAP_IH2_BASE + 0x18)
 146 #define OMAP_IH2_ILR0           (OMAP_IH2_BASE + 0x1c)
 147 #define OMAP_IH2_ISR            (OMAP_IH2_BASE + 0x9c)
 148
 149 #define IRQ_ITR_REG_OFFSET      0x00
 150 #define IRQ_MIR_REG_OFFSET      0x04
 151 #define IRQ_SIR_IRQ_REG_OFFSET  0x10
 152 #define IRQ_SIR_FIQ_REG_OFFSET  0x14
 153 #define IRQ_CONTROL_REG_OFFSET  0x18
 154 #define IRQ_ISR_REG_OFFSET      0x9c
 155 #define IRQ_ILR0_REG_OFFSET     0x1c
 156 #define IRQ_GMR_REG_OFFSET      0xa0
 157
 158 /*
 159  * ----------------------------------------------------------------------------
 160  * System control registers
 161  * ----------------------------------------------------------------------------
 162  */
 163 #define MOD_CONF_CTRL_0         0xfffe1080
 164 #define MOD_CONF_CTRL_1         0xfffe1110
 165
 166 /*
 167  * ----------------------------------------------------------------------------
 168  * Pin multiplexing registers
 169  * ----------------------------------------------------------------------------
 170  */
 171 #define FUNC_MUX_CTRL_0         0xfffe1000
 172 #define FUNC_MUX_CTRL_1         0xfffe1004
 173 #define FUNC_MUX_CTRL_2         0xfffe1008
 174 #define COMP_MODE_CTRL_0        0xfffe100c
 175 #define FUNC_MUX_CTRL_3         0xfffe1010
 176 #define FUNC_MUX_CTRL_4         0xfffe1014
 177 #define FUNC_MUX_CTRL_5         0xfffe1018
 178 #define FUNC_MUX_CTRL_6         0xfffe101C
 179 #define FUNC_MUX_CTRL_7         0xfffe1020
 180 #define FUNC_MUX_CTRL_8         0xfffe1024
 181 #define FUNC_MUX_CTRL_9         0xfffe1028
 182 #define FUNC_MUX_CTRL_A         0xfffe102C
 183 #define FUNC_MUX_CTRL_B         0xfffe1030
 184 #define FUNC_MUX_CTRL_C         0xfffe1034
 185 #define FUNC_MUX_CTRL_D         0xfffe1038
 186 #define PULL_DWN_CTRL_0         0xfffe1040
 187 #define PULL_DWN_CTRL_1         0xfffe1044
 188 #define PULL_DWN_CTRL_2         0xfffe1048
 189 #define PULL_DWN_CTRL_3         0xfffe104c
 190 #define PULL_DWN_CTRL_4         0xfffe10ac
 191
 192 /* OMAP-1610 specific multiplexing registers */
 193 #define FUNC_MUX_CTRL_E         0xfffe1090
 194 #define FUNC_MUX_CTRL_F         0xfffe1094
 195 #define FUNC_MUX_CTRL_10        0xfffe1098
 196 #define FUNC_MUX_CTRL_11        0xfffe109c
 197 #define FUNC_MUX_CTRL_12        0xfffe10a0
 198 #define PU_PD_SEL_0             0xfffe10b4
 199 #define PU_PD_SEL_1             0xfffe10b8
 200 #define PU_PD_SEL_2             0xfffe10bc
 201 #define PU_PD_SEL_3             0xfffe10c0
 202 #define PU_PD_SEL_4             0xfffe10c4
 203
 204 /* Timer32K for 1610 and 1710*/
 205 #define OMAP_TIMER32K_BASE      0xFFFBC400
 206
 207 /*
 208  * ---------------------------------------------------------------------------
 209  * TIPB bus interface
 210  * ---------------------------------------------------------------------------
 211  */
 212 #define TIPB_PUBLIC_CNTL_BASE           0xfffed300
 213 #define MPU_PUBLIC_TIPB_CNTL            (TIPB_PUBLIC_CNTL_BASE + 0x8)
 214 #define TIPB_PRIVATE_CNTL_BASE          0xfffeca00
 215 #define MPU_PRIVATE_TIPB_CNTL           (TIPB_PRIVATE_CNTL_BASE + 0x8)
 216
 217 /*
 218  * ----------------------------------------------------------------------------
 219  * MPUI interface
 220  * ----------------------------------------------------------------------------
 221  */
 222 #define MPUI_BASE                       (0xfffec900)
 223 #define MPUI_CTRL                       (MPUI_BASE + 0x0)
 224 #define MPUI_DEBUG_ADDR                 (MPUI_BASE + 0x4)
 225 #define MPUI_DEBUG_DATA                 (MPUI_BASE + 0x8)
 226 #define MPUI_DEBUG_FLAG                 (MPUI_BASE + 0xc)
 227 #define MPUI_STATUS_REG                 (MPUI_BASE + 0x10)
 228 #define MPUI_DSP_STATUS                 (MPUI_BASE + 0x14)
 229 #define MPUI_DSP_BOOT_CONFIG            (MPUI_BASE + 0x18)
 230 #define MPUI_DSP_API_CONFIG             (MPUI_BASE + 0x1c)
 231
 232 /*
 233  * ----------------------------------------------------------------------------
 234  * LED Pulse Generator
 235  * ----------------------------------------------------------------------------
 236  */
 237 #define OMAP_LPG1_BASE                  0xfffbd000
 238 #define OMAP_LPG2_BASE                  0xfffbd800
 239 #define OMAP_LPG1_LCR                   (OMAP_LPG1_BASE + 0x00)
 240 #define OMAP_LPG1_PMR                   (OMAP_LPG1_BASE + 0x04)
 241 #define OMAP_LPG2_LCR                   (OMAP_LPG2_BASE + 0x00)
 242 #define OMAP_LPG2_PMR                   (OMAP_LPG2_BASE + 0x04)
 243
 244 #ifndef __ASSEMBLER__
 245
 246 /*
 247  * ---------------------------------------------------------------------------
 248  * Serial ports
 249  * ---------------------------------------------------------------------------
 250  */
 251 #define OMAP_UART1_BASE         (unsigned char *)0xfffb0000
 252 #define OMAP_UART2_BASE         (unsigned char *)0xfffb0800
 253 #define OMAP_UART3_BASE         (unsigned char *)0xfffb9800
 254 #define OMAP_MAX_NR_PORTS       3
 255 #define OMAP1510_BASE_BAUD      (12000000/16)
 256 #define OMAP16XX_BASE_BAUD      (48000000/16)
 257
 258 #define is_omap_port(p) ({int __ret = 0;                        \
 259                         if (p == IO_ADDRESS(OMAP_UART1_BASE) || \
 260                             p == IO_ADDRESS(OMAP_UART2_BASE) || \
 261                             p == IO_ADDRESS(OMAP_UART3_BASE))   \
 262                                 __ret = 1;                      \
 263                         __ret;                                  \
 264                         })
 265
 266 /*
 267  * ---------------------------------------------------------------------------
 268  * Processor specific defines
 269  * ---------------------------------------------------------------------------
 270  */
 271 #ifdef CONFIG_ARCH_OMAP730
 272 #include "omap730.h"
 273 #endif
 274
 275 #ifdef CONFIG_ARCH_OMAP1510
 276 #include "omap1510.h"
 277 #endif
 278
 279 #ifdef CONFIG_ARCH_OMAP16XX
 280 #include "omap16xx.h"
 281 #endif
 282
 283 /*
 284  * ---------------------------------------------------------------------------
 285  * Board specific defines
 286  * ---------------------------------------------------------------------------
 287  */
 288
 289 #ifdef CONFIG_MACH_OMAP_INNOVATOR
 290 #include "board-innovator.h"
 291 #endif
 292
 293 #ifdef CONFIG_MACH_OMAP_H2
 294 #include "board-h2.h"
 295 #endif
 296
 297 #ifdef CONFIG_MACH_OMAP_PERSEUS2
 298 #include "board-perseus2.h"
 299 #endif
 300
 301 #ifdef CONFIG_MACH_OMAP_H3
 302 #include "board-h3.h"
 303 #endif
 304
 305 #ifdef CONFIG_MACH_OMAP_H4
 306 #include "board-h4.h"
 307 #error "Support for H4 board not yet implemented."
 308 #endif
 309
 310 #ifdef CONFIG_MACH_OMAP_OSK
 311 #include "board-osk.h"
 312 #endif
 313
 314 #ifdef CONFIG_MACH_VOICEBLUE
 315 #include "board-voiceblue.h"
 316 #endif
 317
 318 #ifdef CONFIG_MACH_NETSTAR
 319 #include "board-netstar.h"
 320 #endif
 321
 322 #endif /* !__ASSEMBLER__ */
 323
 324 #endif  /* __ASM_ARCH_OMAP_HARDWARE_H */