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[TG3]: Add tagged status support.
[linux-2.6/verdex.git] / include / asm-arm / arch-omap / mux.h
blob39f99decbb7ba2f64d69108ea7b5a7f579f4554d
1 /*
2 * linux/include/asm-arm/arch-omap/mux.h
3 *
4 * Table of the Omap register configurations for the FUNC_MUX and
5 * PULL_DWN combinations.
6 *
7 * Copyright (C) 2003 Nokia Corporation
8 *
9 * Written by Tony Lindgren <tony.lindgren@nokia.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 *
25 * NOTE: Please use the following naming style for new pin entries.
26 * For example, W8_1610_MMC2_DAT0, where:
27 * - W8 = ball
28 * - 1610 = 1510 or 1610, none if common for both 1510 and 1610
29 * - MMC2_DAT0 = function
30 *
31 * Change log:
32 * Added entry for the I2C interface. (02Feb 2004)
33 * Copyright (C) 2004 Texas Instruments
34 *
35 * Added entry for the keypad and uwire CS1. (09Mar 2004)
36 * Copyright (C) 2004 Texas Instruments
37 *
38 */
39
40 #ifndef __ASM_ARCH_MUX_H
41 #define __ASM_ARCH_MUX_H
42
43 #define PU_PD_SEL_NA 0 /* No pu_pd reg available */
44 #define PULL_DWN_CTRL_NA 0 /* No pull-down control needed */
45
46 #ifdef CONFIG_OMAP_MUX_DEBUG
47 #define MUX_REG(reg, mode_offset, mode) .mux_reg_name = "FUNC_MUX_CTRL_"#reg, \
48 .mux_reg = FUNC_MUX_CTRL_##reg, \
49 .mask_offset = mode_offset, \
50 .mask = mode,
51
52 #define PULL_REG(reg, bit, status) .pull_name = "PULL_DWN_CTRL_"#reg, \
53 .pull_reg = PULL_DWN_CTRL_##reg, \
54 .pull_bit = bit, \
55 .pull_val = status,
56
57 #define PU_PD_REG(reg, status) .pu_pd_name = "PU_PD_SEL_"#reg, \
58 .pu_pd_reg = PU_PD_SEL_##reg, \
59 .pu_pd_val = status,
60
61 #else
62
63 #define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \
64 .mask_offset = mode_offset, \
65 .mask = mode,
66
67 #define PULL_REG(reg, bit, status) .pull_reg = PULL_DWN_CTRL_##reg, \
68 .pull_bit = bit, \
69 .pull_val = status,
70
71 #define PU_PD_REG(reg, status) .pu_pd_reg = PU_PD_SEL_##reg, \
72 .pu_pd_val = status,
73
74 #endif /* CONFIG_OMAP_MUX_DEBUG */
75
76 #define MUX_CFG(desc, mux_reg, mode_offset, mode, \
77 pull_reg, pull_bit, pull_status, \
78 pu_pd_reg, pu_pd_status, debug_status) \
79 { \
80 .name = desc, \
81 .debug = debug_status, \
82 MUX_REG(mux_reg, mode_offset, mode) \
83 PULL_REG(pull_reg, pull_bit, pull_status) \
84 PU_PD_REG(pu_pd_reg, pu_pd_status) \
85 },
86
87 #define PULL_DISABLED 0
88 #define PULL_ENABLED 1
89
90 #define PULL_DOWN 0
91 #define PULL_UP 1
92
93 typedef struct {
94 char *name;
95 unsigned char busy;
96 unsigned char debug;
97
98 const char *mux_reg_name;
99 const unsigned int mux_reg;
100 const unsigned char mask_offset;
101 const unsigned char mask;
102
103 const char *pull_name;
104 const unsigned int pull_reg;
105 const unsigned char pull_val;
106 const unsigned char pull_bit;
107
108 const char *pu_pd_name;
109 const unsigned int pu_pd_reg;
110 const unsigned char pu_pd_val;
111 } reg_cfg_set;
112
113 /*
114 * Lookup table for FUNC_MUX and PULL_DWN register combinations for each
115 * device. See also reg_cfg_table below for the register values.
116 */
117 typedef enum {
118 /* UART1 (BT_UART_GATING)*/
119 UART1_TX = 0,
120 UART1_RTS,
121
122 /* UART2 (COM_UART_GATING)*/
123 UART2_TX,
124 UART2_RX,
125 UART2_CTS,
126 UART2_RTS,
127
128 /* UART3 (GIGA_UART_GATING) */
129 UART3_TX,
130 UART3_RX,
131 UART3_CTS,
132 UART3_RTS,
133 UART3_CLKREQ,
134 UART3_BCLK, /* 12MHz clock out */
135 Y15_1610_UART3_RTS,
136
137 /* PWT & PWL */
138 PWT,
139 PWL,
140
141 /* USB master generic */
142 R18_USB_VBUS,
143 R18_1510_USB_GPIO0,
144 W4_USB_PUEN,
145 W4_USB_CLKO,
146 W4_USB_HIGHZ,
147 W4_GPIO58,
148
149 /* USB1 master */
150 USB1_SUSP,
151 USB1_SEO,
152 W13_1610_USB1_SE0,
153 USB1_TXEN,
154 USB1_TXD,
155 USB1_VP,
156 USB1_VM,
157 USB1_RCV,
158 USB1_SPEED,
159 R13_1610_USB1_SPEED,
160 R13_1710_USB1_SE0,
161
162 /* USB2 master */
163 USB2_SUSP,
164 USB2_VP,
165 USB2_TXEN,
166 USB2_VM,
167 USB2_RCV,
168 USB2_SEO,
169 USB2_TXD,
170
171 /* OMAP-1510 GPIO */
172 R18_1510_GPIO0,
173 R19_1510_GPIO1,
174 M14_1510_GPIO2,
175
176 /* OMAP1610 GPIO */
177 P18_1610_GPIO3,
178 Y15_1610_GPIO17,
179
180 /* OMAP-1710 GPIO */
181 R18_1710_GPIO0,
182 V2_1710_GPIO10,
183 N21_1710_GPIO14,
184 W15_1710_GPIO40,
185
186 /* MPUIO */
187 MPUIO2,
188 MPUIO4,
189 MPUIO5,
190 T20_1610_MPUIO5,
191 W11_1610_MPUIO6,
192 V10_1610_MPUIO7,
193 W11_1610_MPUIO9,
194 V10_1610_MPUIO10,
195 W10_1610_MPUIO11,
196 E20_1610_MPUIO13,
197 U20_1610_MPUIO14,
198 E19_1610_MPUIO15,
199
200 /* MCBSP2 */
201 MCBSP2_CLKR,
202 MCBSP2_CLKX,
203 MCBSP2_DR,
204 MCBSP2_DX,
205 MCBSP2_FSR,
206 MCBSP2_FSX,
207
208 /* MCBSP3 */
209 MCBSP3_CLKX,
210
211 /* Misc ballouts */
212 BALLOUT_V8_ARMIO3,
213
214 /* OMAP-1610 MMC2 */
215 W8_1610_MMC2_DAT0,
216 V8_1610_MMC2_DAT1,
217 W15_1610_MMC2_DAT2,
218 R10_1610_MMC2_DAT3,
219 Y10_1610_MMC2_CLK,
220 Y8_1610_MMC2_CMD,
221 V9_1610_MMC2_CMDDIR,
222 V5_1610_MMC2_DATDIR0,
223 W19_1610_MMC2_DATDIR1,
224 R18_1610_MMC2_CLKIN,
225
226 /* OMAP-1610 External Trace Interface */
227 M19_1610_ETM_PSTAT0,
228 L15_1610_ETM_PSTAT1,
229 L18_1610_ETM_PSTAT2,
230 L19_1610_ETM_D0,
231 J19_1610_ETM_D6,
232 J18_1610_ETM_D7,
233
234 /* OMAP-1610 GPIO */
235 P20_1610_GPIO4,
236 V9_1610_GPIO7,
237 W8_1610_GPIO9,
238 N19_1610_GPIO13,
239 P10_1610_GPIO22,
240 V5_1610_GPIO24,
241 AA20_1610_GPIO_41,
242 W19_1610_GPIO48,
243 M7_1610_GPIO62,
244
245 /* OMAP-1610 uWire */
246 V19_1610_UWIRE_SCLK,
247 U18_1610_UWIRE_SDI,
248 W21_1610_UWIRE_SDO,
249 N14_1610_UWIRE_CS0,
250 P15_1610_UWIRE_CS0,
251 N15_1610_UWIRE_CS1,
252
253 /* OMAP-1610 Flash */
254 L3_1610_FLASH_CS2B_OE,
255 M8_1610_FLASH_CS2B_WE,
256
257 /* First MMC */
258 MMC_CMD,
259 MMC_DAT1,
260 MMC_DAT2,
261 MMC_DAT0,
262 MMC_CLK,
263 MMC_DAT3,
264
265 /* OMAP-1710 MMC CMDDIR and DATDIR0 */
266 M15_1710_MMC_CLKI,
267 P19_1710_MMC_CMDDIR,
268 P20_1710_MMC_DATDIR0,
269
270 /* OMAP-1610 USB0 alternate pin configuration */
271 W9_USB0_TXEN,
272 AA9_USB0_VP,
273 Y5_USB0_RCV,
274 R9_USB0_VM,
275 V6_USB0_TXD,
276 W5_USB0_SE0,
277 V9_USB0_SPEED,
278 V9_USB0_SUSP,
279
280 /* USB2 */
281 W9_USB2_TXEN,
282 AA9_USB2_VP,
283 Y5_USB2_RCV,
284 R9_USB2_VM,
285 V6_USB2_TXD,
286 W5_USB2_SE0,
287
288 /* UART1 1610 */
289
290 R13_1610_UART1_TX,
291 V14_1610_UART1_RX,
292 R14_1610_UART1_CTS,
293 AA15_1610_UART1_RTS,
294
295 /* I2C OMAP-1610 */
296 I2C_SCL,
297 I2C_SDA,
298
299 /* Keypad */
300 F18_1610_KBC0,
301 D20_1610_KBC1,
302 D19_1610_KBC2,
303 E18_1610_KBC3,
304 C21_1610_KBC4,
305 G18_1610_KBR0,
306 F19_1610_KBR1,
307 H14_1610_KBR2,
308 E20_1610_KBR3,
309 E19_1610_KBR4,
310 N19_1610_KBR5,
311
312 /* Power management */
313 T20_1610_LOW_PWR,
314
315 /* MCLK Settings */
316 V5_1710_MCLK_ON,
317 V5_1710_MCLK_OFF,
318 R10_1610_MCLK_ON,
319 R10_1610_MCLK_OFF,
320
321 /* CompactFlash controller */
322 P11_1610_CF_CD2,
323 R11_1610_CF_IOIS16,
324 V10_1610_CF_IREQ,
325 W10_1610_CF_RESET,
326 W11_1610_CF_CD1,
327 } reg_cfg_t;
328
329 #if defined(__MUX_C__) && defined(CONFIG_OMAP_MUX)
330
331 /*
332 * Table of various FUNC_MUX and PULL_DWN combinations for each device.
333 * See also reg_cfg_t above for the lookup table.
334 */
335 static reg_cfg_set __initdata_or_module
336 reg_cfg_table[] = {
337 /*
338 * description mux mode mux pull pull pull pu_pd pu dbg
339 * reg offset mode reg bit ena reg
340 */
341 MUX_CFG("UART1_TX", 9, 21, 1, 2, 3, 0, NA, 0, 0)
342 MUX_CFG("UART1_RTS", 9, 12, 1, 2, 0, 0, NA, 0, 0)
343
344 /* UART2 (COM_UART_GATING), conflicts with USB2 */
345 MUX_CFG("UART2_TX", C, 27, 1, 3, 3, 0, NA, 0, 0)
346 MUX_CFG("UART2_RX", C, 18, 0, 3, 1, 1, NA, 0, 0)
347 MUX_CFG("UART2_CTS", C, 21, 0, 3, 1, 1, NA, 0, 0)
348 MUX_CFG("UART2_RTS", C, 24, 1, 3, 2, 0, NA, 0, 0)
349
350 /* UART3 (GIGA_UART_GATING) */
351 MUX_CFG("UART3_TX", 6, 0, 1, 0, 30, 0, NA, 0, 0)
352 MUX_CFG("UART3_RX", 6, 3, 0, 0, 31, 1, NA, 0, 0)
353 MUX_CFG("UART3_CTS", 5, 12, 2, 0, 24, 0, NA, 0, 0)
354 MUX_CFG("UART3_RTS", 5, 15, 2, 0, 25, 0, NA, 0, 0)
355 MUX_CFG("UART3_CLKREQ", 9, 27, 0, 2, 5, 0, NA, 0, 0)
356 MUX_CFG("UART3_BCLK", A, 0, 0, 2, 6, 0, NA, 0, 0)
357 MUX_CFG("Y15_1610_UART3_RTS", A, 0, 1, 2, 6, 0, NA, 0, 0)
358
359 /* PWT & PWL, conflicts with UART3 */
360 MUX_CFG("PWT", 6, 0, 2, 0, 30, 0, NA, 0, 0)
361 MUX_CFG("PWL", 6, 3, 1, 0, 31, 1, NA, 0, 0)
362
363 /* USB internal master generic */
364 MUX_CFG("R18_USB_VBUS", 7, 9, 2, 1, 11, 0, NA, 0, 1)
365 MUX_CFG("R18_1510_USB_GPIO0", 7, 9, 0, 1, 11, 1, NA, 0, 1)
366 /* works around erratum: W4_USB_PUEN and W4_USB_PUDIS are switched! */
367 MUX_CFG("W4_USB_PUEN", D, 3, 3, 3, 5, 1, NA, 0, 1)
368 MUX_CFG("W4_USB_CLKO", D, 3, 1, 3, 5, 0, NA, 0, 1)
369 MUX_CFG("W4_USB_HIGHZ", D, 3, 4, 3, 5, 0, 3, 0, 1)
370 MUX_CFG("W4_GPIO58", D, 3, 7, 3, 5, 0, 3, 0, 1)
371
372 /* USB1 master */
373 MUX_CFG("USB1_SUSP", 8, 27, 2, 1, 27, 0, NA, 0, 1)
374 MUX_CFG("USB1_SE0", 9, 0, 2, 1, 28, 0, NA, 0, 1)
375 MUX_CFG("W13_1610_USB1_SE0", 9, 0, 4, 1, 28, 0, NA, 0, 1)
376 MUX_CFG("USB1_TXEN", 9, 3, 2, 1, 29, 0, NA, 0, 1)
377 MUX_CFG("USB1_TXD", 9, 24, 1, 2, 4, 0, NA, 0, 1)
378 MUX_CFG("USB1_VP", A, 3, 1, 2, 7, 0, NA, 0, 1)
379 MUX_CFG("USB1_VM", A, 6, 1, 2, 8, 0, NA, 0, 1)
380 MUX_CFG("USB1_RCV", A, 9, 1, 2, 9, 0, NA, 0, 1)
381 MUX_CFG("USB1_SPEED", A, 12, 2, 2, 10, 0, NA, 0, 1)
382 MUX_CFG("R13_1610_USB1_SPEED", A, 12, 5, 2, 10, 0, NA, 0, 1)
383 MUX_CFG("R13_1710_USB1_SEO", A, 12, 5, 2, 10, 0, NA, 0, 1)
384
385 /* USB2 master */
386 MUX_CFG("USB2_SUSP", B, 3, 1, 2, 17, 0, NA, 0, 1)
387 MUX_CFG("USB2_VP", B, 6, 1, 2, 18, 0, NA, 0, 1)
388 MUX_CFG("USB2_TXEN", B, 9, 1, 2, 19, 0, NA, 0, 1)
389 MUX_CFG("USB2_VM", C, 18, 1, 3, 0, 0, NA, 0, 1)
390 MUX_CFG("USB2_RCV", C, 21, 1, 3, 1, 0, NA, 0, 1)
391 MUX_CFG("USB2_SE0", C, 24, 2, 3, 2, 0, NA, 0, 1)
392 MUX_CFG("USB2_TXD", C, 27, 2, 3, 3, 0, NA, 0, 1)
393
394 /* OMAP-1510 GPIO */
395 MUX_CFG("R18_1510_GPIO0", 7, 9, 0, 1, 11, 1, 0, 0, 1)
396 MUX_CFG("R19_1510_GPIO1", 7, 6, 0, 1, 10, 1, 0, 0, 1)
397 MUX_CFG("M14_1510_GPIO2", 7, 3, 0, 1, 9, 1, 0, 0, 1)
398
399 /* OMAP1610 GPIO */
400 MUX_CFG("P18_1610_GPIO3", 7, 0, 0, 1, 8, 0, NA, 0, 1)
401 MUX_CFG("Y15_1610_GPIO17", A, 0, 7, 2, 6, 0, NA, 0, 1)
402
403 /* OMAP-1710 GPIO */
404 MUX_CFG("R18_1710_GPIO0", 7, 9, 0, 1, 11, 1, 1, 1, 1)
405 MUX_CFG("V2_1710_GPIO10", F, 27, 1, 4, 3, 1, 4, 1, 1)
406 MUX_CFG("N21_1710_GPIO14", 6, 9, 0, 1, 1, 1, 1, 1, 1)
407 MUX_CFG("W15_1710_GPIO40", 9, 27, 7, 2, 5, 1, 2, 1, 1)
408
409 /* MPUIO */
410 MUX_CFG("MPUIO2", 7, 18, 0, 1, 1, 1, NA, 0, 1)
411 MUX_CFG("MPUIO4", 7, 15, 0, 1, 13, 1, NA, 0, 1)
412 MUX_CFG("MPUIO5", 7, 12, 0, 1, 12, 1, NA, 0, 1)
413
414 MUX_CFG("T20_1610_MPUIO5", 7, 12, 0, 1, 12, 0, 3, 0, 1)
415 MUX_CFG("W11_1610_MPUIO6", 10, 15, 2, 3, 8, 0, 3, 0, 1)
416 MUX_CFG("V10_1610_MPUIO7", A, 24, 2, 2, 14, 0, 2, 0, 1)
417 MUX_CFG("W11_1610_MPUIO9", 10, 15, 1, 3, 8, 0, 3, 0, 1)
418 MUX_CFG("V10_1610_MPUIO10", A, 24, 1, 2, 14, 0, 2, 0, 1)
419 MUX_CFG("W10_1610_MPUIO11", A, 18, 2, 2, 11, 0, 2, 0, 1)
420 MUX_CFG("E20_1610_MPUIO13", 3, 21, 1, 0, 7, 0, 0, 0, 1)
421 MUX_CFG("U20_1610_MPUIO14", 9, 6, 6, 0, 30, 0, 0, 0, 1)
422 MUX_CFG("E19_1610_MPUIO15", 3, 18, 1, 0, 6, 0, 0, 0, 1)
423
424 /* MCBSP2 */
425 MUX_CFG("MCBSP2_CLKR", C, 6, 0, 2, 27, 1, NA, 0, 1)
426 MUX_CFG("MCBSP2_CLKX", C, 9, 0, 2, 29, 1, NA, 0, 1)
427 MUX_CFG("MCBSP2_DR", C, 0, 0, 2, 26, 1, NA, 0, 1)
428 MUX_CFG("MCBSP2_DX", C, 15, 0, 2, 31, 1, NA, 0, 1)
429 MUX_CFG("MCBSP2_FSR", C, 12, 0, 2, 30, 1, NA, 0, 1)
430 MUX_CFG("MCBSP2_FSX", C, 3, 0, 2, 27, 1, NA, 0, 1)
431
432 /* MCBSP3 NOTE: Mode must 1 for clock */
433 MUX_CFG("MCBSP3_CLKX", 9, 3, 1, 1, 29, 0, NA, 0, 1)
434
435 /* Misc ballouts */
436 MUX_CFG("BALLOUT_V8_ARMIO3", B, 18, 0, 2, 25, 1, NA, 0, 1)
437
438 /* OMAP-1610 MMC2 */
439 MUX_CFG("W8_1610_MMC2_DAT0", B, 21, 6, 2, 23, 1, 2, 1, 1)
440 MUX_CFG("V8_1610_MMC2_DAT1", B, 27, 6, 2, 25, 1, 2, 1, 1)
441 MUX_CFG("W15_1610_MMC2_DAT2", 9, 12, 6, 2, 5, 1, 2, 1, 1)
442 MUX_CFG("R10_1610_MMC2_DAT3", B, 18, 6, 2, 22, 1, 2, 1, 1)
443 MUX_CFG("Y10_1610_MMC2_CLK", B, 3, 6, 2, 17, 0, 2, 0, 1)
444 MUX_CFG("Y8_1610_MMC2_CMD", B, 24, 6, 2, 24, 1, 2, 1, 1)
445 MUX_CFG("V9_1610_MMC2_CMDDIR", B, 12, 6, 2, 20, 0, 2, 1, 1)
446 MUX_CFG("V5_1610_MMC2_DATDIR0", B, 15, 6, 2, 21, 0, 2, 1, 1)
447 MUX_CFG("W19_1610_MMC2_DATDIR1", 8, 15, 6, 1, 23, 0, 1, 1, 1)
448 MUX_CFG("R18_1610_MMC2_CLKIN", 7, 9, 6, 1, 11, 0, 1, 11, 1)
449
450 /* OMAP-1610 External Trace Interface */
451 MUX_CFG("M19_1610_ETM_PSTAT0", 5, 27, 1, 0, 29, 0, 0, 0, 1)
452 MUX_CFG("L15_1610_ETM_PSTAT1", 5, 24, 1, 0, 28, 0, 0, 0, 1)
453 MUX_CFG("L18_1610_ETM_PSTAT2", 5, 21, 1, 0, 27, 0, 0, 0, 1)
454 MUX_CFG("L19_1610_ETM_D0", 5, 18, 1, 0, 26, 0, 0, 0, 1)
455 MUX_CFG("J19_1610_ETM_D6", 5, 0, 1, 0, 20, 0, 0, 0, 1)
456 MUX_CFG("J18_1610_ETM_D7", 5, 27, 1, 0, 19, 0, 0, 0, 1)
457
458 /* OMAP-1610 GPIO */
459 MUX_CFG("P20_1610_GPIO4", 6, 27, 0, 1, 7, 0, 1, 1, 1)
460 MUX_CFG("V9_1610_GPIO7", B, 12, 1, 2, 20, 0, 2, 1, 1)
461 MUX_CFG("W8_1610_GPIO9", B, 21, 0, 2, 23, 0, 2, 1, 1)
462 MUX_CFG("N19_1610_GPIO13", 6, 12, 0, 1, 2, 0, 1, 1, 1)
463 MUX_CFG("P10_1610_GPIO22", C, 0, 7, 2, 26, 0, 2, 1, 1)
464 MUX_CFG("V5_1610_GPIO24", B, 15, 7, 2, 21, 0, 2, 1, 1)
465 MUX_CFG("AA20_1610_GPIO_41", 9, 9, 7, 1, 31, 0, 1, 1, 1)
466 MUX_CFG("W19_1610_GPIO48", 8, 15, 7, 1, 23, 1, 1, 0, 1)
467 MUX_CFG("M7_1610_GPIO62", 10, 0, 0, 4, 24, 0, 4, 0, 1)
468
469 /* OMAP-1610 uWire */
470 MUX_CFG("V19_1610_UWIRE_SCLK", 8, 6, 0, 1, 20, 0, 1, 1, 1)
471 MUX_CFG("U18_1610_UWIRE_SDI", 8, 0, 0, 1, 18, 0, 1, 1, 1)
472 MUX_CFG("W21_1610_UWIRE_SDO", 8, 3, 0, 1, 19, 0, 1, 1, 1)
473 MUX_CFG("N14_1610_UWIRE_CS0", 8, 9, 1, 1, 21, 0, 1, 1, 1)
474 MUX_CFG("P15_1610_UWIRE_CS3", 8, 12, 1, 1, 22, 0, 1, 1, 1)
475 MUX_CFG("N15_1610_UWIRE_CS1", 7, 18, 2, 1, 14, 0, NA, 0, 1)
476
477 /* OMAP-1610 Flash */
478 MUX_CFG("L3_1610_FLASH_CS2B_OE",10, 6, 1, NA, 0, 0, NA, 0, 1)
479 MUX_CFG("M8_1610_FLASH_CS2B_WE",10, 3, 1, NA, 0, 0, NA, 0, 1)
480
481 /* First MMC interface, same on 1510, 1610 and 1710 */
482 MUX_CFG("MMC_CMD", A, 27, 0, 2, 15, 1, 2, 1, 1)
483 MUX_CFG("MMC_DAT1", A, 24, 0, 2, 14, 1, 2, 1, 1)
484 MUX_CFG("MMC_DAT2", A, 18, 0, 2, 12, 1, 2, 1, 1)
485 MUX_CFG("MMC_DAT0", B, 0, 0, 2, 16, 1, 2, 1, 1)
486 MUX_CFG("MMC_CLK", A, 21, 0, NA, 0, 0, NA, 0, 1)
487 MUX_CFG("MMC_DAT3", 10, 15, 0, 3, 8, 1, 3, 1, 1)
488 MUX_CFG("M15_1710_MMC_CLKI", 6, 21, 2, 0, 0, 0, NA, 0, 1)
489 MUX_CFG("P19_1710_MMC_CMDDIR", 6, 24, 6, 0, 0, 0, NA, 0, 1)
490 MUX_CFG("P20_1710_MMC_DATDIR0", 6, 27, 5, 0, 0, 0, NA, 0, 1)
491
492 /* OMAP-1610 USB0 alternate configuration */
493 MUX_CFG("W9_USB0_TXEN", B, 9, 5, 2, 19, 0, 2, 0, 1)
494 MUX_CFG("AA9_USB0_VP", B, 6, 5, 2, 18, 0, 2, 0, 1)
495 MUX_CFG("Y5_USB0_RCV", C, 21, 5, 3, 1, 0, 1, 0, 1)
496 MUX_CFG("R9_USB0_VM", C, 18, 5, 3, 0, 0, 3, 0, 1)
497 MUX_CFG("V6_USB0_TXD", C, 27, 5, 3, 3, 0, 3, 0, 1)
498 MUX_CFG("W5_USB0_SE0", C, 24, 5, 3, 2, 0, 3, 0, 1)
499 MUX_CFG("V9_USB0_SPEED", B, 12, 5, 2, 20, 0, 2, 0, 1)
500 MUX_CFG("Y10_USB0_SUSP", B, 3, 5, 2, 17, 0, 2, 0, 1)
501
502 /* USB2 interface */
503 MUX_CFG("W9_USB2_TXEN", B, 9, 1, NA, 0, 0, NA, 0, 1)
504 MUX_CFG("AA9_USB2_VP", B, 6, 1, NA, 0, 0, NA, 0, 1)
505 MUX_CFG("Y5_USB2_RCV", C, 21, 1, NA, 0, 0, NA, 0, 1)
506 MUX_CFG("R8_USB2_VM", C, 18, 1, NA, 0, 0, NA, 0, 1)
507 MUX_CFG("V6_USB2_TXD", C, 27, 2, NA, 0, 0, NA, 0, 1)
508 MUX_CFG("W5_USB2_SE0", C, 24, 2, NA, 0, 0, NA, 0, 1)
509
510
511 /* UART1 */
512 MUX_CFG("R13_1610_UART1_TX", A, 12, 6, 2, 10, 0, 2, 10, 1)
513 MUX_CFG("V14_1610_UART1_RX", 9, 18, 0, 2, 2, 0, 2, 2, 1)
514 MUX_CFG("R14_1610_UART1_CTS", 9, 15, 0, 2, 1, 0, 2, 1, 1)
515 MUX_CFG("AA15_1610_UART1_RTS", 9, 12, 1, 2, 0, 0, 2, 0, 1)
516
517 /* I2C interface */
518 MUX_CFG("I2C_SCL", 7, 24, 0, NA, 0, 0, NA, 0, 0)
519 MUX_CFG("I2C_SDA", 7, 27, 0, NA, 0, 0, NA, 0, 0)
520
521 /* Keypad */
522 MUX_CFG("F18_1610_KBC0", 3, 15, 0, 0, 5, 1, 0, 0, 0)
523 MUX_CFG("D20_1610_KBC1", 3, 12, 0, 0, 4, 1, 0, 0, 0)
524 MUX_CFG("D19_1610_KBC2", 3, 9, 0, 0, 3, 1, 0, 0, 0)
525 MUX_CFG("E18_1610_KBC3", 3, 6, 0, 0, 2, 1, 0, 0, 0)
526 MUX_CFG("C21_1610_KBC4", 3, 3, 0, 0, 1, 1, 0, 0, 0)
527 MUX_CFG("G18_1610_KBR0", 4, 0, 0, 0, 10, 1, 0, 1, 0)
528 MUX_CFG("F19_1610_KBR1", 3, 27, 0, 0, 9, 1, 0, 1, 0)
529 MUX_CFG("H14_1610_KBR2", 3, 24, 0, 0, 8, 1, 0, 1, 0)
530 MUX_CFG("E20_1610_KBR3", 3, 21, 0, 0, 7, 1, 0, 1, 0)
531 MUX_CFG("E19_1610_KBR4", 3, 18, 0, 0, 6, 1, 0, 1, 0)
532 MUX_CFG("N19_1610_KBR5", 6, 12, 1, 1, 2, 1, 1, 1, 0)
533
534 /* Power management */
535 MUX_CFG("T20_1610_LOW_PWR", 7, 12, 1, NA, 0, 0, NA, 0, 0)
536
537 /* MCLK Settings */
538 MUX_CFG("V5_1710_MCLK_ON", B, 15, 0, NA, 0, 0, NA, 0, 0)
539 MUX_CFG("V5_1710_MCLK_OFF", B, 15, 6, NA, 0, 0, NA, 0, 0)
540 MUX_CFG("R10_1610_MCLK_ON", B, 18, 0, NA, 22, 0, NA, 1, 0)
541 MUX_CFG("R10_1610_MCLK_OFF", B, 18, 6, 2, 22, 1, 2, 1, 1)
542
543 /* CompactFlash controller, conflicts with MMC1 */
544 MUX_CFG("P11_1610_CF_CD2", A, 27, 3, 2, 15, 1, 2, 1, 1)
545 MUX_CFG("R11_1610_CF_IOIS16", B, 0, 3, 2, 16, 1, 2, 1, 1)
546 MUX_CFG("V10_1610_CF_IREQ", A, 24, 3, 2, 14, 0, 2, 0, 1)
547 MUX_CFG("W10_1610_CF_RESET", A, 18, 3, 2, 12, 1, 2, 1, 1)
548 MUX_CFG("W11_1610_CF_CD1", 10, 15, 3, 3, 8, 1, 3, 1, 1)
549 };
550
551 #endif /* __MUX_C__ */
552
553 #ifdef CONFIG_OMAP_MUX
554 /* setup pin muxing in Linux */
555 extern int omap_cfg_reg(reg_cfg_t reg_cfg);
556 #else
557 /* boot loader does it all (no warnings from CONFIG_OMAP_MUX_WARNINGS) */
558 static inline int omap_cfg_reg(reg_cfg_t reg_cfg) { return 0; }
559 #endif
560
561 #endif
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