include/asm-arm/cacheflush.h

   1 /*
   2  *  linux/include/asm-arm/cacheflush.h
   3  *
   4  *  Copyright (C) 1999-2002 Russell King
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 #ifndef _ASMARM_CACHEFLUSH_H
  11 #define _ASMARM_CACHEFLUSH_H
  12
  13 #include <linux/config.h>
  14 #include <linux/sched.h>
  15 #include <linux/mm.h>
  16
  17 #include <asm/mman.h>
  18 #include <asm/glue.h>
  19
  20 /*
  21  *      Cache Model
  22  *      ===========
  23  */
  24 #undef _CACHE
  25 #undef MULTI_CACHE
  26
  27 #if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710)
  28 # ifdef _CACHE
  29 #  define MULTI_CACHE 1
  30 # else
  31 #  define _CACHE v3
  32 # endif
  33 #endif
  34
  35 #if defined(CONFIG_CPU_ARM720T)
  36 # ifdef _CACHE
  37 #  define MULTI_CACHE 1
  38 # else
  39 #  define _CACHE v4
  40 # endif
  41 #endif
  42
  43 #if defined(CONFIG_CPU_ARM920T) || defined(CONFIG_CPU_ARM922T) || \
  44     defined(CONFIG_CPU_ARM925T) || defined(CONFIG_CPU_ARM1020)
  45 # define MULTI_CACHE 1
  46 #endif
  47
  48 #if defined(CONFIG_CPU_ARM926T)
  49 # ifdef _CACHE
  50 #  define MULTI_CACHE 1
  51 # else
  52 #  define _CACHE arm926
  53 # endif
  54 #endif
  55
  56 #if defined(CONFIG_CPU_SA110) || defined(CONFIG_CPU_SA1100)
  57 # ifdef _CACHE
  58 #  define MULTI_CACHE 1
  59 # else
  60 #  define _CACHE v4wb
  61 # endif
  62 #endif
  63
  64 #if defined(CONFIG_CPU_XSCALE)
  65 # ifdef _CACHE
  66 #  define MULTI_CACHE 1
  67 # else
  68 #  define _CACHE xscale
  69 # endif
  70 #endif
  71
  72 #if defined(CONFIG_CPU_V6)
  73 //# ifdef _CACHE
  74 #  define MULTI_CACHE 1
  75 //# else
  76 //#  define _CACHE v6
  77 //# endif
  78 #endif
  79
  80 #if !defined(_CACHE) && !defined(MULTI_CACHE)
  81 #error Unknown cache maintainence model
  82 #endif
  83
  84 /*
  85  * This flag is used to indicate that the page pointed to by a pte
  86  * is dirty and requires cleaning before returning it to the user.
  87  */
  88 #define PG_dcache_dirty PG_arch_1
  89
  90 /*
  91  *      MM Cache Management
  92  *      ===================
  93  *
  94  *      The arch/arm/mm/cache-*.S and arch/arm/mm/proc-*.S files
  95  *      implement these methods.
  96  *
  97  *      Start addresses are inclusive and end addresses are exclusive;
  98  *      start addresses should be rounded down, end addresses up.
  99  *
 100  *      See Documentation/cachetlb.txt for more information.
 101  *      Please note that the implementation of these, and the required
 102  *      effects are cache-type (VIVT/VIPT/PIPT) specific.
 103  *
 104  *      flush_cache_kern_all()
 105  *
 106  *              Unconditionally clean and invalidate the entire cache.
 107  *
 108  *      flush_cache_user_mm(mm)
 109  *
 110  *              Clean and invalidate all user space cache entries
 111  *              before a change of page tables.
 112  *
 113  *      flush_cache_user_range(start, end, flags)
 114  *
 115  *              Clean and invalidate a range of cache entries in the
 116  *              specified address space before a change of page tables.
 117  *              - start - user start address (inclusive, page aligned)
 118  *              - end   - user end address   (exclusive, page aligned)
 119  *              - flags - vma->vm_flags field
 120  *
 121  *      coherent_kern_range(start, end)
 122  *
 123  *              Ensure coherency between the Icache and the Dcache in the
 124  *              region described by start, end.  If you have non-snooping
 125  *              Harvard caches, you need to implement this function.
 126  *              - start  - virtual start address
 127  *              - end    - virtual end address
 128  *
 129  *      DMA Cache Coherency
 130  *      ===================
 131  *
 132  *      dma_inv_range(start, end)
 133  *
 134  *              Invalidate (discard) the specified virtual address range.
 135  *              May not write back any entries.  If 'start' or 'end'
 136  *              are not cache line aligned, those lines must be written
 137  *              back.
 138  *              - start  - virtual start address
 139  *              - end    - virtual end address
 140  *
 141  *      dma_clean_range(start, end)
 142  *
 143  *              Clean (write back) the specified virtual address range.
 144  *              - start  - virtual start address
 145  *              - end    - virtual end address
 146  *
 147  *      dma_flush_range(start, end)
 148  *
 149  *              Clean and invalidate the specified virtual address range.
 150  *              - start  - virtual start address
 151  *              - end    - virtual end address
 152  */
 153
 154 struct cpu_cache_fns {
 155         void (*flush_kern_all)(void);
 156         void (*flush_user_all)(void);
 157         void (*flush_user_range)(unsigned long, unsigned long, unsigned int);
 158
 159         void (*coherent_kern_range)(unsigned long, unsigned long);
 160         void (*coherent_user_range)(unsigned long, unsigned long);
 161         void (*flush_kern_dcache_page)(void *);
 162
 163         void (*dma_inv_range)(unsigned long, unsigned long);
 164         void (*dma_clean_range)(unsigned long, unsigned long);
 165         void (*dma_flush_range)(unsigned long, unsigned long);
 166 };
 167
 168 /*
 169  * Select the calling method
 170  */
 171 #ifdef MULTI_CACHE
 172
 173 extern struct cpu_cache_fns cpu_cache;
 174
 175 #define __cpuc_flush_kern_all           cpu_cache.flush_kern_all
 176 #define __cpuc_flush_user_all           cpu_cache.flush_user_all
 177 #define __cpuc_flush_user_range         cpu_cache.flush_user_range
 178 #define __cpuc_coherent_kern_range      cpu_cache.coherent_kern_range
 179 #define __cpuc_coherent_user_range      cpu_cache.coherent_user_range
 180 #define __cpuc_flush_dcache_page        cpu_cache.flush_kern_dcache_page
 181
 182 /*
 183  * These are private to the dma-mapping API.  Do not use directly.
 184  * Their sole purpose is to ensure that data held in the cache
 185  * is visible to DMA, or data written by DMA to system memory is
 186  * visible to the CPU.
 187  */
 188 #define dmac_inv_range                  cpu_cache.dma_inv_range
 189 #define dmac_clean_range                cpu_cache.dma_clean_range
 190 #define dmac_flush_range                cpu_cache.dma_flush_range
 191
 192 #else
 193
 194 #define __cpuc_flush_kern_all           __glue(_CACHE,_flush_kern_cache_all)
 195 #define __cpuc_flush_user_all           __glue(_CACHE,_flush_user_cache_all)
 196 #define __cpuc_flush_user_range         __glue(_CACHE,_flush_user_cache_range)
 197 #define __cpuc_coherent_kern_range      __glue(_CACHE,_coherent_kern_range)
 198 #define __cpuc_coherent_user_range      __glue(_CACHE,_coherent_user_range)
 199 #define __cpuc_flush_dcache_page        __glue(_CACHE,_flush_kern_dcache_page)
 200
 201 extern void __cpuc_flush_kern_all(void);
 202 extern void __cpuc_flush_user_all(void);
 203 extern void __cpuc_flush_user_range(unsigned long, unsigned long, unsigned int);
 204 extern void __cpuc_coherent_kern_range(unsigned long, unsigned long);
 205 extern void __cpuc_coherent_user_range(unsigned long, unsigned long);
 206 extern void __cpuc_flush_dcache_page(void *);
 207
 208 /*
 209  * These are private to the dma-mapping API.  Do not use directly.
 210  * Their sole purpose is to ensure that data held in the cache
 211  * is visible to DMA, or data written by DMA to system memory is
 212  * visible to the CPU.
 213  */
 214 #define dmac_inv_range                  __glue(_CACHE,_dma_inv_range)
 215 #define dmac_clean_range                __glue(_CACHE,_dma_clean_range)
 216 #define dmac_flush_range                __glue(_CACHE,_dma_flush_range)
 217
 218 extern void dmac_inv_range(unsigned long, unsigned long);
 219 extern void dmac_clean_range(unsigned long, unsigned long);
 220 extern void dmac_flush_range(unsigned long, unsigned long);
 221
 222 #endif
 223
 224 /*
 225  * flush_cache_vmap() is used when creating mappings (eg, via vmap,
 226  * vmalloc, ioremap etc) in kernel space for pages.  Since the
 227  * direct-mappings of these pages may contain cached data, we need
 228  * to do a full cache flush to ensure that writebacks don't corrupt
 229  * data placed into these pages via the new mappings.
 230  */
 231 #define flush_cache_vmap(start, end)            flush_cache_all()
 232 #define flush_cache_vunmap(start, end)          flush_cache_all()
 233
 234 /*
 235  * Copy user data from/to a page which is mapped into a different
 236  * processes address space.  Really, we want to allow our "user
 237  * space" model to handle this.
 238  */
 239 #define copy_to_user_page(vma, page, vaddr, dst, src, len) \
 240         do {                                                    \
 241                 flush_cache_page(vma, vaddr, page_to_pfn(page));\
 242                 memcpy(dst, src, len);                          \
 243                 flush_dcache_page(page);                        \
 244         } while (0)
 245
 246 #define copy_from_user_page(vma, page, vaddr, dst, src, len) \
 247         do {                                                    \
 248                 flush_cache_page(vma, vaddr, page_to_pfn(page));\
 249                 memcpy(dst, src, len);                          \
 250         } while (0)
 251
 252 /*
 253  * Convert calls to our calling convention.
 254  */
 255 #define flush_cache_all()               __cpuc_flush_kern_all()
 256
 257 static inline void flush_cache_mm(struct mm_struct *mm)
 258 {
 259         if (cpu_isset(smp_processor_id(), mm->cpu_vm_mask))
 260                 __cpuc_flush_user_all();
 261 }
 262
 263 static inline void
 264 flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
 265 {
 266         if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask))
 267                 __cpuc_flush_user_range(start & PAGE_MASK, PAGE_ALIGN(end),
 268                                         vma->vm_flags);
 269 }
 270
 271 static inline void
 272 flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn)
 273 {
 274         if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) {
 275                 unsigned long addr = user_addr & PAGE_MASK;
 276                 __cpuc_flush_user_range(addr, addr + PAGE_SIZE, vma->vm_flags);
 277         }
 278 }
 279
 280 /*
 281  * flush_cache_user_range is used when we want to ensure that the
 282  * Harvard caches are synchronised for the user space address range.
 283  * This is used for the ARM private sys_cacheflush system call.
 284  */
 285 #define flush_cache_user_range(vma,start,end) \
 286         __cpuc_coherent_user_range((start) & PAGE_MASK, PAGE_ALIGN(end))
 287
 288 /*
 289  * Perform necessary cache operations to ensure that data previously
 290  * stored within this range of addresses can be executed by the CPU.
 291  */
 292 #define flush_icache_range(s,e)         __cpuc_coherent_kern_range(s,e)
 293
 294 /*
 295  * Perform necessary cache operations to ensure that the TLB will
 296  * see data written in the specified area.
 297  */
 298 #define clean_dcache_area(start,size)   cpu_dcache_clean_area(start, size)
 299
 300 /*
 301  * flush_dcache_page is used when the kernel has written to the page
 302  * cache page at virtual address page->virtual.
 303  *
 304  * If this page isn't mapped (ie, page_mapping == NULL), or it might
 305  * have userspace mappings, then we _must_ always clean + invalidate
 306  * the dcache entries associated with the kernel mapping.
 307  *
 308  * Otherwise we can defer the operation, and clean the cache when we are
 309  * about to change to user space.  This is the same method as used on SPARC64.
 310  * See update_mmu_cache for the user space part.
 311  */
 312 extern void flush_dcache_page(struct page *);
 313
 314 #define flush_dcache_mmap_lock(mapping) \
 315         write_lock_irq(&(mapping)->tree_lock)
 316 #define flush_dcache_mmap_unlock(mapping) \
 317         write_unlock_irq(&(mapping)->tree_lock)
 318
 319 #define flush_icache_user_range(vma,page,addr,len) \
 320         flush_dcache_page(page)
 321
 322 /*
 323  * We don't appear to need to do anything here.  In fact, if we did, we'd
 324  * duplicate cache flushing elsewhere performed by flush_dcache_page().
 325  */
 326 #define flush_icache_page(vma,page)     do { } while (0)
 327
 328 #define __cacheid_present(val)          (val != read_cpuid(CPUID_ID))
 329 #define __cacheid_vivt(val)             ((val & (15 << 25)) != (14 << 25))
 330 #define __cacheid_vipt(val)             ((val & (15 << 25)) == (14 << 25))
 331 #define __cacheid_vipt_nonaliasing(val) ((val & (15 << 25 | 1 << 23)) == (14 << 25))
 332 #define __cacheid_vipt_aliasing(val)    ((val & (15 << 25 | 1 << 23)) == (14 << 25 | 1 << 23))
 333
 334 #if defined(CONFIG_CPU_CACHE_VIVT) && !defined(CONFIG_CPU_CACHE_VIPT)
 335
 336 #define cache_is_vivt()                 1
 337 #define cache_is_vipt()                 0
 338 #define cache_is_vipt_nonaliasing()     0
 339 #define cache_is_vipt_aliasing()        0
 340
 341 #elif defined(CONFIG_CPU_CACHE_VIPT)
 342
 343 #define cache_is_vivt()                 0
 344 #define cache_is_vipt()                 1
 345 #define cache_is_vipt_nonaliasing()                                     \
 346         ({                                                              \
 347                 unsigned int __val = read_cpuid(CPUID_CACHETYPE);       \
 348                 __cacheid_vipt_nonaliasing(__val);                      \
 349         })
 350
 351 #define cache_is_vipt_aliasing()                                        \
 352         ({                                                              \
 353                 unsigned int __val = read_cpuid(CPUID_CACHETYPE);       \
 354                 __cacheid_vipt_aliasing(__val);                         \
 355         })
 356
 357 #else
 358
 359 #define cache_is_vivt()                                                 \
 360         ({                                                              \
 361                 unsigned int __val = read_cpuid(CPUID_CACHETYPE);       \
 362                 (!__cacheid_present(__val)) || __cacheid_vivt(__val);   \
 363         })
 364
 365 #define cache_is_vipt()                                                 \
 366         ({                                                              \
 367                 unsigned int __val = read_cpuid(CPUID_CACHETYPE);       \
 368                 __cacheid_present(__val) && __cacheid_vipt(__val);      \
 369         })
 370
 371 #define cache_is_vipt_nonaliasing()                                     \
 372         ({                                                              \
 373                 unsigned int __val = read_cpuid(CPUID_CACHETYPE);       \
 374                 __cacheid_present(__val) &&                             \
 375                  __cacheid_vipt_nonaliasing(__val);                     \
 376         })
 377
 378 #define cache_is_vipt_aliasing()                                        \
 379         ({                                                              \
 380                 unsigned int __val = read_cpuid(CPUID_CACHETYPE);       \
 381                 __cacheid_present(__val) &&                             \
 382                  __cacheid_vipt_aliasing(__val);                        \
 383         })
 384
 385 #endif
 386
 387 #endif