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[TG3]: Add tagged status support.
[linux-2.6/verdex.git] / include / asm-ia64 / pal.h
blob2303a10ee595405455d4f4520d3a334fd2fdfe56
1 #ifndef _ASM_IA64_PAL_H
2 #define _ASM_IA64_PAL_H
3
4 /*
5 * Processor Abstraction Layer definitions.
6 *
7 * This is based on Intel IA-64 Architecture Software Developer's Manual rev 1.0
8 * chapter 11 IA-64 Processor Abstraction Layer
9 *
10 * Copyright (C) 1998-2001 Hewlett-Packard Co
11 * David Mosberger-Tang <davidm@hpl.hp.com>
12 * Stephane Eranian <eranian@hpl.hp.com>
13 * Copyright (C) 1999 VA Linux Systems
14 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
15 * Copyright (C) 1999 Srinivasa Prasad Thirumalachar <sprasad@sprasad.engr.sgi.com>
16 *
17 * 99/10/01 davidm Make sure we pass zero for reserved parameters.
18 * 00/03/07 davidm Updated pal_cache_flush() to be in sync with PAL v2.6.
19 * 00/03/23 cfleck Modified processor min-state save area to match updated PAL & SAL info
20 * 00/05/24 eranian Updated to latest PAL spec, fix structures bugs, added
21 * 00/05/25 eranian Support for stack calls, and static physical calls
22 * 00/06/18 eranian Support for stacked physical calls
23 */
24
25 /*
26 * Note that some of these calls use a static-register only calling
27 * convention which has nothing to do with the regular calling
28 * convention.
29 */
30 #define PAL_CACHE_FLUSH 1 /* flush i/d cache */
31 #define PAL_CACHE_INFO 2 /* get detailed i/d cache info */
32 #define PAL_CACHE_INIT 3 /* initialize i/d cache */
33 #define PAL_CACHE_SUMMARY 4 /* get summary of cache heirarchy */
34 #define PAL_MEM_ATTRIB 5 /* list supported memory attributes */
35 #define PAL_PTCE_INFO 6 /* purge TLB info */
36 #define PAL_VM_INFO 7 /* return supported virtual memory features */
37 #define PAL_VM_SUMMARY 8 /* return summary on supported vm features */
38 #define PAL_BUS_GET_FEATURES 9 /* return processor bus interface features settings */
39 #define PAL_BUS_SET_FEATURES 10 /* set processor bus features */
40 #define PAL_DEBUG_INFO 11 /* get number of debug registers */
41 #define PAL_FIXED_ADDR 12 /* get fixed component of processors's directed address */
42 #define PAL_FREQ_BASE 13 /* base frequency of the platform */
43 #define PAL_FREQ_RATIOS 14 /* ratio of processor, bus and ITC frequency */
44 #define PAL_PERF_MON_INFO 15 /* return performance monitor info */
45 #define PAL_PLATFORM_ADDR 16 /* set processor interrupt block and IO port space addr */
46 #define PAL_PROC_GET_FEATURES 17 /* get configurable processor features & settings */
47 #define PAL_PROC_SET_FEATURES 18 /* enable/disable configurable processor features */
48 #define PAL_RSE_INFO 19 /* return rse information */
49 #define PAL_VERSION 20 /* return version of PAL code */
50 #define PAL_MC_CLEAR_LOG 21 /* clear all processor log info */
51 #define PAL_MC_DRAIN 22 /* drain operations which could result in an MCA */
52 #define PAL_MC_EXPECTED 23 /* set/reset expected MCA indicator */
53 #define PAL_MC_DYNAMIC_STATE 24 /* get processor dynamic state */
54 #define PAL_MC_ERROR_INFO 25 /* get processor MCA info and static state */
55 #define PAL_MC_RESUME 26 /* Return to interrupted process */
56 #define PAL_MC_REGISTER_MEM 27 /* Register memory for PAL to use during MCAs and inits */
57 #define PAL_HALT 28 /* enter the low power HALT state */
58 #define PAL_HALT_LIGHT 29 /* enter the low power light halt state*/
59 #define PAL_COPY_INFO 30 /* returns info needed to relocate PAL */
60 #define PAL_CACHE_LINE_INIT 31 /* init tags & data of cache line */
61 #define PAL_PMI_ENTRYPOINT 32 /* register PMI memory entry points with the processor */
62 #define PAL_ENTER_IA_32_ENV 33 /* enter IA-32 system environment */
63 #define PAL_VM_PAGE_SIZE 34 /* return vm TC and page walker page sizes */
64
65 #define PAL_MEM_FOR_TEST 37 /* get amount of memory needed for late processor test */
66 #define PAL_CACHE_PROT_INFO 38 /* get i/d cache protection info */
67 #define PAL_REGISTER_INFO 39 /* return AR and CR register information*/
68 #define PAL_SHUTDOWN 40 /* enter processor shutdown state */
69 #define PAL_PREFETCH_VISIBILITY 41 /* Make Processor Prefetches Visible */
70 #define PAL_LOGICAL_TO_PHYSICAL 42 /* returns information on logical to physical processor mapping */
71
72 #define PAL_COPY_PAL 256 /* relocate PAL procedures and PAL PMI */
73 #define PAL_HALT_INFO 257 /* return the low power capabilities of processor */
74 #define PAL_TEST_PROC 258 /* perform late processor self-test */
75 #define PAL_CACHE_READ 259 /* read tag & data of cacheline for diagnostic testing */
76 #define PAL_CACHE_WRITE 260 /* write tag & data of cacheline for diagnostic testing */
77 #define PAL_VM_TR_READ 261 /* read contents of translation register */
78
79 #ifndef __ASSEMBLY__
80
81 #include <linux/types.h>
82 #include <asm/fpu.h>
83
84 /*
85 * Data types needed to pass information into PAL procedures and
86 * interpret information returned by them.
87 */
88
89 /* Return status from the PAL procedure */
90 typedef s64 pal_status_t;
91
92 #define PAL_STATUS_SUCCESS 0 /* No error */
93 #define PAL_STATUS_UNIMPLEMENTED (-1) /* Unimplemented procedure */
94 #define PAL_STATUS_EINVAL (-2) /* Invalid argument */
95 #define PAL_STATUS_ERROR (-3) /* Error */
96 #define PAL_STATUS_CACHE_INIT_FAIL (-4) /* Could not initialize the
97 * specified level and type of
98 * cache without sideeffects
99 * and "restrict" was 1
100 */
101
102 /* Processor cache level in the heirarchy */
103 typedef u64 pal_cache_level_t;
104 #define PAL_CACHE_LEVEL_L0 0 /* L0 */
105 #define PAL_CACHE_LEVEL_L1 1 /* L1 */
106 #define PAL_CACHE_LEVEL_L2 2 /* L2 */
107
108
109 /* Processor cache type at a particular level in the heirarchy */
110
111 typedef u64 pal_cache_type_t;
112 #define PAL_CACHE_TYPE_INSTRUCTION 1 /* Instruction cache */
113 #define PAL_CACHE_TYPE_DATA 2 /* Data or unified cache */
114 #define PAL_CACHE_TYPE_INSTRUCTION_DATA 3 /* Both Data & Instruction */
115
116
117 #define PAL_CACHE_FLUSH_INVALIDATE 1 /* Invalidate clean lines */
118 #define PAL_CACHE_FLUSH_CHK_INTRS 2 /* check for interrupts/mc while flushing */
119
120 /* Processor cache line size in bytes */
121 typedef int pal_cache_line_size_t;
122
123 /* Processor cache line state */
124 typedef u64 pal_cache_line_state_t;
125 #define PAL_CACHE_LINE_STATE_INVALID 0 /* Invalid */
126 #define PAL_CACHE_LINE_STATE_SHARED 1 /* Shared */
127 #define PAL_CACHE_LINE_STATE_EXCLUSIVE 2 /* Exclusive */
128 #define PAL_CACHE_LINE_STATE_MODIFIED 3 /* Modified */
129
130 typedef struct pal_freq_ratio {
131 u64 den : 32, num : 32; /* numerator & denominator */
132 } itc_ratio, proc_ratio;
133
134 typedef union pal_cache_config_info_1_s {
135 struct {
136 u64 u : 1, /* 0 Unified cache ? */
137 at : 2, /* 2-1 Cache mem attr*/
138 reserved : 5, /* 7-3 Reserved */
139 associativity : 8, /* 16-8 Associativity*/
140 line_size : 8, /* 23-17 Line size */
141 stride : 8, /* 31-24 Stride */
142 store_latency : 8, /*39-32 Store latency*/
143 load_latency : 8, /* 47-40 Load latency*/
144 store_hints : 8, /* 55-48 Store hints*/
145 load_hints : 8; /* 63-56 Load hints */
146 } pcci1_bits;
147 u64 pcci1_data;
148 } pal_cache_config_info_1_t;
149
150 typedef union pal_cache_config_info_2_s {
151 struct {
152 u64 cache_size : 32, /*cache size in bytes*/
153
154
155 alias_boundary : 8, /* 39-32 aliased addr
156 * separation for max
157 * performance.
158 */
159 tag_ls_bit : 8, /* 47-40 LSb of addr*/
160 tag_ms_bit : 8, /* 55-48 MSb of addr*/
161 reserved : 8; /* 63-56 Reserved */
162 } pcci2_bits;
163 u64 pcci2_data;
164 } pal_cache_config_info_2_t;
165
166
167 typedef struct pal_cache_config_info_s {
168 pal_status_t pcci_status;
169 pal_cache_config_info_1_t pcci_info_1;
170 pal_cache_config_info_2_t pcci_info_2;
171 u64 pcci_reserved;
172 } pal_cache_config_info_t;
173
174 #define pcci_ld_hints pcci_info_1.pcci1_bits.load_hints
175 #define pcci_st_hints pcci_info_1.pcci1_bits.store_hints
176 #define pcci_ld_latency pcci_info_1.pcci1_bits.load_latency
177 #define pcci_st_latency pcci_info_1.pcci1_bits.store_latency
178 #define pcci_stride pcci_info_1.pcci1_bits.stride
179 #define pcci_line_size pcci_info_1.pcci1_bits.line_size
180 #define pcci_assoc pcci_info_1.pcci1_bits.associativity
181 #define pcci_cache_attr pcci_info_1.pcci1_bits.at
182 #define pcci_unified pcci_info_1.pcci1_bits.u
183 #define pcci_tag_msb pcci_info_2.pcci2_bits.tag_ms_bit
184 #define pcci_tag_lsb pcci_info_2.pcci2_bits.tag_ls_bit
185 #define pcci_alias_boundary pcci_info_2.pcci2_bits.alias_boundary
186 #define pcci_cache_size pcci_info_2.pcci2_bits.cache_size
187
188
189
190 /* Possible values for cache attributes */
191
192 #define PAL_CACHE_ATTR_WT 0 /* Write through cache */
193 #define PAL_CACHE_ATTR_WB 1 /* Write back cache */
194 #define PAL_CACHE_ATTR_WT_OR_WB 2 /* Either write thru or write
195 * back depending on TLB
196 * memory attributes
197 */
198
199
200 /* Possible values for cache hints */
201
202 #define PAL_CACHE_HINT_TEMP_1 0 /* Temporal level 1 */
203 #define PAL_CACHE_HINT_NTEMP_1 1 /* Non-temporal level 1 */
204 #define PAL_CACHE_HINT_NTEMP_ALL 3 /* Non-temporal all levels */
205
206 /* Processor cache protection information */
207 typedef union pal_cache_protection_element_u {
208 u32 pcpi_data;
209 struct {
210 u32 data_bits : 8, /* # data bits covered by
211 * each unit of protection
212 */
213
214 tagprot_lsb : 6, /* Least -do- */
215 tagprot_msb : 6, /* Most Sig. tag address
216 * bit that this
217 * protection covers.
218 */
219 prot_bits : 6, /* # of protection bits */
220 method : 4, /* Protection method */
221 t_d : 2; /* Indicates which part
222 * of the cache this
223 * protection encoding
224 * applies.
225 */
226 } pcp_info;
227 } pal_cache_protection_element_t;
228
229 #define pcpi_cache_prot_part pcp_info.t_d
230 #define pcpi_prot_method pcp_info.method
231 #define pcpi_prot_bits pcp_info.prot_bits
232 #define pcpi_tagprot_msb pcp_info.tagprot_msb
233 #define pcpi_tagprot_lsb pcp_info.tagprot_lsb
234 #define pcpi_data_bits pcp_info.data_bits
235
236 /* Processor cache part encodings */
237 #define PAL_CACHE_PROT_PART_DATA 0 /* Data protection */
238 #define PAL_CACHE_PROT_PART_TAG 1 /* Tag protection */
239 #define PAL_CACHE_PROT_PART_TAG_DATA 2 /* Tag+data protection (tag is
240 * more significant )
241 */
242 #define PAL_CACHE_PROT_PART_DATA_TAG 3 /* Data+tag protection (data is
243 * more significant )
244 */
245 #define PAL_CACHE_PROT_PART_MAX 6
246
247
248 typedef struct pal_cache_protection_info_s {
249 pal_status_t pcpi_status;
250 pal_cache_protection_element_t pcp_info[PAL_CACHE_PROT_PART_MAX];
251 } pal_cache_protection_info_t;
252
253
254 /* Processor cache protection method encodings */
255 #define PAL_CACHE_PROT_METHOD_NONE 0 /* No protection */
256 #define PAL_CACHE_PROT_METHOD_ODD_PARITY 1 /* Odd parity */
257 #define PAL_CACHE_PROT_METHOD_EVEN_PARITY 2 /* Even parity */
258 #define PAL_CACHE_PROT_METHOD_ECC 3 /* ECC protection */
259
260
261 /* Processor cache line identification in the heirarchy */
262 typedef union pal_cache_line_id_u {
263 u64 pclid_data;
264 struct {
265 u64 cache_type : 8, /* 7-0 cache type */
266 level : 8, /* 15-8 level of the
267 * cache in the
268 * heirarchy.
269 */
270 way : 8, /* 23-16 way in the set
271 */
272 part : 8, /* 31-24 part of the
273 * cache
274 */
275 reserved : 32; /* 63-32 is reserved*/
276 } pclid_info_read;
277 struct {
278 u64 cache_type : 8, /* 7-0 cache type */
279 level : 8, /* 15-8 level of the
280 * cache in the
281 * heirarchy.
282 */
283 way : 8, /* 23-16 way in the set
284 */
285 part : 8, /* 31-24 part of the
286 * cache
287 */
288 mesi : 8, /* 39-32 cache line
289 * state
290 */
291 start : 8, /* 47-40 lsb of data to
292 * invert
293 */
294 length : 8, /* 55-48 #bits to
295 * invert
296 */
297 trigger : 8; /* 63-56 Trigger error
298 * by doing a load
299 * after the write
300 */
301
302 } pclid_info_write;
303 } pal_cache_line_id_u_t;
304
305 #define pclid_read_part pclid_info_read.part
306 #define pclid_read_way pclid_info_read.way
307 #define pclid_read_level pclid_info_read.level
308 #define pclid_read_cache_type pclid_info_read.cache_type
309
310 #define pclid_write_trigger pclid_info_write.trigger
311 #define pclid_write_length pclid_info_write.length
312 #define pclid_write_start pclid_info_write.start
313 #define pclid_write_mesi pclid_info_write.mesi
314 #define pclid_write_part pclid_info_write.part
315 #define pclid_write_way pclid_info_write.way
316 #define pclid_write_level pclid_info_write.level
317 #define pclid_write_cache_type pclid_info_write.cache_type
318
319 /* Processor cache line part encodings */
320 #define PAL_CACHE_LINE_ID_PART_DATA 0 /* Data */
321 #define PAL_CACHE_LINE_ID_PART_TAG 1 /* Tag */
322 #define PAL_CACHE_LINE_ID_PART_DATA_PROT 2 /* Data protection */
323 #define PAL_CACHE_LINE_ID_PART_TAG_PROT 3 /* Tag protection */
324 #define PAL_CACHE_LINE_ID_PART_DATA_TAG_PROT 4 /* Data+tag
325 * protection
326 */
327 typedef struct pal_cache_line_info_s {
328 pal_status_t pcli_status; /* Return status of the read cache line
329 * info call.
330 */
331 u64 pcli_data; /* 64-bit data, tag, protection bits .. */
332 u64 pcli_data_len; /* data length in bits */
333 pal_cache_line_state_t pcli_cache_line_state; /* mesi state */
334
335 } pal_cache_line_info_t;
336
337
338 /* Machine Check related crap */
339
340 /* Pending event status bits */
341 typedef u64 pal_mc_pending_events_t;
342
343 #define PAL_MC_PENDING_MCA (1 << 0)
344 #define PAL_MC_PENDING_INIT (1 << 1)
345
346 /* Error information type */
347 typedef u64 pal_mc_info_index_t;
348
349 #define PAL_MC_INFO_PROCESSOR 0 /* Processor */
350 #define PAL_MC_INFO_CACHE_CHECK 1 /* Cache check */
351 #define PAL_MC_INFO_TLB_CHECK 2 /* Tlb check */
352 #define PAL_MC_INFO_BUS_CHECK 3 /* Bus check */
353 #define PAL_MC_INFO_REQ_ADDR 4 /* Requestor address */
354 #define PAL_MC_INFO_RESP_ADDR 5 /* Responder address */
355 #define PAL_MC_INFO_TARGET_ADDR 6 /* Target address */
356 #define PAL_MC_INFO_IMPL_DEP 7 /* Implementation
357 * dependent
358 */
359
360
361 typedef struct pal_process_state_info_s {
362 u64 reserved1 : 2,
363 rz : 1, /* PAL_CHECK processor
364 * rendezvous
365 * successful.
366 */
367
368 ra : 1, /* PAL_CHECK attempted
369 * a rendezvous.
370 */
371 me : 1, /* Distinct multiple
372 * errors occurred
373 */
374
375 mn : 1, /* Min. state save
376 * area has been
377 * registered with PAL
378 */
379
380 sy : 1, /* Storage integrity
381 * synched
382 */
383
384
385 co : 1, /* Continuable */
386 ci : 1, /* MC isolated */
387 us : 1, /* Uncontained storage
388 * damage.
389 */
390
391
392 hd : 1, /* Non-essential hw
393 * lost (no loss of
394 * functionality)
395 * causing the
396 * processor to run in
397 * degraded mode.
398 */
399
400 tl : 1, /* 1 => MC occurred
401 * after an instr was
402 * executed but before
403 * the trap that
404 * resulted from instr
405 * execution was
406 * generated.
407 * (Trap Lost )
408 */
409 mi : 1, /* More information available
410 * call PAL_MC_ERROR_INFO
411 */
412 pi : 1, /* Precise instruction pointer */
413 pm : 1, /* Precise min-state save area */
414
415 dy : 1, /* Processor dynamic
416 * state valid
417 */
418
419
420 in : 1, /* 0 = MC, 1 = INIT */
421 rs : 1, /* RSE valid */
422 cm : 1, /* MC corrected */
423 ex : 1, /* MC is expected */
424 cr : 1, /* Control regs valid*/
425 pc : 1, /* Perf cntrs valid */
426 dr : 1, /* Debug regs valid */
427 tr : 1, /* Translation regs
428 * valid
429 */
430 rr : 1, /* Region regs valid */
431 ar : 1, /* App regs valid */
432 br : 1, /* Branch regs valid */
433 pr : 1, /* Predicate registers
434 * valid
435 */
436
437 fp : 1, /* fp registers valid*/
438 b1 : 1, /* Preserved bank one
439 * general registers
440 * are valid
441 */
442 b0 : 1, /* Preserved bank zero
443 * general registers
444 * are valid
445 */
446 gr : 1, /* General registers
447 * are valid
448 * (excl. banked regs)
449 */
450 dsize : 16, /* size of dynamic
451 * state returned
452 * by the processor
453 */
454
455 reserved2 : 11,
456 cc : 1, /* Cache check */
457 tc : 1, /* TLB check */
458 bc : 1, /* Bus check */
459 rc : 1, /* Register file check */
460 uc : 1; /* Uarch check */
461
462 } pal_processor_state_info_t;
463
464 typedef struct pal_cache_check_info_s {
465 u64 op : 4, /* Type of cache
466 * operation that
467 * caused the machine
468 * check.
469 */
470 level : 2, /* Cache level */
471 reserved1 : 2,
472 dl : 1, /* Failure in data part
473 * of cache line
474 */
475 tl : 1, /* Failure in tag part
476 * of cache line
477 */
478 dc : 1, /* Failure in dcache */
479 ic : 1, /* Failure in icache */
480 mesi : 3, /* Cache line state */
481 mv : 1, /* mesi valid */
482 way : 5, /* Way in which the
483 * error occurred
484 */
485 wiv : 1, /* Way field valid */
486 reserved2 : 10,
487
488 index : 20, /* Cache line index */
489 reserved3 : 2,
490
491 is : 1, /* instruction set (1 == ia32) */
492 iv : 1, /* instruction set field valid */
493 pl : 2, /* privilege level */
494 pv : 1, /* privilege level field valid */
495 mcc : 1, /* Machine check corrected */
496 tv : 1, /* Target address
497 * structure is valid
498 */
499 rq : 1, /* Requester identifier
500 * structure is valid
501 */
502 rp : 1, /* Responder identifier
503 * structure is valid
504 */
505 pi : 1; /* Precise instruction pointer
506 * structure is valid
507 */
508 } pal_cache_check_info_t;
509
510 typedef struct pal_tlb_check_info_s {
511
512 u64 tr_slot : 8, /* Slot# of TR where
513 * error occurred
514 */
515 trv : 1, /* tr_slot field is valid */
516 reserved1 : 1,
517 level : 2, /* TLB level where failure occurred */
518 reserved2 : 4,
519 dtr : 1, /* Fail in data TR */
520 itr : 1, /* Fail in inst TR */
521 dtc : 1, /* Fail in data TC */
522 itc : 1, /* Fail in inst. TC */
523 op : 4, /* Cache operation */
524 reserved3 : 30,
525
526 is : 1, /* instruction set (1 == ia32) */
527 iv : 1, /* instruction set field valid */
528 pl : 2, /* privilege level */
529 pv : 1, /* privilege level field valid */
530 mcc : 1, /* Machine check corrected */
531 tv : 1, /* Target address
532 * structure is valid
533 */
534 rq : 1, /* Requester identifier
535 * structure is valid
536 */
537 rp : 1, /* Responder identifier
538 * structure is valid
539 */
540 pi : 1; /* Precise instruction pointer
541 * structure is valid
542 */
543 } pal_tlb_check_info_t;
544
545 typedef struct pal_bus_check_info_s {
546 u64 size : 5, /* Xaction size */
547 ib : 1, /* Internal bus error */
548 eb : 1, /* External bus error */
549 cc : 1, /* Error occurred
550 * during cache-cache
551 * transfer.
552 */
553 type : 8, /* Bus xaction type*/
554 sev : 5, /* Bus error severity*/
555 hier : 2, /* Bus hierarchy level */
556 reserved1 : 1,
557 bsi : 8, /* Bus error status
558 * info
559 */
560 reserved2 : 22,
561
562 is : 1, /* instruction set (1 == ia32) */
563 iv : 1, /* instruction set field valid */
564 pl : 2, /* privilege level */
565 pv : 1, /* privilege level field valid */
566 mcc : 1, /* Machine check corrected */
567 tv : 1, /* Target address
568 * structure is valid
569 */
570 rq : 1, /* Requester identifier
571 * structure is valid
572 */
573 rp : 1, /* Responder identifier
574 * structure is valid
575 */
576 pi : 1; /* Precise instruction pointer
577 * structure is valid
578 */
579 } pal_bus_check_info_t;
580
581 typedef struct pal_reg_file_check_info_s {
582 u64 id : 4, /* Register file identifier */
583 op : 4, /* Type of register
584 * operation that
585 * caused the machine
586 * check.
587 */
588 reg_num : 7, /* Register number */
589 rnv : 1, /* reg_num valid */
590 reserved2 : 38,
591
592 is : 1, /* instruction set (1 == ia32) */
593 iv : 1, /* instruction set field valid */
594 pl : 2, /* privilege level */
595 pv : 1, /* privilege level field valid */
596 mcc : 1, /* Machine check corrected */
597 reserved3 : 3,
598 pi : 1; /* Precise instruction pointer
599 * structure is valid
600 */
601 } pal_reg_file_check_info_t;
602
603 typedef struct pal_uarch_check_info_s {
604 u64 sid : 5, /* Structure identification */
605 level : 3, /* Level of failure */
606 array_id : 4, /* Array identification */
607 op : 4, /* Type of
608 * operation that
609 * caused the machine
610 * check.
611 */
612 way : 6, /* Way of structure */
613 wv : 1, /* way valid */
614 xv : 1, /* index valid */
615 reserved1 : 8,
616 index : 8, /* Index or set of the uarch
617 * structure that failed.
618 */
619 reserved2 : 24,
620
621 is : 1, /* instruction set (1 == ia32) */
622 iv : 1, /* instruction set field valid */
623 pl : 2, /* privilege level */
624 pv : 1, /* privilege level field valid */
625 mcc : 1, /* Machine check corrected */
626 tv : 1, /* Target address
627 * structure is valid
628 */
629 rq : 1, /* Requester identifier
630 * structure is valid
631 */
632 rp : 1, /* Responder identifier
633 * structure is valid
634 */
635 pi : 1; /* Precise instruction pointer
636 * structure is valid
637 */
638 } pal_uarch_check_info_t;
639
640 typedef union pal_mc_error_info_u {
641 u64 pmei_data;
642 pal_processor_state_info_t pme_processor;
643 pal_cache_check_info_t pme_cache;
644 pal_tlb_check_info_t pme_tlb;
645 pal_bus_check_info_t pme_bus;
646 pal_reg_file_check_info_t pme_reg_file;
647 pal_uarch_check_info_t pme_uarch;
648 } pal_mc_error_info_t;
649
650 #define pmci_proc_unknown_check pme_processor.uc
651 #define pmci_proc_bus_check pme_processor.bc
652 #define pmci_proc_tlb_check pme_processor.tc
653 #define pmci_proc_cache_check pme_processor.cc
654 #define pmci_proc_dynamic_state_size pme_processor.dsize
655 #define pmci_proc_gpr_valid pme_processor.gr
656 #define pmci_proc_preserved_bank0_gpr_valid pme_processor.b0
657 #define pmci_proc_preserved_bank1_gpr_valid pme_processor.b1
658 #define pmci_proc_fp_valid pme_processor.fp
659 #define pmci_proc_predicate_regs_valid pme_processor.pr
660 #define pmci_proc_branch_regs_valid pme_processor.br
661 #define pmci_proc_app_regs_valid pme_processor.ar
662 #define pmci_proc_region_regs_valid pme_processor.rr
663 #define pmci_proc_translation_regs_valid pme_processor.tr
664 #define pmci_proc_debug_regs_valid pme_processor.dr
665 #define pmci_proc_perf_counters_valid pme_processor.pc
666 #define pmci_proc_control_regs_valid pme_processor.cr
667 #define pmci_proc_machine_check_expected pme_processor.ex
668 #define pmci_proc_machine_check_corrected pme_processor.cm
669 #define pmci_proc_rse_valid pme_processor.rs
670 #define pmci_proc_machine_check_or_init pme_processor.in
671 #define pmci_proc_dynamic_state_valid pme_processor.dy
672 #define pmci_proc_operation pme_processor.op
673 #define pmci_proc_trap_lost pme_processor.tl
674 #define pmci_proc_hardware_damage pme_processor.hd
675 #define pmci_proc_uncontained_storage_damage pme_processor.us
676 #define pmci_proc_machine_check_isolated pme_processor.ci
677 #define pmci_proc_continuable pme_processor.co
678 #define pmci_proc_storage_intergrity_synced pme_processor.sy
679 #define pmci_proc_min_state_save_area_regd pme_processor.mn
680 #define pmci_proc_distinct_multiple_errors pme_processor.me
681 #define pmci_proc_pal_attempted_rendezvous pme_processor.ra
682 #define pmci_proc_pal_rendezvous_complete pme_processor.rz
683
684
685 #define pmci_cache_level pme_cache.level
686 #define pmci_cache_line_state pme_cache.mesi
687 #define pmci_cache_line_state_valid pme_cache.mv
688 #define pmci_cache_line_index pme_cache.index
689 #define pmci_cache_instr_cache_fail pme_cache.ic
690 #define pmci_cache_data_cache_fail pme_cache.dc
691 #define pmci_cache_line_tag_fail pme_cache.tl
692 #define pmci_cache_line_data_fail pme_cache.dl
693 #define pmci_cache_operation pme_cache.op
694 #define pmci_cache_way_valid pme_cache.wv
695 #define pmci_cache_target_address_valid pme_cache.tv
696 #define pmci_cache_way pme_cache.way
697 #define pmci_cache_mc pme_cache.mc
698
699 #define pmci_tlb_instr_translation_cache_fail pme_tlb.itc
700 #define pmci_tlb_data_translation_cache_fail pme_tlb.dtc
701 #define pmci_tlb_instr_translation_reg_fail pme_tlb.itr
702 #define pmci_tlb_data_translation_reg_fail pme_tlb.dtr
703 #define pmci_tlb_translation_reg_slot pme_tlb.tr_slot
704 #define pmci_tlb_mc pme_tlb.mc
705
706 #define pmci_bus_status_info pme_bus.bsi
707 #define pmci_bus_req_address_valid pme_bus.rq
708 #define pmci_bus_resp_address_valid pme_bus.rp
709 #define pmci_bus_target_address_valid pme_bus.tv
710 #define pmci_bus_error_severity pme_bus.sev
711 #define pmci_bus_transaction_type pme_bus.type
712 #define pmci_bus_cache_cache_transfer pme_bus.cc
713 #define pmci_bus_transaction_size pme_bus.size
714 #define pmci_bus_internal_error pme_bus.ib
715 #define pmci_bus_external_error pme_bus.eb
716 #define pmci_bus_mc pme_bus.mc
717
718 /*
719 * NOTE: this min_state_save area struct only includes the 1KB
720 * architectural state save area. The other 3 KB is scratch space
721 * for PAL.
722 */
723
724 typedef struct pal_min_state_area_s {
725 u64 pmsa_nat_bits; /* nat bits for saved GRs */
726 u64 pmsa_gr[15]; /* GR1 - GR15 */
727 u64 pmsa_bank0_gr[16]; /* GR16 - GR31 */
728 u64 pmsa_bank1_gr[16]; /* GR16 - GR31 */
729 u64 pmsa_pr; /* predicate registers */
730 u64 pmsa_br0; /* branch register 0 */
731 u64 pmsa_rsc; /* ar.rsc */
732 u64 pmsa_iip; /* cr.iip */
733 u64 pmsa_ipsr; /* cr.ipsr */
734 u64 pmsa_ifs; /* cr.ifs */
735 u64 pmsa_xip; /* previous iip */
736 u64 pmsa_xpsr; /* previous psr */
737 u64 pmsa_xfs; /* previous ifs */
738 u64 pmsa_br1; /* branch register 1 */
739 u64 pmsa_reserved[70]; /* pal_min_state_area should total to 1KB */
740 } pal_min_state_area_t;
741
742
743 struct ia64_pal_retval {
744 /*
745 * A zero status value indicates call completed without error.
746 * A negative status value indicates reason of call failure.
747 * A positive status value indicates success but an
748 * informational value should be printed (e.g., "reboot for
749 * change to take effect").
750 */
751 s64 status;
752 u64 v0;
753 u64 v1;
754 u64 v2;
755 };
756
757 /*
758 * Note: Currently unused PAL arguments are generally labeled
759 * "reserved" so the value specified in the PAL documentation
760 * (generally 0) MUST be passed. Reserved parameters are not optional
761 * parameters.
762 */
763 extern struct ia64_pal_retval ia64_pal_call_static (u64, u64, u64, u64, u64);
764 extern struct ia64_pal_retval ia64_pal_call_stacked (u64, u64, u64, u64);
765 extern struct ia64_pal_retval ia64_pal_call_phys_static (u64, u64, u64, u64);
766 extern struct ia64_pal_retval ia64_pal_call_phys_stacked (u64, u64, u64, u64);
767 extern void ia64_save_scratch_fpregs (struct ia64_fpreg *);
768 extern void ia64_load_scratch_fpregs (struct ia64_fpreg *);
769
770 #define PAL_CALL(iprv,a0,a1,a2,a3) do { \
771 struct ia64_fpreg fr[6]; \
772 ia64_save_scratch_fpregs(fr); \
773 iprv = ia64_pal_call_static(a0, a1, a2, a3, 0); \
774 ia64_load_scratch_fpregs(fr); \
775 } while (0)
776
777 #define PAL_CALL_IC_OFF(iprv,a0,a1,a2,a3) do { \
778 struct ia64_fpreg fr[6]; \
779 ia64_save_scratch_fpregs(fr); \
780 iprv = ia64_pal_call_static(a0, a1, a2, a3, 1); \
781 ia64_load_scratch_fpregs(fr); \
782 } while (0)
783
784 #define PAL_CALL_STK(iprv,a0,a1,a2,a3) do { \
785 struct ia64_fpreg fr[6]; \
786 ia64_save_scratch_fpregs(fr); \
787 iprv = ia64_pal_call_stacked(a0, a1, a2, a3); \
788 ia64_load_scratch_fpregs(fr); \
789 } while (0)
790
791 #define PAL_CALL_PHYS(iprv,a0,a1,a2,a3) do { \
792 struct ia64_fpreg fr[6]; \
793 ia64_save_scratch_fpregs(fr); \
794 iprv = ia64_pal_call_phys_static(a0, a1, a2, a3); \
795 ia64_load_scratch_fpregs(fr); \
796 } while (0)
797
798 #define PAL_CALL_PHYS_STK(iprv,a0,a1,a2,a3) do { \
799 struct ia64_fpreg fr[6]; \
800 ia64_save_scratch_fpregs(fr); \
801 iprv = ia64_pal_call_phys_stacked(a0, a1, a2, a3); \
802 ia64_load_scratch_fpregs(fr); \
803 } while (0)
804
805 typedef int (*ia64_pal_handler) (u64, ...);
806 extern ia64_pal_handler ia64_pal;
807 extern void ia64_pal_handler_init (void *);
808
809 extern ia64_pal_handler ia64_pal;
810
811 extern pal_cache_config_info_t l0d_cache_config_info;
812 extern pal_cache_config_info_t l0i_cache_config_info;
813 extern pal_cache_config_info_t l1_cache_config_info;
814 extern pal_cache_config_info_t l2_cache_config_info;
815
816 extern pal_cache_protection_info_t l0d_cache_protection_info;
817 extern pal_cache_protection_info_t l0i_cache_protection_info;
818 extern pal_cache_protection_info_t l1_cache_protection_info;
819 extern pal_cache_protection_info_t l2_cache_protection_info;
820
821 extern pal_cache_config_info_t pal_cache_config_info_get(pal_cache_level_t,
822 pal_cache_type_t);
823
824 extern pal_cache_protection_info_t pal_cache_protection_info_get(pal_cache_level_t,
825 pal_cache_type_t);
826
827
828 extern void pal_error(int);
829
830
831 /* Useful wrappers for the current list of pal procedures */
832
833 typedef union pal_bus_features_u {
834 u64 pal_bus_features_val;
835 struct {
836 u64 pbf_reserved1 : 29;
837 u64 pbf_req_bus_parking : 1;
838 u64 pbf_bus_lock_mask : 1;
839 u64 pbf_enable_half_xfer_rate : 1;
840 u64 pbf_reserved2 : 22;
841 u64 pbf_disable_xaction_queueing : 1;
842 u64 pbf_disable_resp_err_check : 1;
843 u64 pbf_disable_berr_check : 1;
844 u64 pbf_disable_bus_req_internal_err_signal : 1;
845 u64 pbf_disable_bus_req_berr_signal : 1;
846 u64 pbf_disable_bus_init_event_check : 1;
847 u64 pbf_disable_bus_init_event_signal : 1;
848 u64 pbf_disable_bus_addr_err_check : 1;
849 u64 pbf_disable_bus_addr_err_signal : 1;
850 u64 pbf_disable_bus_data_err_check : 1;
851 } pal_bus_features_s;
852 } pal_bus_features_u_t;
853
854 extern void pal_bus_features_print (u64);
855
856 /* Provide information about configurable processor bus features */
857 static inline s64
858 ia64_pal_bus_get_features (pal_bus_features_u_t *features_avail,
859 pal_bus_features_u_t *features_status,
860 pal_bus_features_u_t *features_control)
861 {
862 struct ia64_pal_retval iprv;
863 PAL_CALL_PHYS(iprv, PAL_BUS_GET_FEATURES, 0, 0, 0);
864 if (features_avail)
865 features_avail->pal_bus_features_val = iprv.v0;
866 if (features_status)
867 features_status->pal_bus_features_val = iprv.v1;
868 if (features_control)
869 features_control->pal_bus_features_val = iprv.v2;
870 return iprv.status;
871 }
872
873 /* Enables/disables specific processor bus features */
874 static inline s64
875 ia64_pal_bus_set_features (pal_bus_features_u_t feature_select)
876 {
877 struct ia64_pal_retval iprv;
878 PAL_CALL_PHYS(iprv, PAL_BUS_SET_FEATURES, feature_select.pal_bus_features_val, 0, 0);
879 return iprv.status;
880 }
881
882 /* Get detailed cache information */
883 static inline s64
884 ia64_pal_cache_config_info (u64 cache_level, u64 cache_type, pal_cache_config_info_t *conf)
885 {
886 struct ia64_pal_retval iprv;
887
888 PAL_CALL(iprv, PAL_CACHE_INFO, cache_level, cache_type, 0);
889
890 if (iprv.status == 0) {
891 conf->pcci_status = iprv.status;
892 conf->pcci_info_1.pcci1_data = iprv.v0;
893 conf->pcci_info_2.pcci2_data = iprv.v1;
894 conf->pcci_reserved = iprv.v2;
895 }
896 return iprv.status;
897
898 }
899
900 /* Get detailed cche protection information */
901 static inline s64
902 ia64_pal_cache_prot_info (u64 cache_level, u64 cache_type, pal_cache_protection_info_t *prot)
903 {
904 struct ia64_pal_retval iprv;
905
906 PAL_CALL(iprv, PAL_CACHE_PROT_INFO, cache_level, cache_type, 0);
907
908 if (iprv.status == 0) {
909 prot->pcpi_status = iprv.status;
910 prot->pcp_info[0].pcpi_data = iprv.v0 & 0xffffffff;
911 prot->pcp_info[1].pcpi_data = iprv.v0 >> 32;
912 prot->pcp_info[2].pcpi_data = iprv.v1 & 0xffffffff;
913 prot->pcp_info[3].pcpi_data = iprv.v1 >> 32;
914 prot->pcp_info[4].pcpi_data = iprv.v2 & 0xffffffff;
915 prot->pcp_info[5].pcpi_data = iprv.v2 >> 32;
916 }
917 return iprv.status;
918 }
919
920 /*
921 * Flush the processor instruction or data caches. *PROGRESS must be
922 * initialized to zero before calling this for the first time..
923 */
924 static inline s64
925 ia64_pal_cache_flush (u64 cache_type, u64 invalidate, u64 *progress, u64 *vector)
926 {
927 struct ia64_pal_retval iprv;
928 PAL_CALL_IC_OFF(iprv, PAL_CACHE_FLUSH, cache_type, invalidate, *progress);
929 if (vector)
930 *vector = iprv.v0;
931 *progress = iprv.v1;
932 return iprv.status;
933 }
934
935
936 /* Initialize the processor controlled caches */
937 static inline s64
938 ia64_pal_cache_init (u64 level, u64 cache_type, u64 rest)
939 {
940 struct ia64_pal_retval iprv;
941 PAL_CALL(iprv, PAL_CACHE_INIT, level, cache_type, rest);
942 return iprv.status;
943 }
944
945 /* Initialize the tags and data of a data or unified cache line of
946 * processor controlled cache to known values without the availability
947 * of backing memory.
948 */
949 static inline s64
950 ia64_pal_cache_line_init (u64 physical_addr, u64 data_value)
951 {
952 struct ia64_pal_retval iprv;
953 PAL_CALL(iprv, PAL_CACHE_LINE_INIT, physical_addr, data_value, 0);
954 return iprv.status;
955 }
956
957
958 /* Read the data and tag of a processor controlled cache line for diags */
959 static inline s64
960 ia64_pal_cache_read (pal_cache_line_id_u_t line_id, u64 physical_addr)
961 {
962 struct ia64_pal_retval iprv;
963 PAL_CALL(iprv, PAL_CACHE_READ, line_id.pclid_data, physical_addr, 0);
964 return iprv.status;
965 }
966
967 /* Return summary information about the heirarchy of caches controlled by the processor */
968 static inline s64
969 ia64_pal_cache_summary (u64 *cache_levels, u64 *unique_caches)
970 {
971 struct ia64_pal_retval iprv;
972 PAL_CALL(iprv, PAL_CACHE_SUMMARY, 0, 0, 0);
973 if (cache_levels)
974 *cache_levels = iprv.v0;
975 if (unique_caches)
976 *unique_caches = iprv.v1;
977 return iprv.status;
978 }
979
980 /* Write the data and tag of a processor-controlled cache line for diags */
981 static inline s64
982 ia64_pal_cache_write (pal_cache_line_id_u_t line_id, u64 physical_addr, u64 data)
983 {
984 struct ia64_pal_retval iprv;
985 PAL_CALL(iprv, PAL_CACHE_WRITE, line_id.pclid_data, physical_addr, data);
986 return iprv.status;
987 }
988
989
990 /* Return the parameters needed to copy relocatable PAL procedures from ROM to memory */
991 static inline s64
992 ia64_pal_copy_info (u64 copy_type, u64 num_procs, u64 num_iopics,
993 u64 *buffer_size, u64 *buffer_align)
994 {
995 struct ia64_pal_retval iprv;
996 PAL_CALL(iprv, PAL_COPY_INFO, copy_type, num_procs, num_iopics);
997 if (buffer_size)
998 *buffer_size = iprv.v0;
999 if (buffer_align)
1000 *buffer_align = iprv.v1;
1001 return iprv.status;
1002 }
1003
1004 /* Copy relocatable PAL procedures from ROM to memory */
1005 static inline s64
1006 ia64_pal_copy_pal (u64 target_addr, u64 alloc_size, u64 processor, u64 *pal_proc_offset)
1007 {
1008 struct ia64_pal_retval iprv;
1009 PAL_CALL(iprv, PAL_COPY_PAL, target_addr, alloc_size, processor);
1010 if (pal_proc_offset)
1011 *pal_proc_offset = iprv.v0;
1012 return iprv.status;
1013 }
1014
1015 /* Return the number of instruction and data debug register pairs */
1016 static inline s64
1017 ia64_pal_debug_info (u64 *inst_regs, u64 *data_regs)
1018 {
1019 struct ia64_pal_retval iprv;
1020 PAL_CALL(iprv, PAL_DEBUG_INFO, 0, 0, 0);
1021 if (inst_regs)
1022 *inst_regs = iprv.v0;
1023 if (data_regs)
1024 *data_regs = iprv.v1;
1025
1026 return iprv.status;
1027 }
1028
1029 #ifdef TBD
1030 /* Switch from IA64-system environment to IA-32 system environment */
1031 static inline s64
1032 ia64_pal_enter_ia32_env (ia32_env1, ia32_env2, ia32_env3)
1033 {
1034 struct ia64_pal_retval iprv;
1035 PAL_CALL(iprv, PAL_ENTER_IA_32_ENV, ia32_env1, ia32_env2, ia32_env3);
1036 return iprv.status;
1037 }
1038 #endif
1039
1040 /* Get unique geographical address of this processor on its bus */
1041 static inline s64
1042 ia64_pal_fixed_addr (u64 *global_unique_addr)
1043 {
1044 struct ia64_pal_retval iprv;
1045 PAL_CALL(iprv, PAL_FIXED_ADDR, 0, 0, 0);
1046 if (global_unique_addr)
1047 *global_unique_addr = iprv.v0;
1048 return iprv.status;
1049 }
1050
1051 /* Get base frequency of the platform if generated by the processor */
1052 static inline s64
1053 ia64_pal_freq_base (u64 *platform_base_freq)
1054 {
1055 struct ia64_pal_retval iprv;
1056 PAL_CALL(iprv, PAL_FREQ_BASE, 0, 0, 0);
1057 if (platform_base_freq)
1058 *platform_base_freq = iprv.v0;
1059 return iprv.status;
1060 }
1061
1062 /*
1063 * Get the ratios for processor frequency, bus frequency and interval timer to
1064 * to base frequency of the platform
1065 */
1066 static inline s64
1067 ia64_pal_freq_ratios (struct pal_freq_ratio *proc_ratio, struct pal_freq_ratio *bus_ratio,
1068 struct pal_freq_ratio *itc_ratio)
1069 {
1070 struct ia64_pal_retval iprv;
1071 PAL_CALL(iprv, PAL_FREQ_RATIOS, 0, 0, 0);
1072 if (proc_ratio)
1073 *(u64 *)proc_ratio = iprv.v0;
1074 if (bus_ratio)
1075 *(u64 *)bus_ratio = iprv.v1;
1076 if (itc_ratio)
1077 *(u64 *)itc_ratio = iprv.v2;
1078 return iprv.status;
1079 }
1080
1081 /* Make the processor enter HALT or one of the implementation dependent low
1082 * power states where prefetching and execution are suspended and cache and
1083 * TLB coherency is not maintained.
1084 */
1085 static inline s64
1086 ia64_pal_halt (u64 halt_state)
1087 {
1088 struct ia64_pal_retval iprv;
1089 PAL_CALL(iprv, PAL_HALT, halt_state, 0, 0);
1090 return iprv.status;
1091 }
1092
1093 typedef union pal_power_mgmt_info_u {
1094 u64 ppmi_data;
1095 struct {
1096 u64 exit_latency : 16,
1097 entry_latency : 16,
1098 power_consumption : 28,
1099 im : 1,
1100 co : 1,
1101 reserved : 2;
1102 } pal_power_mgmt_info_s;
1103 } pal_power_mgmt_info_u_t;
1104
1105 /* Return information about processor's optional power management capabilities. */
1106 static inline s64
1107 ia64_pal_halt_info (pal_power_mgmt_info_u_t *power_buf)
1108 {
1109 struct ia64_pal_retval iprv;
1110 PAL_CALL_STK(iprv, PAL_HALT_INFO, (unsigned long) power_buf, 0, 0);
1111 return iprv.status;
1112 }
1113
1114 /* Cause the processor to enter LIGHT HALT state, where prefetching and execution are
1115 * suspended, but cache and TLB coherency is maintained.
1116 */
1117 static inline s64
1118 ia64_pal_halt_light (void)
1119 {
1120 struct ia64_pal_retval iprv;
1121 PAL_CALL(iprv, PAL_HALT_LIGHT, 0, 0, 0);
1122 return iprv.status;
1123 }
1124
1125 /* Clear all the processor error logging registers and reset the indicator that allows
1126 * the error logging registers to be written. This procedure also checks the pending
1127 * machine check bit and pending INIT bit and reports their states.
1128 */
1129 static inline s64
1130 ia64_pal_mc_clear_log (u64 *pending_vector)
1131 {
1132 struct ia64_pal_retval iprv;
1133 PAL_CALL(iprv, PAL_MC_CLEAR_LOG, 0, 0, 0);
1134 if (pending_vector)
1135 *pending_vector = iprv.v0;
1136 return iprv.status;
1137 }
1138
1139 /* Ensure that all outstanding transactions in a processor are completed or that any
1140 * MCA due to thes outstanding transaction is taken.
1141 */
1142 static inline s64
1143 ia64_pal_mc_drain (void)
1144 {
1145 struct ia64_pal_retval iprv;
1146 PAL_CALL(iprv, PAL_MC_DRAIN, 0, 0, 0);
1147 return iprv.status;
1148 }
1149
1150 /* Return the machine check dynamic processor state */
1151 static inline s64
1152 ia64_pal_mc_dynamic_state (u64 offset, u64 *size, u64 *pds)
1153 {
1154 struct ia64_pal_retval iprv;
1155 PAL_CALL(iprv, PAL_MC_DYNAMIC_STATE, offset, 0, 0);
1156 if (size)
1157 *size = iprv.v0;
1158 if (pds)
1159 *pds = iprv.v1;
1160 return iprv.status;
1161 }
1162
1163 /* Return processor machine check information */
1164 static inline s64
1165 ia64_pal_mc_error_info (u64 info_index, u64 type_index, u64 *size, u64 *error_info)
1166 {
1167 struct ia64_pal_retval iprv;
1168 PAL_CALL(iprv, PAL_MC_ERROR_INFO, info_index, type_index, 0);
1169 if (size)
1170 *size = iprv.v0;
1171 if (error_info)
1172 *error_info = iprv.v1;
1173 return iprv.status;
1174 }
1175
1176 /* Inform PALE_CHECK whether a machine check is expected so that PALE_CHECK willnot
1177 * attempt to correct any expected machine checks.
1178 */
1179 static inline s64
1180 ia64_pal_mc_expected (u64 expected, u64 *previous)
1181 {
1182 struct ia64_pal_retval iprv;
1183 PAL_CALL(iprv, PAL_MC_EXPECTED, expected, 0, 0);
1184 if (previous)
1185 *previous = iprv.v0;
1186 return iprv.status;
1187 }
1188
1189 /* Register a platform dependent location with PAL to which it can save
1190 * minimal processor state in the event of a machine check or initialization
1191 * event.
1192 */
1193 static inline s64
1194 ia64_pal_mc_register_mem (u64 physical_addr)
1195 {
1196 struct ia64_pal_retval iprv;
1197 PAL_CALL(iprv, PAL_MC_REGISTER_MEM, physical_addr, 0, 0);
1198 return iprv.status;
1199 }
1200
1201 /* Restore minimal architectural processor state, set CMC interrupt if necessary
1202 * and resume execution
1203 */
1204 static inline s64
1205 ia64_pal_mc_resume (u64 set_cmci, u64 save_ptr)
1206 {
1207 struct ia64_pal_retval iprv;
1208 PAL_CALL(iprv, PAL_MC_RESUME, set_cmci, save_ptr, 0);
1209 return iprv.status;
1210 }
1211
1212 /* Return the memory attributes implemented by the processor */
1213 static inline s64
1214 ia64_pal_mem_attrib (u64 *mem_attrib)
1215 {
1216 struct ia64_pal_retval iprv;
1217 PAL_CALL(iprv, PAL_MEM_ATTRIB, 0, 0, 0);
1218 if (mem_attrib)
1219 *mem_attrib = iprv.v0 & 0xff;
1220 return iprv.status;
1221 }
1222
1223 /* Return the amount of memory needed for second phase of processor
1224 * self-test and the required alignment of memory.
1225 */
1226 static inline s64
1227 ia64_pal_mem_for_test (u64 *bytes_needed, u64 *alignment)
1228 {
1229 struct ia64_pal_retval iprv;
1230 PAL_CALL(iprv, PAL_MEM_FOR_TEST, 0, 0, 0);
1231 if (bytes_needed)
1232 *bytes_needed = iprv.v0;
1233 if (alignment)
1234 *alignment = iprv.v1;
1235 return iprv.status;
1236 }
1237
1238 typedef union pal_perf_mon_info_u {
1239 u64 ppmi_data;
1240 struct {
1241 u64 generic : 8,
1242 width : 8,
1243 cycles : 8,
1244 retired : 8,
1245 reserved : 32;
1246 } pal_perf_mon_info_s;
1247 } pal_perf_mon_info_u_t;
1248
1249 /* Return the performance monitor information about what can be counted
1250 * and how to configure the monitors to count the desired events.
1251 */
1252 static inline s64
1253 ia64_pal_perf_mon_info (u64 *pm_buffer, pal_perf_mon_info_u_t *pm_info)
1254 {
1255 struct ia64_pal_retval iprv;
1256 PAL_CALL(iprv, PAL_PERF_MON_INFO, (unsigned long) pm_buffer, 0, 0);
1257 if (pm_info)
1258 pm_info->ppmi_data = iprv.v0;
1259 return iprv.status;
1260 }
1261
1262 /* Specifies the physical address of the processor interrupt block
1263 * and I/O port space.
1264 */
1265 static inline s64
1266 ia64_pal_platform_addr (u64 type, u64 physical_addr)
1267 {
1268 struct ia64_pal_retval iprv;
1269 PAL_CALL(iprv, PAL_PLATFORM_ADDR, type, physical_addr, 0);
1270 return iprv.status;
1271 }
1272
1273 /* Set the SAL PMI entrypoint in memory */
1274 static inline s64
1275 ia64_pal_pmi_entrypoint (u64 sal_pmi_entry_addr)
1276 {
1277 struct ia64_pal_retval iprv;
1278 PAL_CALL(iprv, PAL_PMI_ENTRYPOINT, sal_pmi_entry_addr, 0, 0);
1279 return iprv.status;
1280 }
1281
1282 struct pal_features_s;
1283 /* Provide information about configurable processor features */
1284 static inline s64
1285 ia64_pal_proc_get_features (u64 *features_avail,
1286 u64 *features_status,
1287 u64 *features_control)
1288 {
1289 struct ia64_pal_retval iprv;
1290 PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, 0, 0);
1291 if (iprv.status == 0) {
1292 *features_avail = iprv.v0;
1293 *features_status = iprv.v1;
1294 *features_control = iprv.v2;
1295 }
1296 return iprv.status;
1297 }
1298
1299 /* Enable/disable processor dependent features */
1300 static inline s64
1301 ia64_pal_proc_set_features (u64 feature_select)
1302 {
1303 struct ia64_pal_retval iprv;
1304 PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES, feature_select, 0, 0);
1305 return iprv.status;
1306 }
1307
1308 /*
1309 * Put everything in a struct so we avoid the global offset table whenever
1310 * possible.
1311 */
1312 typedef struct ia64_ptce_info_s {
1313 u64 base;
1314 u32 count[2];
1315 u32 stride[2];
1316 } ia64_ptce_info_t;
1317
1318 /* Return the information required for the architected loop used to purge
1319 * (initialize) the entire TC
1320 */
1321 static inline s64
1322 ia64_get_ptce (ia64_ptce_info_t *ptce)
1323 {
1324 struct ia64_pal_retval iprv;
1325
1326 if (!ptce)
1327 return -1;
1328
1329 PAL_CALL(iprv, PAL_PTCE_INFO, 0, 0, 0);
1330 if (iprv.status == 0) {
1331 ptce->base = iprv.v0;
1332 ptce->count[0] = iprv.v1 >> 32;
1333 ptce->count[1] = iprv.v1 & 0xffffffff;
1334 ptce->stride[0] = iprv.v2 >> 32;
1335 ptce->stride[1] = iprv.v2 & 0xffffffff;
1336 }
1337 return iprv.status;
1338 }
1339
1340 /* Return info about implemented application and control registers. */
1341 static inline s64
1342 ia64_pal_register_info (u64 info_request, u64 *reg_info_1, u64 *reg_info_2)
1343 {
1344 struct ia64_pal_retval iprv;
1345 PAL_CALL(iprv, PAL_REGISTER_INFO, info_request, 0, 0);
1346 if (reg_info_1)
1347 *reg_info_1 = iprv.v0;
1348 if (reg_info_2)
1349 *reg_info_2 = iprv.v1;
1350 return iprv.status;
1351 }
1352
1353 typedef union pal_hints_u {
1354 u64 ph_data;
1355 struct {
1356 u64 si : 1,
1357 li : 1,
1358 reserved : 62;
1359 } pal_hints_s;
1360 } pal_hints_u_t;
1361
1362 /* Return information about the register stack and RSE for this processor
1363 * implementation.
1364 */
1365 static inline s64
1366 ia64_pal_rse_info (u64 *num_phys_stacked, pal_hints_u_t *hints)
1367 {
1368 struct ia64_pal_retval iprv;
1369 PAL_CALL(iprv, PAL_RSE_INFO, 0, 0, 0);
1370 if (num_phys_stacked)
1371 *num_phys_stacked = iprv.v0;
1372 if (hints)
1373 hints->ph_data = iprv.v1;
1374 return iprv.status;
1375 }
1376
1377 /* Cause the processor to enter SHUTDOWN state, where prefetching and execution are
1378 * suspended, but cause cache and TLB coherency to be maintained.
1379 * This is usually called in IA-32 mode.
1380 */
1381 static inline s64
1382 ia64_pal_shutdown (void)
1383 {
1384 struct ia64_pal_retval iprv;
1385 PAL_CALL(iprv, PAL_SHUTDOWN, 0, 0, 0);
1386 return iprv.status;
1387 }
1388
1389 /* Perform the second phase of processor self-test. */
1390 static inline s64
1391 ia64_pal_test_proc (u64 test_addr, u64 test_size, u64 attributes, u64 *self_test_state)
1392 {
1393 struct ia64_pal_retval iprv;
1394 PAL_CALL(iprv, PAL_TEST_PROC, test_addr, test_size, attributes);
1395 if (self_test_state)
1396 *self_test_state = iprv.v0;
1397 return iprv.status;
1398 }
1399
1400 typedef union pal_version_u {
1401 u64 pal_version_val;
1402 struct {
1403 u64 pv_pal_b_rev : 8;
1404 u64 pv_pal_b_model : 8;
1405 u64 pv_reserved1 : 8;
1406 u64 pv_pal_vendor : 8;
1407 u64 pv_pal_a_rev : 8;
1408 u64 pv_pal_a_model : 8;
1409 u64 pv_reserved2 : 16;
1410 } pal_version_s;
1411 } pal_version_u_t;
1412
1413
1414 /* Return PAL version information */
1415 static inline s64
1416 ia64_pal_version (pal_version_u_t *pal_min_version, pal_version_u_t *pal_cur_version)
1417 {
1418 struct ia64_pal_retval iprv;
1419 PAL_CALL_PHYS(iprv, PAL_VERSION, 0, 0, 0);
1420 if (pal_min_version)
1421 pal_min_version->pal_version_val = iprv.v0;
1422
1423 if (pal_cur_version)
1424 pal_cur_version->pal_version_val = iprv.v1;
1425
1426 return iprv.status;
1427 }
1428
1429 typedef union pal_tc_info_u {
1430 u64 pti_val;
1431 struct {
1432 u64 num_sets : 8,
1433 associativity : 8,
1434 num_entries : 16,
1435 pf : 1,
1436 unified : 1,
1437 reduce_tr : 1,
1438 reserved : 29;
1439 } pal_tc_info_s;
1440 } pal_tc_info_u_t;
1441
1442 #define tc_reduce_tr pal_tc_info_s.reduce_tr
1443 #define tc_unified pal_tc_info_s.unified
1444 #define tc_pf pal_tc_info_s.pf
1445 #define tc_num_entries pal_tc_info_s.num_entries
1446 #define tc_associativity pal_tc_info_s.associativity
1447 #define tc_num_sets pal_tc_info_s.num_sets
1448
1449
1450 /* Return information about the virtual memory characteristics of the processor
1451 * implementation.
1452 */
1453 static inline s64
1454 ia64_pal_vm_info (u64 tc_level, u64 tc_type, pal_tc_info_u_t *tc_info, u64 *tc_pages)
1455 {
1456 struct ia64_pal_retval iprv;
1457 PAL_CALL(iprv, PAL_VM_INFO, tc_level, tc_type, 0);
1458 if (tc_info)
1459 tc_info->pti_val = iprv.v0;
1460 if (tc_pages)
1461 *tc_pages = iprv.v1;
1462 return iprv.status;
1463 }
1464
1465 /* Get page size information about the virtual memory characteristics of the processor
1466 * implementation.
1467 */
1468 static inline s64
1469 ia64_pal_vm_page_size (u64 *tr_pages, u64 *vw_pages)
1470 {
1471 struct ia64_pal_retval iprv;
1472 PAL_CALL(iprv, PAL_VM_PAGE_SIZE, 0, 0, 0);
1473 if (tr_pages)
1474 *tr_pages = iprv.v0;
1475 if (vw_pages)
1476 *vw_pages = iprv.v1;
1477 return iprv.status;
1478 }
1479
1480 typedef union pal_vm_info_1_u {
1481 u64 pvi1_val;
1482 struct {
1483 u64 vw : 1,
1484 phys_add_size : 7,
1485 key_size : 8,
1486 max_pkr : 8,
1487 hash_tag_id : 8,
1488 max_dtr_entry : 8,
1489 max_itr_entry : 8,
1490 max_unique_tcs : 8,
1491 num_tc_levels : 8;
1492 } pal_vm_info_1_s;
1493 } pal_vm_info_1_u_t;
1494
1495 typedef union pal_vm_info_2_u {
1496 u64 pvi2_val;
1497 struct {
1498 u64 impl_va_msb : 8,
1499 rid_size : 8,
1500 reserved : 48;
1501 } pal_vm_info_2_s;
1502 } pal_vm_info_2_u_t;
1503
1504 /* Get summary information about the virtual memory characteristics of the processor
1505 * implementation.
1506 */
1507 static inline s64
1508 ia64_pal_vm_summary (pal_vm_info_1_u_t *vm_info_1, pal_vm_info_2_u_t *vm_info_2)
1509 {
1510 struct ia64_pal_retval iprv;
1511 PAL_CALL(iprv, PAL_VM_SUMMARY, 0, 0, 0);
1512 if (vm_info_1)
1513 vm_info_1->pvi1_val = iprv.v0;
1514 if (vm_info_2)
1515 vm_info_2->pvi2_val = iprv.v1;
1516 return iprv.status;
1517 }
1518
1519 typedef union pal_itr_valid_u {
1520 u64 piv_val;
1521 struct {
1522 u64 access_rights_valid : 1,
1523 priv_level_valid : 1,
1524 dirty_bit_valid : 1,
1525 mem_attr_valid : 1,
1526 reserved : 60;
1527 } pal_tr_valid_s;
1528 } pal_tr_valid_u_t;
1529
1530 /* Read a translation register */
1531 static inline s64
1532 ia64_pal_tr_read (u64 reg_num, u64 tr_type, u64 *tr_buffer, pal_tr_valid_u_t *tr_valid)
1533 {
1534 struct ia64_pal_retval iprv;
1535 PAL_CALL_PHYS_STK(iprv, PAL_VM_TR_READ, reg_num, tr_type,(u64)ia64_tpa(tr_buffer));
1536 if (tr_valid)
1537 tr_valid->piv_val = iprv.v0;
1538 return iprv.status;
1539 }
1540
1541 /*
1542 * PAL_PREFETCH_VISIBILITY transaction types
1543 */
1544 #define PAL_VISIBILITY_VIRTUAL 0
1545 #define PAL_VISIBILITY_PHYSICAL 1
1546
1547 /*
1548 * PAL_PREFETCH_VISIBILITY return codes
1549 */
1550 #define PAL_VISIBILITY_OK 1
1551 #define PAL_VISIBILITY_OK_REMOTE_NEEDED 0
1552 #define PAL_VISIBILITY_INVAL_ARG -2
1553 #define PAL_VISIBILITY_ERROR -3
1554
1555 static inline s64
1556 ia64_pal_prefetch_visibility (s64 trans_type)
1557 {
1558 struct ia64_pal_retval iprv;
1559 PAL_CALL(iprv, PAL_PREFETCH_VISIBILITY, trans_type, 0, 0);
1560 return iprv.status;
1561 }
1562
1563 /* data structure for getting information on logical to physical mappings */
1564 typedef union pal_log_overview_u {
1565 struct {
1566 u64 num_log :16, /* Total number of logical
1567 * processors on this die
1568 */
1569 tpc :8, /* Threads per core */
1570 reserved3 :8, /* Reserved */
1571 cpp :8, /* Cores per processor */
1572 reserved2 :8, /* Reserved */
1573 ppid :8, /* Physical processor ID */
1574 reserved1 :8; /* Reserved */
1575 } overview_bits;
1576 u64 overview_data;
1577 } pal_log_overview_t;
1578
1579 typedef union pal_proc_n_log_info1_u{
1580 struct {
1581 u64 tid :16, /* Thread id */
1582 reserved2 :16, /* Reserved */
1583 cid :16, /* Core id */
1584 reserved1 :16; /* Reserved */
1585 } ppli1_bits;
1586 u64 ppli1_data;
1587 } pal_proc_n_log_info1_t;
1588
1589 typedef union pal_proc_n_log_info2_u {
1590 struct {
1591 u64 la :16, /* Logical address */
1592 reserved :48; /* Reserved */
1593 } ppli2_bits;
1594 u64 ppli2_data;
1595 } pal_proc_n_log_info2_t;
1596
1597 typedef struct pal_logical_to_physical_s
1598 {
1599 pal_log_overview_t overview;
1600 pal_proc_n_log_info1_t ppli1;
1601 pal_proc_n_log_info2_t ppli2;
1602 } pal_logical_to_physical_t;
1603
1604 #define overview_num_log overview.overview_bits.num_log
1605 #define overview_tpc overview.overview_bits.tpc
1606 #define overview_cpp overview.overview_bits.cpp
1607 #define overview_ppid overview.overview_bits.ppid
1608 #define log1_tid ppli1.ppli1_bits.tid
1609 #define log1_cid ppli1.ppli1_bits.cid
1610 #define log2_la ppli2.ppli2_bits.la
1611
1612 /* Get information on logical to physical processor mappings. */
1613 static inline s64
1614 ia64_pal_logical_to_phys(u64 proc_number, pal_logical_to_physical_t *mapping)
1615 {
1616 struct ia64_pal_retval iprv;
1617
1618 PAL_CALL(iprv, PAL_LOGICAL_TO_PHYSICAL, proc_number, 0, 0);
1619
1620 if (iprv.status == PAL_STATUS_SUCCESS)
1621 {
1622 if (proc_number == 0)
1623 mapping->overview.overview_data = iprv.v0;
1624 mapping->ppli1.ppli1_data = iprv.v1;
1625 mapping->ppli2.ppli2_data = iprv.v2;
1626 }
1627
1628 return iprv.status;
1629 }
1630 #endif /* __ASSEMBLY__ */
1631
1632 #endif /* _ASM_IA64_PAL_H */
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