include/asm-ppc/pci-bridge.h

   1 #ifdef __KERNEL__
   2 #ifndef _ASM_PCI_BRIDGE_H
   3 #define _ASM_PCI_BRIDGE_H
   4
   5 #include <linux/ioport.h>
   6 #include <linux/pci.h>
   7
   8 struct device_node;
   9 struct pci_controller;
  10
  11 /*
  12  * pci_io_base returns the memory address at which you can access
  13  * the I/O space for PCI bus number `bus' (or NULL on error).
  14  */
  15 extern void __iomem *pci_bus_io_base(unsigned int bus);
  16 extern unsigned long pci_bus_io_base_phys(unsigned int bus);
  17 extern unsigned long pci_bus_mem_base_phys(unsigned int bus);
  18
  19 /* Allocate a new PCI host bridge structure */
  20 extern struct pci_controller* pcibios_alloc_controller(void);
  21
  22 /* Helper function for setting up resources */
  23 extern void pci_init_resource(struct resource *res, unsigned long start,
  24                               unsigned long end, int flags, char *name);
  25
  26 /* Get the PCI host controller for a bus */
  27 extern struct pci_controller* pci_bus_to_hose(int bus);
  28
  29 /* Get the PCI host controller for an OF device */
  30 extern struct pci_controller*
  31 pci_find_hose_for_OF_device(struct device_node* node);
  32
  33 /* Fill up host controller resources from the OF node */
  34 extern void
  35 pci_process_bridge_OF_ranges(struct pci_controller *hose,
  36                            struct device_node *dev, int primary);
  37
  38 /*
  39  * Structure of a PCI controller (host bridge)
  40  */
  41 struct pci_controller {
  42         int index;                      /* PCI domain number */
  43         struct pci_controller *next;
  44         struct pci_bus *bus;
  45         void *arch_data;
  46
  47         int first_busno;
  48         int last_busno;
  49         int bus_offset;
  50
  51         void __iomem *io_base_virt;
  52         unsigned long io_base_phys;
  53
  54         /* Some machines (PReP) have a non 1:1 mapping of
  55          * the PCI memory space in the CPU bus space
  56          */
  57         unsigned long pci_mem_offset;
  58
  59         struct pci_ops *ops;
  60         volatile unsigned int __iomem *cfg_addr;
  61         volatile void __iomem *cfg_data;
  62         /*
  63          * If set, indirect method will set the cfg_type bit as
  64          * needed to generate type 1 configuration transactions.
  65          */
  66         int set_cfg_type;
  67
  68         /* Currently, we limit ourselves to 1 IO range and 3 mem
  69          * ranges since the common pci_bus structure can't handle more
  70          */
  71         struct resource io_resource;
  72         struct resource mem_resources[3];
  73         int mem_resource_count;
  74
  75         /* Host bridge I/O and Memory space
  76          * Used for BAR placement algorithms
  77          */
  78         struct resource io_space;
  79         struct resource mem_space;
  80 };
  81
  82 /* These are used for config access before all the PCI probing
  83    has been done. */
  84 int early_read_config_byte(struct pci_controller *hose, int bus, int dev_fn,
  85                            int where, u8 *val);
  86 int early_read_config_word(struct pci_controller *hose, int bus, int dev_fn,
  87                            int where, u16 *val);
  88 int early_read_config_dword(struct pci_controller *hose, int bus, int dev_fn,
  89                             int where, u32 *val);
  90 int early_write_config_byte(struct pci_controller *hose, int bus, int dev_fn,
  91                             int where, u8 val);
  92 int early_write_config_word(struct pci_controller *hose, int bus, int dev_fn,
  93                             int where, u16 val);
  94 int early_write_config_dword(struct pci_controller *hose, int bus, int dev_fn,
  95                              int where, u32 val);
  96
  97 extern void setup_indirect_pci_nomap(struct pci_controller* hose,
  98                                void __iomem *cfg_addr, void __iomem *cfg_data);
  99 extern void setup_indirect_pci(struct pci_controller* hose,
 100                                u32 cfg_addr, u32 cfg_data);
 101 extern void setup_grackle(struct pci_controller *hose);
 102
 103 extern unsigned char common_swizzle(struct pci_dev *, unsigned char *);
 104
 105 /*
 106  *   The following code swizzles for exactly one bridge.  The routine
 107  *   common_swizzle below handles multiple bridges.  But there are a
 108  *   some boards that don't follow the PCI spec's suggestion so we
 109  *   break this piece out separately.
 110  */
 111 static inline unsigned char bridge_swizzle(unsigned char pin,
 112                 unsigned char idsel)
 113 {
 114         return (((pin-1) + idsel) % 4) + 1;
 115 }
 116
 117 /*
 118  * The following macro is used to lookup irqs in a standard table
 119  * format for those PPC systems that do not already have PCI
 120  * interrupts properly routed.
 121  */
 122 /* FIXME - double check this */
 123 #define PCI_IRQ_TABLE_LOOKUP                                                \
 124 ({ long _ctl_ = -1;                                                         \
 125    if (idsel >= min_idsel && idsel <= max_idsel && pin <= irqs_per_slot)    \
 126      _ctl_ = pci_irq_table[idsel - min_idsel][pin-1];                       \
 127    _ctl_; })
 128
 129 /*
 130  * Scan the buses below a given PCI host bridge and assign suitable
 131  * resources to all devices found.
 132  */
 133 extern int pciauto_bus_scan(struct pci_controller *, int);
 134
 135 #endif
 136 #endif /* __KERNEL__ */