include/asm-ppc64/iSeries/IoHriProcessorVpd.h

   1 /*
   2  * IoHriProcessorVpd.h
   3  * Copyright (C) 2001  Mike Corrigan IBM Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  18  */
  19 #ifndef _IOHRIPROCESSORVPD_H
  20 #define _IOHRIPROCESSORVPD_H
  21
  22 //===================================================================
  23 //
  24 //      This struct maps Processor Vpd that is DMAd to SLIC by CSP
  25 //
  26
  27 #include <asm/types.h>
  28
  29 struct IoHriProcessorVpd
  30 {
  31
  32         u8      xFormat;                // VPD format indicator         x00-x00
  33         u8      xProcStatus:8;          // Processor State              x01-x01
  34         u8      xSecondaryThreadCount;  // Secondary thread cnt         x02-x02
  35         u8      xSrcType:1;             // Src Type                     x03-x03
  36         u8      xSrcSoft:1;             // Src stay soft                ...
  37         u8      xSrcParable:1;          // Src parable                  ...
  38         u8      xRsvd1:5;               // Reserved                     ...
  39         u16     xHvPhysicalProcIndex;   // Hypervisor physical proc index04-x05
  40         u16     xRsvd2;                 // Reserved                     x06-x07
  41         u32     xHwNodeId;              // Hardware node id             x08-x0B
  42         u32     xHwProcId;              // Hardware processor id        x0C-x0F
  43
  44         u32     xTypeNum;               // Card Type/CCIN number        x10-x13
  45         u32     xModelNum;              // Model/Feature number         x14-x17
  46         u64     xSerialNum;             // Serial number                x18-x1F
  47         char xPartNum[12];              // Book Part or FPU number      x20-x2B
  48         char xMfgID[4];                 // Manufacturing ID             x2C-x2F
  49
  50         u32     xProcFreq;              // Processor Frequency          x30-x33
  51         u32     xTimeBaseFreq;          // Time Base Frequency          x34-x37
  52
  53         u32     xChipEcLevel;           // Chip EC Levels               x38-x3B
  54         u32     xProcIdReg;             // PIR SPR value                x3C-x3F
  55         u32     xPVR;                   // PVR value                    x40-x43
  56         u8      xRsvd3[12];             // Reserved                     x44-x4F
  57
  58         u32     xInstCacheSize;         // Instruction cache size in KB x50-x53
  59         u32     xInstBlockSize;         // Instruction cache block size x54-x57
  60         u32     xDataCacheOperandSize;  // Data cache operand size      x58-x5B
  61         u32     xInstCacheOperandSize;  // Inst cache operand size      x5C-x5F
  62
  63         u32     xDataL1CacheSizeKB;     // L1 data cache size in KB     x60-x63
  64         u32     xDataL1CacheLineSize;   // L1 data cache block size     x64-x67
  65         u64     xRsvd4;                 // Reserved                     x68-x6F
  66
  67         u32     xDataL2CacheSizeKB;     // L2 data cache size in KB     x70-x73
  68         u32     xDataL2CacheLineSize;   // L2 data cache block size     x74-x77
  69         u64     xRsvd5;                 // Reserved                     x78-x7F
  70
  71         u32     xDataL3CacheSizeKB;     // L3 data cache size in KB     x80-x83
  72         u32     xDataL3CacheLineSize;   // L3 data cache block size     x84-x87
  73         u64     xRsvd6;                 // Reserved                     x88-x8F
  74
  75         u64     xFruLabel;              // Card Location Label          x90-x97
  76         u8      xSlotsOnCard;           // Slots on card (0=no slots)   x98-x98
  77         u8      xPartLocFlag;           // Location flag (0-pluggable 1-imbedded) x99-x99
  78         u16     xSlotMapIndex;          // Index in slot map table      x9A-x9B
  79         u8      xSmartCardPortNo;       // Smart card port number       x9C-x9C
  80         u8      xRsvd7;                 // Reserved                     x9D-x9D
  81         u16     xFrameIdAndRackUnit;    // Frame ID and rack unit adr   x9E-x9F
  82
  83         u8      xRsvd8[24];             // Reserved                     xA0-xB7
  84
  85         char xProcSrc[72];              // CSP format SRC               xB8-xFF
  86 };
  87
  88 #endif /* _IOHRIPROCESSORVPD_H */