include/asm-sparc/irq.h

   1 /* $Id: irq.h,v 1.32 2000/08/26 02:42:28 anton Exp $
   2  * irq.h: IRQ registers on the Sparc.
   3  *
   4  * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
   5  */
   6
   7 #ifndef _SPARC_IRQ_H
   8 #define _SPARC_IRQ_H
   9
  10 #include <linux/config.h>
  11 #include <linux/linkage.h>
  12 #include <linux/threads.h>     /* For NR_CPUS */
  13 #include <linux/interrupt.h>
  14
  15 #include <asm/system.h>     /* For SUN4M_NCPUS */
  16 #include <asm/btfixup.h>
  17
  18 #define __irq_ino(irq) irq
  19 #define __irq_pil(irq) irq
  20 BTFIXUPDEF_CALL(char *, __irq_itoa, unsigned int)
  21 #define __irq_itoa(irq) BTFIXUP_CALL(__irq_itoa)(irq)
  22
  23 #define NR_IRQS    16
  24
  25 #define irq_canonicalize(irq)   (irq)
  26
  27 /* Dave Redman (djhr@tadpole.co.uk)
  28  * changed these to function pointers.. it saves cycles and will allow
  29  * the irq dependencies to be split into different files at a later date
  30  * sun4c_irq.c, sun4m_irq.c etc so we could reduce the kernel size.
  31  * Jakub Jelinek (jj@sunsite.mff.cuni.cz)
  32  * Changed these to btfixup entities... It saves cycles :)
  33  */
  34 BTFIXUPDEF_CALL(void, disable_irq, unsigned int)
  35 BTFIXUPDEF_CALL(void, enable_irq, unsigned int)
  36 BTFIXUPDEF_CALL(void, disable_pil_irq, unsigned int)
  37 BTFIXUPDEF_CALL(void, enable_pil_irq, unsigned int)
  38 BTFIXUPDEF_CALL(void, clear_clock_irq, void)
  39 BTFIXUPDEF_CALL(void, clear_profile_irq, int)
  40 BTFIXUPDEF_CALL(void, load_profile_irq, int, unsigned int)
  41
  42 static inline void disable_irq_nosync(unsigned int irq)
  43 {
  44         BTFIXUP_CALL(disable_irq)(irq);
  45 }
  46
  47 static inline void disable_irq(unsigned int irq)
  48 {
  49         BTFIXUP_CALL(disable_irq)(irq);
  50 }
  51
  52 static inline void enable_irq(unsigned int irq)
  53 {
  54         BTFIXUP_CALL(enable_irq)(irq);
  55 }
  56
  57 static inline void disable_pil_irq(unsigned int irq)
  58 {
  59         BTFIXUP_CALL(disable_pil_irq)(irq);
  60 }
  61
  62 static inline void enable_pil_irq(unsigned int irq)
  63 {
  64         BTFIXUP_CALL(enable_pil_irq)(irq);
  65 }
  66
  67 static inline void clear_clock_irq(void)
  68 {
  69         BTFIXUP_CALL(clear_clock_irq)();
  70 }
  71
  72 static inline void clear_profile_irq(int irq)
  73 {
  74         BTFIXUP_CALL(clear_profile_irq)(irq);
  75 }
  76
  77 static inline void load_profile_irq(int cpu, int limit)
  78 {
  79         BTFIXUP_CALL(load_profile_irq)(cpu, limit);
  80 }
  81
  82 extern void (*sparc_init_timers)(irqreturn_t (*lvl10_irq)(int, void *, struct pt_regs *));
  83 extern void claim_ticker14(irqreturn_t (*irq_handler)(int, void *, struct pt_regs *),
  84                            int irq,
  85                            unsigned int timeout);
  86
  87 #ifdef CONFIG_SMP
  88 BTFIXUPDEF_CALL(void, set_cpu_int, int, int)
  89 BTFIXUPDEF_CALL(void, clear_cpu_int, int, int)
  90 BTFIXUPDEF_CALL(void, set_irq_udt, int)
  91
  92 #define set_cpu_int(cpu,level) BTFIXUP_CALL(set_cpu_int)(cpu,level)
  93 #define clear_cpu_int(cpu,level) BTFIXUP_CALL(clear_cpu_int)(cpu,level)
  94 #define set_irq_udt(cpu) BTFIXUP_CALL(set_irq_udt)(cpu)
  95 #endif
  96
  97 extern int request_fast_irq(unsigned int irq, irqreturn_t (*handler)(int, void *, struct pt_regs *), unsigned long flags, __const__ char *devname);
  98
  99 /* On the sun4m, just like the timers, we have both per-cpu and master
 100  * interrupt registers.
 101  */
 102
 103 /* These registers are used for sending/receiving irqs from/to
 104  * different cpu's.
 105  */
 106 struct sun4m_intreg_percpu {
 107         unsigned int tbt;        /* Interrupts still pending for this cpu. */
 108
 109         /* These next two registers are WRITE-ONLY and are only
 110          * "on bit" sensitive, "off bits" written have NO affect.
 111          */
 112         unsigned int clear;  /* Clear this cpus irqs here. */
 113         unsigned int set;    /* Set this cpus irqs here. */
 114         unsigned char space[PAGE_SIZE - 12];
 115 };
 116
 117 /*
 118  * djhr
 119  * Actually the clear and set fields in this struct are misleading..
 120  * according to the SLAVIO manual (and the same applies for the SEC)
 121  * the clear field clears bits in the mask which will ENABLE that IRQ
 122  * the set field sets bits in the mask to DISABLE the IRQ.
 123  *
 124  * Also the undirected_xx address in the SLAVIO is defined as
 125  * RESERVED and write only..
 126  *
 127  * DAVEM_NOTE: The SLAVIO only specifies behavior on uniprocessor
 128  *             sun4m machines, for MP the layout makes more sense.
 129  */
 130 struct sun4m_intregs {
 131         struct sun4m_intreg_percpu cpu_intregs[SUN4M_NCPUS];
 132         unsigned int tbt;                /* IRQ's that are still pending. */
 133         unsigned int irqs;               /* Master IRQ bits. */
 134
 135         /* Again, like the above, two these registers are WRITE-ONLY. */
 136         unsigned int clear;              /* Clear master IRQ's by setting bits here. */
 137         unsigned int set;                /* Set master IRQ's by setting bits here. */
 138
 139         /* This register is both READ and WRITE. */
 140         unsigned int undirected_target;  /* Which cpu gets undirected irqs. */
 141 };
 142
 143 extern struct sun4m_intregs *sun4m_interrupts;
 144
 145 /*
 146  * Bit field defines for the interrupt registers on various
 147  * Sparc machines.
 148  */
 149
 150 /* The sun4c interrupt register. */
 151 #define SUN4C_INT_ENABLE  0x01     /* Allow interrupts. */
 152 #define SUN4C_INT_E14     0x80     /* Enable level 14 IRQ. */
 153 #define SUN4C_INT_E10     0x20     /* Enable level 10 IRQ. */
 154 #define SUN4C_INT_E8      0x10     /* Enable level 8 IRQ. */
 155 #define SUN4C_INT_E6      0x08     /* Enable level 6 IRQ. */
 156 #define SUN4C_INT_E4      0x04     /* Enable level 4 IRQ. */
 157 #define SUN4C_INT_E1      0x02     /* Enable level 1 IRQ. */
 158
 159 /* Dave Redman (djhr@tadpole.co.uk)
 160  * The sun4m interrupt registers.
 161  */
 162 #define SUN4M_INT_ENABLE        0x80000000
 163 #define SUN4M_INT_E14           0x00000080
 164 #define SUN4M_INT_E10           0x00080000
 165
 166 #define SUN4M_HARD_INT(x)       (0x000000001 << (x))
 167 #define SUN4M_SOFT_INT(x)       (0x000010000 << (x))
 168
 169 #define SUN4M_INT_MASKALL       0x80000000        /* mask all interrupts */
 170 #define SUN4M_INT_MODULE_ERR    0x40000000        /* module error */
 171 #define SUN4M_INT_M2S_WRITE     0x20000000        /* write buffer error */
 172 #define SUN4M_INT_ECC           0x10000000        /* ecc memory error */
 173 #define SUN4M_INT_FLOPPY        0x00400000        /* floppy disk */
 174 #define SUN4M_INT_MODULE        0x00200000        /* module interrupt */
 175 #define SUN4M_INT_VIDEO         0x00100000        /* onboard video */
 176 #define SUN4M_INT_REALTIME      0x00080000        /* system timer */
 177 #define SUN4M_INT_SCSI          0x00040000        /* onboard scsi */
 178 #define SUN4M_INT_AUDIO         0x00020000        /* audio/isdn */
 179 #define SUN4M_INT_ETHERNET      0x00010000        /* onboard ethernet */
 180 #define SUN4M_INT_SERIAL        0x00008000        /* serial ports */
 181 #define SUN4M_INT_KBDMS         0x00004000        /* keyboard/mouse */
 182 #define SUN4M_INT_SBUSBITS      0x00003F80        /* sbus int bits */
 183
 184 #define SUN4M_INT_SBUS(x)       (1 << (x+7))
 185 #define SUN4M_INT_VME(x)        (1 << (x))
 186
 187 struct irqaction;
 188 struct pt_regs;
 189 int handle_IRQ_event(unsigned int, struct pt_regs *, struct irqaction *);
 190
 191 #endif