arch/arm/mach-ixp4xx/common.c

   1 /*
   2  * arch/arm/mach-ixp4xx/common.c
   3  *
   4  * Generic code shared across all IXP4XX platforms
   5  *
   6  * Maintainer: Deepak Saxena <dsaxena@plexity.net>
   7  *
   8  * Copyright 2002 (c) Intel Corporation
   9  * Copyright 2003-2004 (c) MontaVista, Software, Inc.
  10  *
  11  * This file is licensed under  the terms of the GNU General Public
  12  * License version 2. This program is licensed "as is" without any
  13  * warranty of any kind, whether express or implied.
  14  */
  15
  16 #include <linux/config.h>
  17 #include <linux/kernel.h>
  18 #include <linux/mm.h>
  19 #include <linux/init.h>
  20 #include <linux/serial.h>
  21 #include <linux/sched.h>
  22 #include <linux/tty.h>
  23 #include <linux/serial_core.h>
  24 #include <linux/bootmem.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/bitops.h>
  27 #include <linux/time.h>
  28 #include <linux/timex.h>
  29
  30 #include <asm/hardware.h>
  31 #include <asm/uaccess.h>
  32 #include <asm/io.h>
  33 #include <asm/pgtable.h>
  34 #include <asm/page.h>
  35 #include <asm/irq.h>
  36
  37 #include <asm/mach/map.h>
  38 #include <asm/mach/irq.h>
  39 #include <asm/mach/time.h>
  40
  41 /*************************************************************************
  42  * IXP4xx chipset I/O mapping
  43  *************************************************************************/
  44 static struct map_desc ixp4xx_io_desc[] __initdata = {
  45         {       /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */
  46                 .virtual        = IXP4XX_PERIPHERAL_BASE_VIRT,
  47                 .physical       = IXP4XX_PERIPHERAL_BASE_PHYS,
  48                 .length         = IXP4XX_PERIPHERAL_REGION_SIZE,
  49                 .type           = MT_DEVICE
  50         }, {    /* Expansion Bus Config Registers */
  51                 .virtual        = IXP4XX_EXP_CFG_BASE_VIRT,
  52                 .physical       = IXP4XX_EXP_CFG_BASE_PHYS,
  53                 .length         = IXP4XX_EXP_CFG_REGION_SIZE,
  54                 .type           = MT_DEVICE
  55         }, {    /* PCI Registers */
  56                 .virtual        = IXP4XX_PCI_CFG_BASE_VIRT,
  57                 .physical       = IXP4XX_PCI_CFG_BASE_PHYS,
  58                 .length         = IXP4XX_PCI_CFG_REGION_SIZE,
  59                 .type           = MT_DEVICE
  60         },
  61 #ifdef CONFIG_DEBUG_LL
  62         {       /* Debug UART mapping */
  63                 .virtual        = IXP4XX_DEBUG_UART_BASE_VIRT,
  64                 .physical       = IXP4XX_DEBUG_UART_BASE_PHYS,
  65                 .length         = IXP4XX_DEBUG_UART_REGION_SIZE,
  66                 .type           = MT_DEVICE
  67         }
  68 #endif
  69 };
  70
  71 void __init ixp4xx_map_io(void)
  72 {
  73         iotable_init(ixp4xx_io_desc, ARRAY_SIZE(ixp4xx_io_desc));
  74 }
  75
  76
  77 /*************************************************************************
  78  * IXP4xx chipset IRQ handling
  79  *
  80  * TODO: GPIO IRQs should be marked invalid until the user of the IRQ
  81  *       (be it PCI or something else) configures that GPIO line
  82  *       as an IRQ.
  83  **************************************************************************/
  84 enum ixp4xx_irq_type {
  85         IXP4XX_IRQ_LEVEL, IXP4XX_IRQ_EDGE
  86 };
  87
  88 static void ixp4xx_config_irq(unsigned irq, enum ixp4xx_irq_type type);
  89
  90 /*
  91  * IRQ -> GPIO mapping table
  92  */
  93 static int irq2gpio[32] = {
  94         -1, -1, -1, -1, -1, -1,  0,  1,
  95         -1, -1, -1, -1, -1, -1, -1, -1,
  96         -1, -1, -1,  2,  3,  4,  5,  6,
  97          7,  8,  9, 10, 11, 12, -1, -1,
  98 };
  99
 100 static int ixp4xx_set_irq_type(unsigned int irq, unsigned int type)
 101 {
 102         int line = irq2gpio[irq];
 103         u32 int_style;
 104         enum ixp4xx_irq_type irq_type;
 105         volatile u32 *int_reg;
 106
 107         /*
 108          * Only for GPIO IRQs
 109          */
 110         if (line < 0)
 111                 return -EINVAL;
 112
 113         if (type & IRQT_BOTHEDGE) {
 114                 int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL;
 115                 irq_type = IXP4XX_IRQ_EDGE;
 116         } else  if (type & IRQT_RISING) {
 117                 int_style = IXP4XX_GPIO_STYLE_RISING_EDGE;
 118                 irq_type = IXP4XX_IRQ_EDGE;
 119         } else if (type & IRQT_FALLING) {
 120                 int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE;
 121                 irq_type = IXP4XX_IRQ_EDGE;
 122         } else if (type & IRQT_HIGH) {
 123                 int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH;
 124                 irq_type = IXP4XX_IRQ_LEVEL;
 125         } else if (type & IRQT_LOW) {
 126                 int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW;
 127                 irq_type = IXP4XX_IRQ_LEVEL;
 128         }
 129
 130         ixp4xx_config_irq(irq, irq_type);
 131
 132         if (line >= 8) {        /* pins 8-15 */
 133                 line -= 8;
 134                 int_reg = IXP4XX_GPIO_GPIT2R;
 135         } else {                /* pins 0-7 */
 136                 int_reg = IXP4XX_GPIO_GPIT1R;
 137         }
 138
 139         /* Clear the style for the appropriate pin */
 140         *int_reg &= ~(IXP4XX_GPIO_STYLE_CLEAR <<
 141                         (line * IXP4XX_GPIO_STYLE_SIZE));
 142
 143         /* Set the new style */
 144         *int_reg |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE));
 145 }
 146
 147 static void ixp4xx_irq_mask(unsigned int irq)
 148 {
 149         if (cpu_is_ixp46x() && irq >= 32)
 150                 *IXP4XX_ICMR2 &= ~(1 << (irq - 32));
 151         else
 152                 *IXP4XX_ICMR &= ~(1 << irq);
 153 }
 154
 155 static void ixp4xx_irq_unmask(unsigned int irq)
 156 {
 157         if (cpu_is_ixp46x() && irq >= 32)
 158                 *IXP4XX_ICMR2 |= (1 << (irq - 32));
 159         else
 160                 *IXP4XX_ICMR |= (1 << irq);
 161 }
 162
 163 static void ixp4xx_irq_ack(unsigned int irq)
 164 {
 165         int line = (irq < 32) ? irq2gpio[irq] : -1;
 166
 167         if (line >= 0)
 168                 gpio_line_isr_clear(line);
 169 }
 170
 171 /*
 172  * Level triggered interrupts on GPIO lines can only be cleared when the
 173  * interrupt condition disappears.
 174  */
 175 static void ixp4xx_irq_level_unmask(unsigned int irq)
 176 {
 177         ixp4xx_irq_ack(irq);
 178         ixp4xx_irq_unmask(irq);
 179 }
 180
 181 static struct irqchip ixp4xx_irq_level_chip = {
 182         .ack            = ixp4xx_irq_mask,
 183         .mask           = ixp4xx_irq_mask,
 184         .unmask         = ixp4xx_irq_level_unmask,
 185         .set_type       = ixp4xx_set_irq_type,
 186 };
 187
 188 static struct irqchip ixp4xx_irq_edge_chip = {
 189         .ack            = ixp4xx_irq_ack,
 190         .mask           = ixp4xx_irq_mask,
 191         .unmask         = ixp4xx_irq_unmask,
 192         .set_type       = ixp4xx_set_irq_type,
 193 };
 194
 195 static void ixp4xx_config_irq(unsigned irq, enum ixp4xx_irq_type type)
 196 {
 197         switch (type) {
 198         case IXP4XX_IRQ_LEVEL:
 199                 set_irq_chip(irq, &ixp4xx_irq_level_chip);
 200                 set_irq_handler(irq, do_level_IRQ);
 201                 break;
 202         case IXP4XX_IRQ_EDGE:
 203                 set_irq_chip(irq, &ixp4xx_irq_edge_chip);
 204                 set_irq_handler(irq, do_edge_IRQ);
 205                 break;
 206         }
 207         set_irq_flags(irq, IRQF_VALID);
 208 }
 209
 210 void __init ixp4xx_init_irq(void)
 211 {
 212         int i = 0;
 213
 214         /* Route all sources to IRQ instead of FIQ */
 215         *IXP4XX_ICLR = 0x0;
 216
 217         /* Disable all interrupt */
 218         *IXP4XX_ICMR = 0x0;
 219
 220         if (cpu_is_ixp46x()) {
 221                 /* Route upper 32 sources to IRQ instead of FIQ */
 222                 *IXP4XX_ICLR2 = 0x00;
 223
 224                 /* Disable upper 32 interrupts */
 225                 *IXP4XX_ICMR2 = 0x00;
 226         }
 227
 228         /* Default to all level triggered */
 229         for(i = 0; i < NR_IRQS; i++)
 230                 ixp4xx_config_irq(i, IXP4XX_IRQ_LEVEL);
 231 }
 232
 233
 234 /*************************************************************************
 235  * IXP4xx timer tick
 236  * We use OS timer1 on the CPU for the timer tick and the timestamp
 237  * counter as a source of real clock ticks to account for missed jiffies.
 238  *************************************************************************/
 239
 240 static unsigned volatile last_jiffy_time;
 241
 242 #define CLOCK_TICKS_PER_USEC    ((CLOCK_TICK_RATE + USEC_PER_SEC/2) / USEC_PER_SEC)
 243
 244 /* IRQs are disabled before entering here from do_gettimeofday() */
 245 static unsigned long ixp4xx_gettimeoffset(void)
 246 {
 247         u32 elapsed;
 248
 249         elapsed = *IXP4XX_OSTS - last_jiffy_time;
 250
 251         return elapsed / CLOCK_TICKS_PER_USEC;
 252 }
 253
 254 static irqreturn_t ixp4xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 255 {
 256         write_seqlock(&xtime_lock);
 257
 258         /* Clear Pending Interrupt by writing '1' to it */
 259         *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
 260
 261         /*
 262          * Catch up with the real idea of time
 263          */
 264         while ((*IXP4XX_OSTS - last_jiffy_time) > LATCH) {
 265                 timer_tick(regs);
 266                 last_jiffy_time += LATCH;
 267         }
 268
 269         write_sequnlock(&xtime_lock);
 270
 271         return IRQ_HANDLED;
 272 }
 273
 274 static struct irqaction ixp4xx_timer_irq = {
 275         .name           = "IXP4xx Timer Tick",
 276         .flags          = SA_INTERRUPT | SA_TIMER,
 277         .handler        = ixp4xx_timer_interrupt,
 278 };
 279
 280 static void __init ixp4xx_timer_init(void)
 281 {
 282         /* Clear Pending Interrupt by writing '1' to it */
 283         *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
 284
 285         /* Setup the Timer counter value */
 286         *IXP4XX_OSRT1 = (LATCH & ~IXP4XX_OST_RELOAD_MASK) | IXP4XX_OST_ENABLE;
 287
 288         /* Reset time-stamp counter */
 289         *IXP4XX_OSTS = 0;
 290         last_jiffy_time = 0;
 291
 292         /* Connect the interrupt handler and enable the interrupt */
 293         setup_irq(IRQ_IXP4XX_TIMER1, &ixp4xx_timer_irq);
 294 }
 295
 296 struct sys_timer ixp4xx_timer = {
 297         .init           = ixp4xx_timer_init,
 298         .offset         = ixp4xx_gettimeoffset,
 299 };
 300
 301 static struct resource ixp46x_i2c_resources[] = {
 302         [0] = {
 303                 .start  = 0xc8011000,
 304                 .end    = 0xc801101c,
 305                 .flags  = IORESOURCE_MEM,
 306         },
 307         [1] = {
 308                 .start  = IRQ_IXP4XX_I2C,
 309                 .end    = IRQ_IXP4XX_I2C,
 310                 .flags  = IORESOURCE_IRQ
 311         }
 312 };
 313
 314 /*
 315  * I2C controller. The IXP46x uses the same block as the IOP3xx, so
 316  * we just use the same device name.
 317  */
 318 static struct platform_device ixp46x_i2c_controller = {
 319         .name           = "IOP3xx-I2C",
 320         .id             = 0,
 321         .num_resources  = 2,
 322         .resource       = ixp46x_i2c_resources
 323 };
 324
 325 static struct platform_device *ixp46x_devices[] __initdata = {
 326         &ixp46x_i2c_controller
 327 };
 328
 329 void __init ixp4xx_sys_init(void)
 330 {
 331         if (cpu_is_ixp46x()) {
 332                 platform_add_devices(ixp46x_devices,
 333                                 ARRAY_SIZE(ixp46x_devices));
 334         }
 335 }
 336