arch/mips/kernel/irq_cpu.c

   1 /*
   2  * Copyright 2001 MontaVista Software Inc.
   3  * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
   4  *
   5  * Copyright (C) 2001 Ralf Baechle
   6  *
   7  * This file define the irq handler for MIPS CPU interrupts.
   8  *
   9  * This program is free software; you can redistribute  it and/or modify it
  10  * under  the terms of  the GNU General  Public License as published by the
  11  * Free Software Foundation;  either version 2 of the  License, or (at your
  12  * option) any later version.
  13  */
  14
  15 /*
  16  * Almost all MIPS CPUs define 8 interrupt sources.  They are typically
  17  * level triggered (i.e., cannot be cleared from CPU; must be cleared from
  18  * device).  The first two are software interrupts which we don't really
  19  * use or support.  The last one is usually the CPU timer interrupt if
  20  * counter register is present or, for CPUs with an external FPU, by
  21  * convention it's the FPU exception interrupt.
  22  *
  23  * Don't even think about using this on SMP.  You have been warned.
  24  *
  25  * This file exports one global function:
  26  *      void mips_cpu_irq_init(int irq_base);
  27  */
  28 #include <linux/init.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/kernel.h>
  31
  32 #include <asm/irq_cpu.h>
  33 #include <asm/mipsregs.h>
  34 #include <asm/system.h>
  35
  36 static int mips_cpu_irq_base;
  37
  38 static inline void unmask_mips_irq(unsigned int irq)
  39 {
  40         clear_c0_cause(0x100 << (irq - mips_cpu_irq_base));
  41         set_c0_status(0x100 << (irq - mips_cpu_irq_base));
  42 }
  43
  44 static inline void mask_mips_irq(unsigned int irq)
  45 {
  46         clear_c0_status(0x100 << (irq - mips_cpu_irq_base));
  47 }
  48
  49 static inline void mips_cpu_irq_enable(unsigned int irq)
  50 {
  51         unsigned long flags;
  52
  53         local_irq_save(flags);
  54         unmask_mips_irq(irq);
  55         local_irq_restore(flags);
  56 }
  57
  58 static void mips_cpu_irq_disable(unsigned int irq)
  59 {
  60         unsigned long flags;
  61
  62         local_irq_save(flags);
  63         mask_mips_irq(irq);
  64         local_irq_restore(flags);
  65 }
  66
  67 static unsigned int mips_cpu_irq_startup(unsigned int irq)
  68 {
  69         mips_cpu_irq_enable(irq);
  70
  71         return 0;
  72 }
  73
  74 #define mips_cpu_irq_shutdown   mips_cpu_irq_disable
  75
  76 /*
  77  * While we ack the interrupt interrupts are disabled and thus we don't need
  78  * to deal with concurrency issues.  Same for mips_cpu_irq_end.
  79  */
  80 static void mips_cpu_irq_ack(unsigned int irq)
  81 {
  82         /* Only necessary for soft interrupts */
  83         clear_c0_cause(0x100 << (irq - mips_cpu_irq_base));
  84
  85         mask_mips_irq(irq);
  86 }
  87
  88 static void mips_cpu_irq_end(unsigned int irq)
  89 {
  90         if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
  91                 unmask_mips_irq(irq);
  92 }
  93
  94 static hw_irq_controller mips_cpu_irq_controller = {
  95         "MIPS",
  96         mips_cpu_irq_startup,
  97         mips_cpu_irq_shutdown,
  98         mips_cpu_irq_enable,
  99         mips_cpu_irq_disable,
 100         mips_cpu_irq_ack,
 101         mips_cpu_irq_end,
 102         NULL                    /* no affinity stuff for UP */
 103 };
 104
 105
 106 void __init mips_cpu_irq_init(int irq_base)
 107 {
 108         int i;
 109
 110         for (i = irq_base; i < irq_base + 8; i++) {
 111                 irq_desc[i].status = IRQ_DISABLED;
 112                 irq_desc[i].action = NULL;
 113                 irq_desc[i].depth = 1;
 114                 irq_desc[i].handler = &mips_cpu_irq_controller;
 115         }
 116
 117         mips_cpu_irq_base = irq_base;
 118 }