arch/i386/kernel/cpu/mtrr/centaur.c

   1 #include <linux/init.h>
   2 #include <linux/mm.h>
   3 #include <asm/mtrr.h>
   4 #include <asm/msr.h>
   5 #include "mtrr.h"
   6
   7 static struct {
   8         unsigned long high;
   9         unsigned long low;
  10 } centaur_mcr[8];
  11
  12 static u8 centaur_mcr_reserved;
  13 static u8 centaur_mcr_type;     /* 0 for winchip, 1 for winchip2 */
  14
  15 /*
  16  *      Report boot time MCR setups
  17  */
  18
  19 static int
  20 centaur_get_free_region(unsigned long base, unsigned long size)
  21 /*  [SUMMARY] Get a free MTRR.
  22     <base> The starting (base) address of the region.
  23     <size> The size (in bytes) of the region.
  24     [RETURNS] The index of the region on success, else -1 on error.
  25 */
  26 {
  27         int i, max;
  28         mtrr_type ltype;
  29         unsigned long lbase;
  30         unsigned int lsize;
  31
  32         max = num_var_ranges;
  33         for (i = 0; i < max; ++i) {
  34                 if (centaur_mcr_reserved & (1 << i))
  35                         continue;
  36                 mtrr_if->get(i, &lbase, &lsize, &ltype);
  37                 if (lsize == 0)
  38                         return i;
  39         }
  40         return -ENOSPC;
  41 }
  42
  43 void
  44 mtrr_centaur_report_mcr(int mcr, u32 lo, u32 hi)
  45 {
  46         centaur_mcr[mcr].low = lo;
  47         centaur_mcr[mcr].high = hi;
  48 }
  49
  50 static void
  51 centaur_get_mcr(unsigned int reg, unsigned long *base,
  52                 unsigned int *size, mtrr_type * type)
  53 {
  54         *base = centaur_mcr[reg].high >> PAGE_SHIFT;
  55         *size = -(centaur_mcr[reg].low & 0xfffff000) >> PAGE_SHIFT;
  56         *type = MTRR_TYPE_WRCOMB;       /*  If it is there, it is write-combining  */
  57         if (centaur_mcr_type == 1 && ((centaur_mcr[reg].low & 31) & 2))
  58                 *type = MTRR_TYPE_UNCACHABLE;
  59         if (centaur_mcr_type == 1 && (centaur_mcr[reg].low & 31) == 25)
  60                 *type = MTRR_TYPE_WRBACK;
  61         if (centaur_mcr_type == 0 && (centaur_mcr[reg].low & 31) == 31)
  62                 *type = MTRR_TYPE_WRBACK;
  63
  64 }
  65
  66 static void centaur_set_mcr(unsigned int reg, unsigned long base,
  67                             unsigned long size, mtrr_type type)
  68 {
  69         unsigned long low, high;
  70
  71         if (size == 0) {
  72                 /*  Disable  */
  73                 high = low = 0;
  74         } else {
  75                 high = base << PAGE_SHIFT;
  76                 if (centaur_mcr_type == 0)
  77                         low = -size << PAGE_SHIFT | 0x1f;       /* only support write-combining... */
  78                 else {
  79                         if (type == MTRR_TYPE_UNCACHABLE)
  80                                 low = -size << PAGE_SHIFT | 0x02;       /* NC */
  81                         else
  82                                 low = -size << PAGE_SHIFT | 0x09;       /* WWO,WC */
  83                 }
  84         }
  85         centaur_mcr[reg].high = high;
  86         centaur_mcr[reg].low = low;
  87         wrmsr(MSR_IDT_MCR0 + reg, low, high);
  88 }
  89
  90 #if 0
  91 /*
  92  *      Initialise the later (saner) Winchip MCR variant. In this version
  93  *      the BIOS can pass us the registers it has used (but not their values)
  94  *      and the control register is read/write
  95  */
  96
  97 static void __init
  98 centaur_mcr1_init(void)
  99 {
 100         unsigned i;
 101         u32 lo, hi;
 102
 103         /* Unfortunately, MCR's are read-only, so there is no way to
 104          * find out what the bios might have done.
 105          */
 106
 107         rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
 108         if (((lo >> 17) & 7) == 1) {    /* Type 1 Winchip2 MCR */
 109                 lo &= ~0x1C0;   /* clear key */
 110                 lo |= 0x040;    /* set key to 1 */
 111                 wrmsr(MSR_IDT_MCR_CTRL, lo, hi);        /* unlock MCR */
 112         }
 113
 114         centaur_mcr_type = 1;
 115
 116         /*
 117          *  Clear any unconfigured MCR's.
 118          */
 119
 120         for (i = 0; i < 8; ++i) {
 121                 if (centaur_mcr[i].high == 0 && centaur_mcr[i].low == 0) {
 122                         if (!(lo & (1 << (9 + i))))
 123                                 wrmsr(MSR_IDT_MCR0 + i, 0, 0);
 124                         else
 125                                 /*
 126                                  *      If the BIOS set up an MCR we cannot see it
 127                                  *      but we don't wish to obliterate it
 128                                  */
 129                                 centaur_mcr_reserved |= (1 << i);
 130                 }
 131         }
 132         /*
 133          *  Throw the main write-combining switch...
 134          *  However if OOSTORE is enabled then people have already done far
 135          *  cleverer things and we should behave.
 136          */
 137
 138         lo |= 15;               /* Write combine enables */
 139         wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
 140 }
 141
 142 /*
 143  *      Initialise the original winchip with read only MCR registers
 144  *      no used bitmask for the BIOS to pass on and write only control
 145  */
 146
 147 static void __init
 148 centaur_mcr0_init(void)
 149 {
 150         unsigned i;
 151
 152         /* Unfortunately, MCR's are read-only, so there is no way to
 153          * find out what the bios might have done.
 154          */
 155
 156         /* Clear any unconfigured MCR's.
 157          * This way we are sure that the centaur_mcr array contains the actual
 158          * values. The disadvantage is that any BIOS tweaks are thus undone.
 159          *
 160          */
 161         for (i = 0; i < 8; ++i) {
 162                 if (centaur_mcr[i].high == 0 && centaur_mcr[i].low == 0)
 163                         wrmsr(MSR_IDT_MCR0 + i, 0, 0);
 164         }
 165
 166         wrmsr(MSR_IDT_MCR_CTRL, 0x01F0001F, 0); /* Write only */
 167 }
 168
 169 /*
 170  *      Initialise Winchip series MCR registers
 171  */
 172
 173 static void __init
 174 centaur_mcr_init(void)
 175 {
 176         struct set_mtrr_context ctxt;
 177
 178         set_mtrr_prepare_save(&ctxt);
 179         set_mtrr_cache_disable(&ctxt);
 180
 181         if (boot_cpu_data.x86_model == 4)
 182                 centaur_mcr0_init();
 183         else if (boot_cpu_data.x86_model == 8 || boot_cpu_data.x86_model == 9)
 184                 centaur_mcr1_init();
 185
 186         set_mtrr_done(&ctxt);
 187 }
 188 #endif
 189
 190 static int centaur_validate_add_page(unsigned long base,
 191                                      unsigned long size, unsigned int type)
 192 {
 193         /*
 194          *  FIXME: Winchip2 supports uncached
 195          */
 196         if (type != MTRR_TYPE_WRCOMB &&
 197             (centaur_mcr_type == 0 || type != MTRR_TYPE_UNCACHABLE)) {
 198                 printk(KERN_WARNING
 199                        "mtrr: only write-combining%s supported\n",
 200                        centaur_mcr_type ? " and uncacheable are"
 201                        : " is");
 202                 return -EINVAL;
 203         }
 204         return 0;
 205 }
 206
 207 static struct mtrr_ops centaur_mtrr_ops = {
 208         .vendor            = X86_VENDOR_CENTAUR,
 209 //      .init              = centaur_mcr_init,
 210         .set               = centaur_set_mcr,
 211         .get               = centaur_get_mcr,
 212         .get_free_region   = centaur_get_free_region,
 213         .validate_add_page = centaur_validate_add_page,
 214         .have_wrcomb       = positive_have_wrcomb,
 215 };
 216
 217 int __init centaur_init_mtrr(void)
 218 {
 219         set_mtrr_ops(&centaur_mtrr_ops);
 220         return 0;
 221 }
 222
 223 //arch_initcall(centaur_init_mtrr);