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[PATCH] fix memory scribble in arch/i386/pci/fixup.c
[linux-2.6/verdex.git] / sound / i2c / l3 / uda1341.c
blobe13122f3fc50947258372f8b728311dca009a3d6
1 /*
2 * Philips UDA1341 mixer device driver
3 * Copyright (c) 2002 Tomas Kasparek <tomas.kasparek@seznam.cz>
4 *
5 * Portions are Copyright (C) 2000 Lernout & Hauspie Speech Products, N.V.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License.
9 *
10 * History:
11 *
12 * 2002-03-13 Tomas Kasparek initial release - based on uda1341.c from OSS
13 * 2002-03-28 Tomas Kasparek basic mixer is working (volume, bass, treble)
14 * 2002-03-30 Tomas Kasparek proc filesystem support, complete mixer and DSP
15 * features support
16 * 2002-04-12 Tomas Kasparek proc interface update, code cleanup
17 * 2002-05-12 Tomas Kasparek another code cleanup
18 */
19
20 /* $Id: uda1341.c,v 1.15 2005/01/03 12:05:20 tiwai Exp $ */
21
22 #include <sound/driver.h>
23 #include <linux/module.h>
24 #include <linux/init.h>
25 #include <linux/types.h>
26 #include <linux/slab.h>
27 #include <linux/errno.h>
28 #include <linux/ioctl.h>
29
30 #include <asm/uaccess.h>
31
32 #include <sound/core.h>
33 #include <sound/control.h>
34 #include <sound/initval.h>
35 #include <sound/info.h>
36
37 #include <linux/l3/l3.h>
38
39 #include <sound/uda1341.h>
40
41 /* {{{ HW regs definition */
42
43 #define STAT0 0x00
44 #define STAT1 0x80
45 #define STAT_MASK 0x80
46
47 #define DATA0_0 0x00
48 #define DATA0_1 0x40
49 #define DATA0_2 0x80
50 #define DATA_MASK 0xc0
51
52 #define IS_DATA0(x) ((x) >= data0_0 && (x) <= data0_2)
53 #define IS_DATA1(x) ((x) == data1)
54 #define IS_STATUS(x) ((x) == stat0 || (x) == stat1)
55 #define IS_EXTEND(x) ((x) >= ext0 && (x) <= ext6)
56
57 /* }}} */
58
59 enum uda1341_regs_names {
60 stat0,
61 stat1,
62 data0_0,
63 data0_1,
64 data0_2,
65 data1,
66 ext0,
67 ext1,
68 ext2,
69 empty,
70 ext4,
71 ext5,
72 ext6,
73 uda1341_reg_last,
74 };
75
76 const char *uda1341_reg_names[] = {
77 "stat 0 ",
78 "stat 1 ",
79 "data 00",
80 "data 01",
81 "data 02",
82 "data 1 ",
83 "ext 0",
84 "ext 1",
85 "ext 2",
86 "empty",
87 "ext 4",
88 "ext 5",
89 "ext 6",
90 };
91
92 const int uda1341_enum_items[] = {
93 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
94 2, //peak - before/after
95 4, //deemp - none/32/44.1/48
96 0,
97 4, //filter - flat/min/min/max
98 0, 0, 0,
99 4, //mixer - differ/line/mic/mixer
100 0, 0, 0, 0, 0,
101 };
102
103 const char ** uda1341_enum_names[] = {
104 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
105 peak_names, //peak - before/after
106 deemp_names, //deemp - none/32/44.1/48
107 NULL,
108 filter_names, //filter - flat/min/min/max
109 NULL, NULL, NULL,
110 mixer_names, //mixer - differ/line/mic/mixer
111 NULL, NULL, NULL, NULL, NULL,
112 };
113
114 typedef int uda1341_cfg[CMD_LAST];
115
116 typedef struct uda1341 uda1341_t;
117
118 struct uda1341 {
119 int (*write) (struct l3_client *uda1341, unsigned short reg, unsigned short val);
120 int (*read) (struct l3_client *uda1341, unsigned short reg);
121 unsigned char regs[uda1341_reg_last];
122 int active;
123 spinlock_t reg_lock;
124 snd_card_t *card;
125 uda1341_cfg cfg;
126 #ifdef CONFIG_PM
127 unsigned char suspend_regs[uda1341_reg_last];
128 uda1341_cfg suspend_cfg;
129 #endif
130 };
131
132 //hack for ALSA magic casting
133 typedef struct l3_client l3_client_t;
134
135 /* transfer 8bit integer into string with binary representation */
136 void int2str_bin8(uint8_t val, char *buf){
137 const int size = sizeof(val) * 8;
138 int i;
139
140 for (i= 0; i < size; i++){
141 *(buf++) = (val >> (size - 1)) ? '1' : '0';
142 val <<= 1;
143 }
144 *buf = '\0'; //end the string with zero
145 }
146
147 /* {{{ HW manipulation routines */
148
149 int snd_uda1341_codec_write(struct l3_client *clnt, unsigned short reg, unsigned short val)
150 {
151 struct uda1341 *uda = clnt->driver_data;
152 unsigned char buf[2] = { 0xc0, 0xe0 }; // for EXT addressing
153 int err = 0;
154
155 uda->regs[reg] = val;
156
157 if (uda->active) {
158 if (IS_DATA0(reg)) {
159 err = l3_write(clnt, UDA1341_DATA0, (const unsigned char *)&val, 1);
160 } else if (IS_DATA1(reg)) {
161 err = l3_write(clnt, UDA1341_DATA1, (const unsigned char *)&val, 1);
162 } else if (IS_STATUS(reg)) {
163 err = l3_write(clnt, UDA1341_STATUS, (const unsigned char *)&val, 1);
164 } else if (IS_EXTEND(reg)) {
165 buf[0] |= (reg - ext0) & 0x7; //EXT address
166 buf[1] |= val; //EXT data
167 err = l3_write(clnt, UDA1341_DATA0, (const unsigned char *)buf, 2);
168 }
169 } else
170 printk(KERN_ERR "UDA1341 codec not active!\n");
171 return err;
172 }
173
174 int snd_uda1341_codec_read(struct l3_client *clnt, unsigned short reg)
175 {
176 unsigned char val;
177 int err;
178
179 err = l3_read(clnt, reg, &val, 1);
180 if (err == 1)
181 // use just 6bits - the rest is address of the reg
182 return val & 63;
183 return err < 0 ? err : -EIO;
184 }
185
186 static inline int snd_uda1341_valid_reg(struct l3_client *clnt, unsigned short reg)
187 {
188 return reg < uda1341_reg_last;
189 }
190
191 int snd_uda1341_update_bits(struct l3_client *clnt, unsigned short reg, unsigned short mask,
192 unsigned short shift, unsigned short value, int flush)
193 {
194 int change;
195 unsigned short old, new;
196 struct uda1341 *uda = clnt->driver_data;
197
198 #if 0
199 printk(KERN_DEBUG "update_bits: reg: %s mask: %d shift: %d val: %d\n",
200 uda1341_reg_names[reg], mask, shift, value);
201 #endif
202
203 if (!snd_uda1341_valid_reg(clnt, reg))
204 return -EINVAL;
205 spin_lock(&uda->reg_lock);
206 old = uda->regs[reg];
207 new = (old & ~(mask << shift)) | (value << shift);
208 change = old != new;
209 if (change) {
210 if (flush) uda->write(clnt, reg, new);
211 uda->regs[reg] = new;
212 }
213 spin_unlock(&uda->reg_lock);
214 return change;
215 }
216
217 int snd_uda1341_cfg_write(struct l3_client *clnt, unsigned short what,
218 unsigned short value, int flush)
219 {
220 struct uda1341 *uda = clnt->driver_data;
221 int ret = 0;
222 #ifdef CONFIG_PM
223 int reg;
224 #endif
225
226 #if 0
227 printk(KERN_DEBUG "cfg_write what: %d value: %d\n", what, value);
228 #endif
229
230 uda->cfg[what] = value;
231
232 switch(what) {
233 case CMD_RESET:
234 ret = snd_uda1341_update_bits(clnt, data0_2, 1, 2, 1, flush); // MUTE
235 ret = snd_uda1341_update_bits(clnt, stat0, 1, 6, 1, flush); // RESET
236 ret = snd_uda1341_update_bits(clnt, stat0, 1, 6, 0, flush); // RESTORE
237 uda->cfg[CMD_RESET]=0;
238 break;
239 case CMD_FS:
240 ret = snd_uda1341_update_bits(clnt, stat0, 3, 4, value, flush);
241 break;
242 case CMD_FORMAT:
243 ret = snd_uda1341_update_bits(clnt, stat0, 7, 1, value, flush);
244 break;
245 case CMD_OGAIN:
246 ret = snd_uda1341_update_bits(clnt, stat1, 1, 6, value, flush);
247 break;
248 case CMD_IGAIN:
249 ret = snd_uda1341_update_bits(clnt, stat1, 1, 5, value, flush);
250 break;
251 case CMD_DAC:
252 ret = snd_uda1341_update_bits(clnt, stat1, 1, 0, value, flush);
253 break;
254 case CMD_ADC:
255 ret = snd_uda1341_update_bits(clnt, stat1, 1, 1, value, flush);
256 break;
257 case CMD_VOLUME:
258 ret = snd_uda1341_update_bits(clnt, data0_0, 63, 0, value, flush);
259 break;
260 case CMD_BASS:
261 ret = snd_uda1341_update_bits(clnt, data0_1, 15, 2, value, flush);
262 break;
263 case CMD_TREBBLE:
264 ret = snd_uda1341_update_bits(clnt, data0_1, 3, 0, value, flush);
265 break;
266 case CMD_PEAK:
267 ret = snd_uda1341_update_bits(clnt, data0_2, 1, 5, value, flush);
268 break;
269 case CMD_DEEMP:
270 ret = snd_uda1341_update_bits(clnt, data0_2, 3, 3, value, flush);
271 break;
272 case CMD_MUTE:
273 ret = snd_uda1341_update_bits(clnt, data0_2, 1, 2, value, flush);
274 break;
275 case CMD_FILTER:
276 ret = snd_uda1341_update_bits(clnt, data0_2, 3, 0, value, flush);
277 break;
278 case CMD_CH1:
279 ret = snd_uda1341_update_bits(clnt, ext0, 31, 0, value, flush);
280 break;
281 case CMD_CH2:
282 ret = snd_uda1341_update_bits(clnt, ext1, 31, 0, value, flush);
283 break;
284 case CMD_MIC:
285 ret = snd_uda1341_update_bits(clnt, ext2, 7, 2, value, flush);
286 break;
287 case CMD_MIXER:
288 ret = snd_uda1341_update_bits(clnt, ext2, 3, 0, value, flush);
289 break;
290 case CMD_AGC:
291 ret = snd_uda1341_update_bits(clnt, ext4, 1, 4, value, flush);
292 break;
293 case CMD_IG:
294 ret = snd_uda1341_update_bits(clnt, ext4, 3, 0, value & 0x3, flush);
295 ret = snd_uda1341_update_bits(clnt, ext5, 31, 0, value >> 2, flush);
296 break;
297 case CMD_AGC_TIME:
298 ret = snd_uda1341_update_bits(clnt, ext6, 7, 2, value, flush);
299 break;
300 case CMD_AGC_LEVEL:
301 ret = snd_uda1341_update_bits(clnt, ext6, 3, 0, value, flush);
302 break;
303 #ifdef CONFIG_PM
304 case CMD_SUSPEND:
305 for (reg = stat0; reg < uda1341_reg_last; reg++)
306 uda->suspend_regs[reg] = uda->regs[reg];
307 for (reg = 0; reg < CMD_LAST; reg++)
308 uda->suspend_cfg[reg] = uda->cfg[reg];
309 break;
310 case CMD_RESUME:
311 for (reg = stat0; reg < uda1341_reg_last; reg++)
312 snd_uda1341_codec_write(clnt, reg, uda->suspend_regs[reg]);
313 for (reg = 0; reg < CMD_LAST; reg++)
314 uda->cfg[reg] = uda->suspend_cfg[reg];
315 break;
316 #endif
317 default:
318 ret = -EINVAL;
319 break;
320 }
321
322 if (!uda->active)
323 printk(KERN_ERR "UDA1341 codec not active!\n");
324 return ret;
325 }
326
327 /* }}} */
328
329 /* {{{ Proc interface */
330
331 static void snd_uda1341_proc_read(snd_info_entry_t *entry,
332 snd_info_buffer_t * buffer)
333 {
334 struct l3_client *clnt = entry->private_data;
335 struct uda1341 *uda = clnt->driver_data;
336 int peak;
337
338 peak = snd_uda1341_codec_read(clnt, UDA1341_DATA1);
339 if (peak < 0)
340 peak = 0;
341
342 snd_iprintf(buffer, "%s\n\n", uda->card->longname);
343
344 // for information about computed values see UDA1341TS datasheet pages 15 - 21
345 snd_iprintf(buffer, "DAC power : %s\n", uda->cfg[CMD_DAC] ? "on" : "off");
346 snd_iprintf(buffer, "ADC power : %s\n", uda->cfg[CMD_ADC] ? "on" : "off");
347 snd_iprintf(buffer, "Clock frequency : %s\n", fs_names[uda->cfg[CMD_FS]]);
348 snd_iprintf(buffer, "Data format : %s\n\n", format_names[uda->cfg[CMD_FORMAT]]);
349
350 snd_iprintf(buffer, "Filter mode : %s\n", filter_names[uda->cfg[CMD_FILTER]]);
351 snd_iprintf(buffer, "Mixer mode : %s\n", mixer_names[uda->cfg[CMD_MIXER]]);
352 snd_iprintf(buffer, "De-emphasis : %s\n", deemp_names[uda->cfg[CMD_DEEMP]]);
353 snd_iprintf(buffer, "Peak detection pos. : %s\n", uda->cfg[CMD_PEAK] ? "after" : "before");
354 snd_iprintf(buffer, "Peak value : %s\n\n", peak_value[peak]);
355
356 snd_iprintf(buffer, "Automatic Gain Ctrl : %s\n", uda->cfg[CMD_AGC] ? "on" : "off");
357 snd_iprintf(buffer, "AGC attack time : %d ms\n", AGC_atime[uda->cfg[CMD_AGC_TIME]]);
358 snd_iprintf(buffer, "AGC decay time : %d ms\n", AGC_dtime[uda->cfg[CMD_AGC_TIME]]);
359 snd_iprintf(buffer, "AGC output level : %s dB\n\n", AGC_level[uda->cfg[CMD_AGC_LEVEL]]);
360
361 snd_iprintf(buffer, "Mute : %s\n", uda->cfg[CMD_MUTE] ? "on" : "off");
362
363 if (uda->cfg[CMD_VOLUME] == 0)
364 snd_iprintf(buffer, "Volume : 0 dB\n");
365 else if (uda->cfg[CMD_VOLUME] < 62)
366 snd_iprintf(buffer, "Volume : %d dB\n", -1*uda->cfg[CMD_VOLUME] +1);
367 else
368 snd_iprintf(buffer, "Volume : -INF dB\n");
369 snd_iprintf(buffer, "Bass : %s\n", bass_values[uda->cfg[CMD_FILTER]][uda->cfg[CMD_BASS]]);
370 snd_iprintf(buffer, "Trebble : %d dB\n", uda->cfg[CMD_FILTER] ? 2*uda->cfg[CMD_TREBBLE] : 0);
371 snd_iprintf(buffer, "Input Gain (6dB) : %s\n", uda->cfg[CMD_IGAIN] ? "on" : "off");
372 snd_iprintf(buffer, "Output Gain (6dB) : %s\n", uda->cfg[CMD_OGAIN] ? "on" : "off");
373 snd_iprintf(buffer, "Mic sensitivity : %s\n", mic_sens_value[uda->cfg[CMD_MIC]]);
374
375
376 if(uda->cfg[CMD_CH1] < 31)
377 snd_iprintf(buffer, "Mixer gain channel 1: -%d.%c dB\n",
378 ((uda->cfg[CMD_CH1] >> 1) * 3) + (uda->cfg[CMD_CH1] & 1),
379 uda->cfg[CMD_CH1] & 1 ? '5' : '0');
380 else
381 snd_iprintf(buffer, "Mixer gain channel 1: -INF dB\n");
382 if(uda->cfg[CMD_CH2] < 31)
383 snd_iprintf(buffer, "Mixer gain channel 2: -%d.%c dB\n",
384 ((uda->cfg[CMD_CH2] >> 1) * 3) + (uda->cfg[CMD_CH2] & 1),
385 uda->cfg[CMD_CH2] & 1 ? '5' : '0');
386 else
387 snd_iprintf(buffer, "Mixer gain channel 2: -INF dB\n");
388
389 if(uda->cfg[CMD_IG] > 5)
390 snd_iprintf(buffer, "Input Amp. Gain ch 2: %d.%c dB\n",
391 (uda->cfg[CMD_IG] >> 1) -3, uda->cfg[CMD_IG] & 1 ? '5' : '0');
392 else
393 snd_iprintf(buffer, "Input Amp. Gain ch 2: %s dB\n", ig_small_value[uda->cfg[CMD_IG]]);
394 }
395
396 static void snd_uda1341_proc_regs_read(snd_info_entry_t *entry,
397 snd_info_buffer_t * buffer)
398 {
399 struct l3_client *clnt = entry->private_data;
400 struct uda1341 *uda = clnt->driver_data;
401 int reg;
402 char buf[12];
403
404 spin_lock(&uda->reg_lock);
405 for (reg = 0; reg < uda1341_reg_last; reg ++) {
406 if (reg == empty)
407 continue;
408 int2str_bin8(uda->regs[reg], buf);
409 snd_iprintf(buffer, "%s = %s\n", uda1341_reg_names[reg], buf);
410 }
411
412 int2str_bin8(snd_uda1341_codec_read(clnt, UDA1341_DATA1), buf);
413 snd_iprintf(buffer, "DATA1 = %s\n", buf);
414
415 spin_unlock(&uda->reg_lock);
416 }
417
418 static void __devinit snd_uda1341_proc_init(snd_card_t *card, struct l3_client *clnt)
419 {
420 snd_info_entry_t *entry;
421
422 if (! snd_card_proc_new(card, "uda1341", &entry))
423 snd_info_set_text_ops(entry, clnt, 1024, snd_uda1341_proc_read);
424 if (! snd_card_proc_new(card, "uda1341-regs", &entry))
425 snd_info_set_text_ops(entry, clnt, 1024, snd_uda1341_proc_regs_read);
426 }
427
428 /* }}} */
429
430 /* {{{ Mixer controls setting */
431
432 /* {{{ UDA1341 single functions */
433
434 #define UDA1341_SINGLE(xname, where, reg, shift, mask, invert) \
435 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_uda1341_info_single, \
436 .get = snd_uda1341_get_single, .put = snd_uda1341_put_single, \
437 .private_value = where | (reg << 5) | (shift << 9) | (mask << 12) | (invert << 18) \
438 }
439
440 static int snd_uda1341_info_single(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
441 {
442 int mask = (kcontrol->private_value >> 12) & 63;
443
444 uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
445 uinfo->count = 1;
446 uinfo->value.integer.min = 0;
447 uinfo->value.integer.max = mask;
448 return 0;
449 }
450
451 static int snd_uda1341_get_single(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
452 {
453 struct l3_client *clnt = snd_kcontrol_chip(kcontrol);
454 uda1341_t *uda = clnt->driver_data;
455 int where = kcontrol->private_value & 31;
456 int mask = (kcontrol->private_value >> 12) & 63;
457 int invert = (kcontrol->private_value >> 18) & 1;
458
459 ucontrol->value.integer.value[0] = uda->cfg[where];
460 if (invert)
461 ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
462
463 return 0;
464 }
465
466 static int snd_uda1341_put_single(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
467 {
468 struct l3_client *clnt = snd_kcontrol_chip(kcontrol);
469 uda1341_t *uda = clnt->driver_data;
470 int where = kcontrol->private_value & 31;
471 int reg = (kcontrol->private_value >> 5) & 15;
472 int shift = (kcontrol->private_value >> 9) & 7;
473 int mask = (kcontrol->private_value >> 12) & 63;
474 int invert = (kcontrol->private_value >> 18) & 1;
475 unsigned short val;
476
477 val = (ucontrol->value.integer.value[0] & mask);
478 if (invert)
479 val = mask - val;
480
481 uda->cfg[where] = val;
482 return snd_uda1341_update_bits(clnt, reg, mask, shift, val, FLUSH);
483 }
484
485 /* }}} */
486
487 /* {{{ UDA1341 enum functions */
488
489 #define UDA1341_ENUM(xname, where, reg, shift, mask, invert) \
490 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_uda1341_info_enum, \
491 .get = snd_uda1341_get_enum, .put = snd_uda1341_put_enum, \
492 .private_value = where | (reg << 5) | (shift << 9) | (mask << 12) | (invert << 18) \
493 }
494
495 static int snd_uda1341_info_enum(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
496 {
497 int where = kcontrol->private_value & 31;
498 const char **texts;
499
500 // this register we don't handle this way
501 if (!uda1341_enum_items[where])
502 return -EINVAL;
503
504 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
505 uinfo->count = 1;
506 uinfo->value.enumerated.items = uda1341_enum_items[where];
507
508 if (uinfo->value.enumerated.item >= uda1341_enum_items[where])
509 uinfo->value.enumerated.item = uda1341_enum_items[where] - 1;
510
511 texts = uda1341_enum_names[where];
512 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
513 return 0;
514 }
515
516 static int snd_uda1341_get_enum(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
517 {
518 struct l3_client *clnt = snd_kcontrol_chip(kcontrol);
519 uda1341_t *uda = clnt->driver_data;
520 int where = kcontrol->private_value & 31;
521
522 ucontrol->value.enumerated.item[0] = uda->cfg[where];
523 return 0;
524 }
525
526 static int snd_uda1341_put_enum(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
527 {
528 struct l3_client *clnt = snd_kcontrol_chip(kcontrol);
529 uda1341_t *uda = clnt->driver_data;
530 int where = kcontrol->private_value & 31;
531 int reg = (kcontrol->private_value >> 5) & 15;
532 int shift = (kcontrol->private_value >> 9) & 7;
533 int mask = (kcontrol->private_value >> 12) & 63;
534
535 uda->cfg[where] = (ucontrol->value.enumerated.item[0] & mask);
536
537 return snd_uda1341_update_bits(clnt, reg, mask, shift, uda->cfg[where], FLUSH);
538 }
539
540 /* }}} */
541
542 /* {{{ UDA1341 2regs functions */
543
544 #define UDA1341_2REGS(xname, where, reg_1, reg_2, shift_1, shift_2, mask_1, mask_2, invert) \
545 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), .info = snd_uda1341_info_2regs, \
546 .get = snd_uda1341_get_2regs, .put = snd_uda1341_put_2regs, \
547 .private_value = where | (reg_1 << 5) | (reg_2 << 9) | (shift_1 << 13) | (shift_2 << 16) | \
548 (mask_1 << 19) | (mask_2 << 25) | (invert << 31) \
549 }
550
551
552 static int snd_uda1341_info_2regs(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
553 {
554 int mask_1 = (kcontrol->private_value >> 19) & 63;
555 int mask_2 = (kcontrol->private_value >> 25) & 63;
556 int mask;
557
558 mask = (mask_2 + 1) * (mask_1 + 1) - 1;
559 uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
560 uinfo->count = 1;
561 uinfo->value.integer.min = 0;
562 uinfo->value.integer.max = mask;
563 return 0;
564 }
565
566 static int snd_uda1341_get_2regs(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
567 {
568 struct l3_client *clnt = snd_kcontrol_chip(kcontrol);
569 uda1341_t *uda = clnt->driver_data;
570 int where = kcontrol->private_value & 31;
571 int mask_1 = (kcontrol->private_value >> 19) & 63;
572 int mask_2 = (kcontrol->private_value >> 25) & 63;
573 int invert = (kcontrol->private_value >> 31) & 1;
574 int mask;
575
576 mask = (mask_2 + 1) * (mask_1 + 1) - 1;
577
578 ucontrol->value.integer.value[0] = uda->cfg[where];
579 if (invert)
580 ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
581 return 0;
582 }
583
584 static int snd_uda1341_put_2regs(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
585 {
586 struct l3_client *clnt = snd_kcontrol_chip(kcontrol);
587 uda1341_t *uda = clnt->driver_data;
588 int where = kcontrol->private_value & 31;
589 int reg_1 = (kcontrol->private_value >> 5) & 15;
590 int reg_2 = (kcontrol->private_value >> 9) & 15;
591 int shift_1 = (kcontrol->private_value >> 13) & 7;
592 int shift_2 = (kcontrol->private_value >> 16) & 7;
593 int mask_1 = (kcontrol->private_value >> 19) & 63;
594 int mask_2 = (kcontrol->private_value >> 25) & 63;
595 int invert = (kcontrol->private_value >> 31) & 1;
596 int mask;
597 unsigned short val1, val2, val;
598
599 val = ucontrol->value.integer.value[0];
600
601 mask = (mask_2 + 1) * (mask_1 + 1) - 1;
602
603 val1 = val & mask_1;
604 val2 = (val / (mask_1 + 1)) & mask_2;
605
606 if (invert) {
607 val1 = mask_1 - val1;
608 val2 = mask_2 - val2;
609 }
610
611 uda->cfg[where] = invert ? mask - val : val;
612
613 //FIXME - return value
614 snd_uda1341_update_bits(clnt, reg_1, mask_1, shift_1, val1, FLUSH);
615 return snd_uda1341_update_bits(clnt, reg_2, mask_2, shift_2, val2, FLUSH);
616 }
617
618 /* }}} */
619
620 static snd_kcontrol_new_t snd_uda1341_controls[] = {
621 UDA1341_SINGLE("Master Playback Switch", CMD_MUTE, data0_2, 2, 1, 1),
622 UDA1341_SINGLE("Master Playback Volume", CMD_VOLUME, data0_0, 0, 63, 1),
623
624 UDA1341_SINGLE("Bass Playback Volume", CMD_BASS, data0_1, 2, 15, 0),
625 UDA1341_SINGLE("Treble Playback Volume", CMD_TREBBLE, data0_1, 0, 3, 0),
626
627 UDA1341_SINGLE("Input Gain Switch", CMD_IGAIN, stat1, 5, 1, 0),
628 UDA1341_SINGLE("Output Gain Switch", CMD_OGAIN, stat1, 6, 1, 0),
629
630 UDA1341_SINGLE("Mixer Gain Channel 1 Volume", CMD_CH1, ext0, 0, 31, 1),
631 UDA1341_SINGLE("Mixer Gain Channel 2 Volume", CMD_CH2, ext1, 0, 31, 1),
632
633 UDA1341_SINGLE("Mic Sensitivity Volume", CMD_MIC, ext2, 2, 7, 0),
634
635 UDA1341_SINGLE("AGC Output Level", CMD_AGC_LEVEL, ext6, 0, 3, 0),
636 UDA1341_SINGLE("AGC Time Constant", CMD_AGC_TIME, ext6, 2, 7, 0),
637 UDA1341_SINGLE("AGC Time Constant Switch", CMD_AGC, ext4, 4, 1, 0),
638
639 UDA1341_SINGLE("DAC Power", CMD_DAC, stat1, 0, 1, 0),
640 UDA1341_SINGLE("ADC Power", CMD_ADC, stat1, 1, 1, 0),
641
642 UDA1341_ENUM("Peak detection", CMD_PEAK, data0_2, 5, 1, 0),
643 UDA1341_ENUM("De-emphasis", CMD_DEEMP, data0_2, 3, 3, 0),
644 UDA1341_ENUM("Mixer mode", CMD_MIXER, ext2, 0, 3, 0),
645 UDA1341_ENUM("Filter mode", CMD_FILTER, data0_2, 0, 3, 0),
646
647 UDA1341_2REGS("Gain Input Amplifier Gain (channel 2)", CMD_IG, ext4, ext5, 0, 0, 3, 31, 0),
648 };
649
650 static void uda1341_free(struct l3_client *uda1341)
651 {
652 l3_detach_client(uda1341); // calls kfree for driver_data (uda1341_t)
653 kfree(uda1341);
654 }
655
656 static int uda1341_dev_free(snd_device_t *device)
657 {
658 struct l3_client *clnt = device->device_data;
659 uda1341_free(clnt);
660 return 0;
661 }
662
663 int __init snd_chip_uda1341_mixer_new(snd_card_t *card, struct l3_client **clnt)
664 {
665 static snd_device_ops_t ops = {
666 .dev_free = uda1341_dev_free,
667 };
668 struct l3_client *uda1341;
669 int idx, err;
670
671 snd_assert(card != NULL, return -EINVAL);
672
673 uda1341 = kcalloc(1, sizeof(*uda1341), GFP_KERNEL);
674 if (uda1341 == NULL)
675 return -ENOMEM;
676
677 if ((err = l3_attach_client(uda1341, "l3-bit-sa1100-gpio", "snd-uda1341"))) {
678 kfree(uda1341);
679 return err;
680 }
681
682 if ((err = snd_device_new(card, SNDRV_DEV_CODEC, uda1341, &ops)) < 0) {
683 l3_detach_client(uda1341);
684 kfree(uda1341);
685 return err;
686 }
687
688 for (idx = 0; idx < ARRAY_SIZE(snd_uda1341_controls); idx++) {
689 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_uda1341_controls[idx], uda1341))) < 0)
690 return err;
691 }
692
693 *clnt = uda1341;
694 strcpy(card->mixername, "UDA1341TS Mixer");
695 ((uda1341_t *)uda1341->driver_data)->card = card;
696
697 snd_uda1341_proc_init(card, uda1341);
698
699 return 0;
700 }
701
702 /* }}} */
703
704 /* {{{ L3 operations */
705
706 static int uda1341_attach(struct l3_client *clnt)
707 {
708 struct uda1341 *uda;
709
710 uda = kcalloc(1, sizeof(*uda), 0, GFP_KERNEL);
711 if (!uda)
712 return -ENOMEM;
713
714 /* init fixed parts of my copy of registers */
715 uda->regs[stat0] = STAT0;
716 uda->regs[stat1] = STAT1;
717
718 uda->regs[data0_0] = DATA0_0;
719 uda->regs[data0_1] = DATA0_1;
720 uda->regs[data0_2] = DATA0_2;
721
722 uda->write = snd_uda1341_codec_write;
723 uda->read = snd_uda1341_codec_read;
724
725 spin_lock_init(&uda->reg_lock);
726
727 clnt->driver_data = uda;
728 return 0;
729 }
730
731 static void uda1341_detach(struct l3_client *clnt)
732 {
733 kfree(clnt->driver_data);
734 }
735
736 static int
737 uda1341_command(struct l3_client *clnt, int cmd, void *arg)
738 {
739 if (cmd != CMD_READ_REG)
740 return snd_uda1341_cfg_write(clnt, cmd, (int) arg, FLUSH);
741
742 return snd_uda1341_codec_read(clnt, (int) arg);
743 }
744
745 static int uda1341_open(struct l3_client *clnt)
746 {
747 struct uda1341 *uda = clnt->driver_data;
748
749 uda->active = 1;
750
751 /* init default configuration */
752 snd_uda1341_cfg_write(clnt, CMD_RESET, 0, REGS_ONLY);
753 snd_uda1341_cfg_write(clnt, CMD_FS, F256, FLUSH); // unknown state after reset
754 snd_uda1341_cfg_write(clnt, CMD_FORMAT, LSB16, FLUSH); // unknown state after reset
755 snd_uda1341_cfg_write(clnt, CMD_OGAIN, ON, FLUSH); // default off after reset
756 snd_uda1341_cfg_write(clnt, CMD_IGAIN, ON, FLUSH); // default off after reset
757 snd_uda1341_cfg_write(clnt, CMD_DAC, ON, FLUSH); // ??? default value after reset
758 snd_uda1341_cfg_write(clnt, CMD_ADC, ON, FLUSH); // ??? default value after reset
759 snd_uda1341_cfg_write(clnt, CMD_VOLUME, 20, FLUSH); // default 0dB after reset
760 snd_uda1341_cfg_write(clnt, CMD_BASS, 0, REGS_ONLY); // default value after reset
761 snd_uda1341_cfg_write(clnt, CMD_TREBBLE, 0, REGS_ONLY); // default value after reset
762 snd_uda1341_cfg_write(clnt, CMD_PEAK, AFTER, REGS_ONLY);// default value after reset
763 snd_uda1341_cfg_write(clnt, CMD_DEEMP, NONE, REGS_ONLY);// default value after reset
764 //at this moment should be QMUTED by h3600_audio_init
765 snd_uda1341_cfg_write(clnt, CMD_MUTE, OFF, REGS_ONLY); // default value after reset
766 snd_uda1341_cfg_write(clnt, CMD_FILTER, MAX, FLUSH); // defaul flat after reset
767 snd_uda1341_cfg_write(clnt, CMD_CH1, 31, FLUSH); // default value after reset
768 snd_uda1341_cfg_write(clnt, CMD_CH2, 4, FLUSH); // default value after reset
769 snd_uda1341_cfg_write(clnt, CMD_MIC, 4, FLUSH); // default 0dB after reset
770 snd_uda1341_cfg_write(clnt, CMD_MIXER, MIXER, FLUSH); // default doub.dif.mode
771 snd_uda1341_cfg_write(clnt, CMD_AGC, OFF, FLUSH); // default value after reset
772 snd_uda1341_cfg_write(clnt, CMD_IG, 0, FLUSH); // unknown state after reset
773 snd_uda1341_cfg_write(clnt, CMD_AGC_TIME, 0, FLUSH); // default value after reset
774 snd_uda1341_cfg_write(clnt, CMD_AGC_LEVEL, 0, FLUSH); // default value after reset
775
776 return 0;
777 }
778
779 static void uda1341_close(struct l3_client *clnt)
780 {
781 struct uda1341 *uda = clnt->driver_data;
782
783 uda->active = 0;
784 }
785
786 /* }}} */
787
788 /* {{{ Module and L3 initialization */
789
790 static struct l3_ops uda1341_ops = {
791 .open = uda1341_open,
792 .command = uda1341_command,
793 .close = uda1341_close,
794 };
795
796 static struct l3_driver uda1341_driver = {
797 .name = UDA1341_ALSA_NAME,
798 .attach_client = uda1341_attach,
799 .detach_client = uda1341_detach,
800 .ops = &uda1341_ops,
801 .owner = THIS_MODULE,
802 };
803
804 static int __init uda1341_init(void)
805 {
806 return l3_add_driver(&uda1341_driver);
807 }
808
809 static void __exit uda1341_exit(void)
810 {
811 l3_del_driver(&uda1341_driver);
812 }
813
814 module_init(uda1341_init);
815 module_exit(uda1341_exit);
816
817 MODULE_AUTHOR("Tomas Kasparek <tomas.kasparek@seznam.cz>");
818 MODULE_LICENSE("GPL");
819 MODULE_DESCRIPTION("Philips UDA1341 CODEC driver for ALSA");
820 MODULE_SUPPORTED_DEVICE("{{UDA1341,UDA1341TS}}");
821
822 EXPORT_SYMBOL(snd_chip_uda1341_mixer_new);
823
824 /* }}} */
825
826 /*
827 * Local variables:
828 * indent-tabs-mode: t
829 * End:
830 */
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