2 * Copyright (C) 2012 Altera <www.altera.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 /include/ "skeleton.dtsi"
35 compatible = "arm,cortex-a9";
38 next-level-cache = <&L2>;
41 compatible = "arm,cortex-a9";
44 next-level-cache = <&L2>;
49 compatible = "arm,cortex-a9-gic";
50 #interrupt-cells = <3>;
52 reg = <0xfffed000 0x1000>,
59 compatible = "simple-bus";
61 interrupt-parent = <&intc>;
65 compatible = "arm,amba-bus";
71 compatible = "arm,pl330", "arm,primecell";
72 reg = <0xffe01000 0x1000>;
73 interrupts = <0 180 4>;
77 gmac0: stmmac@ff700000 {
78 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
79 reg = <0xff700000 0x2000>;
80 interrupts = <0 115 4>;
81 interrupt-names = "macirq";
82 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
86 L2: l2-cache@fffef000 {
87 compatible = "arm,pl310-cache";
88 reg = <0xfffef000 0x1000>;
89 interrupts = <0 38 0x04>;
96 compatible = "arm,cortex-a9-twd-timer";
97 reg = <0xfffec600 0x100>;
98 interrupts = <1 13 0xf04>;
101 timer0: timer@ffc08000 {
102 compatible = "snps,dw-apb-timer-sp";
103 interrupts = <0 167 4>;
104 clock-frequency = <200000000>;
105 reg = <0xffc08000 0x1000>;
108 timer1: timer@ffc09000 {
109 compatible = "snps,dw-apb-timer-sp";
110 interrupts = <0 168 4>;
111 clock-frequency = <200000000>;
112 reg = <0xffc09000 0x1000>;
115 timer2: timer@ffd00000 {
116 compatible = "snps,dw-apb-timer-osc";
117 interrupts = <0 169 4>;
118 clock-frequency = <200000000>;
119 reg = <0xffd00000 0x1000>;
122 timer3: timer@ffd01000 {
123 compatible = "snps,dw-apb-timer-osc";
124 interrupts = <0 170 4>;
125 clock-frequency = <200000000>;
126 reg = <0xffd01000 0x1000>;
129 uart0: uart@ffc02000 {
130 compatible = "snps,dw-apb-uart";
131 reg = <0xffc02000 0x1000>;
132 clock-frequency = <7372800>;
133 interrupts = <0 162 4>;
138 uart1: uart@ffc03000 {
139 compatible = "snps,dw-apb-uart";
140 reg = <0xffc03000 0x1000>;
141 clock-frequency = <7372800>;
142 interrupts = <0 163 4>;