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initial commit with v3.6.7
[linux-3.6.7-moxart.git] / arch / arm / mach-at91 / at91sam9263_devices.c
blob9877963c29e77ca9b90ae8d984f8eeadd39ffc7b
1 /*
2 * arch/arm/mach-at91/at91sam9263_devices.c
3 *
4 * Copyright (C) 2007 Atmel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12 #include <asm/mach/arch.h>
13 #include <asm/mach/map.h>
14
15 #include <linux/dma-mapping.h>
16 #include <linux/gpio.h>
17 #include <linux/platform_device.h>
18 #include <linux/i2c-gpio.h>
19
20 #include <linux/fb.h>
21 #include <video/atmel_lcdc.h>
22
23 #include <mach/board.h>
24 #include <mach/at91sam9263.h>
25 #include <mach/at91sam9263_matrix.h>
26 #include <mach/at91_matrix.h>
27 #include <mach/at91sam9_smc.h>
28
29 #include "generic.h"
30
31
32 /* --------------------------------------------------------------------
33 * USB Host
34 * -------------------------------------------------------------------- */
35
36 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
37 static u64 ohci_dmamask = DMA_BIT_MASK(32);
38 static struct at91_usbh_data usbh_data;
39
40 static struct resource usbh_resources[] = {
41 [0] = {
42 .start = AT91SAM9263_UHP_BASE,
43 .end = AT91SAM9263_UHP_BASE + SZ_1M - 1,
44 .flags = IORESOURCE_MEM,
45 },
46 [1] = {
47 .start = NR_IRQS_LEGACY + AT91SAM9263_ID_UHP,
48 .end = NR_IRQS_LEGACY + AT91SAM9263_ID_UHP,
49 .flags = IORESOURCE_IRQ,
50 },
51 };
52
53 static struct platform_device at91_usbh_device = {
54 .name = "at91_ohci",
55 .id = -1,
56 .dev = {
57 .dma_mask = &ohci_dmamask,
58 .coherent_dma_mask = DMA_BIT_MASK(32),
59 .platform_data = &usbh_data,
60 },
61 .resource = usbh_resources,
62 .num_resources = ARRAY_SIZE(usbh_resources),
63 };
64
65 void __init at91_add_device_usbh(struct at91_usbh_data *data)
66 {
67 int i;
68
69 if (!data)
70 return;
71
72 /* Enable VBus control for UHP ports */
73 for (i = 0; i < data->ports; i++) {
74 if (gpio_is_valid(data->vbus_pin[i]))
75 at91_set_gpio_output(data->vbus_pin[i],
76 data->vbus_pin_active_low[i]);
77 }
78
79 /* Enable overcurrent notification */
80 for (i = 0; i < data->ports; i++) {
81 if (data->overcurrent_pin[i])
82 at91_set_gpio_input(data->overcurrent_pin[i], 1);
83 }
84
85 usbh_data = *data;
86 platform_device_register(&at91_usbh_device);
87 }
88 #else
89 void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
90 #endif
91
92
93 /* --------------------------------------------------------------------
94 * USB Device (Gadget)
95 * -------------------------------------------------------------------- */
96
97 #if defined(CONFIG_USB_AT91) || defined(CONFIG_USB_AT91_MODULE)
98 static struct at91_udc_data udc_data;
99
100 static struct resource udc_resources[] = {
101 [0] = {
102 .start = AT91SAM9263_BASE_UDP,
103 .end = AT91SAM9263_BASE_UDP + SZ_16K - 1,
104 .flags = IORESOURCE_MEM,
105 },
106 [1] = {
107 .start = NR_IRQS_LEGACY + AT91SAM9263_ID_UDP,
108 .end = NR_IRQS_LEGACY + AT91SAM9263_ID_UDP,
109 .flags = IORESOURCE_IRQ,
110 },
111 };
112
113 static struct platform_device at91_udc_device = {
114 .name = "at91_udc",
115 .id = -1,
116 .dev = {
117 .platform_data = &udc_data,
118 },
119 .resource = udc_resources,
120 .num_resources = ARRAY_SIZE(udc_resources),
121 };
122
123 void __init at91_add_device_udc(struct at91_udc_data *data)
124 {
125 if (!data)
126 return;
127
128 if (gpio_is_valid(data->vbus_pin)) {
129 at91_set_gpio_input(data->vbus_pin, 0);
130 at91_set_deglitch(data->vbus_pin, 1);
131 }
132
133 /* Pullup pin is handled internally by USB device peripheral */
134
135 udc_data = *data;
136 platform_device_register(&at91_udc_device);
137 }
138 #else
139 void __init at91_add_device_udc(struct at91_udc_data *data) {}
140 #endif
141
142
143 /* --------------------------------------------------------------------
144 * Ethernet
145 * -------------------------------------------------------------------- */
146
147 #if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
148 static u64 eth_dmamask = DMA_BIT_MASK(32);
149 static struct macb_platform_data eth_data;
150
151 static struct resource eth_resources[] = {
152 [0] = {
153 .start = AT91SAM9263_BASE_EMAC,
154 .end = AT91SAM9263_BASE_EMAC + SZ_16K - 1,
155 .flags = IORESOURCE_MEM,
156 },
157 [1] = {
158 .start = NR_IRQS_LEGACY + AT91SAM9263_ID_EMAC,
159 .end = NR_IRQS_LEGACY + AT91SAM9263_ID_EMAC,
160 .flags = IORESOURCE_IRQ,
161 },
162 };
163
164 static struct platform_device at91sam9263_eth_device = {
165 .name = "macb",
166 .id = -1,
167 .dev = {
168 .dma_mask = &eth_dmamask,
169 .coherent_dma_mask = DMA_BIT_MASK(32),
170 .platform_data = &eth_data,
171 },
172 .resource = eth_resources,
173 .num_resources = ARRAY_SIZE(eth_resources),
174 };
175
176 void __init at91_add_device_eth(struct macb_platform_data *data)
177 {
178 if (!data)
179 return;
180
181 if (gpio_is_valid(data->phy_irq_pin)) {
182 at91_set_gpio_input(data->phy_irq_pin, 0);
183 at91_set_deglitch(data->phy_irq_pin, 1);
184 }
185
186 /* Pins used for MII and RMII */
187 at91_set_A_periph(AT91_PIN_PE21, 0); /* ETXCK_EREFCK */
188 at91_set_B_periph(AT91_PIN_PC25, 0); /* ERXDV */
189 at91_set_A_periph(AT91_PIN_PE25, 0); /* ERX0 */
190 at91_set_A_periph(AT91_PIN_PE26, 0); /* ERX1 */
191 at91_set_A_periph(AT91_PIN_PE27, 0); /* ERXER */
192 at91_set_A_periph(AT91_PIN_PE28, 0); /* ETXEN */
193 at91_set_A_periph(AT91_PIN_PE23, 0); /* ETX0 */
194 at91_set_A_periph(AT91_PIN_PE24, 0); /* ETX1 */
195 at91_set_A_periph(AT91_PIN_PE30, 0); /* EMDIO */
196 at91_set_A_periph(AT91_PIN_PE29, 0); /* EMDC */
197
198 if (!data->is_rmii) {
199 at91_set_A_periph(AT91_PIN_PE22, 0); /* ECRS */
200 at91_set_B_periph(AT91_PIN_PC26, 0); /* ECOL */
201 at91_set_B_periph(AT91_PIN_PC22, 0); /* ERX2 */
202 at91_set_B_periph(AT91_PIN_PC23, 0); /* ERX3 */
203 at91_set_B_periph(AT91_PIN_PC27, 0); /* ERXCK */
204 at91_set_B_periph(AT91_PIN_PC20, 0); /* ETX2 */
205 at91_set_B_periph(AT91_PIN_PC21, 0); /* ETX3 */
206 at91_set_B_periph(AT91_PIN_PC24, 0); /* ETXER */
207 }
208
209 eth_data = *data;
210 platform_device_register(&at91sam9263_eth_device);
211 }
212 #else
213 void __init at91_add_device_eth(struct macb_platform_data *data) {}
214 #endif
215
216
217 /* --------------------------------------------------------------------
218 * MMC / SD
219 * -------------------------------------------------------------------- */
220
221 #if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
222 static u64 mmc_dmamask = DMA_BIT_MASK(32);
223 static struct at91_mmc_data mmc0_data, mmc1_data;
224
225 static struct resource mmc0_resources[] = {
226 [0] = {
227 .start = AT91SAM9263_BASE_MCI0,
228 .end = AT91SAM9263_BASE_MCI0 + SZ_16K - 1,
229 .flags = IORESOURCE_MEM,
230 },
231 [1] = {
232 .start = NR_IRQS_LEGACY + AT91SAM9263_ID_MCI0,
233 .end = NR_IRQS_LEGACY + AT91SAM9263_ID_MCI0,
234 .flags = IORESOURCE_IRQ,
235 },
236 };
237
238 static struct platform_device at91sam9263_mmc0_device = {
239 .name = "at91_mci",
240 .id = 0,
241 .dev = {
242 .dma_mask = &mmc_dmamask,
243 .coherent_dma_mask = DMA_BIT_MASK(32),
244 .platform_data = &mmc0_data,
245 },
246 .resource = mmc0_resources,
247 .num_resources = ARRAY_SIZE(mmc0_resources),
248 };
249
250 static struct resource mmc1_resources[] = {
251 [0] = {
252 .start = AT91SAM9263_BASE_MCI1,
253 .end = AT91SAM9263_BASE_MCI1 + SZ_16K - 1,
254 .flags = IORESOURCE_MEM,
255 },
256 [1] = {
257 .start = NR_IRQS_LEGACY + AT91SAM9263_ID_MCI1,
258 .end = NR_IRQS_LEGACY + AT91SAM9263_ID_MCI1,
259 .flags = IORESOURCE_IRQ,
260 },
261 };
262
263 static struct platform_device at91sam9263_mmc1_device = {
264 .name = "at91_mci",
265 .id = 1,
266 .dev = {
267 .dma_mask = &mmc_dmamask,
268 .coherent_dma_mask = DMA_BIT_MASK(32),
269 .platform_data = &mmc1_data,
270 },
271 .resource = mmc1_resources,
272 .num_resources = ARRAY_SIZE(mmc1_resources),
273 };
274
275 void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
276 {
277 if (!data)
278 return;
279
280 /* input/irq */
281 if (gpio_is_valid(data->det_pin)) {
282 at91_set_gpio_input(data->det_pin, 1);
283 at91_set_deglitch(data->det_pin, 1);
284 }
285 if (gpio_is_valid(data->wp_pin))
286 at91_set_gpio_input(data->wp_pin, 1);
287 if (gpio_is_valid(data->vcc_pin))
288 at91_set_gpio_output(data->vcc_pin, 0);
289
290 if (mmc_id == 0) { /* MCI0 */
291 /* CLK */
292 at91_set_A_periph(AT91_PIN_PA12, 0);
293
294 if (data->slot_b) {
295 /* CMD */
296 at91_set_A_periph(AT91_PIN_PA16, 1);
297
298 /* DAT0, maybe DAT1..DAT3 */
299 at91_set_A_periph(AT91_PIN_PA17, 1);
300 if (data->wire4) {
301 at91_set_A_periph(AT91_PIN_PA18, 1);
302 at91_set_A_periph(AT91_PIN_PA19, 1);
303 at91_set_A_periph(AT91_PIN_PA20, 1);
304 }
305 } else {
306 /* CMD */
307 at91_set_A_periph(AT91_PIN_PA1, 1);
308
309 /* DAT0, maybe DAT1..DAT3 */
310 at91_set_A_periph(AT91_PIN_PA0, 1);
311 if (data->wire4) {
312 at91_set_A_periph(AT91_PIN_PA3, 1);
313 at91_set_A_periph(AT91_PIN_PA4, 1);
314 at91_set_A_periph(AT91_PIN_PA5, 1);
315 }
316 }
317
318 mmc0_data = *data;
319 platform_device_register(&at91sam9263_mmc0_device);
320 } else { /* MCI1 */
321 /* CLK */
322 at91_set_A_periph(AT91_PIN_PA6, 0);
323
324 if (data->slot_b) {
325 /* CMD */
326 at91_set_A_periph(AT91_PIN_PA21, 1);
327
328 /* DAT0, maybe DAT1..DAT3 */
329 at91_set_A_periph(AT91_PIN_PA22, 1);
330 if (data->wire4) {
331 at91_set_A_periph(AT91_PIN_PA23, 1);
332 at91_set_A_periph(AT91_PIN_PA24, 1);
333 at91_set_A_periph(AT91_PIN_PA25, 1);
334 }
335 } else {
336 /* CMD */
337 at91_set_A_periph(AT91_PIN_PA7, 1);
338
339 /* DAT0, maybe DAT1..DAT3 */
340 at91_set_A_periph(AT91_PIN_PA8, 1);
341 if (data->wire4) {
342 at91_set_A_periph(AT91_PIN_PA9, 1);
343 at91_set_A_periph(AT91_PIN_PA10, 1);
344 at91_set_A_periph(AT91_PIN_PA11, 1);
345 }
346 }
347
348 mmc1_data = *data;
349 platform_device_register(&at91sam9263_mmc1_device);
350 }
351 }
352 #else
353 void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
354 #endif
355
356 /* --------------------------------------------------------------------
357 * Compact Flash (PCMCIA or IDE)
358 * -------------------------------------------------------------------- */
359
360 #if defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE) || \
361 defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE)
362
363 static struct at91_cf_data cf0_data;
364
365 static struct resource cf0_resources[] = {
366 [0] = {
367 .start = AT91_CHIPSELECT_4,
368 .end = AT91_CHIPSELECT_4 + SZ_256M - 1,
369 .flags = IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT,
370 }
371 };
372
373 static struct platform_device cf0_device = {
374 .id = 0,
375 .dev = {
376 .platform_data = &cf0_data,
377 },
378 .resource = cf0_resources,
379 .num_resources = ARRAY_SIZE(cf0_resources),
380 };
381
382 static struct at91_cf_data cf1_data;
383
384 static struct resource cf1_resources[] = {
385 [0] = {
386 .start = AT91_CHIPSELECT_5,
387 .end = AT91_CHIPSELECT_5 + SZ_256M - 1,
388 .flags = IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT,
389 }
390 };
391
392 static struct platform_device cf1_device = {
393 .id = 1,
394 .dev = {
395 .platform_data = &cf1_data,
396 },
397 .resource = cf1_resources,
398 .num_resources = ARRAY_SIZE(cf1_resources),
399 };
400
401 void __init at91_add_device_cf(struct at91_cf_data *data)
402 {
403 unsigned long ebi0_csa;
404 struct platform_device *pdev;
405
406 if (!data)
407 return;
408
409 /*
410 * assign CS4 or CS5 to SMC with Compact Flash logic support,
411 * we assume SMC timings are configured by board code,
412 * except True IDE where timings are controlled by driver
413 */
414 ebi0_csa = at91_matrix_read(AT91_MATRIX_EBI0CSA);
415 switch (data->chipselect) {
416 case 4:
417 at91_set_A_periph(AT91_PIN_PD6, 0); /* EBI0_NCS4/CFCS0 */
418 ebi0_csa |= AT91_MATRIX_EBI0_CS4A_SMC_CF1;
419 cf0_data = *data;
420 pdev = &cf0_device;
421 break;
422 case 5:
423 at91_set_A_periph(AT91_PIN_PD7, 0); /* EBI0_NCS5/CFCS1 */
424 ebi0_csa |= AT91_MATRIX_EBI0_CS5A_SMC_CF2;
425 cf1_data = *data;
426 pdev = &cf1_device;
427 break;
428 default:
429 printk(KERN_ERR "AT91 CF: bad chip-select requested (%u)\n",
430 data->chipselect);
431 return;
432 }
433 at91_matrix_write(AT91_MATRIX_EBI0CSA, ebi0_csa);
434
435 if (gpio_is_valid(data->det_pin)) {
436 at91_set_gpio_input(data->det_pin, 1);
437 at91_set_deglitch(data->det_pin, 1);
438 }
439
440 if (gpio_is_valid(data->irq_pin)) {
441 at91_set_gpio_input(data->irq_pin, 1);
442 at91_set_deglitch(data->irq_pin, 1);
443 }
444
445 if (gpio_is_valid(data->vcc_pin))
446 /* initially off */
447 at91_set_gpio_output(data->vcc_pin, 0);
448
449 /* enable EBI controlled pins */
450 at91_set_A_periph(AT91_PIN_PD5, 1); /* NWAIT */
451 at91_set_A_periph(AT91_PIN_PD8, 0); /* CFCE1 */
452 at91_set_A_periph(AT91_PIN_PD9, 0); /* CFCE2 */
453 at91_set_A_periph(AT91_PIN_PD14, 0); /* CFNRW */
454
455 pdev->name = (data->flags & AT91_CF_TRUE_IDE) ? "pata_at91" : "at91_cf";
456 platform_device_register(pdev);
457 }
458 #else
459 void __init at91_add_device_cf(struct at91_cf_data *data) {}
460 #endif
461
462 /* --------------------------------------------------------------------
463 * NAND / SmartMedia
464 * -------------------------------------------------------------------- */
465
466 #if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
467 static struct atmel_nand_data nand_data;
468
469 #define NAND_BASE AT91_CHIPSELECT_3
470
471 static struct resource nand_resources[] = {
472 [0] = {
473 .start = NAND_BASE,
474 .end = NAND_BASE + SZ_256M - 1,
475 .flags = IORESOURCE_MEM,
476 },
477 [1] = {
478 .start = AT91SAM9263_BASE_ECC0,
479 .end = AT91SAM9263_BASE_ECC0 + SZ_512 - 1,
480 .flags = IORESOURCE_MEM,
481 }
482 };
483
484 static struct platform_device at91sam9263_nand_device = {
485 .name = "atmel_nand",
486 .id = -1,
487 .dev = {
488 .platform_data = &nand_data,
489 },
490 .resource = nand_resources,
491 .num_resources = ARRAY_SIZE(nand_resources),
492 };
493
494 void __init at91_add_device_nand(struct atmel_nand_data *data)
495 {
496 unsigned long csa;
497
498 if (!data)
499 return;
500
501 csa = at91_matrix_read(AT91_MATRIX_EBI0CSA);
502 at91_matrix_write(AT91_MATRIX_EBI0CSA, csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
503
504 /* enable pin */
505 if (gpio_is_valid(data->enable_pin))
506 at91_set_gpio_output(data->enable_pin, 1);
507
508 /* ready/busy pin */
509 if (gpio_is_valid(data->rdy_pin))
510 at91_set_gpio_input(data->rdy_pin, 1);
511
512 /* card detect pin */
513 if (gpio_is_valid(data->det_pin))
514 at91_set_gpio_input(data->det_pin, 1);
515
516 nand_data = *data;
517 platform_device_register(&at91sam9263_nand_device);
518 }
519 #else
520 void __init at91_add_device_nand(struct atmel_nand_data *data) {}
521 #endif
522
523
524 /* --------------------------------------------------------------------
525 * TWI (i2c)
526 * -------------------------------------------------------------------- */
527
528 /*
529 * Prefer the GPIO code since the TWI controller isn't robust
530 * (gets overruns and underruns under load) and can only issue
531 * repeated STARTs in one scenario (the driver doesn't yet handle them).
532 */
533 #if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
534
535 static struct i2c_gpio_platform_data pdata = {
536 .sda_pin = AT91_PIN_PB4,
537 .sda_is_open_drain = 1,
538 .scl_pin = AT91_PIN_PB5,
539 .scl_is_open_drain = 1,
540 .udelay = 2, /* ~100 kHz */
541 };
542
543 static struct platform_device at91sam9263_twi_device = {
544 .name = "i2c-gpio",
545 .id = 0,
546 .dev.platform_data = &pdata,
547 };
548
549 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
550 {
551 at91_set_GPIO_periph(AT91_PIN_PB4, 1); /* TWD (SDA) */
552 at91_set_multi_drive(AT91_PIN_PB4, 1);
553
554 at91_set_GPIO_periph(AT91_PIN_PB5, 1); /* TWCK (SCL) */
555 at91_set_multi_drive(AT91_PIN_PB5, 1);
556
557 i2c_register_board_info(0, devices, nr_devices);
558 platform_device_register(&at91sam9263_twi_device);
559 }
560
561 #elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
562
563 static struct resource twi_resources[] = {
564 [0] = {
565 .start = AT91SAM9263_BASE_TWI,
566 .end = AT91SAM9263_BASE_TWI + SZ_16K - 1,
567 .flags = IORESOURCE_MEM,
568 },
569 [1] = {
570 .start = NR_IRQS_LEGACY + AT91SAM9263_ID_TWI,
571 .end = NR_IRQS_LEGACY + AT91SAM9263_ID_TWI,
572 .flags = IORESOURCE_IRQ,
573 },
574 };
575
576 static struct platform_device at91sam9263_twi_device = {
577 .name = "at91_i2c",
578 .id = -1,
579 .resource = twi_resources,
580 .num_resources = ARRAY_SIZE(twi_resources),
581 };
582
583 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
584 {
585 /* pins used for TWI interface */
586 at91_set_A_periph(AT91_PIN_PB4, 0); /* TWD */
587 at91_set_multi_drive(AT91_PIN_PB4, 1);
588
589 at91_set_A_periph(AT91_PIN_PB5, 0); /* TWCK */
590 at91_set_multi_drive(AT91_PIN_PB5, 1);
591
592 i2c_register_board_info(0, devices, nr_devices);
593 platform_device_register(&at91sam9263_twi_device);
594 }
595 #else
596 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
597 #endif
598
599
600 /* --------------------------------------------------------------------
601 * SPI
602 * -------------------------------------------------------------------- */
603
604 #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
605 static u64 spi_dmamask = DMA_BIT_MASK(32);
606
607 static struct resource spi0_resources[] = {
608 [0] = {
609 .start = AT91SAM9263_BASE_SPI0,
610 .end = AT91SAM9263_BASE_SPI0 + SZ_16K - 1,
611 .flags = IORESOURCE_MEM,
612 },
613 [1] = {
614 .start = NR_IRQS_LEGACY + AT91SAM9263_ID_SPI0,
615 .end = NR_IRQS_LEGACY + AT91SAM9263_ID_SPI0,
616 .flags = IORESOURCE_IRQ,
617 },
618 };
619
620 static struct platform_device at91sam9263_spi0_device = {
621 .name = "atmel_spi",
622 .id = 0,
623 .dev = {
624 .dma_mask = &spi_dmamask,
625 .coherent_dma_mask = DMA_BIT_MASK(32),
626 },
627 .resource = spi0_resources,
628 .num_resources = ARRAY_SIZE(spi0_resources),
629 };
630
631 static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA5, AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PB11 };
632
633 static struct resource spi1_resources[] = {
634 [0] = {
635 .start = AT91SAM9263_BASE_SPI1,
636 .end = AT91SAM9263_BASE_SPI1 + SZ_16K - 1,
637 .flags = IORESOURCE_MEM,
638 },
639 [1] = {
640 .start = NR_IRQS_LEGACY + AT91SAM9263_ID_SPI1,
641 .end = NR_IRQS_LEGACY + AT91SAM9263_ID_SPI1,
642 .flags = IORESOURCE_IRQ,
643 },
644 };
645
646 static struct platform_device at91sam9263_spi1_device = {
647 .name = "atmel_spi",
648 .id = 1,
649 .dev = {
650 .dma_mask = &spi_dmamask,
651 .coherent_dma_mask = DMA_BIT_MASK(32),
652 },
653 .resource = spi1_resources,
654 .num_resources = ARRAY_SIZE(spi1_resources),
655 };
656
657 static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB15, AT91_PIN_PB16, AT91_PIN_PB17, AT91_PIN_PB18 };
658
659 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
660 {
661 int i;
662 unsigned long cs_pin;
663 short enable_spi0 = 0;
664 short enable_spi1 = 0;
665
666 /* Choose SPI chip-selects */
667 for (i = 0; i < nr_devices; i++) {
668 if (devices[i].controller_data)
669 cs_pin = (unsigned long) devices[i].controller_data;
670 else if (devices[i].bus_num == 0)
671 cs_pin = spi0_standard_cs[devices[i].chip_select];
672 else
673 cs_pin = spi1_standard_cs[devices[i].chip_select];
674
675 if (!gpio_is_valid(cs_pin))
676 continue;
677
678 if (devices[i].bus_num == 0)
679 enable_spi0 = 1;
680 else
681 enable_spi1 = 1;
682
683 /* enable chip-select pin */
684 at91_set_gpio_output(cs_pin, 1);
685
686 /* pass chip-select pin to driver */
687 devices[i].controller_data = (void *) cs_pin;
688 }
689
690 spi_register_board_info(devices, nr_devices);
691
692 /* Configure SPI bus(es) */
693 if (enable_spi0) {
694 at91_set_B_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
695 at91_set_B_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
696 at91_set_B_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
697
698 platform_device_register(&at91sam9263_spi0_device);
699 }
700 if (enable_spi1) {
701 at91_set_A_periph(AT91_PIN_PB12, 0); /* SPI1_MISO */
702 at91_set_A_periph(AT91_PIN_PB13, 0); /* SPI1_MOSI */
703 at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_SPCK */
704
705 platform_device_register(&at91sam9263_spi1_device);
706 }
707 }
708 #else
709 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
710 #endif
711
712
713 /* --------------------------------------------------------------------
714 * AC97
715 * -------------------------------------------------------------------- */
716
717 #if defined(CONFIG_SND_ATMEL_AC97C) || defined(CONFIG_SND_ATMEL_AC97C_MODULE)
718 static u64 ac97_dmamask = DMA_BIT_MASK(32);
719 static struct ac97c_platform_data ac97_data;
720
721 static struct resource ac97_resources[] = {
722 [0] = {
723 .start = AT91SAM9263_BASE_AC97C,
724 .end = AT91SAM9263_BASE_AC97C + SZ_16K - 1,
725 .flags = IORESOURCE_MEM,
726 },
727 [1] = {
728 .start = NR_IRQS_LEGACY + AT91SAM9263_ID_AC97C,
729 .end = NR_IRQS_LEGACY + AT91SAM9263_ID_AC97C,
730 .flags = IORESOURCE_IRQ,
731 },
732 };
733
734 static struct platform_device at91sam9263_ac97_device = {
735 .name = "atmel_ac97c",
736 .id = 0,
737 .dev = {
738 .dma_mask = &ac97_dmamask,
739 .coherent_dma_mask = DMA_BIT_MASK(32),
740 .platform_data = &ac97_data,
741 },
742 .resource = ac97_resources,
743 .num_resources = ARRAY_SIZE(ac97_resources),
744 };
745
746 void __init at91_add_device_ac97(struct ac97c_platform_data *data)
747 {
748 if (!data)
749 return;
750
751 at91_set_A_periph(AT91_PIN_PB0, 0); /* AC97FS */
752 at91_set_A_periph(AT91_PIN_PB1, 0); /* AC97CK */
753 at91_set_A_periph(AT91_PIN_PB2, 0); /* AC97TX */
754 at91_set_A_periph(AT91_PIN_PB3, 0); /* AC97RX */
755
756 /* reset */
757 if (gpio_is_valid(data->reset_pin))
758 at91_set_gpio_output(data->reset_pin, 0);
759
760 ac97_data = *data;
761 platform_device_register(&at91sam9263_ac97_device);
762 }
763 #else
764 void __init at91_add_device_ac97(struct ac97c_platform_data *data) {}
765 #endif
766
767 /* --------------------------------------------------------------------
768 * CAN Controller
769 * -------------------------------------------------------------------- */
770
771 #if defined(CONFIG_CAN_AT91) || defined(CONFIG_CAN_AT91_MODULE)
772 static struct resource can_resources[] = {
773 [0] = {
774 .start = AT91SAM9263_BASE_CAN,
775 .end = AT91SAM9263_BASE_CAN + SZ_16K - 1,
776 .flags = IORESOURCE_MEM,
777 },
778 [1] = {
779 .start = NR_IRQS_LEGACY + AT91SAM9263_ID_CAN,
780 .end = NR_IRQS_LEGACY + AT91SAM9263_ID_CAN,
781 .flags = IORESOURCE_IRQ,
782 },
783 };
784
785 static struct platform_device at91sam9263_can_device = {
786 .name = "at91_can",
787 .id = -1,
788 .resource = can_resources,
789 .num_resources = ARRAY_SIZE(can_resources),
790 };
791
792 void __init at91_add_device_can(struct at91_can_data *data)
793 {
794 at91_set_A_periph(AT91_PIN_PA13, 0); /* CANTX */
795 at91_set_A_periph(AT91_PIN_PA14, 0); /* CANRX */
796 at91sam9263_can_device.dev.platform_data = data;
797
798 platform_device_register(&at91sam9263_can_device);
799 }
800 #else
801 void __init at91_add_device_can(struct at91_can_data *data) {}
802 #endif
803
804 /* --------------------------------------------------------------------
805 * LCD Controller
806 * -------------------------------------------------------------------- */
807
808 #if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
809 static u64 lcdc_dmamask = DMA_BIT_MASK(32);
810 static struct atmel_lcdfb_info lcdc_data;
811
812 static struct resource lcdc_resources[] = {
813 [0] = {
814 .start = AT91SAM9263_LCDC_BASE,
815 .end = AT91SAM9263_LCDC_BASE + SZ_4K - 1,
816 .flags = IORESOURCE_MEM,
817 },
818 [1] = {
819 .start = NR_IRQS_LEGACY + AT91SAM9263_ID_LCDC,
820 .end = NR_IRQS_LEGACY + AT91SAM9263_ID_LCDC,
821 .flags = IORESOURCE_IRQ,
822 },
823 };
824
825 static struct platform_device at91_lcdc_device = {
826 .name = "atmel_lcdfb",
827 .id = 0,
828 .dev = {
829 .dma_mask = &lcdc_dmamask,
830 .coherent_dma_mask = DMA_BIT_MASK(32),
831 .platform_data = &lcdc_data,
832 },
833 .resource = lcdc_resources,
834 .num_resources = ARRAY_SIZE(lcdc_resources),
835 };
836
837 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
838 {
839 if (!data)
840 return;
841
842 at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */
843 at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */
844 at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */
845 at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */
846 at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */
847 at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */
848 at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */
849 at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */
850 at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */
851 at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */
852 at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */
853 at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */
854 at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */
855 at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD13 */
856 at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */
857 at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */
858 at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */
859 at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */
860 at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */
861 at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD21 */
862 at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD22 */
863 at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD23 */
864
865 lcdc_data = *data;
866 platform_device_register(&at91_lcdc_device);
867 }
868 #else
869 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
870 #endif
871
872
873 /* --------------------------------------------------------------------
874 * Image Sensor Interface
875 * -------------------------------------------------------------------- */
876
877 #if defined(CONFIG_VIDEO_AT91_ISI) || defined(CONFIG_VIDEO_AT91_ISI_MODULE)
878
879 struct resource isi_resources[] = {
880 [0] = {
881 .start = AT91SAM9263_BASE_ISI,
882 .end = AT91SAM9263_BASE_ISI + SZ_16K - 1,
883 .flags = IORESOURCE_MEM,
884 },
885 [1] = {
886 .start = NR_IRQS_LEGACY + AT91SAM9263_ID_ISI,
887 .end = NR_IRQS_LEGACY + AT91SAM9263_ID_ISI,
888 .flags = IORESOURCE_IRQ,
889 },
890 };
891
892 static struct platform_device at91sam9263_isi_device = {
893 .name = "at91_isi",
894 .id = -1,
895 .resource = isi_resources,
896 .num_resources = ARRAY_SIZE(isi_resources),
897 };
898
899 void __init at91_add_device_isi(struct isi_platform_data *data,
900 bool use_pck_as_mck)
901 {
902 at91_set_A_periph(AT91_PIN_PE0, 0); /* ISI_D0 */
903 at91_set_A_periph(AT91_PIN_PE1, 0); /* ISI_D1 */
904 at91_set_A_periph(AT91_PIN_PE2, 0); /* ISI_D2 */
905 at91_set_A_periph(AT91_PIN_PE3, 0); /* ISI_D3 */
906 at91_set_A_periph(AT91_PIN_PE4, 0); /* ISI_D4 */
907 at91_set_A_periph(AT91_PIN_PE5, 0); /* ISI_D5 */
908 at91_set_A_periph(AT91_PIN_PE6, 0); /* ISI_D6 */
909 at91_set_A_periph(AT91_PIN_PE7, 0); /* ISI_D7 */
910 at91_set_A_periph(AT91_PIN_PE8, 0); /* ISI_PCK */
911 at91_set_A_periph(AT91_PIN_PE9, 0); /* ISI_HSYNC */
912 at91_set_A_periph(AT91_PIN_PE10, 0); /* ISI_VSYNC */
913 at91_set_B_periph(AT91_PIN_PE12, 0); /* ISI_PD8 */
914 at91_set_B_periph(AT91_PIN_PE13, 0); /* ISI_PD9 */
915 at91_set_B_periph(AT91_PIN_PE14, 0); /* ISI_PD10 */
916 at91_set_B_periph(AT91_PIN_PE15, 0); /* ISI_PD11 */
917
918 if (use_pck_as_mck) {
919 at91_set_B_periph(AT91_PIN_PE11, 0); /* ISI_MCK (PCK3) */
920
921 /* TODO: register the PCK for ISI_MCK and set its parent */
922 }
923 }
924 #else
925 void __init at91_add_device_isi(struct isi_platform_data *data,
926 bool use_pck_as_mck) {}
927 #endif
928
929
930 /* --------------------------------------------------------------------
931 * Timer/Counter block
932 * -------------------------------------------------------------------- */
933
934 #ifdef CONFIG_ATMEL_TCLIB
935
936 static struct resource tcb_resources[] = {
937 [0] = {
938 .start = AT91SAM9263_BASE_TCB0,
939 .end = AT91SAM9263_BASE_TCB0 + SZ_16K - 1,
940 .flags = IORESOURCE_MEM,
941 },
942 [1] = {
943 .start = NR_IRQS_LEGACY + AT91SAM9263_ID_TCB,
944 .end = NR_IRQS_LEGACY + AT91SAM9263_ID_TCB,
945 .flags = IORESOURCE_IRQ,
946 },
947 };
948
949 static struct platform_device at91sam9263_tcb_device = {
950 .name = "atmel_tcb",
951 .id = 0,
952 .resource = tcb_resources,
953 .num_resources = ARRAY_SIZE(tcb_resources),
954 };
955
956 #if defined(CONFIG_OF)
957 static struct of_device_id tcb_ids[] = {
958 { .compatible = "atmel,at91rm9200-tcb" },
959 { /*sentinel*/ }
960 };
961 #endif
962
963 static void __init at91_add_device_tc(void)
964 {
965 #if defined(CONFIG_OF)
966 struct device_node *np;
967
968 np = of_find_matching_node(NULL, tcb_ids);
969 if (np) {
970 of_node_put(np);
971 return;
972 }
973 #endif
974
975 platform_device_register(&at91sam9263_tcb_device);
976 }
977 #else
978 static void __init at91_add_device_tc(void) { }
979 #endif
980
981
982 /* --------------------------------------------------------------------
983 * RTT
984 * -------------------------------------------------------------------- */
985
986 static struct resource rtt0_resources[] = {
987 {
988 .start = AT91SAM9263_BASE_RTT0,
989 .end = AT91SAM9263_BASE_RTT0 + SZ_16 - 1,
990 .flags = IORESOURCE_MEM,
991 }, {
992 .flags = IORESOURCE_MEM,
993 }, {
994 .flags = IORESOURCE_IRQ,
995 }
996 };
997
998 static struct platform_device at91sam9263_rtt0_device = {
999 .name = "at91_rtt",
1000 .id = 0,
1001 .resource = rtt0_resources,
1002 };
1003
1004 static struct resource rtt1_resources[] = {
1005 {
1006 .start = AT91SAM9263_BASE_RTT1,
1007 .end = AT91SAM9263_BASE_RTT1 + SZ_16 - 1,
1008 .flags = IORESOURCE_MEM,
1009 }, {
1010 .flags = IORESOURCE_MEM,
1011 }, {
1012 .flags = IORESOURCE_IRQ,
1013 }
1014 };
1015
1016 static struct platform_device at91sam9263_rtt1_device = {
1017 .name = "at91_rtt",
1018 .id = 1,
1019 .resource = rtt1_resources,
1020 };
1021
1022 #if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
1023 static void __init at91_add_device_rtt_rtc(void)
1024 {
1025 struct platform_device *pdev;
1026 struct resource *r;
1027
1028 switch (CONFIG_RTC_DRV_AT91SAM9_RTT) {
1029 case 0:
1030 /*
1031 * The second resource is needed only for the chosen RTT:
1032 * GPBR will serve as the storage for RTC time offset
1033 */
1034 at91sam9263_rtt0_device.num_resources = 3;
1035 at91sam9263_rtt1_device.num_resources = 1;
1036 pdev = &at91sam9263_rtt0_device;
1037 r = rtt0_resources;
1038 break;
1039 case 1:
1040 at91sam9263_rtt0_device.num_resources = 1;
1041 at91sam9263_rtt1_device.num_resources = 3;
1042 pdev = &at91sam9263_rtt1_device;
1043 r = rtt1_resources;
1044 break;
1045 default:
1046 pr_err("at91sam9263: only supports 2 RTT (%d)\n",
1047 CONFIG_RTC_DRV_AT91SAM9_RTT);
1048 return;
1049 }
1050
1051 pdev->name = "rtc-at91sam9";
1052 r[1].start = AT91SAM9263_BASE_GPBR + 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
1053 r[1].end = r[1].start + 3;
1054 r[2].start = NR_IRQS_LEGACY + AT91_ID_SYS;
1055 r[2].end = NR_IRQS_LEGACY + AT91_ID_SYS;
1056 }
1057 #else
1058 static void __init at91_add_device_rtt_rtc(void)
1059 {
1060 /* Only one resource is needed: RTT not used as RTC */
1061 at91sam9263_rtt0_device.num_resources = 1;
1062 at91sam9263_rtt1_device.num_resources = 1;
1063 }
1064 #endif
1065
1066 static void __init at91_add_device_rtt(void)
1067 {
1068 at91_add_device_rtt_rtc();
1069 platform_device_register(&at91sam9263_rtt0_device);
1070 platform_device_register(&at91sam9263_rtt1_device);
1071 }
1072
1073
1074 /* --------------------------------------------------------------------
1075 * Watchdog
1076 * -------------------------------------------------------------------- */
1077
1078 #if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
1079 static struct resource wdt_resources[] = {
1080 {
1081 .start = AT91SAM9263_BASE_WDT,
1082 .end = AT91SAM9263_BASE_WDT + SZ_16 - 1,
1083 .flags = IORESOURCE_MEM,
1084 }
1085 };
1086
1087 static struct platform_device at91sam9263_wdt_device = {
1088 .name = "at91_wdt",
1089 .id = -1,
1090 .resource = wdt_resources,
1091 .num_resources = ARRAY_SIZE(wdt_resources),
1092 };
1093
1094 static void __init at91_add_device_watchdog(void)
1095 {
1096 platform_device_register(&at91sam9263_wdt_device);
1097 }
1098 #else
1099 static void __init at91_add_device_watchdog(void) {}
1100 #endif
1101
1102
1103 /* --------------------------------------------------------------------
1104 * PWM
1105 * --------------------------------------------------------------------*/
1106
1107 #if defined(CONFIG_ATMEL_PWM)
1108 static u32 pwm_mask;
1109
1110 static struct resource pwm_resources[] = {
1111 [0] = {
1112 .start = AT91SAM9263_BASE_PWMC,
1113 .end = AT91SAM9263_BASE_PWMC + SZ_16K - 1,
1114 .flags = IORESOURCE_MEM,
1115 },
1116 [1] = {
1117 .start = NR_IRQS_LEGACY + AT91SAM9263_ID_PWMC,
1118 .end = NR_IRQS_LEGACY + AT91SAM9263_ID_PWMC,
1119 .flags = IORESOURCE_IRQ,
1120 },
1121 };
1122
1123 static struct platform_device at91sam9263_pwm0_device = {
1124 .name = "atmel_pwm",
1125 .id = -1,
1126 .dev = {
1127 .platform_data = &pwm_mask,
1128 },
1129 .resource = pwm_resources,
1130 .num_resources = ARRAY_SIZE(pwm_resources),
1131 };
1132
1133 void __init at91_add_device_pwm(u32 mask)
1134 {
1135 if (mask & (1 << AT91_PWM0))
1136 at91_set_B_periph(AT91_PIN_PB7, 1); /* enable PWM0 */
1137
1138 if (mask & (1 << AT91_PWM1))
1139 at91_set_B_periph(AT91_PIN_PB8, 1); /* enable PWM1 */
1140
1141 if (mask & (1 << AT91_PWM2))
1142 at91_set_B_periph(AT91_PIN_PC29, 1); /* enable PWM2 */
1143
1144 if (mask & (1 << AT91_PWM3))
1145 at91_set_B_periph(AT91_PIN_PB29, 1); /* enable PWM3 */
1146
1147 pwm_mask = mask;
1148
1149 platform_device_register(&at91sam9263_pwm0_device);
1150 }
1151 #else
1152 void __init at91_add_device_pwm(u32 mask) {}
1153 #endif
1154
1155
1156 /* --------------------------------------------------------------------
1157 * SSC -- Synchronous Serial Controller
1158 * -------------------------------------------------------------------- */
1159
1160 #if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
1161 static u64 ssc0_dmamask = DMA_BIT_MASK(32);
1162
1163 static struct resource ssc0_resources[] = {
1164 [0] = {
1165 .start = AT91SAM9263_BASE_SSC0,
1166 .end = AT91SAM9263_BASE_SSC0 + SZ_16K - 1,
1167 .flags = IORESOURCE_MEM,
1168 },
1169 [1] = {
1170 .start = NR_IRQS_LEGACY + AT91SAM9263_ID_SSC0,
1171 .end = NR_IRQS_LEGACY + AT91SAM9263_ID_SSC0,
1172 .flags = IORESOURCE_IRQ,
1173 },
1174 };
1175
1176 static struct platform_device at91sam9263_ssc0_device = {
1177 .name = "ssc",
1178 .id = 0,
1179 .dev = {
1180 .dma_mask = &ssc0_dmamask,
1181 .coherent_dma_mask = DMA_BIT_MASK(32),
1182 },
1183 .resource = ssc0_resources,
1184 .num_resources = ARRAY_SIZE(ssc0_resources),
1185 };
1186
1187 static inline void configure_ssc0_pins(unsigned pins)
1188 {
1189 if (pins & ATMEL_SSC_TF)
1190 at91_set_B_periph(AT91_PIN_PB0, 1);
1191 if (pins & ATMEL_SSC_TK)
1192 at91_set_B_periph(AT91_PIN_PB1, 1);
1193 if (pins & ATMEL_SSC_TD)
1194 at91_set_B_periph(AT91_PIN_PB2, 1);
1195 if (pins & ATMEL_SSC_RD)
1196 at91_set_B_periph(AT91_PIN_PB3, 1);
1197 if (pins & ATMEL_SSC_RK)
1198 at91_set_B_periph(AT91_PIN_PB4, 1);
1199 if (pins & ATMEL_SSC_RF)
1200 at91_set_B_periph(AT91_PIN_PB5, 1);
1201 }
1202
1203 static u64 ssc1_dmamask = DMA_BIT_MASK(32);
1204
1205 static struct resource ssc1_resources[] = {
1206 [0] = {
1207 .start = AT91SAM9263_BASE_SSC1,
1208 .end = AT91SAM9263_BASE_SSC1 + SZ_16K - 1,
1209 .flags = IORESOURCE_MEM,
1210 },
1211 [1] = {
1212 .start = NR_IRQS_LEGACY + AT91SAM9263_ID_SSC1,
1213 .end = NR_IRQS_LEGACY + AT91SAM9263_ID_SSC1,
1214 .flags = IORESOURCE_IRQ,
1215 },
1216 };
1217
1218 static struct platform_device at91sam9263_ssc1_device = {
1219 .name = "ssc",
1220 .id = 1,
1221 .dev = {
1222 .dma_mask = &ssc1_dmamask,
1223 .coherent_dma_mask = DMA_BIT_MASK(32),
1224 },
1225 .resource = ssc1_resources,
1226 .num_resources = ARRAY_SIZE(ssc1_resources),
1227 };
1228
1229 static inline void configure_ssc1_pins(unsigned pins)
1230 {
1231 if (pins & ATMEL_SSC_TF)
1232 at91_set_A_periph(AT91_PIN_PB6, 1);
1233 if (pins & ATMEL_SSC_TK)
1234 at91_set_A_periph(AT91_PIN_PB7, 1);
1235 if (pins & ATMEL_SSC_TD)
1236 at91_set_A_periph(AT91_PIN_PB8, 1);
1237 if (pins & ATMEL_SSC_RD)
1238 at91_set_A_periph(AT91_PIN_PB9, 1);
1239 if (pins & ATMEL_SSC_RK)
1240 at91_set_A_periph(AT91_PIN_PB10, 1);
1241 if (pins & ATMEL_SSC_RF)
1242 at91_set_A_periph(AT91_PIN_PB11, 1);
1243 }
1244
1245 /*
1246 * SSC controllers are accessed through library code, instead of any
1247 * kind of all-singing/all-dancing driver. For example one could be
1248 * used by a particular I2S audio codec's driver, while another one
1249 * on the same system might be used by a custom data capture driver.
1250 */
1251 void __init at91_add_device_ssc(unsigned id, unsigned pins)
1252 {
1253 struct platform_device *pdev;
1254
1255 /*
1256 * NOTE: caller is responsible for passing information matching
1257 * "pins" to whatever will be using each particular controller.
1258 */
1259 switch (id) {
1260 case AT91SAM9263_ID_SSC0:
1261 pdev = &at91sam9263_ssc0_device;
1262 configure_ssc0_pins(pins);
1263 break;
1264 case AT91SAM9263_ID_SSC1:
1265 pdev = &at91sam9263_ssc1_device;
1266 configure_ssc1_pins(pins);
1267 break;
1268 default:
1269 return;
1270 }
1271
1272 platform_device_register(pdev);
1273 }
1274
1275 #else
1276 void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
1277 #endif
1278
1279
1280 /* --------------------------------------------------------------------
1281 * UART
1282 * -------------------------------------------------------------------- */
1283
1284 #if defined(CONFIG_SERIAL_ATMEL)
1285
1286 static struct resource dbgu_resources[] = {
1287 [0] = {
1288 .start = AT91SAM9263_BASE_DBGU,
1289 .end = AT91SAM9263_BASE_DBGU + SZ_512 - 1,
1290 .flags = IORESOURCE_MEM,
1291 },
1292 [1] = {
1293 .start = NR_IRQS_LEGACY + AT91_ID_SYS,
1294 .end = NR_IRQS_LEGACY + AT91_ID_SYS,
1295 .flags = IORESOURCE_IRQ,
1296 },
1297 };
1298
1299 static struct atmel_uart_data dbgu_data = {
1300 .use_dma_tx = 0,
1301 .use_dma_rx = 0, /* DBGU not capable of receive DMA */
1302 };
1303
1304 static u64 dbgu_dmamask = DMA_BIT_MASK(32);
1305
1306 static struct platform_device at91sam9263_dbgu_device = {
1307 .name = "atmel_usart",
1308 .id = 0,
1309 .dev = {
1310 .dma_mask = &dbgu_dmamask,
1311 .coherent_dma_mask = DMA_BIT_MASK(32),
1312 .platform_data = &dbgu_data,
1313 },
1314 .resource = dbgu_resources,
1315 .num_resources = ARRAY_SIZE(dbgu_resources),
1316 };
1317
1318 static inline void configure_dbgu_pins(void)
1319 {
1320 at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */
1321 at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */
1322 }
1323
1324 static struct resource uart0_resources[] = {
1325 [0] = {
1326 .start = AT91SAM9263_BASE_US0,
1327 .end = AT91SAM9263_BASE_US0 + SZ_16K - 1,
1328 .flags = IORESOURCE_MEM,
1329 },
1330 [1] = {
1331 .start = NR_IRQS_LEGACY + AT91SAM9263_ID_US0,
1332 .end = NR_IRQS_LEGACY + AT91SAM9263_ID_US0,
1333 .flags = IORESOURCE_IRQ,
1334 },
1335 };
1336
1337 static struct atmel_uart_data uart0_data = {
1338 .use_dma_tx = 1,
1339 .use_dma_rx = 1,
1340 };
1341
1342 static u64 uart0_dmamask = DMA_BIT_MASK(32);
1343
1344 static struct platform_device at91sam9263_uart0_device = {
1345 .name = "atmel_usart",
1346 .id = 1,
1347 .dev = {
1348 .dma_mask = &uart0_dmamask,
1349 .coherent_dma_mask = DMA_BIT_MASK(32),
1350 .platform_data = &uart0_data,
1351 },
1352 .resource = uart0_resources,
1353 .num_resources = ARRAY_SIZE(uart0_resources),
1354 };
1355
1356 static inline void configure_usart0_pins(unsigned pins)
1357 {
1358 at91_set_A_periph(AT91_PIN_PA26, 1); /* TXD0 */
1359 at91_set_A_periph(AT91_PIN_PA27, 0); /* RXD0 */
1360
1361 if (pins & ATMEL_UART_RTS)
1362 at91_set_A_periph(AT91_PIN_PA28, 0); /* RTS0 */
1363 if (pins & ATMEL_UART_CTS)
1364 at91_set_A_periph(AT91_PIN_PA29, 0); /* CTS0 */
1365 }
1366
1367 static struct resource uart1_resources[] = {
1368 [0] = {
1369 .start = AT91SAM9263_BASE_US1,
1370 .end = AT91SAM9263_BASE_US1 + SZ_16K - 1,
1371 .flags = IORESOURCE_MEM,
1372 },
1373 [1] = {
1374 .start = NR_IRQS_LEGACY + AT91SAM9263_ID_US1,
1375 .end = NR_IRQS_LEGACY + AT91SAM9263_ID_US1,
1376 .flags = IORESOURCE_IRQ,
1377 },
1378 };
1379
1380 static struct atmel_uart_data uart1_data = {
1381 .use_dma_tx = 1,
1382 .use_dma_rx = 1,
1383 };
1384
1385 static u64 uart1_dmamask = DMA_BIT_MASK(32);
1386
1387 static struct platform_device at91sam9263_uart1_device = {
1388 .name = "atmel_usart",
1389 .id = 2,
1390 .dev = {
1391 .dma_mask = &uart1_dmamask,
1392 .coherent_dma_mask = DMA_BIT_MASK(32),
1393 .platform_data = &uart1_data,
1394 },
1395 .resource = uart1_resources,
1396 .num_resources = ARRAY_SIZE(uart1_resources),
1397 };
1398
1399 static inline void configure_usart1_pins(unsigned pins)
1400 {
1401 at91_set_A_periph(AT91_PIN_PD0, 1); /* TXD1 */
1402 at91_set_A_periph(AT91_PIN_PD1, 0); /* RXD1 */
1403
1404 if (pins & ATMEL_UART_RTS)
1405 at91_set_B_periph(AT91_PIN_PD7, 0); /* RTS1 */
1406 if (pins & ATMEL_UART_CTS)
1407 at91_set_B_periph(AT91_PIN_PD8, 0); /* CTS1 */
1408 }
1409
1410 static struct resource uart2_resources[] = {
1411 [0] = {
1412 .start = AT91SAM9263_BASE_US2,
1413 .end = AT91SAM9263_BASE_US2 + SZ_16K - 1,
1414 .flags = IORESOURCE_MEM,
1415 },
1416 [1] = {
1417 .start = NR_IRQS_LEGACY + AT91SAM9263_ID_US2,
1418 .end = NR_IRQS_LEGACY + AT91SAM9263_ID_US2,
1419 .flags = IORESOURCE_IRQ,
1420 },
1421 };
1422
1423 static struct atmel_uart_data uart2_data = {
1424 .use_dma_tx = 1,
1425 .use_dma_rx = 1,
1426 };
1427
1428 static u64 uart2_dmamask = DMA_BIT_MASK(32);
1429
1430 static struct platform_device at91sam9263_uart2_device = {
1431 .name = "atmel_usart",
1432 .id = 3,
1433 .dev = {
1434 .dma_mask = &uart2_dmamask,
1435 .coherent_dma_mask = DMA_BIT_MASK(32),
1436 .platform_data = &uart2_data,
1437 },
1438 .resource = uart2_resources,
1439 .num_resources = ARRAY_SIZE(uart2_resources),
1440 };
1441
1442 static inline void configure_usart2_pins(unsigned pins)
1443 {
1444 at91_set_A_periph(AT91_PIN_PD2, 1); /* TXD2 */
1445 at91_set_A_periph(AT91_PIN_PD3, 0); /* RXD2 */
1446
1447 if (pins & ATMEL_UART_RTS)
1448 at91_set_B_periph(AT91_PIN_PD5, 0); /* RTS2 */
1449 if (pins & ATMEL_UART_CTS)
1450 at91_set_B_periph(AT91_PIN_PD6, 0); /* CTS2 */
1451 }
1452
1453 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
1454
1455 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1456 {
1457 struct platform_device *pdev;
1458 struct atmel_uart_data *pdata;
1459
1460 switch (id) {
1461 case 0: /* DBGU */
1462 pdev = &at91sam9263_dbgu_device;
1463 configure_dbgu_pins();
1464 break;
1465 case AT91SAM9263_ID_US0:
1466 pdev = &at91sam9263_uart0_device;
1467 configure_usart0_pins(pins);
1468 break;
1469 case AT91SAM9263_ID_US1:
1470 pdev = &at91sam9263_uart1_device;
1471 configure_usart1_pins(pins);
1472 break;
1473 case AT91SAM9263_ID_US2:
1474 pdev = &at91sam9263_uart2_device;
1475 configure_usart2_pins(pins);
1476 break;
1477 default:
1478 return;
1479 }
1480 pdata = pdev->dev.platform_data;
1481 pdata->num = portnr; /* update to mapped ID */
1482
1483 if (portnr < ATMEL_MAX_UART)
1484 at91_uarts[portnr] = pdev;
1485 }
1486
1487 void __init at91_add_device_serial(void)
1488 {
1489 int i;
1490
1491 for (i = 0; i < ATMEL_MAX_UART; i++) {
1492 if (at91_uarts[i])
1493 platform_device_register(at91_uarts[i]);
1494 }
1495 }
1496 #else
1497 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1498 void __init at91_add_device_serial(void) {}
1499 #endif
1500
1501
1502 /* -------------------------------------------------------------------- */
1503 /*
1504 * These devices are always present and don't need any board-specific
1505 * setup.
1506 */
1507 static int __init at91_add_standard_devices(void)
1508 {
1509 if (of_have_populated_dt())
1510 return 0;
1511
1512 at91_add_device_rtt();
1513 at91_add_device_watchdog();
1514 at91_add_device_tc();
1515 return 0;
1516 }
1517
1518 arch_initcall(at91_add_standard_devices);
Linux ARM platform port for MOXA ART SoC