11 config RWSEM_GENERIC_SPINLOCK
14 config RWSEM_XCHGADD_ALGORITHM
20 select HAVE_ARCH_TRACEHOOK
21 select HAVE_DYNAMIC_FTRACE
22 select HAVE_FTRACE_MCOUNT_RECORD
23 select HAVE_FUNCTION_GRAPH_TRACER
24 select HAVE_FUNCTION_TRACER
25 select HAVE_FUNCTION_TRACE_MCOUNT_TEST
28 select HAVE_KERNEL_GZIP if RAMKERNEL
29 select HAVE_KERNEL_BZIP2 if RAMKERNEL
30 select HAVE_KERNEL_LZMA if RAMKERNEL
31 select HAVE_KERNEL_LZO if RAMKERNEL
33 select HAVE_PERF_EVENTS
34 select ARCH_HAVE_CUSTOM_GPIO_H
35 select ARCH_WANT_OPTIONAL_GPIOLIB
36 select ARCH_WANT_IPC_PARSE_VERSION
37 select HAVE_GENERIC_HARDIRQS
38 select GENERIC_ATOMIC64
39 select GENERIC_IRQ_PROBE
40 select IRQ_PER_CPU if SMP
41 select USE_GENERIC_SMP_HELPERS if SMP
42 select HAVE_NMI_WATCHDOG if NMI_WATCHDOG
43 select GENERIC_SMP_IDLE_THREAD
44 select ARCH_USES_GETTIMEOFFSET if !GENERIC_CLOCKEVENTS
59 config FORCE_MAX_ZONEORDER
63 config GENERIC_CALIBRATE_DELAY
66 config LOCKDEP_SUPPORT
69 config STACKTRACE_SUPPORT
72 config TRACE_IRQFLAGS_SUPPORT
77 source "kernel/Kconfig.preempt"
79 source "kernel/Kconfig.freezer"
81 menu "Blackfin Processor Options"
83 comment "Processor and Board Settings"
92 BF512 Processor Support.
97 BF514 Processor Support.
102 BF516 Processor Support.
107 BF518 Processor Support.
112 BF522 Processor Support.
117 BF523 Processor Support.
122 BF524 Processor Support.
127 BF525 Processor Support.
132 BF526 Processor Support.
137 BF527 Processor Support.
142 BF531 Processor Support.
147 BF532 Processor Support.
152 BF533 Processor Support.
157 BF534 Processor Support.
162 BF536 Processor Support.
167 BF537 Processor Support.
172 BF538 Processor Support.
177 BF539 Processor Support.
182 BF542 Processor Support.
187 BF542 Processor Support.
192 BF544 Processor Support.
197 BF544 Processor Support.
202 BF547 Processor Support.
207 BF547 Processor Support.
212 BF548 Processor Support.
217 BF548 Processor Support.
222 BF549 Processor Support.
227 BF549 Processor Support.
232 BF561 Processor Support.
238 BF609 Processor Support.
244 select TICKSOURCE_CORETMR
245 bool "Symmetric multi-processing support"
247 This enables support for systems with more than one CPU,
248 like the dual core BF561. If you have a system with only one
249 CPU, say N. If you have a system with more than one CPU, say Y.
251 If you don't know what to do here, say N.
259 bool "Support for hot-pluggable CPUs"
260 depends on SMP && HOTPLUG
265 default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
266 default 2 if (BF537 || BF536 || BF534)
267 default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
268 default 4 if (BF538 || BF539)
272 default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
273 default 3 if (BF537 || BF536 || BF534 || BF54xM)
274 default 5 if (BF561 || BF538 || BF539)
275 default 6 if (BF533 || BF532 || BF531)
279 default BF_REV_0_0 if (BF51x || BF52x || BF60x)
280 default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
281 default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
285 depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x)
289 depends on (BF51x || BF52x || (BF54x && !BF54xM))
293 depends on (BF51x || BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
297 depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
301 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
305 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
309 depends on (BF533 || BF532 || BF531)
321 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
324 config MEM_MT48LC64M4A2FB_7E
326 depends on (BFIN533_STAMP)
329 config MEM_MT48LC16M16A2TG_75
331 depends on (BFIN533_EZKIT || BFIN561_EZKIT \
332 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \
333 || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \
334 || BFIN527_BLUETECHNIX_CM)
337 config MEM_MT48LC32M8A2_75
339 depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
342 config MEM_MT48LC8M32B2B5_7
344 depends on (BFIN561_BLUETECHNIX_CM)
347 config MEM_MT48LC32M16A2TG_75
349 depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP || BFIN527_AD7160EVAL)
352 config MEM_MT48H32M16LFCJ_75
354 depends on (BFIN526_EZBRD)
357 config MEM_MT47H64M16
359 depends on (BFIN609_EZKIT)
362 source "arch/blackfin/mach-bf518/Kconfig"
363 source "arch/blackfin/mach-bf527/Kconfig"
364 source "arch/blackfin/mach-bf533/Kconfig"
365 source "arch/blackfin/mach-bf561/Kconfig"
366 source "arch/blackfin/mach-bf537/Kconfig"
367 source "arch/blackfin/mach-bf538/Kconfig"
368 source "arch/blackfin/mach-bf548/Kconfig"
369 source "arch/blackfin/mach-bf609/Kconfig"
371 menu "Board customizations"
374 bool "Default bootloader kernel arguments"
377 string "Initial kernel command string"
378 depends on CMDLINE_BOOL
379 default "console=ttyBF0,57600"
381 If you don't have a boot loader capable of passing a command line string
382 to the kernel, you may specify one here. As a minimum, you should specify
383 the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
386 hex "Kernel load address for booting"
388 range 0x1000 0x20000000
390 This option allows you to set the load address of the kernel.
391 This can be useful if you are on a board which has a small amount
392 of memory or you wish to reserve some memory at the beginning of
395 Note that you need to keep this value above 4k (0x1000) as this
396 memory region is used to capture NULL pointer references as well
397 as some core kernel functions.
399 config PHY_RAM_BASE_ADDRESS
400 hex "Physical RAM Base"
403 set BF609 FPGA physical SRAM base address
406 hex "Kernel ROM Base"
409 range 0x20000000 0x20400000 if !(BF54x || BF561 || BF60x)
410 range 0x20000000 0x30000000 if (BF54x || BF561)
411 range 0xB0000000 0xC0000000 if (BF60x)
413 Make sure your ROM base does not include any file-header
414 information that is prepended to the kernel.
416 For example, the bootable U-Boot format (created with
417 mkimage) has a 64 byte header (0x40). So while the image
418 you write to flash might start at say 0x20080000, you have
419 to add 0x40 to get the kernel's ROM base as it will come
422 comment "Clock/PLL Setup"
425 int "Frequency of the crystal on the board in Hz"
426 default "10000000" if BFIN532_IP0X
427 default "11059200" if BFIN533_STAMP
428 default "24576000" if PNAV10
429 default "25000000" # most people use this
430 default "27000000" if BFIN533_EZKIT
431 default "30000000" if BFIN561_EZKIT
432 default "24000000" if BFIN527_AD7160EVAL
434 The frequency of CLKIN crystal oscillator on the board in Hz.
435 Warning: This value should match the crystal on the board. Otherwise,
436 peripherals won't work properly.
438 config BFIN_KERNEL_CLOCK
439 bool "Re-program Clocks while Kernel boots?"
442 This option decides if kernel clocks are re-programed from the
443 bootloader settings. If the clocks are not set, the SDRAM settings
444 are also not changed, and the Bootloader does 100% of the hardware
449 depends on BFIN_KERNEL_CLOCK && (!BF60x)
454 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
457 If this is set the clock will be divided by 2, before it goes to the PLL.
461 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
463 default "22" if BFIN533_EZKIT
464 default "45" if BFIN533_STAMP
465 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
466 default "22" if BFIN533_BLUETECHNIX_CM
467 default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
468 default "20" if (BFIN561_EZKIT || BF609)
469 default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
470 default "25" if BFIN527_AD7160EVAL
472 This controls the frequency of the on-chip PLL. This can be between 1 and 64.
473 PLL Frequency = (Crystal Frequency) * (this setting)
476 prompt "Core Clock Divider"
477 depends on BFIN_KERNEL_CLOCK
480 This sets the frequency of the core. It can be 1, 2, 4 or 8
481 Core Frequency = (PLL frequency) / (this setting)
497 int "System Clock Divider"
498 depends on BFIN_KERNEL_CLOCK
502 This sets the frequency of the system clock (including SDRAM or DDR) on
503 !BF60x else it set the clock for system buses and provides the
504 source from which SCLK0 and SCLK1 are derived.
505 This can be between 1 and 15
506 System Clock = (PLL frequency) / (this setting)
509 int "System Clock0 Divider"
510 depends on BFIN_KERNEL_CLOCK && BF60x
514 This sets the frequency of the system clock0 for PVP and all other
515 peripherals not clocked by SCLK1.
516 This can be between 1 and 15
517 System Clock0 = (System Clock) / (this setting)
520 int "System Clock1 Divider"
521 depends on BFIN_KERNEL_CLOCK && BF60x
525 This sets the frequency of the system clock1 (including SPORT, SPI and ACM).
526 This can be between 1 and 15
527 System Clock1 = (System Clock) / (this setting)
530 int "DDR Clock Divider"
531 depends on BFIN_KERNEL_CLOCK && BF60x
535 This sets the frequency of the DDR memory.
536 This can be between 1 and 15
537 DDR Clock = (PLL frequency) / (this setting)
540 prompt "DDR SDRAM Chip Type"
541 depends on BFIN_KERNEL_CLOCK
543 default MEM_MT46V32M16_5B
545 config MEM_MT46V32M16_6T
548 config MEM_MT46V32M16_5B
553 prompt "DDR/SDRAM Timing"
554 depends on BFIN_KERNEL_CLOCK && !BF60x
555 default BFIN_KERNEL_CLOCK_MEMINIT_CALC
557 This option allows you to specify Blackfin SDRAM/DDR Timing parameters
558 The calculated SDRAM timing parameters may not be 100%
559 accurate - This option is therefore marked experimental.
561 config BFIN_KERNEL_CLOCK_MEMINIT_CALC
562 bool "Calculate Timings (EXPERIMENTAL)"
563 depends on EXPERIMENTAL
565 config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
566 bool "Provide accurate Timings based on target SCLK"
568 Please consult the Blackfin Hardware Reference Manuals as well
569 as the memory device datasheet.
570 http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
573 menu "Memory Init Control"
574 depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
591 config MEM_EBIU_DDRQUE
608 # Max & Min Speeds for various Chips
612 default 400000000 if BF512
613 default 400000000 if BF514
614 default 400000000 if BF516
615 default 400000000 if BF518
616 default 400000000 if BF522
617 default 600000000 if BF523
618 default 400000000 if BF524
619 default 600000000 if BF525
620 default 400000000 if BF526
621 default 600000000 if BF527
622 default 400000000 if BF531
623 default 400000000 if BF532
624 default 750000000 if BF533
625 default 500000000 if BF534
626 default 400000000 if BF536
627 default 600000000 if BF537
628 default 533333333 if BF538
629 default 533333333 if BF539
630 default 600000000 if BF542
631 default 533333333 if BF544
632 default 600000000 if BF547
633 default 600000000 if BF548
634 default 533333333 if BF549
635 default 600000000 if BF561
636 default 800000000 if BF609
644 default 200000000 if BF609
651 comment "Kernel Timer/Scheduler"
653 source kernel/Kconfig.hz
655 config SET_GENERIC_CLOCKEVENTS
656 bool "Generic clock events"
658 select GENERIC_CLOCKEVENTS
660 menu "Clock event device"
661 depends on GENERIC_CLOCKEVENTS
662 config TICKSOURCE_GPTMR0
667 config TICKSOURCE_CORETMR
673 depends on GENERIC_CLOCKEVENTS
674 config CYCLES_CLOCKSOURCE
677 depends on !BFIN_SCRATCH_REG_CYCLES
680 If you say Y here, you will enable support for using the 'cycles'
681 registers as a clock source. Doing so means you will be unable to
682 safely write to the 'cycles' register during runtime. You will
683 still be able to read it (such as for performance monitoring), but
684 writing the registers will most likely crash the kernel.
686 config GPTMR0_CLOCKSOURCE
689 depends on !TICKSOURCE_GPTMR0
695 prompt "Blackfin Exception Scratch Register"
696 default BFIN_SCRATCH_REG_RETN
698 Select the resource to reserve for the Exception handler:
699 - RETN: Non-Maskable Interrupt (NMI)
700 - RETE: Exception Return (JTAG/ICE)
701 - CYCLES: Performance counter
703 If you are unsure, please select "RETN".
705 config BFIN_SCRATCH_REG_RETN
708 Use the RETN register in the Blackfin exception handler
709 as a stack scratch register. This means you cannot
710 safely use NMI on the Blackfin while running Linux, but
711 you can debug the system with a JTAG ICE and use the
712 CYCLES performance registers.
714 If you are unsure, please select "RETN".
716 config BFIN_SCRATCH_REG_RETE
719 Use the RETE register in the Blackfin exception handler
720 as a stack scratch register. This means you cannot
721 safely use a JTAG ICE while debugging a Blackfin board,
722 but you can safely use the CYCLES performance registers
725 If you are unsure, please select "RETN".
727 config BFIN_SCRATCH_REG_CYCLES
730 Use the CYCLES register in the Blackfin exception handler
731 as a stack scratch register. This means you cannot
732 safely use the CYCLES performance registers on a Blackfin
733 board at anytime, but you can debug the system with a JTAG
736 If you are unsure, please select "RETN".
743 menu "Blackfin Kernel Optimizations"
745 comment "Memory Optimizations"
748 bool "Locate interrupt entry code in L1 Memory"
752 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
753 into L1 instruction memory. (less latency)
755 config EXCPT_IRQ_SYSC_L1
756 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
760 If enabled, the entire ASM lowlevel exception and interrupt entry code
761 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
765 bool "Locate frequently called do_irq dispatcher function in L1 Memory"
769 If enabled, the frequently called do_irq dispatcher function is linked
770 into L1 instruction memory. (less latency)
772 config CORE_TIMER_IRQ_L1
773 bool "Locate frequently called timer_interrupt() function in L1 Memory"
777 If enabled, the frequently called timer_interrupt() function is linked
778 into L1 instruction memory. (less latency)
781 bool "Locate frequently idle function in L1 Memory"
785 If enabled, the frequently called idle function is linked
786 into L1 instruction memory. (less latency)
789 bool "Locate kernel schedule function in L1 Memory"
793 If enabled, the frequently called kernel schedule is linked
794 into L1 instruction memory. (less latency)
796 config ARITHMETIC_OPS_L1
797 bool "Locate kernel owned arithmetic functions in L1 Memory"
801 If enabled, arithmetic functions are linked
802 into L1 instruction memory. (less latency)
805 bool "Locate access_ok function in L1 Memory"
809 If enabled, the access_ok function is linked
810 into L1 instruction memory. (less latency)
813 bool "Locate memset function in L1 Memory"
817 If enabled, the memset function is linked
818 into L1 instruction memory. (less latency)
821 bool "Locate memcpy function in L1 Memory"
825 If enabled, the memcpy function is linked
826 into L1 instruction memory. (less latency)
829 bool "locate strcmp function in L1 Memory"
833 If enabled, the strcmp function is linked
834 into L1 instruction memory (less latency).
837 bool "locate strncmp function in L1 Memory"
841 If enabled, the strncmp function is linked
842 into L1 instruction memory (less latency).
845 bool "locate strcpy function in L1 Memory"
849 If enabled, the strcpy function is linked
850 into L1 instruction memory (less latency).
853 bool "locate strncpy function in L1 Memory"
857 If enabled, the strncpy function is linked
858 into L1 instruction memory (less latency).
860 config SYS_BFIN_SPINLOCK_L1
861 bool "Locate sys_bfin_spinlock function in L1 Memory"
865 If enabled, sys_bfin_spinlock function is linked
866 into L1 instruction memory. (less latency)
868 config IP_CHECKSUM_L1
869 bool "Locate IP Checksum function in L1 Memory"
873 If enabled, the IP Checksum function is linked
874 into L1 instruction memory. (less latency)
876 config CACHELINE_ALIGNED_L1
877 bool "Locate cacheline_aligned data to L1 Data Memory"
880 depends on !SMP && !BF531 && !CRC32
882 If enabled, cacheline_aligned data is linked
883 into L1 data memory. (less latency)
885 config SYSCALL_TAB_L1
886 bool "Locate Syscall Table L1 Data Memory"
888 depends on !SMP && !BF531
890 If enabled, the Syscall LUT is linked
891 into L1 data memory. (less latency)
893 config CPLB_SWITCH_TAB_L1
894 bool "Locate CPLB Switch Tables L1 Data Memory"
896 depends on !SMP && !BF531
898 If enabled, the CPLB Switch Tables are linked
899 into L1 data memory. (less latency)
901 config ICACHE_FLUSH_L1
902 bool "Locate icache flush funcs in L1 Inst Memory"
905 If enabled, the Blackfin icache flushing functions are linked
906 into L1 instruction memory.
908 Note that this might be required to address anomalies, but
909 these functions are pretty small, so it shouldn't be too bad.
910 If you are using a processor affected by an anomaly, the build
911 system will double check for you and prevent it.
913 config DCACHE_FLUSH_L1
914 bool "Locate dcache flush funcs in L1 Inst Memory"
918 If enabled, the Blackfin dcache flushing functions are linked
919 into L1 instruction memory.
922 bool "Support locating application stack in L1 Scratch Memory"
926 If enabled the application stack can be located in L1
927 scratch memory (less latency).
929 Currently only works with FLAT binaries.
931 config EXCEPTION_L1_SCRATCH
932 bool "Locate exception stack in L1 Scratch Memory"
934 depends on !SMP && !APP_STACK_L1
936 Whenever an exception occurs, use the L1 Scratch memory for
937 stack storage. You cannot place the stacks of FLAT binaries
938 in L1 when using this option.
940 If you don't use L1 Scratch, then you should say Y here.
942 comment "Speed Optimizations"
943 config BFIN_INS_LOWOVERHEAD
944 bool "ins[bwl] low overhead, higher interrupt latency"
948 Reads on the Blackfin are speculative. In Blackfin terms, this means
949 they can be interrupted at any time (even after they have been issued
950 on to the external bus), and re-issued after the interrupt occurs.
951 For memory - this is not a big deal, since memory does not change if
954 If a FIFO is sitting on the end of the read, it will see two reads,
955 when the core only sees one since the FIFO receives both the read
956 which is cancelled (and not delivered to the core) and the one which
957 is re-issued (which is delivered to the core).
959 To solve this, interrupts are turned off before reads occur to
960 I/O space. This option controls which the overhead/latency of
961 controlling interrupts during this time
962 "n" turns interrupts off every read
963 (higher overhead, but lower interrupt latency)
964 "y" turns interrupts off every loop
965 (low overhead, but longer interrupt latency)
967 default behavior is to leave this set to on (type "Y"). If you are experiencing
968 interrupt latency issues, it is safe and OK to turn this off.
973 prompt "Kernel executes from"
975 Choose the memory type that the kernel will be running in.
980 The kernel will be resident in RAM when running.
985 The kernel will be resident in FLASH/ROM when running.
989 # Common code uses "ROMKERNEL" or "XIP_KERNEL", so define both
998 tristate "Enable Blackfin General Purpose Timers API"
1001 Enable support for the General Purpose Timers API. If you
1004 To compile this driver as a module, choose M here: the module
1005 will be called gptimers.
1008 prompt "Uncached DMA region"
1009 default DMA_UNCACHED_1M
1010 config DMA_UNCACHED_32M
1011 bool "Enable 32M DMA region"
1012 config DMA_UNCACHED_16M
1013 bool "Enable 16M DMA region"
1014 config DMA_UNCACHED_8M
1015 bool "Enable 8M DMA region"
1016 config DMA_UNCACHED_4M
1017 bool "Enable 4M DMA region"
1018 config DMA_UNCACHED_2M
1019 bool "Enable 2M DMA region"
1020 config DMA_UNCACHED_1M
1021 bool "Enable 1M DMA region"
1022 config DMA_UNCACHED_512K
1023 bool "Enable 512K DMA region"
1024 config DMA_UNCACHED_256K
1025 bool "Enable 256K DMA region"
1026 config DMA_UNCACHED_128K
1027 bool "Enable 128K DMA region"
1028 config DMA_UNCACHED_NONE
1029 bool "Disable DMA region"
1033 comment "Cache Support"
1036 bool "Enable ICACHE"
1038 config BFIN_EXTMEM_ICACHEABLE
1039 bool "Enable ICACHE for external memory"
1040 depends on BFIN_ICACHE
1042 config BFIN_L2_ICACHEABLE
1043 bool "Enable ICACHE for L2 SRAM"
1044 depends on BFIN_ICACHE
1045 depends on (BF54x || BF561 || BF60x) && !SMP
1049 bool "Enable DCACHE"
1051 config BFIN_DCACHE_BANKA
1052 bool "Enable only 16k BankA DCACHE - BankB is SRAM"
1053 depends on BFIN_DCACHE && !BF531
1055 config BFIN_EXTMEM_DCACHEABLE
1056 bool "Enable DCACHE for external memory"
1057 depends on BFIN_DCACHE
1060 prompt "External memory DCACHE policy"
1061 depends on BFIN_EXTMEM_DCACHEABLE
1062 default BFIN_EXTMEM_WRITEBACK if !SMP
1063 default BFIN_EXTMEM_WRITETHROUGH if SMP
1064 config BFIN_EXTMEM_WRITEBACK
1069 Cached data will be written back to SDRAM only when needed.
1070 This can give a nice increase in performance, but beware of
1071 broken drivers that do not properly invalidate/flush their
1074 Write Through Policy:
1075 Cached data will always be written back to SDRAM when the
1076 cache is updated. This is a completely safe setting, but
1077 performance is worse than Write Back.
1079 If you are unsure of the options and you want to be safe,
1080 then go with Write Through.
1082 config BFIN_EXTMEM_WRITETHROUGH
1083 bool "Write through"
1086 Cached data will be written back to SDRAM only when needed.
1087 This can give a nice increase in performance, but beware of
1088 broken drivers that do not properly invalidate/flush their
1091 Write Through Policy:
1092 Cached data will always be written back to SDRAM when the
1093 cache is updated. This is a completely safe setting, but
1094 performance is worse than Write Back.
1096 If you are unsure of the options and you want to be safe,
1097 then go with Write Through.
1101 config BFIN_L2_DCACHEABLE
1102 bool "Enable DCACHE for L2 SRAM"
1103 depends on BFIN_DCACHE
1104 depends on (BF54x || BF561 || BF60x) && !SMP
1107 prompt "L2 SRAM DCACHE policy"
1108 depends on BFIN_L2_DCACHEABLE
1109 default BFIN_L2_WRITEBACK
1110 config BFIN_L2_WRITEBACK
1113 config BFIN_L2_WRITETHROUGH
1114 bool "Write through"
1118 comment "Memory Protection Unit"
1120 bool "Enable the memory protection unit (EXPERIMENTAL)"
1123 Use the processor's MPU to protect applications from accessing
1124 memory they do not own. This comes at a performance penalty
1125 and is recommended only for debugging.
1127 comment "Asynchronous Memory Configuration"
1129 menu "EBIU_AMGCTL Global Control"
1132 bool "Enable CLKOUT"
1136 bool "DMA has priority over core for ext. accesses"
1141 bool "Bank 0 16 bit packing enable"
1146 bool "Bank 1 16 bit packing enable"
1151 bool "Bank 2 16 bit packing enable"
1156 bool "Bank 3 16 bit packing enable"
1160 prompt "Enable Asynchronous Memory Banks"
1164 bool "Disable All Banks"
1167 bool "Enable Bank 0"
1169 config C_AMBEN_B0_B1
1170 bool "Enable Bank 0 & 1"
1172 config C_AMBEN_B0_B1_B2
1173 bool "Enable Bank 0 & 1 & 2"
1176 bool "Enable All Banks"
1180 menu "EBIU_AMBCTL Control"
1183 hex "Bank 0 (AMBCTL0.L)"
1186 These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
1187 used to control the Asynchronous Memory Bank 0 settings.
1190 hex "Bank 1 (AMBCTL0.H)"
1192 default 0x5558 if BF54x
1194 These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
1195 used to control the Asynchronous Memory Bank 1 settings.
1198 hex "Bank 2 (AMBCTL1.L)"
1201 These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
1202 used to control the Asynchronous Memory Bank 2 settings.
1205 hex "Bank 3 (AMBCTL1.H)"
1208 These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
1209 used to control the Asynchronous Memory Bank 3 settings.
1213 config EBIU_MBSCTLVAL
1214 hex "EBIU Bank Select Control Register"
1219 hex "Flash Memory Mode Control Register"
1224 hex "Flash Memory Bank Control Register"
1229 #############################################################################
1230 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1236 Support for PCI bus.
1238 source "drivers/pci/Kconfig"
1240 source "drivers/pcmcia/Kconfig"
1242 source "drivers/pci/hotplug/Kconfig"
1246 menu "Executable file formats"
1248 source "fs/Kconfig.binfmt"
1252 menu "Power management options"
1254 source "kernel/power/Kconfig"
1256 config ARCH_SUSPEND_POSSIBLE
1260 prompt "Standby Power Saving Mode"
1261 depends on PM && !BF60x
1262 default PM_BFIN_SLEEP_DEEPER
1263 config PM_BFIN_SLEEP_DEEPER
1266 Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1267 power dissipation by disabling the clock to the processor core (CCLK).
1268 Furthermore, Standby sets the internal power supply voltage (VDDINT)
1269 to 0.85 V to provide the greatest power savings, while preserving the
1271 The PLL and system clock (SCLK) continue to operate at a very low
1272 frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1273 the SDRAM is put into Self Refresh Mode. Typically an external event
1274 such as GPIO interrupt or RTC activity wakes up the processor.
1275 Various Peripherals such as UART, SPORT, PPI may not function as
1276 normal during Sleep Deeper, due to the reduced SCLK frequency.
1277 When in the sleep mode, system DMA access to L1 memory is not supported.
1279 If unsure, select "Sleep Deeper".
1281 config PM_BFIN_SLEEP
1284 Sleep Mode (High Power Savings) - The sleep mode reduces power
1285 dissipation by disabling the clock to the processor core (CCLK).
1286 The PLL and system clock (SCLK), however, continue to operate in
1287 this mode. Typically an external event or RTC activity will wake
1288 up the processor. When in the sleep mode, system DMA access to L1
1289 memory is not supported.
1291 If unsure, select "Sleep Deeper".
1294 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1297 config PM_BFIN_WAKE_PH6
1298 bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1299 depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1302 Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1304 config PM_BFIN_WAKE_GP
1305 bool "Allow Wake-Up from GPIOs"
1306 depends on PM && BF54x
1309 Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1310 (all processors, except ADSP-BF549). This option sets
1311 the general-purpose wake-up enable (GPWE) control bit to enable
1312 wake-up upon detection of an active low signal on the /GPW (PH7) pin.
1313 On ADSP-BF549 this option enables the same functionality on the
1314 /MRXON pin also PH7.
1316 config PM_BFIN_WAKE_PA15
1317 bool "Allow Wake-Up from PA15"
1318 depends on PM && BF60x
1323 config PM_BFIN_WAKE_PA15_POL
1324 int "Wake-up priority"
1325 depends on PM_BFIN_WAKE_PA15
1328 Wake-Up priority 0(low) 1(high)
1330 config PM_BFIN_WAKE_PB15
1331 bool "Allow Wake-Up from PB15"
1332 depends on PM && BF60x
1337 config PM_BFIN_WAKE_PB15_POL
1338 int "Wake-up priority"
1339 depends on PM_BFIN_WAKE_PB15
1342 Wake-Up priority 0(low) 1(high)
1344 config PM_BFIN_WAKE_PC15
1345 bool "Allow Wake-Up from PC15"
1346 depends on PM && BF60x
1351 config PM_BFIN_WAKE_PC15_POL
1352 int "Wake-up priority"
1353 depends on PM_BFIN_WAKE_PC15
1356 Wake-Up priority 0(low) 1(high)
1358 config PM_BFIN_WAKE_PD06
1359 bool "Allow Wake-Up from PD06(ETH0_PHYINT)"
1360 depends on PM && BF60x
1363 Enable PD06(ETH0_PHYINT) Wake-up
1365 config PM_BFIN_WAKE_PD06_POL
1366 int "Wake-up priority"
1367 depends on PM_BFIN_WAKE_PD06
1370 Wake-Up priority 0(low) 1(high)
1372 config PM_BFIN_WAKE_PE12
1373 bool "Allow Wake-Up from PE12(ETH1_PHYINT, PUSH BUTTON)"
1374 depends on PM && BF60x
1377 Enable PE12(ETH1_PHYINT, PUSH BUTTON) Wake-up
1379 config PM_BFIN_WAKE_PE12_POL
1380 int "Wake-up priority"
1381 depends on PM_BFIN_WAKE_PE12
1384 Wake-Up priority 0(low) 1(high)
1386 config PM_BFIN_WAKE_PG04
1387 bool "Allow Wake-Up from PG04(CAN0_RX)"
1388 depends on PM && BF60x
1391 Enable PG04(CAN0_RX) Wake-up
1393 config PM_BFIN_WAKE_PG04_POL
1394 int "Wake-up priority"
1395 depends on PM_BFIN_WAKE_PG04
1398 Wake-Up priority 0(low) 1(high)
1400 config PM_BFIN_WAKE_PG13
1401 bool "Allow Wake-Up from PG13"
1402 depends on PM && BF60x
1407 config PM_BFIN_WAKE_PG13_POL
1408 int "Wake-up priority"
1409 depends on PM_BFIN_WAKE_PG13
1412 Wake-Up priority 0(low) 1(high)
1414 config PM_BFIN_WAKE_USB
1415 bool "Allow Wake-Up from (USB)"
1416 depends on PM && BF60x
1419 Enable (USB) Wake-up
1421 config PM_BFIN_WAKE_USB_POL
1422 int "Wake-up priority"
1423 depends on PM_BFIN_WAKE_USB
1426 Wake-Up priority 0(low) 1(high)
1430 menu "CPU Frequency scaling"
1432 source "drivers/cpufreq/Kconfig"
1434 config BFIN_CPU_FREQ
1437 select CPU_FREQ_TABLE
1441 bool "CPU Voltage scaling"
1442 depends on EXPERIMENTAL
1446 Say Y here if you want CPU voltage scaling according to the CPU frequency.
1447 This option violates the PLL BYPASS recommendation in the Blackfin Processor
1448 manuals. There is a theoretical risk that during VDDINT transitions
1453 source "net/Kconfig"
1455 source "drivers/Kconfig"
1457 source "drivers/firmware/Kconfig"
1461 source "arch/blackfin/Kconfig.debug"
1463 source "security/Kconfig"
1465 source "crypto/Kconfig"
1467 source "lib/Kconfig"