initial commit with v3.6.7
[linux-3.6.7-moxart.git] / arch / mips / include / asm / mach-bcm63xx / bcm63xx_regs.h
blob61f2a2a5099d02ad281290c675604a4e897e9bf9
1 #ifndef BCM63XX_REGS_H_
2 #define BCM63XX_REGS_H_
4 /*************************************************************************
5 * _REG relative to RSET_PERF
6 *************************************************************************/
8 /* Chip Identifier / Revision register */
9 #define PERF_REV_REG 0x0
10 #define REV_CHIPID_SHIFT 16
11 #define REV_CHIPID_MASK (0xffff << REV_CHIPID_SHIFT)
12 #define REV_REVID_SHIFT 0
13 #define REV_REVID_MASK (0xffff << REV_REVID_SHIFT)
15 /* Clock Control register */
16 #define PERF_CKCTL_REG 0x4
18 #define CKCTL_6328_PHYMIPS_EN (1 << 0)
19 #define CKCTL_6328_ADSL_QPROC_EN (1 << 1)
20 #define CKCTL_6328_ADSL_AFE_EN (1 << 2)
21 #define CKCTL_6328_ADSL_EN (1 << 3)
22 #define CKCTL_6328_MIPS_EN (1 << 4)
23 #define CKCTL_6328_SAR_EN (1 << 5)
24 #define CKCTL_6328_PCM_EN (1 << 6)
25 #define CKCTL_6328_USBD_EN (1 << 7)
26 #define CKCTL_6328_USBH_EN (1 << 8)
27 #define CKCTL_6328_HSSPI_EN (1 << 9)
28 #define CKCTL_6328_PCIE_EN (1 << 10)
29 #define CKCTL_6328_ROBOSW_EN (1 << 11)
31 #define CKCTL_6328_ALL_SAFE_EN (CKCTL_6328_PHYMIPS_EN | \
32 CKCTL_6328_ADSL_QPROC_EN | \
33 CKCTL_6328_ADSL_AFE_EN | \
34 CKCTL_6328_ADSL_EN | \
35 CKCTL_6328_SAR_EN | \
36 CKCTL_6328_PCM_EN | \
37 CKCTL_6328_USBD_EN | \
38 CKCTL_6328_USBH_EN | \
39 CKCTL_6328_ROBOSW_EN | \
40 CKCTL_6328_PCIE_EN)
42 #define CKCTL_6338_ADSLPHY_EN (1 << 0)
43 #define CKCTL_6338_MPI_EN (1 << 1)
44 #define CKCTL_6338_DRAM_EN (1 << 2)
45 #define CKCTL_6338_ENET_EN (1 << 4)
46 #define CKCTL_6338_USBS_EN (1 << 4)
47 #define CKCTL_6338_SAR_EN (1 << 5)
48 #define CKCTL_6338_SPI_EN (1 << 9)
50 #define CKCTL_6338_ALL_SAFE_EN (CKCTL_6338_ADSLPHY_EN | \
51 CKCTL_6338_MPI_EN | \
52 CKCTL_6338_ENET_EN | \
53 CKCTL_6338_SAR_EN | \
54 CKCTL_6338_SPI_EN)
56 #define CKCTL_6345_CPU_EN (1 << 0)
57 #define CKCTL_6345_BUS_EN (1 << 1)
58 #define CKCTL_6345_EBI_EN (1 << 2)
59 #define CKCTL_6345_UART_EN (1 << 3)
60 #define CKCTL_6345_ADSLPHY_EN (1 << 4)
61 #define CKCTL_6345_ENET_EN (1 << 7)
62 #define CKCTL_6345_USBH_EN (1 << 8)
64 #define CKCTL_6345_ALL_SAFE_EN (CKCTL_6345_ENET_EN | \
65 CKCTL_6345_USBH_EN | \
66 CKCTL_6345_ADSLPHY_EN)
68 #define CKCTL_6348_ADSLPHY_EN (1 << 0)
69 #define CKCTL_6348_MPI_EN (1 << 1)
70 #define CKCTL_6348_SDRAM_EN (1 << 2)
71 #define CKCTL_6348_M2M_EN (1 << 3)
72 #define CKCTL_6348_ENET_EN (1 << 4)
73 #define CKCTL_6348_SAR_EN (1 << 5)
74 #define CKCTL_6348_USBS_EN (1 << 6)
75 #define CKCTL_6348_USBH_EN (1 << 8)
76 #define CKCTL_6348_SPI_EN (1 << 9)
78 #define CKCTL_6348_ALL_SAFE_EN (CKCTL_6348_ADSLPHY_EN | \
79 CKCTL_6348_M2M_EN | \
80 CKCTL_6348_ENET_EN | \
81 CKCTL_6348_SAR_EN | \
82 CKCTL_6348_USBS_EN | \
83 CKCTL_6348_USBH_EN | \
84 CKCTL_6348_SPI_EN)
86 #define CKCTL_6358_ENET_EN (1 << 4)
87 #define CKCTL_6358_ADSLPHY_EN (1 << 5)
88 #define CKCTL_6358_PCM_EN (1 << 8)
89 #define CKCTL_6358_SPI_EN (1 << 9)
90 #define CKCTL_6358_USBS_EN (1 << 10)
91 #define CKCTL_6358_SAR_EN (1 << 11)
92 #define CKCTL_6358_EMUSB_EN (1 << 17)
93 #define CKCTL_6358_ENET0_EN (1 << 18)
94 #define CKCTL_6358_ENET1_EN (1 << 19)
95 #define CKCTL_6358_USBSU_EN (1 << 20)
96 #define CKCTL_6358_EPHY_EN (1 << 21)
98 #define CKCTL_6358_ALL_SAFE_EN (CKCTL_6358_ENET_EN | \
99 CKCTL_6358_ADSLPHY_EN | \
100 CKCTL_6358_PCM_EN | \
101 CKCTL_6358_SPI_EN | \
102 CKCTL_6358_USBS_EN | \
103 CKCTL_6358_SAR_EN | \
104 CKCTL_6358_EMUSB_EN | \
105 CKCTL_6358_ENET0_EN | \
106 CKCTL_6358_ENET1_EN | \
107 CKCTL_6358_USBSU_EN | \
108 CKCTL_6358_EPHY_EN)
110 #define CKCTL_6368_VDSL_QPROC_EN (1 << 2)
111 #define CKCTL_6368_VDSL_AFE_EN (1 << 3)
112 #define CKCTL_6368_VDSL_BONDING_EN (1 << 4)
113 #define CKCTL_6368_VDSL_EN (1 << 5)
114 #define CKCTL_6368_PHYMIPS_EN (1 << 6)
115 #define CKCTL_6368_SWPKT_USB_EN (1 << 7)
116 #define CKCTL_6368_SWPKT_SAR_EN (1 << 8)
117 #define CKCTL_6368_SPI_EN (1 << 9)
118 #define CKCTL_6368_USBD_EN (1 << 10)
119 #define CKCTL_6368_SAR_EN (1 << 11)
120 #define CKCTL_6368_ROBOSW_EN (1 << 12)
121 #define CKCTL_6368_UTOPIA_EN (1 << 13)
122 #define CKCTL_6368_PCM_EN (1 << 14)
123 #define CKCTL_6368_USBH_EN (1 << 15)
124 #define CKCTL_6368_DISABLE_GLESS_EN (1 << 16)
125 #define CKCTL_6368_NAND_EN (1 << 17)
126 #define CKCTL_6368_IPSEC_EN (1 << 18)
128 #define CKCTL_6368_ALL_SAFE_EN (CKCTL_6368_SWPKT_USB_EN | \
129 CKCTL_6368_SWPKT_SAR_EN | \
130 CKCTL_6368_SPI_EN | \
131 CKCTL_6368_USBD_EN | \
132 CKCTL_6368_SAR_EN | \
133 CKCTL_6368_ROBOSW_EN | \
134 CKCTL_6368_UTOPIA_EN | \
135 CKCTL_6368_PCM_EN | \
136 CKCTL_6368_USBH_EN | \
137 CKCTL_6368_DISABLE_GLESS_EN | \
138 CKCTL_6368_NAND_EN | \
139 CKCTL_6368_IPSEC_EN)
141 /* System PLL Control register */
142 #define PERF_SYS_PLL_CTL_REG 0x8
143 #define SYS_PLL_SOFT_RESET 0x1
145 /* Interrupt Mask register */
146 #define PERF_IRQMASK_6328_REG 0x20
147 #define PERF_IRQMASK_6338_REG 0xc
148 #define PERF_IRQMASK_6345_REG 0xc
149 #define PERF_IRQMASK_6348_REG 0xc
150 #define PERF_IRQMASK_6358_REG 0xc
151 #define PERF_IRQMASK_6368_REG 0x20
153 /* Interrupt Status register */
154 #define PERF_IRQSTAT_6328_REG 0x28
155 #define PERF_IRQSTAT_6338_REG 0x10
156 #define PERF_IRQSTAT_6345_REG 0x10
157 #define PERF_IRQSTAT_6348_REG 0x10
158 #define PERF_IRQSTAT_6358_REG 0x10
159 #define PERF_IRQSTAT_6368_REG 0x28
161 /* External Interrupt Configuration register */
162 #define PERF_EXTIRQ_CFG_REG_6328 0x18
163 #define PERF_EXTIRQ_CFG_REG_6338 0x14
164 #define PERF_EXTIRQ_CFG_REG_6348 0x14
165 #define PERF_EXTIRQ_CFG_REG_6358 0x14
166 #define PERF_EXTIRQ_CFG_REG_6368 0x18
168 #define PERF_EXTIRQ_CFG_REG2_6368 0x1c
170 /* for 6348 only */
171 #define EXTIRQ_CFG_SENSE_6348(x) (1 << (x))
172 #define EXTIRQ_CFG_STAT_6348(x) (1 << (x + 5))
173 #define EXTIRQ_CFG_CLEAR_6348(x) (1 << (x + 10))
174 #define EXTIRQ_CFG_MASK_6348(x) (1 << (x + 15))
175 #define EXTIRQ_CFG_BOTHEDGE_6348(x) (1 << (x + 20))
176 #define EXTIRQ_CFG_LEVELSENSE_6348(x) (1 << (x + 25))
177 #define EXTIRQ_CFG_CLEAR_ALL_6348 (0xf << 10)
178 #define EXTIRQ_CFG_MASK_ALL_6348 (0xf << 15)
180 /* for all others */
181 #define EXTIRQ_CFG_SENSE(x) (1 << (x))
182 #define EXTIRQ_CFG_STAT(x) (1 << (x + 4))
183 #define EXTIRQ_CFG_CLEAR(x) (1 << (x + 8))
184 #define EXTIRQ_CFG_MASK(x) (1 << (x + 12))
185 #define EXTIRQ_CFG_BOTHEDGE(x) (1 << (x + 16))
186 #define EXTIRQ_CFG_LEVELSENSE(x) (1 << (x + 20))
187 #define EXTIRQ_CFG_CLEAR_ALL (0xf << 8)
188 #define EXTIRQ_CFG_MASK_ALL (0xf << 12)
190 /* Soft Reset register */
191 #define PERF_SOFTRESET_REG 0x28
192 #define PERF_SOFTRESET_6328_REG 0x10
193 #define PERF_SOFTRESET_6368_REG 0x10
195 #define SOFTRESET_6328_SPI_MASK (1 << 0)
196 #define SOFTRESET_6328_EPHY_MASK (1 << 1)
197 #define SOFTRESET_6328_SAR_MASK (1 << 2)
198 #define SOFTRESET_6328_ENETSW_MASK (1 << 3)
199 #define SOFTRESET_6328_USBS_MASK (1 << 4)
200 #define SOFTRESET_6328_USBH_MASK (1 << 5)
201 #define SOFTRESET_6328_PCM_MASK (1 << 6)
202 #define SOFTRESET_6328_PCIE_CORE_MASK (1 << 7)
203 #define SOFTRESET_6328_PCIE_MASK (1 << 8)
204 #define SOFTRESET_6328_PCIE_EXT_MASK (1 << 9)
205 #define SOFTRESET_6328_PCIE_HARD_MASK (1 << 10)
207 #define SOFTRESET_6338_SPI_MASK (1 << 0)
208 #define SOFTRESET_6338_ENET_MASK (1 << 2)
209 #define SOFTRESET_6338_USBH_MASK (1 << 3)
210 #define SOFTRESET_6338_USBS_MASK (1 << 4)
211 #define SOFTRESET_6338_ADSL_MASK (1 << 5)
212 #define SOFTRESET_6338_DMAMEM_MASK (1 << 6)
213 #define SOFTRESET_6338_SAR_MASK (1 << 7)
214 #define SOFTRESET_6338_ACLC_MASK (1 << 8)
215 #define SOFTRESET_6338_ADSLMIPSPLL_MASK (1 << 10)
216 #define SOFTRESET_6338_ALL (SOFTRESET_6338_SPI_MASK | \
217 SOFTRESET_6338_ENET_MASK | \
218 SOFTRESET_6338_USBH_MASK | \
219 SOFTRESET_6338_USBS_MASK | \
220 SOFTRESET_6338_ADSL_MASK | \
221 SOFTRESET_6338_DMAMEM_MASK | \
222 SOFTRESET_6338_SAR_MASK | \
223 SOFTRESET_6338_ACLC_MASK | \
224 SOFTRESET_6338_ADSLMIPSPLL_MASK)
226 #define SOFTRESET_6348_SPI_MASK (1 << 0)
227 #define SOFTRESET_6348_ENET_MASK (1 << 2)
228 #define SOFTRESET_6348_USBH_MASK (1 << 3)
229 #define SOFTRESET_6348_USBS_MASK (1 << 4)
230 #define SOFTRESET_6348_ADSL_MASK (1 << 5)
231 #define SOFTRESET_6348_DMAMEM_MASK (1 << 6)
232 #define SOFTRESET_6348_SAR_MASK (1 << 7)
233 #define SOFTRESET_6348_ACLC_MASK (1 << 8)
234 #define SOFTRESET_6348_ADSLMIPSPLL_MASK (1 << 10)
236 #define SOFTRESET_6348_ALL (SOFTRESET_6348_SPI_MASK | \
237 SOFTRESET_6348_ENET_MASK | \
238 SOFTRESET_6348_USBH_MASK | \
239 SOFTRESET_6348_USBS_MASK | \
240 SOFTRESET_6348_ADSL_MASK | \
241 SOFTRESET_6348_DMAMEM_MASK | \
242 SOFTRESET_6348_SAR_MASK | \
243 SOFTRESET_6348_ACLC_MASK | \
244 SOFTRESET_6348_ADSLMIPSPLL_MASK)
246 #define SOFTRESET_6368_SPI_MASK (1 << 0)
247 #define SOFTRESET_6368_MPI_MASK (1 << 3)
248 #define SOFTRESET_6368_EPHY_MASK (1 << 6)
249 #define SOFTRESET_6368_SAR_MASK (1 << 7)
250 #define SOFTRESET_6368_ENETSW_MASK (1 << 10)
251 #define SOFTRESET_6368_USBS_MASK (1 << 11)
252 #define SOFTRESET_6368_USBH_MASK (1 << 12)
253 #define SOFTRESET_6368_PCM_MASK (1 << 13)
255 /* MIPS PLL control register */
256 #define PERF_MIPSPLLCTL_REG 0x34
257 #define MIPSPLLCTL_N1_SHIFT 20
258 #define MIPSPLLCTL_N1_MASK (0x7 << MIPSPLLCTL_N1_SHIFT)
259 #define MIPSPLLCTL_N2_SHIFT 15
260 #define MIPSPLLCTL_N2_MASK (0x1f << MIPSPLLCTL_N2_SHIFT)
261 #define MIPSPLLCTL_M1REF_SHIFT 12
262 #define MIPSPLLCTL_M1REF_MASK (0x7 << MIPSPLLCTL_M1REF_SHIFT)
263 #define MIPSPLLCTL_M2REF_SHIFT 9
264 #define MIPSPLLCTL_M2REF_MASK (0x7 << MIPSPLLCTL_M2REF_SHIFT)
265 #define MIPSPLLCTL_M1CPU_SHIFT 6
266 #define MIPSPLLCTL_M1CPU_MASK (0x7 << MIPSPLLCTL_M1CPU_SHIFT)
267 #define MIPSPLLCTL_M1BUS_SHIFT 3
268 #define MIPSPLLCTL_M1BUS_MASK (0x7 << MIPSPLLCTL_M1BUS_SHIFT)
269 #define MIPSPLLCTL_M2BUS_SHIFT 0
270 #define MIPSPLLCTL_M2BUS_MASK (0x7 << MIPSPLLCTL_M2BUS_SHIFT)
272 /* ADSL PHY PLL Control register */
273 #define PERF_ADSLPLLCTL_REG 0x38
274 #define ADSLPLLCTL_N1_SHIFT 20
275 #define ADSLPLLCTL_N1_MASK (0x7 << ADSLPLLCTL_N1_SHIFT)
276 #define ADSLPLLCTL_N2_SHIFT 15
277 #define ADSLPLLCTL_N2_MASK (0x1f << ADSLPLLCTL_N2_SHIFT)
278 #define ADSLPLLCTL_M1REF_SHIFT 12
279 #define ADSLPLLCTL_M1REF_MASK (0x7 << ADSLPLLCTL_M1REF_SHIFT)
280 #define ADSLPLLCTL_M2REF_SHIFT 9
281 #define ADSLPLLCTL_M2REF_MASK (0x7 << ADSLPLLCTL_M2REF_SHIFT)
282 #define ADSLPLLCTL_M1CPU_SHIFT 6
283 #define ADSLPLLCTL_M1CPU_MASK (0x7 << ADSLPLLCTL_M1CPU_SHIFT)
284 #define ADSLPLLCTL_M1BUS_SHIFT 3
285 #define ADSLPLLCTL_M1BUS_MASK (0x7 << ADSLPLLCTL_M1BUS_SHIFT)
286 #define ADSLPLLCTL_M2BUS_SHIFT 0
287 #define ADSLPLLCTL_M2BUS_MASK (0x7 << ADSLPLLCTL_M2BUS_SHIFT)
289 #define ADSLPLLCTL_VAL(n1, n2, m1ref, m2ref, m1cpu, m1bus, m2bus) \
290 (((n1) << ADSLPLLCTL_N1_SHIFT) | \
291 ((n2) << ADSLPLLCTL_N2_SHIFT) | \
292 ((m1ref) << ADSLPLLCTL_M1REF_SHIFT) | \
293 ((m2ref) << ADSLPLLCTL_M2REF_SHIFT) | \
294 ((m1cpu) << ADSLPLLCTL_M1CPU_SHIFT) | \
295 ((m1bus) << ADSLPLLCTL_M1BUS_SHIFT) | \
296 ((m2bus) << ADSLPLLCTL_M2BUS_SHIFT))
299 /*************************************************************************
300 * _REG relative to RSET_TIMER
301 *************************************************************************/
303 #define BCM63XX_TIMER_COUNT 4
304 #define TIMER_T0_ID 0
305 #define TIMER_T1_ID 1
306 #define TIMER_T2_ID 2
307 #define TIMER_WDT_ID 3
309 /* Timer irqstat register */
310 #define TIMER_IRQSTAT_REG 0
311 #define TIMER_IRQSTAT_TIMER_CAUSE(x) (1 << (x))
312 #define TIMER_IRQSTAT_TIMER0_CAUSE (1 << 0)
313 #define TIMER_IRQSTAT_TIMER1_CAUSE (1 << 1)
314 #define TIMER_IRQSTAT_TIMER2_CAUSE (1 << 2)
315 #define TIMER_IRQSTAT_WDT_CAUSE (1 << 3)
316 #define TIMER_IRQSTAT_TIMER_IR_EN(x) (1 << ((x) + 8))
317 #define TIMER_IRQSTAT_TIMER0_IR_EN (1 << 8)
318 #define TIMER_IRQSTAT_TIMER1_IR_EN (1 << 9)
319 #define TIMER_IRQSTAT_TIMER2_IR_EN (1 << 10)
321 /* Timer control register */
322 #define TIMER_CTLx_REG(x) (0x4 + (x * 4))
323 #define TIMER_CTL0_REG 0x4
324 #define TIMER_CTL1_REG 0x8
325 #define TIMER_CTL2_REG 0xC
326 #define TIMER_CTL_COUNTDOWN_MASK (0x3fffffff)
327 #define TIMER_CTL_MONOTONIC_MASK (1 << 30)
328 #define TIMER_CTL_ENABLE_MASK (1 << 31)
331 /*************************************************************************
332 * _REG relative to RSET_WDT
333 *************************************************************************/
335 /* Watchdog default count register */
336 #define WDT_DEFVAL_REG 0x0
338 /* Watchdog control register */
339 #define WDT_CTL_REG 0x4
341 /* Watchdog control register constants */
342 #define WDT_START_1 (0xff00)
343 #define WDT_START_2 (0x00ff)
344 #define WDT_STOP_1 (0xee00)
345 #define WDT_STOP_2 (0x00ee)
347 /* Watchdog reset length register */
348 #define WDT_RSTLEN_REG 0x8
350 /* Watchdog soft reset register (BCM6328 only) */
351 #define WDT_SOFTRESET_REG 0xc
353 /*************************************************************************
354 * _REG relative to RSET_UARTx
355 *************************************************************************/
357 /* UART Control Register */
358 #define UART_CTL_REG 0x0
359 #define UART_CTL_RXTMOUTCNT_SHIFT 0
360 #define UART_CTL_RXTMOUTCNT_MASK (0x1f << UART_CTL_RXTMOUTCNT_SHIFT)
361 #define UART_CTL_RSTTXDN_SHIFT 5
362 #define UART_CTL_RSTTXDN_MASK (1 << UART_CTL_RSTTXDN_SHIFT)
363 #define UART_CTL_RSTRXFIFO_SHIFT 6
364 #define UART_CTL_RSTRXFIFO_MASK (1 << UART_CTL_RSTRXFIFO_SHIFT)
365 #define UART_CTL_RSTTXFIFO_SHIFT 7
366 #define UART_CTL_RSTTXFIFO_MASK (1 << UART_CTL_RSTTXFIFO_SHIFT)
367 #define UART_CTL_STOPBITS_SHIFT 8
368 #define UART_CTL_STOPBITS_MASK (0xf << UART_CTL_STOPBITS_SHIFT)
369 #define UART_CTL_STOPBITS_1 (0x7 << UART_CTL_STOPBITS_SHIFT)
370 #define UART_CTL_STOPBITS_2 (0xf << UART_CTL_STOPBITS_SHIFT)
371 #define UART_CTL_BITSPERSYM_SHIFT 12
372 #define UART_CTL_BITSPERSYM_MASK (0x3 << UART_CTL_BITSPERSYM_SHIFT)
373 #define UART_CTL_XMITBRK_SHIFT 14
374 #define UART_CTL_XMITBRK_MASK (1 << UART_CTL_XMITBRK_SHIFT)
375 #define UART_CTL_RSVD_SHIFT 15
376 #define UART_CTL_RSVD_MASK (1 << UART_CTL_RSVD_SHIFT)
377 #define UART_CTL_RXPAREVEN_SHIFT 16
378 #define UART_CTL_RXPAREVEN_MASK (1 << UART_CTL_RXPAREVEN_SHIFT)
379 #define UART_CTL_RXPAREN_SHIFT 17
380 #define UART_CTL_RXPAREN_MASK (1 << UART_CTL_RXPAREN_SHIFT)
381 #define UART_CTL_TXPAREVEN_SHIFT 18
382 #define UART_CTL_TXPAREVEN_MASK (1 << UART_CTL_TXPAREVEN_SHIFT)
383 #define UART_CTL_TXPAREN_SHIFT 18
384 #define UART_CTL_TXPAREN_MASK (1 << UART_CTL_TXPAREN_SHIFT)
385 #define UART_CTL_LOOPBACK_SHIFT 20
386 #define UART_CTL_LOOPBACK_MASK (1 << UART_CTL_LOOPBACK_SHIFT)
387 #define UART_CTL_RXEN_SHIFT 21
388 #define UART_CTL_RXEN_MASK (1 << UART_CTL_RXEN_SHIFT)
389 #define UART_CTL_TXEN_SHIFT 22
390 #define UART_CTL_TXEN_MASK (1 << UART_CTL_TXEN_SHIFT)
391 #define UART_CTL_BRGEN_SHIFT 23
392 #define UART_CTL_BRGEN_MASK (1 << UART_CTL_BRGEN_SHIFT)
394 /* UART Baudword register */
395 #define UART_BAUD_REG 0x4
397 /* UART Misc Control register */
398 #define UART_MCTL_REG 0x8
399 #define UART_MCTL_DTR_SHIFT 0
400 #define UART_MCTL_DTR_MASK (1 << UART_MCTL_DTR_SHIFT)
401 #define UART_MCTL_RTS_SHIFT 1
402 #define UART_MCTL_RTS_MASK (1 << UART_MCTL_RTS_SHIFT)
403 #define UART_MCTL_RXFIFOTHRESH_SHIFT 8
404 #define UART_MCTL_RXFIFOTHRESH_MASK (0xf << UART_MCTL_RXFIFOTHRESH_SHIFT)
405 #define UART_MCTL_TXFIFOTHRESH_SHIFT 12
406 #define UART_MCTL_TXFIFOTHRESH_MASK (0xf << UART_MCTL_TXFIFOTHRESH_SHIFT)
407 #define UART_MCTL_RXFIFOFILL_SHIFT 16
408 #define UART_MCTL_RXFIFOFILL_MASK (0x1f << UART_MCTL_RXFIFOFILL_SHIFT)
409 #define UART_MCTL_TXFIFOFILL_SHIFT 24
410 #define UART_MCTL_TXFIFOFILL_MASK (0x1f << UART_MCTL_TXFIFOFILL_SHIFT)
412 /* UART External Input Configuration register */
413 #define UART_EXTINP_REG 0xc
414 #define UART_EXTINP_RI_SHIFT 0
415 #define UART_EXTINP_RI_MASK (1 << UART_EXTINP_RI_SHIFT)
416 #define UART_EXTINP_CTS_SHIFT 1
417 #define UART_EXTINP_CTS_MASK (1 << UART_EXTINP_CTS_SHIFT)
418 #define UART_EXTINP_DCD_SHIFT 2
419 #define UART_EXTINP_DCD_MASK (1 << UART_EXTINP_DCD_SHIFT)
420 #define UART_EXTINP_DSR_SHIFT 3
421 #define UART_EXTINP_DSR_MASK (1 << UART_EXTINP_DSR_SHIFT)
422 #define UART_EXTINP_IRSTAT(x) (1 << (x + 4))
423 #define UART_EXTINP_IRMASK(x) (1 << (x + 8))
424 #define UART_EXTINP_IR_RI 0
425 #define UART_EXTINP_IR_CTS 1
426 #define UART_EXTINP_IR_DCD 2
427 #define UART_EXTINP_IR_DSR 3
428 #define UART_EXTINP_RI_NOSENSE_SHIFT 16
429 #define UART_EXTINP_RI_NOSENSE_MASK (1 << UART_EXTINP_RI_NOSENSE_SHIFT)
430 #define UART_EXTINP_CTS_NOSENSE_SHIFT 17
431 #define UART_EXTINP_CTS_NOSENSE_MASK (1 << UART_EXTINP_CTS_NOSENSE_SHIFT)
432 #define UART_EXTINP_DCD_NOSENSE_SHIFT 18
433 #define UART_EXTINP_DCD_NOSENSE_MASK (1 << UART_EXTINP_DCD_NOSENSE_SHIFT)
434 #define UART_EXTINP_DSR_NOSENSE_SHIFT 19
435 #define UART_EXTINP_DSR_NOSENSE_MASK (1 << UART_EXTINP_DSR_NOSENSE_SHIFT)
437 /* UART Interrupt register */
438 #define UART_IR_REG 0x10
439 #define UART_IR_MASK(x) (1 << (x + 16))
440 #define UART_IR_STAT(x) (1 << (x))
441 #define UART_IR_EXTIP 0
442 #define UART_IR_TXUNDER 1
443 #define UART_IR_TXOVER 2
444 #define UART_IR_TXTRESH 3
445 #define UART_IR_TXRDLATCH 4
446 #define UART_IR_TXEMPTY 5
447 #define UART_IR_RXUNDER 6
448 #define UART_IR_RXOVER 7
449 #define UART_IR_RXTIMEOUT 8
450 #define UART_IR_RXFULL 9
451 #define UART_IR_RXTHRESH 10
452 #define UART_IR_RXNOTEMPTY 11
453 #define UART_IR_RXFRAMEERR 12
454 #define UART_IR_RXPARERR 13
455 #define UART_IR_RXBRK 14
456 #define UART_IR_TXDONE 15
458 /* UART Fifo register */
459 #define UART_FIFO_REG 0x14
460 #define UART_FIFO_VALID_SHIFT 0
461 #define UART_FIFO_VALID_MASK 0xff
462 #define UART_FIFO_FRAMEERR_SHIFT 8
463 #define UART_FIFO_FRAMEERR_MASK (1 << UART_FIFO_FRAMEERR_SHIFT)
464 #define UART_FIFO_PARERR_SHIFT 9
465 #define UART_FIFO_PARERR_MASK (1 << UART_FIFO_PARERR_SHIFT)
466 #define UART_FIFO_BRKDET_SHIFT 10
467 #define UART_FIFO_BRKDET_MASK (1 << UART_FIFO_BRKDET_SHIFT)
468 #define UART_FIFO_ANYERR_MASK (UART_FIFO_FRAMEERR_MASK | \
469 UART_FIFO_PARERR_MASK | \
470 UART_FIFO_BRKDET_MASK)
473 /*************************************************************************
474 * _REG relative to RSET_GPIO
475 *************************************************************************/
477 /* GPIO registers */
478 #define GPIO_CTL_HI_REG 0x0
479 #define GPIO_CTL_LO_REG 0x4
480 #define GPIO_DATA_HI_REG 0x8
481 #define GPIO_DATA_LO_REG 0xC
482 #define GPIO_DATA_LO_REG_6345 0x8
484 /* GPIO mux registers and constants */
485 #define GPIO_MODE_REG 0x18
487 #define GPIO_MODE_6348_G4_DIAG 0x00090000
488 #define GPIO_MODE_6348_G4_UTOPIA 0x00080000
489 #define GPIO_MODE_6348_G4_LEGACY_LED 0x00030000
490 #define GPIO_MODE_6348_G4_MII_SNOOP 0x00020000
491 #define GPIO_MODE_6348_G4_EXT_EPHY 0x00010000
492 #define GPIO_MODE_6348_G3_DIAG 0x00009000
493 #define GPIO_MODE_6348_G3_UTOPIA 0x00008000
494 #define GPIO_MODE_6348_G3_EXT_MII 0x00007000
495 #define GPIO_MODE_6348_G2_DIAG 0x00000900
496 #define GPIO_MODE_6348_G2_PCI 0x00000500
497 #define GPIO_MODE_6348_G1_DIAG 0x00000090
498 #define GPIO_MODE_6348_G1_UTOPIA 0x00000080
499 #define GPIO_MODE_6348_G1_SPI_UART 0x00000060
500 #define GPIO_MODE_6348_G1_SPI_MASTER 0x00000060
501 #define GPIO_MODE_6348_G1_MII_PCCARD 0x00000040
502 #define GPIO_MODE_6348_G1_MII_SNOOP 0x00000020
503 #define GPIO_MODE_6348_G1_EXT_EPHY 0x00000010
504 #define GPIO_MODE_6348_G0_DIAG 0x00000009
505 #define GPIO_MODE_6348_G0_EXT_MII 0x00000007
507 #define GPIO_MODE_6358_EXTRACS (1 << 5)
508 #define GPIO_MODE_6358_UART1 (1 << 6)
509 #define GPIO_MODE_6358_EXTRA_SPI_SS (1 << 7)
510 #define GPIO_MODE_6358_SERIAL_LED (1 << 10)
511 #define GPIO_MODE_6358_UTOPIA (1 << 12)
513 #define GPIO_MODE_6368_ANALOG_AFE_0 (1 << 0)
514 #define GPIO_MODE_6368_ANALOG_AFE_1 (1 << 1)
515 #define GPIO_MODE_6368_SYS_IRQ (1 << 2)
516 #define GPIO_MODE_6368_SERIAL_LED_DATA (1 << 3)
517 #define GPIO_MODE_6368_SERIAL_LED_CLK (1 << 4)
518 #define GPIO_MODE_6368_INET_LED (1 << 5)
519 #define GPIO_MODE_6368_EPHY0_LED (1 << 6)
520 #define GPIO_MODE_6368_EPHY1_LED (1 << 7)
521 #define GPIO_MODE_6368_EPHY2_LED (1 << 8)
522 #define GPIO_MODE_6368_EPHY3_LED (1 << 9)
523 #define GPIO_MODE_6368_ROBOSW_LED_DAT (1 << 10)
524 #define GPIO_MODE_6368_ROBOSW_LED_CLK (1 << 11)
525 #define GPIO_MODE_6368_ROBOSW_LED0 (1 << 12)
526 #define GPIO_MODE_6368_ROBOSW_LED1 (1 << 13)
527 #define GPIO_MODE_6368_USBD_LED (1 << 14)
528 #define GPIO_MODE_6368_NTR_PULSE (1 << 15)
529 #define GPIO_MODE_6368_PCI_REQ1 (1 << 16)
530 #define GPIO_MODE_6368_PCI_GNT1 (1 << 17)
531 #define GPIO_MODE_6368_PCI_INTB (1 << 18)
532 #define GPIO_MODE_6368_PCI_REQ0 (1 << 19)
533 #define GPIO_MODE_6368_PCI_GNT0 (1 << 20)
534 #define GPIO_MODE_6368_PCMCIA_CD1 (1 << 22)
535 #define GPIO_MODE_6368_PCMCIA_CD2 (1 << 23)
536 #define GPIO_MODE_6368_PCMCIA_VS1 (1 << 24)
537 #define GPIO_MODE_6368_PCMCIA_VS2 (1 << 25)
538 #define GPIO_MODE_6368_EBI_CS2 (1 << 26)
539 #define GPIO_MODE_6368_EBI_CS3 (1 << 27)
540 #define GPIO_MODE_6368_SPI_SSN2 (1 << 28)
541 #define GPIO_MODE_6368_SPI_SSN3 (1 << 29)
542 #define GPIO_MODE_6368_SPI_SSN4 (1 << 30)
543 #define GPIO_MODE_6368_SPI_SSN5 (1 << 31)
546 #define GPIO_BASEMODE_6368_REG 0x38
547 #define GPIO_BASEMODE_6368_UART2 0x1
548 #define GPIO_BASEMODE_6368_GPIO 0x0
549 #define GPIO_BASEMODE_6368_MASK 0x7
550 /* those bits must be kept as read in gpio basemode register*/
552 #define GPIO_STRAPBUS_REG 0x40
553 #define STRAPBUS_6358_BOOT_SEL_PARALLEL (1 << 1)
554 #define STRAPBUS_6358_BOOT_SEL_SERIAL (0 << 1)
555 #define STRAPBUS_6368_BOOT_SEL_MASK 0x3
556 #define STRAPBUS_6368_BOOT_SEL_NAND 0
557 #define STRAPBUS_6368_BOOT_SEL_SERIAL 1
558 #define STRAPBUS_6368_BOOT_SEL_PARALLEL 3
561 /*************************************************************************
562 * _REG relative to RSET_ENET
563 *************************************************************************/
565 /* Receiver Configuration register */
566 #define ENET_RXCFG_REG 0x0
567 #define ENET_RXCFG_ALLMCAST_SHIFT 1
568 #define ENET_RXCFG_ALLMCAST_MASK (1 << ENET_RXCFG_ALLMCAST_SHIFT)
569 #define ENET_RXCFG_PROMISC_SHIFT 3
570 #define ENET_RXCFG_PROMISC_MASK (1 << ENET_RXCFG_PROMISC_SHIFT)
571 #define ENET_RXCFG_LOOPBACK_SHIFT 4
572 #define ENET_RXCFG_LOOPBACK_MASK (1 << ENET_RXCFG_LOOPBACK_SHIFT)
573 #define ENET_RXCFG_ENFLOW_SHIFT 5
574 #define ENET_RXCFG_ENFLOW_MASK (1 << ENET_RXCFG_ENFLOW_SHIFT)
576 /* Receive Maximum Length register */
577 #define ENET_RXMAXLEN_REG 0x4
578 #define ENET_RXMAXLEN_SHIFT 0
579 #define ENET_RXMAXLEN_MASK (0x7ff << ENET_RXMAXLEN_SHIFT)
581 /* Transmit Maximum Length register */
582 #define ENET_TXMAXLEN_REG 0x8
583 #define ENET_TXMAXLEN_SHIFT 0
584 #define ENET_TXMAXLEN_MASK (0x7ff << ENET_TXMAXLEN_SHIFT)
586 /* MII Status/Control register */
587 #define ENET_MIISC_REG 0x10
588 #define ENET_MIISC_MDCFREQDIV_SHIFT 0
589 #define ENET_MIISC_MDCFREQDIV_MASK (0x7f << ENET_MIISC_MDCFREQDIV_SHIFT)
590 #define ENET_MIISC_PREAMBLEEN_SHIFT 7
591 #define ENET_MIISC_PREAMBLEEN_MASK (1 << ENET_MIISC_PREAMBLEEN_SHIFT)
593 /* MII Data register */
594 #define ENET_MIIDATA_REG 0x14
595 #define ENET_MIIDATA_DATA_SHIFT 0
596 #define ENET_MIIDATA_DATA_MASK (0xffff << ENET_MIIDATA_DATA_SHIFT)
597 #define ENET_MIIDATA_TA_SHIFT 16
598 #define ENET_MIIDATA_TA_MASK (0x3 << ENET_MIIDATA_TA_SHIFT)
599 #define ENET_MIIDATA_REG_SHIFT 18
600 #define ENET_MIIDATA_REG_MASK (0x1f << ENET_MIIDATA_REG_SHIFT)
601 #define ENET_MIIDATA_PHYID_SHIFT 23
602 #define ENET_MIIDATA_PHYID_MASK (0x1f << ENET_MIIDATA_PHYID_SHIFT)
603 #define ENET_MIIDATA_OP_READ_MASK (0x6 << 28)
604 #define ENET_MIIDATA_OP_WRITE_MASK (0x5 << 28)
606 /* Ethernet Interrupt Mask register */
607 #define ENET_IRMASK_REG 0x18
609 /* Ethernet Interrupt register */
610 #define ENET_IR_REG 0x1c
611 #define ENET_IR_MII (1 << 0)
612 #define ENET_IR_MIB (1 << 1)
613 #define ENET_IR_FLOWC (1 << 2)
615 /* Ethernet Control register */
616 #define ENET_CTL_REG 0x2c
617 #define ENET_CTL_ENABLE_SHIFT 0
618 #define ENET_CTL_ENABLE_MASK (1 << ENET_CTL_ENABLE_SHIFT)
619 #define ENET_CTL_DISABLE_SHIFT 1
620 #define ENET_CTL_DISABLE_MASK (1 << ENET_CTL_DISABLE_SHIFT)
621 #define ENET_CTL_SRESET_SHIFT 2
622 #define ENET_CTL_SRESET_MASK (1 << ENET_CTL_SRESET_SHIFT)
623 #define ENET_CTL_EPHYSEL_SHIFT 3
624 #define ENET_CTL_EPHYSEL_MASK (1 << ENET_CTL_EPHYSEL_SHIFT)
626 /* Transmit Control register */
627 #define ENET_TXCTL_REG 0x30
628 #define ENET_TXCTL_FD_SHIFT 0
629 #define ENET_TXCTL_FD_MASK (1 << ENET_TXCTL_FD_SHIFT)
631 /* Transmit Watermask register */
632 #define ENET_TXWMARK_REG 0x34
633 #define ENET_TXWMARK_WM_SHIFT 0
634 #define ENET_TXWMARK_WM_MASK (0x3f << ENET_TXWMARK_WM_SHIFT)
636 /* MIB Control register */
637 #define ENET_MIBCTL_REG 0x38
638 #define ENET_MIBCTL_RDCLEAR_SHIFT 0
639 #define ENET_MIBCTL_RDCLEAR_MASK (1 << ENET_MIBCTL_RDCLEAR_SHIFT)
641 /* Perfect Match Data Low register */
642 #define ENET_PML_REG(x) (0x58 + (x) * 8)
643 #define ENET_PMH_REG(x) (0x5c + (x) * 8)
644 #define ENET_PMH_DATAVALID_SHIFT 16
645 #define ENET_PMH_DATAVALID_MASK (1 << ENET_PMH_DATAVALID_SHIFT)
647 /* MIB register */
648 #define ENET_MIB_REG(x) (0x200 + (x) * 4)
649 #define ENET_MIB_REG_COUNT 55
652 /*************************************************************************
653 * _REG relative to RSET_ENETDMA
654 *************************************************************************/
656 /* Controller Configuration Register */
657 #define ENETDMA_CFG_REG (0x0)
658 #define ENETDMA_CFG_EN_SHIFT 0
659 #define ENETDMA_CFG_EN_MASK (1 << ENETDMA_CFG_EN_SHIFT)
660 #define ENETDMA_CFG_FLOWCH_MASK(x) (1 << ((x >> 1) + 1))
662 /* Flow Control Descriptor Low Threshold register */
663 #define ENETDMA_FLOWCL_REG(x) (0x4 + (x) * 6)
665 /* Flow Control Descriptor High Threshold register */
666 #define ENETDMA_FLOWCH_REG(x) (0x8 + (x) * 6)
668 /* Flow Control Descriptor Buffer Alloca Threshold register */
669 #define ENETDMA_BUFALLOC_REG(x) (0xc + (x) * 6)
670 #define ENETDMA_BUFALLOC_FORCE_SHIFT 31
671 #define ENETDMA_BUFALLOC_FORCE_MASK (1 << ENETDMA_BUFALLOC_FORCE_SHIFT)
673 /* Channel Configuration register */
674 #define ENETDMA_CHANCFG_REG(x) (0x100 + (x) * 0x10)
675 #define ENETDMA_CHANCFG_EN_SHIFT 0
676 #define ENETDMA_CHANCFG_EN_MASK (1 << ENETDMA_CHANCFG_EN_SHIFT)
677 #define ENETDMA_CHANCFG_PKTHALT_SHIFT 1
678 #define ENETDMA_CHANCFG_PKTHALT_MASK (1 << ENETDMA_CHANCFG_PKTHALT_SHIFT)
680 /* Interrupt Control/Status register */
681 #define ENETDMA_IR_REG(x) (0x104 + (x) * 0x10)
682 #define ENETDMA_IR_BUFDONE_MASK (1 << 0)
683 #define ENETDMA_IR_PKTDONE_MASK (1 << 1)
684 #define ENETDMA_IR_NOTOWNER_MASK (1 << 2)
686 /* Interrupt Mask register */
687 #define ENETDMA_IRMASK_REG(x) (0x108 + (x) * 0x10)
689 /* Maximum Burst Length */
690 #define ENETDMA_MAXBURST_REG(x) (0x10C + (x) * 0x10)
692 /* Ring Start Address register */
693 #define ENETDMA_RSTART_REG(x) (0x200 + (x) * 0x10)
695 /* State Ram Word 2 */
696 #define ENETDMA_SRAM2_REG(x) (0x204 + (x) * 0x10)
698 /* State Ram Word 3 */
699 #define ENETDMA_SRAM3_REG(x) (0x208 + (x) * 0x10)
701 /* State Ram Word 4 */
702 #define ENETDMA_SRAM4_REG(x) (0x20c + (x) * 0x10)
705 /*************************************************************************
706 * _REG relative to RSET_ENETDMAC
707 *************************************************************************/
709 /* Channel Configuration register */
710 #define ENETDMAC_CHANCFG_REG(x) ((x) * 0x10)
711 #define ENETDMAC_CHANCFG_EN_SHIFT 0
712 #define ENETDMAC_CHANCFG_EN_MASK (1 << ENETDMA_CHANCFG_EN_SHIFT)
713 #define ENETDMAC_CHANCFG_PKTHALT_SHIFT 1
714 #define ENETDMAC_CHANCFG_PKTHALT_MASK (1 << ENETDMA_CHANCFG_PKTHALT_SHIFT)
716 /* Interrupt Control/Status register */
717 #define ENETDMAC_IR_REG(x) (0x4 + (x) * 0x10)
718 #define ENETDMAC_IR_BUFDONE_MASK (1 << 0)
719 #define ENETDMAC_IR_PKTDONE_MASK (1 << 1)
720 #define ENETDMAC_IR_NOTOWNER_MASK (1 << 2)
722 /* Interrupt Mask register */
723 #define ENETDMAC_IRMASK_REG(x) (0x8 + (x) * 0x10)
725 /* Maximum Burst Length */
726 #define ENETDMAC_MAXBURST_REG(x) (0xc + (x) * 0x10)
729 /*************************************************************************
730 * _REG relative to RSET_ENETDMAS
731 *************************************************************************/
733 /* Ring Start Address register */
734 #define ENETDMAS_RSTART_REG(x) ((x) * 0x10)
736 /* State Ram Word 2 */
737 #define ENETDMAS_SRAM2_REG(x) (0x4 + (x) * 0x10)
739 /* State Ram Word 3 */
740 #define ENETDMAS_SRAM3_REG(x) (0x8 + (x) * 0x10)
742 /* State Ram Word 4 */
743 #define ENETDMAS_SRAM4_REG(x) (0xc + (x) * 0x10)
746 /*************************************************************************
747 * _REG relative to RSET_ENETSW
748 *************************************************************************/
750 /* MIB register */
751 #define ENETSW_MIB_REG(x) (0x2800 + (x) * 4)
752 #define ENETSW_MIB_REG_COUNT 47
755 /*************************************************************************
756 * _REG relative to RSET_OHCI_PRIV
757 *************************************************************************/
759 #define OHCI_PRIV_REG 0x0
760 #define OHCI_PRIV_PORT1_HOST_SHIFT 0
761 #define OHCI_PRIV_PORT1_HOST_MASK (1 << OHCI_PRIV_PORT1_HOST_SHIFT)
762 #define OHCI_PRIV_REG_SWAP_SHIFT 3
763 #define OHCI_PRIV_REG_SWAP_MASK (1 << OHCI_PRIV_REG_SWAP_SHIFT)
766 /*************************************************************************
767 * _REG relative to RSET_USBH_PRIV
768 *************************************************************************/
770 #define USBH_PRIV_SWAP_6358_REG 0x0
771 #define USBH_PRIV_SWAP_6368_REG 0x1c
773 #define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT 4
774 #define USBH_PRIV_SWAP_EHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT)
775 #define USBH_PRIV_SWAP_EHCI_DATA_SHIFT 3
776 #define USBH_PRIV_SWAP_EHCI_DATA_MASK (1 << USBH_PRIV_SWAP_EHCI_DATA_SHIFT)
777 #define USBH_PRIV_SWAP_OHCI_ENDN_SHIFT 1
778 #define USBH_PRIV_SWAP_OHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_OHCI_ENDN_SHIFT)
779 #define USBH_PRIV_SWAP_OHCI_DATA_SHIFT 0
780 #define USBH_PRIV_SWAP_OHCI_DATA_MASK (1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT)
782 #define USBH_PRIV_TEST_6358_REG 0x24
783 #define USBH_PRIV_TEST_6368_REG 0x14
785 #define USBH_PRIV_SETUP_6368_REG 0x28
786 #define USBH_PRIV_SETUP_IOC_SHIFT 4
787 #define USBH_PRIV_SETUP_IOC_MASK (1 << USBH_PRIV_SETUP_IOC_SHIFT)
791 /*************************************************************************
792 * _REG relative to RSET_MPI
793 *************************************************************************/
795 /* well known (hard wired) chip select */
796 #define MPI_CS_PCMCIA_COMMON 4
797 #define MPI_CS_PCMCIA_ATTR 5
798 #define MPI_CS_PCMCIA_IO 6
800 /* Chip select base register */
801 #define MPI_CSBASE_REG(x) (0x0 + (x) * 8)
802 #define MPI_CSBASE_BASE_SHIFT 13
803 #define MPI_CSBASE_BASE_MASK (0x1ffff << MPI_CSBASE_BASE_SHIFT)
804 #define MPI_CSBASE_SIZE_SHIFT 0
805 #define MPI_CSBASE_SIZE_MASK (0xf << MPI_CSBASE_SIZE_SHIFT)
807 #define MPI_CSBASE_SIZE_8K 0
808 #define MPI_CSBASE_SIZE_16K 1
809 #define MPI_CSBASE_SIZE_32K 2
810 #define MPI_CSBASE_SIZE_64K 3
811 #define MPI_CSBASE_SIZE_128K 4
812 #define MPI_CSBASE_SIZE_256K 5
813 #define MPI_CSBASE_SIZE_512K 6
814 #define MPI_CSBASE_SIZE_1M 7
815 #define MPI_CSBASE_SIZE_2M 8
816 #define MPI_CSBASE_SIZE_4M 9
817 #define MPI_CSBASE_SIZE_8M 10
818 #define MPI_CSBASE_SIZE_16M 11
819 #define MPI_CSBASE_SIZE_32M 12
820 #define MPI_CSBASE_SIZE_64M 13
821 #define MPI_CSBASE_SIZE_128M 14
822 #define MPI_CSBASE_SIZE_256M 15
824 /* Chip select control register */
825 #define MPI_CSCTL_REG(x) (0x4 + (x) * 8)
826 #define MPI_CSCTL_ENABLE_MASK (1 << 0)
827 #define MPI_CSCTL_WAIT_SHIFT 1
828 #define MPI_CSCTL_WAIT_MASK (0x7 << MPI_CSCTL_WAIT_SHIFT)
829 #define MPI_CSCTL_DATA16_MASK (1 << 4)
830 #define MPI_CSCTL_SYNCMODE_MASK (1 << 7)
831 #define MPI_CSCTL_TSIZE_MASK (1 << 8)
832 #define MPI_CSCTL_ENDIANSWAP_MASK (1 << 10)
833 #define MPI_CSCTL_SETUP_SHIFT 16
834 #define MPI_CSCTL_SETUP_MASK (0xf << MPI_CSCTL_SETUP_SHIFT)
835 #define MPI_CSCTL_HOLD_SHIFT 20
836 #define MPI_CSCTL_HOLD_MASK (0xf << MPI_CSCTL_HOLD_SHIFT)
838 /* PCI registers */
839 #define MPI_SP0_RANGE_REG 0x100
840 #define MPI_SP0_REMAP_REG 0x104
841 #define MPI_SP0_REMAP_ENABLE_MASK (1 << 0)
842 #define MPI_SP1_RANGE_REG 0x10C
843 #define MPI_SP1_REMAP_REG 0x110
844 #define MPI_SP1_REMAP_ENABLE_MASK (1 << 0)
846 #define MPI_L2PCFG_REG 0x11C
847 #define MPI_L2PCFG_CFG_TYPE_SHIFT 0
848 #define MPI_L2PCFG_CFG_TYPE_MASK (0x3 << MPI_L2PCFG_CFG_TYPE_SHIFT)
849 #define MPI_L2PCFG_REG_SHIFT 2
850 #define MPI_L2PCFG_REG_MASK (0x3f << MPI_L2PCFG_REG_SHIFT)
851 #define MPI_L2PCFG_FUNC_SHIFT 8
852 #define MPI_L2PCFG_FUNC_MASK (0x7 << MPI_L2PCFG_FUNC_SHIFT)
853 #define MPI_L2PCFG_DEVNUM_SHIFT 11
854 #define MPI_L2PCFG_DEVNUM_MASK (0x1f << MPI_L2PCFG_DEVNUM_SHIFT)
855 #define MPI_L2PCFG_CFG_USEREG_MASK (1 << 30)
856 #define MPI_L2PCFG_CFG_SEL_MASK (1 << 31)
858 #define MPI_L2PMEMRANGE1_REG 0x120
859 #define MPI_L2PMEMBASE1_REG 0x124
860 #define MPI_L2PMEMREMAP1_REG 0x128
861 #define MPI_L2PMEMRANGE2_REG 0x12C
862 #define MPI_L2PMEMBASE2_REG 0x130
863 #define MPI_L2PMEMREMAP2_REG 0x134
864 #define MPI_L2PIORANGE_REG 0x138
865 #define MPI_L2PIOBASE_REG 0x13C
866 #define MPI_L2PIOREMAP_REG 0x140
867 #define MPI_L2P_BASE_MASK (0xffff8000)
868 #define MPI_L2PREMAP_ENABLED_MASK (1 << 0)
869 #define MPI_L2PREMAP_IS_CARDBUS_MASK (1 << 2)
871 #define MPI_PCIMODESEL_REG 0x144
872 #define MPI_PCIMODESEL_BAR1_NOSWAP_MASK (1 << 0)
873 #define MPI_PCIMODESEL_BAR2_NOSWAP_MASK (1 << 1)
874 #define MPI_PCIMODESEL_EXT_ARB_MASK (1 << 2)
875 #define MPI_PCIMODESEL_PREFETCH_SHIFT 4
876 #define MPI_PCIMODESEL_PREFETCH_MASK (0xf << MPI_PCIMODESEL_PREFETCH_SHIFT)
878 #define MPI_LOCBUSCTL_REG 0x14C
879 #define MPI_LOCBUSCTL_EN_PCI_GPIO_MASK (1 << 0)
880 #define MPI_LOCBUSCTL_U2P_NOSWAP_MASK (1 << 1)
882 #define MPI_LOCINT_REG 0x150
883 #define MPI_LOCINT_MASK(x) (1 << (x + 16))
884 #define MPI_LOCINT_STAT(x) (1 << (x))
885 #define MPI_LOCINT_DIR_FAILED 6
886 #define MPI_LOCINT_EXT_PCI_INT 7
887 #define MPI_LOCINT_SERR 8
888 #define MPI_LOCINT_CSERR 9
890 #define MPI_PCICFGCTL_REG 0x178
891 #define MPI_PCICFGCTL_CFGADDR_SHIFT 2
892 #define MPI_PCICFGCTL_CFGADDR_MASK (0x1f << MPI_PCICFGCTL_CFGADDR_SHIFT)
893 #define MPI_PCICFGCTL_WRITEEN_MASK (1 << 7)
895 #define MPI_PCICFGDATA_REG 0x17C
897 /* PCI host bridge custom register */
898 #define BCMPCI_REG_TIMERS 0x40
899 #define REG_TIMER_TRDY_SHIFT 0
900 #define REG_TIMER_TRDY_MASK (0xff << REG_TIMER_TRDY_SHIFT)
901 #define REG_TIMER_RETRY_SHIFT 8
902 #define REG_TIMER_RETRY_MASK (0xff << REG_TIMER_RETRY_SHIFT)
905 /*************************************************************************
906 * _REG relative to RSET_PCMCIA
907 *************************************************************************/
909 #define PCMCIA_C1_REG 0x0
910 #define PCMCIA_C1_CD1_MASK (1 << 0)
911 #define PCMCIA_C1_CD2_MASK (1 << 1)
912 #define PCMCIA_C1_VS1_MASK (1 << 2)
913 #define PCMCIA_C1_VS2_MASK (1 << 3)
914 #define PCMCIA_C1_VS1OE_MASK (1 << 6)
915 #define PCMCIA_C1_VS2OE_MASK (1 << 7)
916 #define PCMCIA_C1_CBIDSEL_SHIFT (8)
917 #define PCMCIA_C1_CBIDSEL_MASK (0x1f << PCMCIA_C1_CBIDSEL_SHIFT)
918 #define PCMCIA_C1_EN_PCMCIA_GPIO_MASK (1 << 13)
919 #define PCMCIA_C1_EN_PCMCIA_MASK (1 << 14)
920 #define PCMCIA_C1_EN_CARDBUS_MASK (1 << 15)
921 #define PCMCIA_C1_RESET_MASK (1 << 18)
923 #define PCMCIA_C2_REG 0x8
924 #define PCMCIA_C2_DATA16_MASK (1 << 0)
925 #define PCMCIA_C2_BYTESWAP_MASK (1 << 1)
926 #define PCMCIA_C2_RWCOUNT_SHIFT 2
927 #define PCMCIA_C2_RWCOUNT_MASK (0x3f << PCMCIA_C2_RWCOUNT_SHIFT)
928 #define PCMCIA_C2_INACTIVE_SHIFT 8
929 #define PCMCIA_C2_INACTIVE_MASK (0x3f << PCMCIA_C2_INACTIVE_SHIFT)
930 #define PCMCIA_C2_SETUP_SHIFT 16
931 #define PCMCIA_C2_SETUP_MASK (0x3f << PCMCIA_C2_SETUP_SHIFT)
932 #define PCMCIA_C2_HOLD_SHIFT 24
933 #define PCMCIA_C2_HOLD_MASK (0x3f << PCMCIA_C2_HOLD_SHIFT)
936 /*************************************************************************
937 * _REG relative to RSET_SDRAM
938 *************************************************************************/
940 #define SDRAM_CFG_REG 0x0
941 #define SDRAM_CFG_ROW_SHIFT 4
942 #define SDRAM_CFG_ROW_MASK (0x3 << SDRAM_CFG_ROW_SHIFT)
943 #define SDRAM_CFG_COL_SHIFT 6
944 #define SDRAM_CFG_COL_MASK (0x3 << SDRAM_CFG_COL_SHIFT)
945 #define SDRAM_CFG_32B_SHIFT 10
946 #define SDRAM_CFG_32B_MASK (1 << SDRAM_CFG_32B_SHIFT)
947 #define SDRAM_CFG_BANK_SHIFT 13
948 #define SDRAM_CFG_BANK_MASK (1 << SDRAM_CFG_BANK_SHIFT)
950 #define SDRAM_MBASE_REG 0xc
952 #define SDRAM_PRIO_REG 0x2C
953 #define SDRAM_PRIO_MIPS_SHIFT 29
954 #define SDRAM_PRIO_MIPS_MASK (1 << SDRAM_PRIO_MIPS_SHIFT)
955 #define SDRAM_PRIO_ADSL_SHIFT 30
956 #define SDRAM_PRIO_ADSL_MASK (1 << SDRAM_PRIO_ADSL_SHIFT)
957 #define SDRAM_PRIO_EN_SHIFT 31
958 #define SDRAM_PRIO_EN_MASK (1 << SDRAM_PRIO_EN_SHIFT)
961 /*************************************************************************
962 * _REG relative to RSET_MEMC
963 *************************************************************************/
965 #define MEMC_CFG_REG 0x4
966 #define MEMC_CFG_32B_SHIFT 1
967 #define MEMC_CFG_32B_MASK (1 << MEMC_CFG_32B_SHIFT)
968 #define MEMC_CFG_COL_SHIFT 3
969 #define MEMC_CFG_COL_MASK (0x3 << MEMC_CFG_COL_SHIFT)
970 #define MEMC_CFG_ROW_SHIFT 6
971 #define MEMC_CFG_ROW_MASK (0x3 << MEMC_CFG_ROW_SHIFT)
974 /*************************************************************************
975 * _REG relative to RSET_DDR
976 *************************************************************************/
978 #define DDR_CSEND_REG 0x8
980 #define DDR_DMIPSPLLCFG_REG 0x18
981 #define DMIPSPLLCFG_M1_SHIFT 0
982 #define DMIPSPLLCFG_M1_MASK (0xff << DMIPSPLLCFG_M1_SHIFT)
983 #define DMIPSPLLCFG_N1_SHIFT 23
984 #define DMIPSPLLCFG_N1_MASK (0x3f << DMIPSPLLCFG_N1_SHIFT)
985 #define DMIPSPLLCFG_N2_SHIFT 29
986 #define DMIPSPLLCFG_N2_MASK (0x7 << DMIPSPLLCFG_N2_SHIFT)
988 #define DDR_DMIPSPLLCFG_6368_REG 0x20
989 #define DMIPSPLLCFG_6368_P1_SHIFT 0
990 #define DMIPSPLLCFG_6368_P1_MASK (0xf << DMIPSPLLCFG_6368_P1_SHIFT)
991 #define DMIPSPLLCFG_6368_P2_SHIFT 4
992 #define DMIPSPLLCFG_6368_P2_MASK (0xf << DMIPSPLLCFG_6368_P2_SHIFT)
993 #define DMIPSPLLCFG_6368_NDIV_SHIFT 16
994 #define DMIPSPLLCFG_6368_NDIV_MASK (0x1ff << DMIPSPLLCFG_6368_NDIV_SHIFT)
996 #define DDR_DMIPSPLLDIV_6368_REG 0x24
997 #define DMIPSPLLDIV_6368_MDIV_SHIFT 0
998 #define DMIPSPLLDIV_6368_MDIV_MASK (0xff << DMIPSPLLDIV_6368_MDIV_SHIFT)
1001 /*************************************************************************
1002 * _REG relative to RSET_M2M
1003 *************************************************************************/
1005 #define M2M_RX 0
1006 #define M2M_TX 1
1008 #define M2M_SRC_REG(x) ((x) * 0x40 + 0x00)
1009 #define M2M_DST_REG(x) ((x) * 0x40 + 0x04)
1010 #define M2M_SIZE_REG(x) ((x) * 0x40 + 0x08)
1012 #define M2M_CTRL_REG(x) ((x) * 0x40 + 0x0c)
1013 #define M2M_CTRL_ENABLE_MASK (1 << 0)
1014 #define M2M_CTRL_IRQEN_MASK (1 << 1)
1015 #define M2M_CTRL_ERROR_CLR_MASK (1 << 6)
1016 #define M2M_CTRL_DONE_CLR_MASK (1 << 7)
1017 #define M2M_CTRL_NOINC_MASK (1 << 8)
1018 #define M2M_CTRL_PCMCIASWAP_MASK (1 << 9)
1019 #define M2M_CTRL_SWAPBYTE_MASK (1 << 10)
1020 #define M2M_CTRL_ENDIAN_MASK (1 << 11)
1022 #define M2M_STAT_REG(x) ((x) * 0x40 + 0x10)
1023 #define M2M_STAT_DONE (1 << 0)
1024 #define M2M_STAT_ERROR (1 << 1)
1026 #define M2M_SRCID_REG(x) ((x) * 0x40 + 0x14)
1027 #define M2M_DSTID_REG(x) ((x) * 0x40 + 0x18)
1029 /*************************************************************************
1030 * _REG relative to RSET_RNG
1031 *************************************************************************/
1033 #define RNG_CTRL 0x00
1034 #define RNG_EN (1 << 0)
1036 #define RNG_STAT 0x04
1037 #define RNG_AVAIL_MASK (0xff000000)
1039 #define RNG_DATA 0x08
1040 #define RNG_THRES 0x0c
1041 #define RNG_MASK 0x10
1043 /*************************************************************************
1044 * _REG relative to RSET_SPI
1045 *************************************************************************/
1047 /* BCM 6338 SPI core */
1048 #define SPI_6338_CMD 0x00 /* 16-bits register */
1049 #define SPI_6338_INT_STATUS 0x02
1050 #define SPI_6338_INT_MASK_ST 0x03
1051 #define SPI_6338_INT_MASK 0x04
1052 #define SPI_6338_ST 0x05
1053 #define SPI_6338_CLK_CFG 0x06
1054 #define SPI_6338_FILL_BYTE 0x07
1055 #define SPI_6338_MSG_TAIL 0x09
1056 #define SPI_6338_RX_TAIL 0x0b
1057 #define SPI_6338_MSG_CTL 0x40 /* 8-bits register */
1058 #define SPI_6338_MSG_CTL_WIDTH 8
1059 #define SPI_6338_MSG_DATA 0x41
1060 #define SPI_6338_MSG_DATA_SIZE 0x3f
1061 #define SPI_6338_RX_DATA 0x80
1062 #define SPI_6338_RX_DATA_SIZE 0x3f
1064 /* BCM 6348 SPI core */
1065 #define SPI_6348_CMD 0x00 /* 16-bits register */
1066 #define SPI_6348_INT_STATUS 0x02
1067 #define SPI_6348_INT_MASK_ST 0x03
1068 #define SPI_6348_INT_MASK 0x04
1069 #define SPI_6348_ST 0x05
1070 #define SPI_6348_CLK_CFG 0x06
1071 #define SPI_6348_FILL_BYTE 0x07
1072 #define SPI_6348_MSG_TAIL 0x09
1073 #define SPI_6348_RX_TAIL 0x0b
1074 #define SPI_6348_MSG_CTL 0x40 /* 8-bits register */
1075 #define SPI_6348_MSG_CTL_WIDTH 8
1076 #define SPI_6348_MSG_DATA 0x41
1077 #define SPI_6348_MSG_DATA_SIZE 0x3f
1078 #define SPI_6348_RX_DATA 0x80
1079 #define SPI_6348_RX_DATA_SIZE 0x3f
1081 /* BCM 6358 SPI core */
1082 #define SPI_6358_MSG_CTL 0x00 /* 16-bits register */
1083 #define SPI_6358_MSG_CTL_WIDTH 16
1084 #define SPI_6358_MSG_DATA 0x02
1085 #define SPI_6358_MSG_DATA_SIZE 0x21e
1086 #define SPI_6358_RX_DATA 0x400
1087 #define SPI_6358_RX_DATA_SIZE 0x220
1088 #define SPI_6358_CMD 0x700 /* 16-bits register */
1089 #define SPI_6358_INT_STATUS 0x702
1090 #define SPI_6358_INT_MASK_ST 0x703
1091 #define SPI_6358_INT_MASK 0x704
1092 #define SPI_6358_ST 0x705
1093 #define SPI_6358_CLK_CFG 0x706
1094 #define SPI_6358_FILL_BYTE 0x707
1095 #define SPI_6358_MSG_TAIL 0x709
1096 #define SPI_6358_RX_TAIL 0x70B
1098 /* BCM 6358 SPI core */
1099 #define SPI_6368_MSG_CTL 0x00 /* 16-bits register */
1100 #define SPI_6368_MSG_CTL_WIDTH 16
1101 #define SPI_6368_MSG_DATA 0x02
1102 #define SPI_6368_MSG_DATA_SIZE 0x21e
1103 #define SPI_6368_RX_DATA 0x400
1104 #define SPI_6368_RX_DATA_SIZE 0x220
1105 #define SPI_6368_CMD 0x700 /* 16-bits register */
1106 #define SPI_6368_INT_STATUS 0x702
1107 #define SPI_6368_INT_MASK_ST 0x703
1108 #define SPI_6368_INT_MASK 0x704
1109 #define SPI_6368_ST 0x705
1110 #define SPI_6368_CLK_CFG 0x706
1111 #define SPI_6368_FILL_BYTE 0x707
1112 #define SPI_6368_MSG_TAIL 0x709
1113 #define SPI_6368_RX_TAIL 0x70B
1115 /* Shared SPI definitions */
1117 /* Message configuration */
1118 #define SPI_FD_RW 0x00
1119 #define SPI_HD_W 0x01
1120 #define SPI_HD_R 0x02
1121 #define SPI_BYTE_CNT_SHIFT 0
1122 #define SPI_6338_MSG_TYPE_SHIFT 6
1123 #define SPI_6348_MSG_TYPE_SHIFT 6
1124 #define SPI_6358_MSG_TYPE_SHIFT 14
1125 #define SPI_6368_MSG_TYPE_SHIFT 14
1127 /* Command */
1128 #define SPI_CMD_NOOP 0x00
1129 #define SPI_CMD_SOFT_RESET 0x01
1130 #define SPI_CMD_HARD_RESET 0x02
1131 #define SPI_CMD_START_IMMEDIATE 0x03
1132 #define SPI_CMD_COMMAND_SHIFT 0
1133 #define SPI_CMD_COMMAND_MASK 0x000f
1134 #define SPI_CMD_DEVICE_ID_SHIFT 4
1135 #define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8
1136 #define SPI_CMD_ONE_BYTE_SHIFT 11
1137 #define SPI_CMD_ONE_WIRE_SHIFT 12
1138 #define SPI_DEV_ID_0 0
1139 #define SPI_DEV_ID_1 1
1140 #define SPI_DEV_ID_2 2
1141 #define SPI_DEV_ID_3 3
1143 /* Interrupt mask */
1144 #define SPI_INTR_CMD_DONE 0x01
1145 #define SPI_INTR_RX_OVERFLOW 0x02
1146 #define SPI_INTR_TX_UNDERFLOW 0x04
1147 #define SPI_INTR_TX_OVERFLOW 0x08
1148 #define SPI_INTR_RX_UNDERFLOW 0x10
1149 #define SPI_INTR_CLEAR_ALL 0x1f
1151 /* Status */
1152 #define SPI_RX_EMPTY 0x02
1153 #define SPI_CMD_BUSY 0x04
1154 #define SPI_SERIAL_BUSY 0x08
1156 /* Clock configuration */
1157 #define SPI_CLK_20MHZ 0x00
1158 #define SPI_CLK_0_391MHZ 0x01
1159 #define SPI_CLK_0_781MHZ 0x02 /* default */
1160 #define SPI_CLK_1_563MHZ 0x03
1161 #define SPI_CLK_3_125MHZ 0x04
1162 #define SPI_CLK_6_250MHZ 0x05
1163 #define SPI_CLK_12_50MHZ 0x06
1164 #define SPI_CLK_MASK 0x07
1165 #define SPI_SSOFFTIME_MASK 0x38
1166 #define SPI_SSOFFTIME_SHIFT 3
1167 #define SPI_BYTE_SWAP 0x80
1169 /*************************************************************************
1170 * _REG relative to RSET_MISC
1171 *************************************************************************/
1172 #define MISC_SERDES_CTRL_REG 0x0
1173 #define SERDES_PCIE_EN (1 << 0)
1174 #define SERDES_PCIE_EXD_EN (1 << 15)
1176 #define MISC_STRAPBUS_6328_REG 0x240
1177 #define STRAPBUS_6328_FCVO_SHIFT 7
1178 #define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT)
1179 #define STRAPBUS_6328_BOOT_SEL_SERIAL (1 << 28)
1180 #define STRAPBUS_6328_BOOT_SEL_NAND (0 << 28)
1182 /*************************************************************************
1183 * _REG relative to RSET_PCIE
1184 *************************************************************************/
1186 #define PCIE_CONFIG2_REG 0x408
1187 #define CONFIG2_BAR1_SIZE_EN 1
1188 #define CONFIG2_BAR1_SIZE_MASK 0xf
1190 #define PCIE_IDVAL3_REG 0x43c
1191 #define IDVAL3_CLASS_CODE_MASK 0xffffff
1192 #define IDVAL3_SUBCLASS_SHIFT 8
1193 #define IDVAL3_CLASS_SHIFT 16
1195 #define PCIE_DLSTATUS_REG 0x1048
1196 #define DLSTATUS_PHYLINKUP (1 << 13)
1198 #define PCIE_BRIDGE_OPT1_REG 0x2820
1199 #define OPT1_RD_BE_OPT_EN (1 << 7)
1200 #define OPT1_RD_REPLY_BE_FIX_EN (1 << 9)
1201 #define OPT1_PCIE_BRIDGE_HOLE_DET_EN (1 << 11)
1202 #define OPT1_L1_INT_STATUS_MASK_POL (1 << 12)
1204 #define PCIE_BRIDGE_OPT2_REG 0x2824
1205 #define OPT2_UBUS_UR_DECODE_DIS (1 << 2)
1206 #define OPT2_TX_CREDIT_CHK_EN (1 << 4)
1207 #define OPT2_CFG_TYPE1_BD_SEL (1 << 7)
1208 #define OPT2_CFG_TYPE1_BUS_NO_SHIFT 16
1209 #define OPT2_CFG_TYPE1_BUS_NO_MASK (0xff << OPT2_CFG_TYPE1_BUS_NO_SHIFT)
1211 #define PCIE_BRIDGE_BAR0_BASEMASK_REG 0x2828
1212 #define PCIE_BRIDGE_BAR1_BASEMASK_REG 0x2830
1213 #define BASEMASK_REMAP_EN (1 << 0)
1214 #define BASEMASK_SWAP_EN (1 << 1)
1215 #define BASEMASK_MASK_SHIFT 4
1216 #define BASEMASK_MASK_MASK (0xfff << BASEMASK_MASK_SHIFT)
1217 #define BASEMASK_BASE_SHIFT 20
1218 #define BASEMASK_BASE_MASK (0xfff << BASEMASK_BASE_SHIFT)
1220 #define PCIE_BRIDGE_BAR0_REBASE_ADDR_REG 0x282c
1221 #define PCIE_BRIDGE_BAR1_REBASE_ADDR_REG 0x2834
1222 #define REBASE_ADDR_BASE_SHIFT 20
1223 #define REBASE_ADDR_BASE_MASK (0xfff << REBASE_ADDR_BASE_SHIFT)
1225 #define PCIE_BRIDGE_RC_INT_MASK_REG 0x2854
1226 #define PCIE_RC_INT_A (1 << 0)
1227 #define PCIE_RC_INT_B (1 << 1)
1228 #define PCIE_RC_INT_C (1 << 2)
1229 #define PCIE_RC_INT_D (1 << 3)
1231 #define PCIE_DEVICE_OFFSET 0x8000
1233 #endif /* BCM63XX_REGS_H_ */