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initial commit with v3.6.7
[linux-3.6.7-moxart.git] / arch / mips / mti-malta / malta-int.c
blobfea823f184794a8a9003ce79afd90cb762a4ed52
1 /*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc.
4 * Copyright (C) 2001 Ralf Baechle
5 *
6 * This program is free software; you can distribute it and/or modify it
7 * under the terms of the GNU General Public License (Version 2) as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
18 *
19 * Routines for generic manipulation of the interrupts found on the MIPS
20 * Malta board.
21 * The interrupt controller is located in the South Bridge a PIIX4 device
22 * with two internal 82C95 interrupt controllers.
23 */
24 #include <linux/init.h>
25 #include <linux/irq.h>
26 #include <linux/sched.h>
27 #include <linux/smp.h>
28 #include <linux/interrupt.h>
29 #include <linux/io.h>
30 #include <linux/kernel_stat.h>
31 #include <linux/kernel.h>
32 #include <linux/random.h>
33
34 #include <asm/traps.h>
35 #include <asm/i8259.h>
36 #include <asm/irq_cpu.h>
37 #include <asm/irq_regs.h>
38 #include <asm/mips-boards/malta.h>
39 #include <asm/mips-boards/maltaint.h>
40 #include <asm/mips-boards/piix4.h>
41 #include <asm/gt64120.h>
42 #include <asm/mips-boards/generic.h>
43 #include <asm/mips-boards/msc01_pci.h>
44 #include <asm/msc01_ic.h>
45 #include <asm/gic.h>
46 #include <asm/gcmpregs.h>
47 #include <asm/setup.h>
48
49 int gcmp_present = -1;
50 int gic_present;
51 static unsigned long _msc01_biu_base;
52 static unsigned long _gcmp_base;
53 static unsigned int ipi_map[NR_CPUS];
54
55 static DEFINE_RAW_SPINLOCK(mips_irq_lock);
56
57 static inline int mips_pcibios_iack(void)
58 {
59 int irq;
60
61 /*
62 * Determine highest priority pending interrupt by performing
63 * a PCI Interrupt Acknowledge cycle.
64 */
65 switch (mips_revision_sconid) {
66 case MIPS_REVISION_SCON_SOCIT:
67 case MIPS_REVISION_SCON_ROCIT:
68 case MIPS_REVISION_SCON_SOCITSC:
69 case MIPS_REVISION_SCON_SOCITSCP:
70 MSC_READ(MSC01_PCI_IACK, irq);
71 irq &= 0xff;
72 break;
73 case MIPS_REVISION_SCON_GT64120:
74 irq = GT_READ(GT_PCI0_IACK_OFS);
75 irq &= 0xff;
76 break;
77 case MIPS_REVISION_SCON_BONITO:
78 /* The following will generate a PCI IACK cycle on the
79 * Bonito controller. It's a little bit kludgy, but it
80 * was the easiest way to implement it in hardware at
81 * the given time.
82 */
83 BONITO_PCIMAP_CFG = 0x20000;
84
85 /* Flush Bonito register block */
86 (void) BONITO_PCIMAP_CFG;
87 iob(); /* sync */
88
89 irq = __raw_readl((u32 *)_pcictrl_bonito_pcicfg);
90 iob(); /* sync */
91 irq &= 0xff;
92 BONITO_PCIMAP_CFG = 0;
93 break;
94 default:
95 printk(KERN_WARNING "Unknown system controller.\n");
96 return -1;
97 }
98 return irq;
99 }
100
101 static inline int get_int(void)
102 {
103 unsigned long flags;
104 int irq;
105 raw_spin_lock_irqsave(&mips_irq_lock, flags);
106
107 irq = mips_pcibios_iack();
108
109 /*
110 * The only way we can decide if an interrupt is spurious
111 * is by checking the 8259 registers. This needs a spinlock
112 * on an SMP system, so leave it up to the generic code...
113 */
114
115 raw_spin_unlock_irqrestore(&mips_irq_lock, flags);
116
117 return irq;
118 }
119
120 static void malta_hw0_irqdispatch(void)
121 {
122 int irq;
123
124 irq = get_int();
125 if (irq < 0) {
126 /* interrupt has already been cleared */
127 return;
128 }
129
130 do_IRQ(MALTA_INT_BASE + irq);
131 }
132
133 static void malta_ipi_irqdispatch(void)
134 {
135 int irq;
136
137 irq = gic_get_int();
138 if (irq < 0)
139 return; /* interrupt has already been cleared */
140
141 do_IRQ(MIPS_GIC_IRQ_BASE + irq);
142 }
143
144 static void corehi_irqdispatch(void)
145 {
146 unsigned int intedge, intsteer, pcicmd, pcibadaddr;
147 unsigned int pcimstat, intisr, inten, intpol;
148 unsigned int intrcause, datalo, datahi;
149 struct pt_regs *regs = get_irq_regs();
150
151 printk(KERN_EMERG "CoreHI interrupt, shouldn't happen, we die here!\n");
152 printk(KERN_EMERG "epc : %08lx\nStatus: %08lx\n"
153 "Cause : %08lx\nbadVaddr : %08lx\n",
154 regs->cp0_epc, regs->cp0_status,
155 regs->cp0_cause, regs->cp0_badvaddr);
156
157 /* Read all the registers and then print them as there is a
158 problem with interspersed printk's upsetting the Bonito controller.
159 Do it for the others too.
160 */
161
162 switch (mips_revision_sconid) {
163 case MIPS_REVISION_SCON_SOCIT:
164 case MIPS_REVISION_SCON_ROCIT:
165 case MIPS_REVISION_SCON_SOCITSC:
166 case MIPS_REVISION_SCON_SOCITSCP:
167 ll_msc_irq();
168 break;
169 case MIPS_REVISION_SCON_GT64120:
170 intrcause = GT_READ(GT_INTRCAUSE_OFS);
171 datalo = GT_READ(GT_CPUERR_ADDRLO_OFS);
172 datahi = GT_READ(GT_CPUERR_ADDRHI_OFS);
173 printk(KERN_EMERG "GT_INTRCAUSE = %08x\n", intrcause);
174 printk(KERN_EMERG "GT_CPUERR_ADDR = %02x%08x\n",
175 datahi, datalo);
176 break;
177 case MIPS_REVISION_SCON_BONITO:
178 pcibadaddr = BONITO_PCIBADADDR;
179 pcimstat = BONITO_PCIMSTAT;
180 intisr = BONITO_INTISR;
181 inten = BONITO_INTEN;
182 intpol = BONITO_INTPOL;
183 intedge = BONITO_INTEDGE;
184 intsteer = BONITO_INTSTEER;
185 pcicmd = BONITO_PCICMD;
186 printk(KERN_EMERG "BONITO_INTISR = %08x\n", intisr);
187 printk(KERN_EMERG "BONITO_INTEN = %08x\n", inten);
188 printk(KERN_EMERG "BONITO_INTPOL = %08x\n", intpol);
189 printk(KERN_EMERG "BONITO_INTEDGE = %08x\n", intedge);
190 printk(KERN_EMERG "BONITO_INTSTEER = %08x\n", intsteer);
191 printk(KERN_EMERG "BONITO_PCICMD = %08x\n", pcicmd);
192 printk(KERN_EMERG "BONITO_PCIBADADDR = %08x\n", pcibadaddr);
193 printk(KERN_EMERG "BONITO_PCIMSTAT = %08x\n", pcimstat);
194 break;
195 }
196
197 die("CoreHi interrupt", regs);
198 }
199
200 static inline int clz(unsigned long x)
201 {
202 __asm__(
203 " .set push \n"
204 " .set mips32 \n"
205 " clz %0, %1 \n"
206 " .set pop \n"
207 : "=r" (x)
208 : "r" (x));
209
210 return x;
211 }
212
213 /*
214 * Version of ffs that only looks at bits 12..15.
215 */
216 static inline unsigned int irq_ffs(unsigned int pending)
217 {
218 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
219 return -clz(pending) + 31 - CAUSEB_IP;
220 #else
221 unsigned int a0 = 7;
222 unsigned int t0;
223
224 t0 = pending & 0xf000;
225 t0 = t0 < 1;
226 t0 = t0 << 2;
227 a0 = a0 - t0;
228 pending = pending << t0;
229
230 t0 = pending & 0xc000;
231 t0 = t0 < 1;
232 t0 = t0 << 1;
233 a0 = a0 - t0;
234 pending = pending << t0;
235
236 t0 = pending & 0x8000;
237 t0 = t0 < 1;
238 /* t0 = t0 << 2; */
239 a0 = a0 - t0;
240 /* pending = pending << t0; */
241
242 return a0;
243 #endif
244 }
245
246 /*
247 * IRQs on the Malta board look basically (barring software IRQs which we
248 * don't use at all and all external interrupt sources are combined together
249 * on hardware interrupt 0 (MIPS IRQ 2)) like:
250 *
251 * MIPS IRQ Source
252 * -------- ------
253 * 0 Software (ignored)
254 * 1 Software (ignored)
255 * 2 Combined hardware interrupt (hw0)
256 * 3 Hardware (ignored)
257 * 4 Hardware (ignored)
258 * 5 Hardware (ignored)
259 * 6 Hardware (ignored)
260 * 7 R4k timer (what we use)
261 *
262 * We handle the IRQ according to _our_ priority which is:
263 *
264 * Highest ---- R4k Timer
265 * Lowest ---- Combined hardware interrupt
266 *
267 * then we just return, if multiple IRQs are pending then we will just take
268 * another exception, big deal.
269 */
270
271 asmlinkage void plat_irq_dispatch(void)
272 {
273 unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
274 int irq;
275
276 if (unlikely(!pending)) {
277 spurious_interrupt();
278 return;
279 }
280
281 irq = irq_ffs(pending);
282
283 if (irq == MIPSCPU_INT_I8259A)
284 malta_hw0_irqdispatch();
285 else if (gic_present && ((1 << irq) & ipi_map[smp_processor_id()]))
286 malta_ipi_irqdispatch();
287 else
288 do_IRQ(MIPS_CPU_IRQ_BASE + irq);
289 }
290
291 #ifdef CONFIG_MIPS_MT_SMP
292
293
294 #define GIC_MIPS_CPU_IPI_RESCHED_IRQ 3
295 #define GIC_MIPS_CPU_IPI_CALL_IRQ 4
296
297 #define MIPS_CPU_IPI_RESCHED_IRQ 0 /* SW int 0 for resched */
298 #define C_RESCHED C_SW0
299 #define MIPS_CPU_IPI_CALL_IRQ 1 /* SW int 1 for resched */
300 #define C_CALL C_SW1
301 static int cpu_ipi_resched_irq, cpu_ipi_call_irq;
302
303 static void ipi_resched_dispatch(void)
304 {
305 do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ);
306 }
307
308 static void ipi_call_dispatch(void)
309 {
310 do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ);
311 }
312
313 static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
314 {
315 scheduler_ipi();
316
317 return IRQ_HANDLED;
318 }
319
320 static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
321 {
322 smp_call_function_interrupt();
323
324 return IRQ_HANDLED;
325 }
326
327 static struct irqaction irq_resched = {
328 .handler = ipi_resched_interrupt,
329 .flags = IRQF_PERCPU,
330 .name = "IPI_resched"
331 };
332
333 static struct irqaction irq_call = {
334 .handler = ipi_call_interrupt,
335 .flags = IRQF_PERCPU,
336 .name = "IPI_call"
337 };
338 #endif /* CONFIG_MIPS_MT_SMP */
339
340 static int gic_resched_int_base;
341 static int gic_call_int_base;
342 #define GIC_RESCHED_INT(cpu) (gic_resched_int_base+(cpu))
343 #define GIC_CALL_INT(cpu) (gic_call_int_base+(cpu))
344
345 unsigned int plat_ipi_call_int_xlate(unsigned int cpu)
346 {
347 return GIC_CALL_INT(cpu);
348 }
349
350 unsigned int plat_ipi_resched_int_xlate(unsigned int cpu)
351 {
352 return GIC_RESCHED_INT(cpu);
353 }
354
355 static struct irqaction i8259irq = {
356 .handler = no_action,
357 .name = "XT-PIC cascade",
358 .flags = IRQF_NO_THREAD,
359 };
360
361 static struct irqaction corehi_irqaction = {
362 .handler = no_action,
363 .name = "CoreHi",
364 .flags = IRQF_NO_THREAD,
365 };
366
367 static msc_irqmap_t __initdata msc_irqmap[] = {
368 {MSC01C_INT_TMR, MSC01_IRQ_EDGE, 0},
369 {MSC01C_INT_PCI, MSC01_IRQ_LEVEL, 0},
370 };
371 static int __initdata msc_nr_irqs = ARRAY_SIZE(msc_irqmap);
372
373 static msc_irqmap_t __initdata msc_eicirqmap[] = {
374 {MSC01E_INT_SW0, MSC01_IRQ_LEVEL, 0},
375 {MSC01E_INT_SW1, MSC01_IRQ_LEVEL, 0},
376 {MSC01E_INT_I8259A, MSC01_IRQ_LEVEL, 0},
377 {MSC01E_INT_SMI, MSC01_IRQ_LEVEL, 0},
378 {MSC01E_INT_COREHI, MSC01_IRQ_LEVEL, 0},
379 {MSC01E_INT_CORELO, MSC01_IRQ_LEVEL, 0},
380 {MSC01E_INT_TMR, MSC01_IRQ_EDGE, 0},
381 {MSC01E_INT_PCI, MSC01_IRQ_LEVEL, 0},
382 {MSC01E_INT_PERFCTR, MSC01_IRQ_LEVEL, 0},
383 {MSC01E_INT_CPUCTR, MSC01_IRQ_LEVEL, 0}
384 };
385
386 static int __initdata msc_nr_eicirqs = ARRAY_SIZE(msc_eicirqmap);
387
388 /*
389 * This GIC specific tabular array defines the association between External
390 * Interrupts and CPUs/Core Interrupts. The nature of the External
391 * Interrupts is also defined here - polarity/trigger.
392 */
393
394 #define GIC_CPU_NMI GIC_MAP_TO_NMI_MSK
395 #define X GIC_UNUSED
396
397 static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = {
398 { X, X, X, X, 0 },
399 { X, X, X, X, 0 },
400 { X, X, X, X, 0 },
401 { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
402 { 0, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
403 { 0, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
404 { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
405 { 0, GIC_CPU_INT4, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
406 { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
407 { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
408 { X, X, X, X, 0 },
409 { X, X, X, X, 0 },
410 { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
411 { 0, GIC_CPU_NMI, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
412 { 0, GIC_CPU_NMI, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
413 { X, X, X, X, 0 },
414 /* The remainder of this table is initialised by fill_ipi_map */
415 };
416 #undef X
417
418 /*
419 * GCMP needs to be detected before any SMP initialisation
420 */
421 int __init gcmp_probe(unsigned long addr, unsigned long size)
422 {
423 if (mips_revision_sconid != MIPS_REVISION_SCON_ROCIT) {
424 gcmp_present = 0;
425 return gcmp_present;
426 }
427
428 if (gcmp_present >= 0)
429 return gcmp_present;
430
431 _gcmp_base = (unsigned long) ioremap_nocache(GCMP_BASE_ADDR, GCMP_ADDRSPACE_SZ);
432 _msc01_biu_base = (unsigned long) ioremap_nocache(MSC01_BIU_REG_BASE, MSC01_BIU_ADDRSPACE_SZ);
433 gcmp_present = (GCMPGCB(GCMPB) & GCMP_GCB_GCMPB_GCMPBASE_MSK) == GCMP_BASE_ADDR;
434
435 if (gcmp_present)
436 pr_debug("GCMP present\n");
437 return gcmp_present;
438 }
439
440 /* Return the number of IOCU's present */
441 int __init gcmp_niocu(void)
442 {
443 return gcmp_present ?
444 (GCMPGCB(GC) & GCMP_GCB_GC_NUMIOCU_MSK) >> GCMP_GCB_GC_NUMIOCU_SHF :
445 0;
446 }
447
448 /* Set GCMP region attributes */
449 void __init gcmp_setregion(int region, unsigned long base,
450 unsigned long mask, int type)
451 {
452 GCMPGCBn(CMxBASE, region) = base;
453 GCMPGCBn(CMxMASK, region) = mask | type;
454 }
455
456 #if defined(CONFIG_MIPS_MT_SMP)
457 static void __init fill_ipi_map1(int baseintr, int cpu, int cpupin)
458 {
459 int intr = baseintr + cpu;
460 gic_intr_map[intr].cpunum = cpu;
461 gic_intr_map[intr].pin = cpupin;
462 gic_intr_map[intr].polarity = GIC_POL_POS;
463 gic_intr_map[intr].trigtype = GIC_TRIG_EDGE;
464 gic_intr_map[intr].flags = GIC_FLAG_IPI;
465 ipi_map[cpu] |= (1 << (cpupin + 2));
466 }
467
468 static void __init fill_ipi_map(void)
469 {
470 int cpu;
471
472 for (cpu = 0; cpu < NR_CPUS; cpu++) {
473 fill_ipi_map1(gic_resched_int_base, cpu, GIC_CPU_INT1);
474 fill_ipi_map1(gic_call_int_base, cpu, GIC_CPU_INT2);
475 }
476 }
477 #endif
478
479 void __init arch_init_ipiirq(int irq, struct irqaction *action)
480 {
481 setup_irq(irq, action);
482 irq_set_handler(irq, handle_percpu_irq);
483 }
484
485 void __init arch_init_irq(void)
486 {
487 init_i8259_irqs();
488
489 if (!cpu_has_veic)
490 mips_cpu_irq_init();
491
492 if (gcmp_present) {
493 GCMPGCB(GICBA) = GIC_BASE_ADDR | GCMP_GCB_GICBA_EN_MSK;
494 gic_present = 1;
495 } else {
496 if (mips_revision_sconid == MIPS_REVISION_SCON_ROCIT) {
497 _msc01_biu_base = (unsigned long)
498 ioremap_nocache(MSC01_BIU_REG_BASE,
499 MSC01_BIU_ADDRSPACE_SZ);
500 gic_present = (REG(_msc01_biu_base, MSC01_SC_CFG) &
501 MSC01_SC_CFG_GICPRES_MSK) >>
502 MSC01_SC_CFG_GICPRES_SHF;
503 }
504 }
505 if (gic_present)
506 pr_debug("GIC present\n");
507
508 switch (mips_revision_sconid) {
509 case MIPS_REVISION_SCON_SOCIT:
510 case MIPS_REVISION_SCON_ROCIT:
511 if (cpu_has_veic)
512 init_msc_irqs(MIPS_MSC01_IC_REG_BASE,
513 MSC01E_INT_BASE, msc_eicirqmap,
514 msc_nr_eicirqs);
515 else
516 init_msc_irqs(MIPS_MSC01_IC_REG_BASE,
517 MSC01C_INT_BASE, msc_irqmap,
518 msc_nr_irqs);
519 break;
520
521 case MIPS_REVISION_SCON_SOCITSC:
522 case MIPS_REVISION_SCON_SOCITSCP:
523 if (cpu_has_veic)
524 init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE,
525 MSC01E_INT_BASE, msc_eicirqmap,
526 msc_nr_eicirqs);
527 else
528 init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE,
529 MSC01C_INT_BASE, msc_irqmap,
530 msc_nr_irqs);
531 }
532
533 if (cpu_has_veic) {
534 set_vi_handler(MSC01E_INT_I8259A, malta_hw0_irqdispatch);
535 set_vi_handler(MSC01E_INT_COREHI, corehi_irqdispatch);
536 setup_irq(MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq);
537 setup_irq(MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction);
538 } else if (cpu_has_vint) {
539 set_vi_handler(MIPSCPU_INT_I8259A, malta_hw0_irqdispatch);
540 set_vi_handler(MIPSCPU_INT_COREHI, corehi_irqdispatch);
541 #ifdef CONFIG_MIPS_MT_SMTC
542 setup_irq_smtc(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq,
543 (0x100 << MIPSCPU_INT_I8259A));
544 setup_irq_smtc(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
545 &corehi_irqaction, (0x100 << MIPSCPU_INT_COREHI));
546 /*
547 * Temporary hack to ensure that the subsidiary device
548 * interrupts coing in via the i8259A, but associated
549 * with low IRQ numbers, will restore the Status.IM
550 * value associated with the i8259A.
551 */
552 {
553 int i;
554
555 for (i = 0; i < 16; i++)
556 irq_hwmask[i] = (0x100 << MIPSCPU_INT_I8259A);
557 }
558 #else /* Not SMTC */
559 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
560 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
561 &corehi_irqaction);
562 #endif /* CONFIG_MIPS_MT_SMTC */
563 } else {
564 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
565 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
566 &corehi_irqaction);
567 }
568
569 if (gic_present) {
570 /* FIXME */
571 int i;
572 #if defined(CONFIG_MIPS_MT_SMP)
573 gic_call_int_base = GIC_NUM_INTRS - NR_CPUS;
574 gic_resched_int_base = gic_call_int_base - NR_CPUS;
575 fill_ipi_map();
576 #endif
577 gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map,
578 ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE);
579 if (!gcmp_present) {
580 /* Enable the GIC */
581 i = REG(_msc01_biu_base, MSC01_SC_CFG);
582 REG(_msc01_biu_base, MSC01_SC_CFG) =
583 (i | (0x1 << MSC01_SC_CFG_GICENA_SHF));
584 pr_debug("GIC Enabled\n");
585 }
586 #if defined(CONFIG_MIPS_MT_SMP)
587 /* set up ipi interrupts */
588 if (cpu_has_vint) {
589 set_vi_handler(MIPSCPU_INT_IPI0, malta_ipi_irqdispatch);
590 set_vi_handler(MIPSCPU_INT_IPI1, malta_ipi_irqdispatch);
591 }
592 /* Argh.. this really needs sorting out.. */
593 printk("CPU%d: status register was %08x\n", smp_processor_id(), read_c0_status());
594 write_c0_status(read_c0_status() | STATUSF_IP3 | STATUSF_IP4);
595 printk("CPU%d: status register now %08x\n", smp_processor_id(), read_c0_status());
596 write_c0_status(0x1100dc00);
597 printk("CPU%d: status register frc %08x\n", smp_processor_id(), read_c0_status());
598 for (i = 0; i < NR_CPUS; i++) {
599 arch_init_ipiirq(MIPS_GIC_IRQ_BASE +
600 GIC_RESCHED_INT(i), &irq_resched);
601 arch_init_ipiirq(MIPS_GIC_IRQ_BASE +
602 GIC_CALL_INT(i), &irq_call);
603 }
604 #endif
605 } else {
606 #if defined(CONFIG_MIPS_MT_SMP)
607 /* set up ipi interrupts */
608 if (cpu_has_veic) {
609 set_vi_handler (MSC01E_INT_SW0, ipi_resched_dispatch);
610 set_vi_handler (MSC01E_INT_SW1, ipi_call_dispatch);
611 cpu_ipi_resched_irq = MSC01E_INT_SW0;
612 cpu_ipi_call_irq = MSC01E_INT_SW1;
613 } else {
614 if (cpu_has_vint) {
615 set_vi_handler (MIPS_CPU_IPI_RESCHED_IRQ, ipi_resched_dispatch);
616 set_vi_handler (MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch);
617 }
618 cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ;
619 cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ;
620 }
621 arch_init_ipiirq(cpu_ipi_resched_irq, &irq_resched);
622 arch_init_ipiirq(cpu_ipi_call_irq, &irq_call);
623 #endif
624 }
625 }
626
627 void malta_be_init(void)
628 {
629 if (gcmp_present) {
630 /* Could change CM error mask register */
631 }
632 }
633
634
635 static char *tr[8] = {
636 "mem", "gcr", "gic", "mmio",
637 "0x04", "0x05", "0x06", "0x07"
638 };
639
640 static char *mcmd[32] = {
641 [0x00] = "0x00",
642 [0x01] = "Legacy Write",
643 [0x02] = "Legacy Read",
644 [0x03] = "0x03",
645 [0x04] = "0x04",
646 [0x05] = "0x05",
647 [0x06] = "0x06",
648 [0x07] = "0x07",
649 [0x08] = "Coherent Read Own",
650 [0x09] = "Coherent Read Share",
651 [0x0a] = "Coherent Read Discard",
652 [0x0b] = "Coherent Ready Share Always",
653 [0x0c] = "Coherent Upgrade",
654 [0x0d] = "Coherent Writeback",
655 [0x0e] = "0x0e",
656 [0x0f] = "0x0f",
657 [0x10] = "Coherent Copyback",
658 [0x11] = "Coherent Copyback Invalidate",
659 [0x12] = "Coherent Invalidate",
660 [0x13] = "Coherent Write Invalidate",
661 [0x14] = "Coherent Completion Sync",
662 [0x15] = "0x15",
663 [0x16] = "0x16",
664 [0x17] = "0x17",
665 [0x18] = "0x18",
666 [0x19] = "0x19",
667 [0x1a] = "0x1a",
668 [0x1b] = "0x1b",
669 [0x1c] = "0x1c",
670 [0x1d] = "0x1d",
671 [0x1e] = "0x1e",
672 [0x1f] = "0x1f"
673 };
674
675 static char *core[8] = {
676 "Invalid/OK", "Invalid/Data",
677 "Shared/OK", "Shared/Data",
678 "Modified/OK", "Modified/Data",
679 "Exclusive/OK", "Exclusive/Data"
680 };
681
682 static char *causes[32] = {
683 "None", "GC_WR_ERR", "GC_RD_ERR", "COH_WR_ERR",
684 "COH_RD_ERR", "MMIO_WR_ERR", "MMIO_RD_ERR", "0x07",
685 "0x08", "0x09", "0x0a", "0x0b",
686 "0x0c", "0x0d", "0x0e", "0x0f",
687 "0x10", "0x11", "0x12", "0x13",
688 "0x14", "0x15", "0x16", "INTVN_WR_ERR",
689 "INTVN_RD_ERR", "0x19", "0x1a", "0x1b",
690 "0x1c", "0x1d", "0x1e", "0x1f"
691 };
692
693 int malta_be_handler(struct pt_regs *regs, int is_fixup)
694 {
695 /* This duplicates the handling in do_be which seems wrong */
696 int retval = is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL;
697
698 if (gcmp_present) {
699 unsigned long cm_error = GCMPGCB(GCMEC);
700 unsigned long cm_addr = GCMPGCB(GCMEA);
701 unsigned long cm_other = GCMPGCB(GCMEO);
702 unsigned long cause, ocause;
703 char buf[256];
704
705 cause = (cm_error & GCMP_GCB_GMEC_ERROR_TYPE_MSK);
706 if (cause != 0) {
707 cause >>= GCMP_GCB_GMEC_ERROR_TYPE_SHF;
708 if (cause < 16) {
709 unsigned long cca_bits = (cm_error >> 15) & 7;
710 unsigned long tr_bits = (cm_error >> 12) & 7;
711 unsigned long mcmd_bits = (cm_error >> 7) & 0x1f;
712 unsigned long stag_bits = (cm_error >> 3) & 15;
713 unsigned long sport_bits = (cm_error >> 0) & 7;
714
715 snprintf(buf, sizeof(buf),
716 "CCA=%lu TR=%s MCmd=%s STag=%lu "
717 "SPort=%lu\n",
718 cca_bits, tr[tr_bits], mcmd[mcmd_bits],
719 stag_bits, sport_bits);
720 } else {
721 /* glob state & sresp together */
722 unsigned long c3_bits = (cm_error >> 18) & 7;
723 unsigned long c2_bits = (cm_error >> 15) & 7;
724 unsigned long c1_bits = (cm_error >> 12) & 7;
725 unsigned long c0_bits = (cm_error >> 9) & 7;
726 unsigned long sc_bit = (cm_error >> 8) & 1;
727 unsigned long mcmd_bits = (cm_error >> 3) & 0x1f;
728 unsigned long sport_bits = (cm_error >> 0) & 7;
729 snprintf(buf, sizeof(buf),
730 "C3=%s C2=%s C1=%s C0=%s SC=%s "
731 "MCmd=%s SPort=%lu\n",
732 core[c3_bits], core[c2_bits],
733 core[c1_bits], core[c0_bits],
734 sc_bit ? "True" : "False",
735 mcmd[mcmd_bits], sport_bits);
736 }
737
738 ocause = (cm_other & GCMP_GCB_GMEO_ERROR_2ND_MSK) >>
739 GCMP_GCB_GMEO_ERROR_2ND_SHF;
740
741 printk("CM_ERROR=%08lx %s <%s>\n", cm_error,
742 causes[cause], buf);
743 printk("CM_ADDR =%08lx\n", cm_addr);
744 printk("CM_OTHER=%08lx %s\n", cm_other, causes[ocause]);
745
746 /* reprime cause register */
747 GCMPGCB(GCMEC) = 0;
748 }
749 }
750
751 return retval;
752 }
Linux ARM platform port for MOXA ART SoC