?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
initial commit with v3.6.7
[linux-3.6.7-moxart.git] / arch / sparc / kernel / perf_event.c
blobac180370e59d5d5ccd8d2fe031a5bde2a73949cc
1 /* Performance event support for sparc64.
2 *
3 * Copyright (C) 2009, 2010 David S. Miller <davem@davemloft.net>
4 *
5 * This code is based almost entirely upon the x86 perf event
6 * code, which is:
7 *
8 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
9 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
10 * Copyright (C) 2009 Jaswinder Singh Rajput
11 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
12 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
13 */
14
15 #include <linux/perf_event.h>
16 #include <linux/kprobes.h>
17 #include <linux/ftrace.h>
18 #include <linux/kernel.h>
19 #include <linux/kdebug.h>
20 #include <linux/mutex.h>
21
22 #include <asm/stacktrace.h>
23 #include <asm/cpudata.h>
24 #include <asm/uaccess.h>
25 #include <linux/atomic.h>
26 #include <asm/nmi.h>
27 #include <asm/pcr.h>
28 #include <asm/perfctr.h>
29 #include <asm/cacheflush.h>
30
31 #include "kernel.h"
32 #include "kstack.h"
33
34 /* Sparc64 chips have two performance counters, 32-bits each, with
35 * overflow interrupts generated on transition from 0xffffffff to 0.
36 * The counters are accessed in one go using a 64-bit register.
37 *
38 * Both counters are controlled using a single control register. The
39 * only way to stop all sampling is to clear all of the context (user,
40 * supervisor, hypervisor) sampling enable bits. But these bits apply
41 * to both counters, thus the two counters can't be enabled/disabled
42 * individually.
43 *
44 * The control register has two event fields, one for each of the two
45 * counters. It's thus nearly impossible to have one counter going
46 * while keeping the other one stopped. Therefore it is possible to
47 * get overflow interrupts for counters not currently "in use" and
48 * that condition must be checked in the overflow interrupt handler.
49 *
50 * So we use a hack, in that we program inactive counters with the
51 * "sw_count0" and "sw_count1" events. These count how many times
52 * the instruction "sethi %hi(0xfc000), %g0" is executed. It's an
53 * unusual way to encode a NOP and therefore will not trigger in
54 * normal code.
55 */
56
57 #define MAX_HWEVENTS 2
58 #define MAX_PERIOD ((1UL << 32) - 1)
59
60 #define PIC_UPPER_INDEX 0
61 #define PIC_LOWER_INDEX 1
62 #define PIC_NO_INDEX -1
63
64 struct cpu_hw_events {
65 /* Number of events currently scheduled onto this cpu.
66 * This tells how many entries in the arrays below
67 * are valid.
68 */
69 int n_events;
70
71 /* Number of new events added since the last hw_perf_disable().
72 * This works because the perf event layer always adds new
73 * events inside of a perf_{disable,enable}() sequence.
74 */
75 int n_added;
76
77 /* Array of events current scheduled on this cpu. */
78 struct perf_event *event[MAX_HWEVENTS];
79
80 /* Array of encoded longs, specifying the %pcr register
81 * encoding and the mask of PIC counters this even can
82 * be scheduled on. See perf_event_encode() et al.
83 */
84 unsigned long events[MAX_HWEVENTS];
85
86 /* The current counter index assigned to an event. When the
87 * event hasn't been programmed into the cpu yet, this will
88 * hold PIC_NO_INDEX. The event->hw.idx value tells us where
89 * we ought to schedule the event.
90 */
91 int current_idx[MAX_HWEVENTS];
92
93 /* Software copy of %pcr register on this cpu. */
94 u64 pcr;
95
96 /* Enabled/disable state. */
97 int enabled;
98
99 unsigned int group_flag;
100 };
101 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { .enabled = 1, };
102
103 /* An event map describes the characteristics of a performance
104 * counter event. In particular it gives the encoding as well as
105 * a mask telling which counters the event can be measured on.
106 */
107 struct perf_event_map {
108 u16 encoding;
109 u8 pic_mask;
110 #define PIC_NONE 0x00
111 #define PIC_UPPER 0x01
112 #define PIC_LOWER 0x02
113 };
114
115 /* Encode a perf_event_map entry into a long. */
116 static unsigned long perf_event_encode(const struct perf_event_map *pmap)
117 {
118 return ((unsigned long) pmap->encoding << 16) | pmap->pic_mask;
119 }
120
121 static u8 perf_event_get_msk(unsigned long val)
122 {
123 return val & 0xff;
124 }
125
126 static u64 perf_event_get_enc(unsigned long val)
127 {
128 return val >> 16;
129 }
130
131 #define C(x) PERF_COUNT_HW_CACHE_##x
132
133 #define CACHE_OP_UNSUPPORTED 0xfffe
134 #define CACHE_OP_NONSENSE 0xffff
135
136 typedef struct perf_event_map cache_map_t
137 [PERF_COUNT_HW_CACHE_MAX]
138 [PERF_COUNT_HW_CACHE_OP_MAX]
139 [PERF_COUNT_HW_CACHE_RESULT_MAX];
140
141 struct sparc_pmu {
142 const struct perf_event_map *(*event_map)(int);
143 const cache_map_t *cache_map;
144 int max_events;
145 int upper_shift;
146 int lower_shift;
147 int event_mask;
148 int hv_bit;
149 int irq_bit;
150 int upper_nop;
151 int lower_nop;
152 };
153
154 static const struct perf_event_map ultra3_perfmon_event_map[] = {
155 [PERF_COUNT_HW_CPU_CYCLES] = { 0x0000, PIC_UPPER | PIC_LOWER },
156 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x0001, PIC_UPPER | PIC_LOWER },
157 [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x0009, PIC_LOWER },
158 [PERF_COUNT_HW_CACHE_MISSES] = { 0x0009, PIC_UPPER },
159 };
160
161 static const struct perf_event_map *ultra3_event_map(int event_id)
162 {
163 return &ultra3_perfmon_event_map[event_id];
164 }
165
166 static const cache_map_t ultra3_cache_map = {
167 [C(L1D)] = {
168 [C(OP_READ)] = {
169 [C(RESULT_ACCESS)] = { 0x09, PIC_LOWER, },
170 [C(RESULT_MISS)] = { 0x09, PIC_UPPER, },
171 },
172 [C(OP_WRITE)] = {
173 [C(RESULT_ACCESS)] = { 0x0a, PIC_LOWER },
174 [C(RESULT_MISS)] = { 0x0a, PIC_UPPER },
175 },
176 [C(OP_PREFETCH)] = {
177 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
178 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
179 },
180 },
181 [C(L1I)] = {
182 [C(OP_READ)] = {
183 [C(RESULT_ACCESS)] = { 0x09, PIC_LOWER, },
184 [C(RESULT_MISS)] = { 0x09, PIC_UPPER, },
185 },
186 [ C(OP_WRITE) ] = {
187 [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE },
188 [ C(RESULT_MISS) ] = { CACHE_OP_NONSENSE },
189 },
190 [ C(OP_PREFETCH) ] = {
191 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
192 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
193 },
194 },
195 [C(LL)] = {
196 [C(OP_READ)] = {
197 [C(RESULT_ACCESS)] = { 0x0c, PIC_LOWER, },
198 [C(RESULT_MISS)] = { 0x0c, PIC_UPPER, },
199 },
200 [C(OP_WRITE)] = {
201 [C(RESULT_ACCESS)] = { 0x0c, PIC_LOWER },
202 [C(RESULT_MISS)] = { 0x0c, PIC_UPPER },
203 },
204 [C(OP_PREFETCH)] = {
205 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
206 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
207 },
208 },
209 [C(DTLB)] = {
210 [C(OP_READ)] = {
211 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
212 [C(RESULT_MISS)] = { 0x12, PIC_UPPER, },
213 },
214 [ C(OP_WRITE) ] = {
215 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
216 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
217 },
218 [ C(OP_PREFETCH) ] = {
219 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
220 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
221 },
222 },
223 [C(ITLB)] = {
224 [C(OP_READ)] = {
225 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
226 [C(RESULT_MISS)] = { 0x11, PIC_UPPER, },
227 },
228 [ C(OP_WRITE) ] = {
229 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
230 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
231 },
232 [ C(OP_PREFETCH) ] = {
233 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
234 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
235 },
236 },
237 [C(BPU)] = {
238 [C(OP_READ)] = {
239 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
240 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
241 },
242 [ C(OP_WRITE) ] = {
243 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
244 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
245 },
246 [ C(OP_PREFETCH) ] = {
247 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
248 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
249 },
250 },
251 [C(NODE)] = {
252 [C(OP_READ)] = {
253 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
254 [C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
255 },
256 [ C(OP_WRITE) ] = {
257 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
258 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
259 },
260 [ C(OP_PREFETCH) ] = {
261 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
262 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
263 },
264 },
265 };
266
267 static const struct sparc_pmu ultra3_pmu = {
268 .event_map = ultra3_event_map,
269 .cache_map = &ultra3_cache_map,
270 .max_events = ARRAY_SIZE(ultra3_perfmon_event_map),
271 .upper_shift = 11,
272 .lower_shift = 4,
273 .event_mask = 0x3f,
274 .upper_nop = 0x1c,
275 .lower_nop = 0x14,
276 };
277
278 /* Niagara1 is very limited. The upper PIC is hard-locked to count
279 * only instructions, so it is free running which creates all kinds of
280 * problems. Some hardware designs make one wonder if the creator
281 * even looked at how this stuff gets used by software.
282 */
283 static const struct perf_event_map niagara1_perfmon_event_map[] = {
284 [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, PIC_UPPER },
285 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x00, PIC_UPPER },
286 [PERF_COUNT_HW_CACHE_REFERENCES] = { 0, PIC_NONE },
287 [PERF_COUNT_HW_CACHE_MISSES] = { 0x03, PIC_LOWER },
288 };
289
290 static const struct perf_event_map *niagara1_event_map(int event_id)
291 {
292 return &niagara1_perfmon_event_map[event_id];
293 }
294
295 static const cache_map_t niagara1_cache_map = {
296 [C(L1D)] = {
297 [C(OP_READ)] = {
298 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
299 [C(RESULT_MISS)] = { 0x03, PIC_LOWER, },
300 },
301 [C(OP_WRITE)] = {
302 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
303 [C(RESULT_MISS)] = { 0x03, PIC_LOWER, },
304 },
305 [C(OP_PREFETCH)] = {
306 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
307 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
308 },
309 },
310 [C(L1I)] = {
311 [C(OP_READ)] = {
312 [C(RESULT_ACCESS)] = { 0x00, PIC_UPPER },
313 [C(RESULT_MISS)] = { 0x02, PIC_LOWER, },
314 },
315 [ C(OP_WRITE) ] = {
316 [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE },
317 [ C(RESULT_MISS) ] = { CACHE_OP_NONSENSE },
318 },
319 [ C(OP_PREFETCH) ] = {
320 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
321 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
322 },
323 },
324 [C(LL)] = {
325 [C(OP_READ)] = {
326 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
327 [C(RESULT_MISS)] = { 0x07, PIC_LOWER, },
328 },
329 [C(OP_WRITE)] = {
330 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
331 [C(RESULT_MISS)] = { 0x07, PIC_LOWER, },
332 },
333 [C(OP_PREFETCH)] = {
334 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
335 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
336 },
337 },
338 [C(DTLB)] = {
339 [C(OP_READ)] = {
340 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
341 [C(RESULT_MISS)] = { 0x05, PIC_LOWER, },
342 },
343 [ C(OP_WRITE) ] = {
344 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
345 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
346 },
347 [ C(OP_PREFETCH) ] = {
348 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
349 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
350 },
351 },
352 [C(ITLB)] = {
353 [C(OP_READ)] = {
354 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
355 [C(RESULT_MISS)] = { 0x04, PIC_LOWER, },
356 },
357 [ C(OP_WRITE) ] = {
358 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
359 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
360 },
361 [ C(OP_PREFETCH) ] = {
362 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
363 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
364 },
365 },
366 [C(BPU)] = {
367 [C(OP_READ)] = {
368 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
369 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
370 },
371 [ C(OP_WRITE) ] = {
372 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
373 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
374 },
375 [ C(OP_PREFETCH) ] = {
376 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
377 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
378 },
379 },
380 [C(NODE)] = {
381 [C(OP_READ)] = {
382 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
383 [C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
384 },
385 [ C(OP_WRITE) ] = {
386 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
387 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
388 },
389 [ C(OP_PREFETCH) ] = {
390 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
391 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
392 },
393 },
394 };
395
396 static const struct sparc_pmu niagara1_pmu = {
397 .event_map = niagara1_event_map,
398 .cache_map = &niagara1_cache_map,
399 .max_events = ARRAY_SIZE(niagara1_perfmon_event_map),
400 .upper_shift = 0,
401 .lower_shift = 4,
402 .event_mask = 0x7,
403 .upper_nop = 0x0,
404 .lower_nop = 0x0,
405 };
406
407 static const struct perf_event_map niagara2_perfmon_event_map[] = {
408 [PERF_COUNT_HW_CPU_CYCLES] = { 0x02ff, PIC_UPPER | PIC_LOWER },
409 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x02ff, PIC_UPPER | PIC_LOWER },
410 [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x0208, PIC_UPPER | PIC_LOWER },
411 [PERF_COUNT_HW_CACHE_MISSES] = { 0x0302, PIC_UPPER | PIC_LOWER },
412 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x0201, PIC_UPPER | PIC_LOWER },
413 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x0202, PIC_UPPER | PIC_LOWER },
414 };
415
416 static const struct perf_event_map *niagara2_event_map(int event_id)
417 {
418 return &niagara2_perfmon_event_map[event_id];
419 }
420
421 static const cache_map_t niagara2_cache_map = {
422 [C(L1D)] = {
423 [C(OP_READ)] = {
424 [C(RESULT_ACCESS)] = { 0x0208, PIC_UPPER | PIC_LOWER, },
425 [C(RESULT_MISS)] = { 0x0302, PIC_UPPER | PIC_LOWER, },
426 },
427 [C(OP_WRITE)] = {
428 [C(RESULT_ACCESS)] = { 0x0210, PIC_UPPER | PIC_LOWER, },
429 [C(RESULT_MISS)] = { 0x0302, PIC_UPPER | PIC_LOWER, },
430 },
431 [C(OP_PREFETCH)] = {
432 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
433 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
434 },
435 },
436 [C(L1I)] = {
437 [C(OP_READ)] = {
438 [C(RESULT_ACCESS)] = { 0x02ff, PIC_UPPER | PIC_LOWER, },
439 [C(RESULT_MISS)] = { 0x0301, PIC_UPPER | PIC_LOWER, },
440 },
441 [ C(OP_WRITE) ] = {
442 [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE },
443 [ C(RESULT_MISS) ] = { CACHE_OP_NONSENSE },
444 },
445 [ C(OP_PREFETCH) ] = {
446 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
447 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
448 },
449 },
450 [C(LL)] = {
451 [C(OP_READ)] = {
452 [C(RESULT_ACCESS)] = { 0x0208, PIC_UPPER | PIC_LOWER, },
453 [C(RESULT_MISS)] = { 0x0330, PIC_UPPER | PIC_LOWER, },
454 },
455 [C(OP_WRITE)] = {
456 [C(RESULT_ACCESS)] = { 0x0210, PIC_UPPER | PIC_LOWER, },
457 [C(RESULT_MISS)] = { 0x0320, PIC_UPPER | PIC_LOWER, },
458 },
459 [C(OP_PREFETCH)] = {
460 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
461 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
462 },
463 },
464 [C(DTLB)] = {
465 [C(OP_READ)] = {
466 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
467 [C(RESULT_MISS)] = { 0x0b08, PIC_UPPER | PIC_LOWER, },
468 },
469 [ C(OP_WRITE) ] = {
470 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
471 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
472 },
473 [ C(OP_PREFETCH) ] = {
474 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
475 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
476 },
477 },
478 [C(ITLB)] = {
479 [C(OP_READ)] = {
480 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
481 [C(RESULT_MISS)] = { 0xb04, PIC_UPPER | PIC_LOWER, },
482 },
483 [ C(OP_WRITE) ] = {
484 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
485 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
486 },
487 [ C(OP_PREFETCH) ] = {
488 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
489 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
490 },
491 },
492 [C(BPU)] = {
493 [C(OP_READ)] = {
494 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
495 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
496 },
497 [ C(OP_WRITE) ] = {
498 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
499 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
500 },
501 [ C(OP_PREFETCH) ] = {
502 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
503 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
504 },
505 },
506 [C(NODE)] = {
507 [C(OP_READ)] = {
508 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
509 [C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
510 },
511 [ C(OP_WRITE) ] = {
512 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
513 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
514 },
515 [ C(OP_PREFETCH) ] = {
516 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
517 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
518 },
519 },
520 };
521
522 static const struct sparc_pmu niagara2_pmu = {
523 .event_map = niagara2_event_map,
524 .cache_map = &niagara2_cache_map,
525 .max_events = ARRAY_SIZE(niagara2_perfmon_event_map),
526 .upper_shift = 19,
527 .lower_shift = 6,
528 .event_mask = 0xfff,
529 .hv_bit = 0x8,
530 .irq_bit = 0x30,
531 .upper_nop = 0x220,
532 .lower_nop = 0x220,
533 };
534
535 static const struct sparc_pmu *sparc_pmu __read_mostly;
536
537 static u64 event_encoding(u64 event_id, int idx)
538 {
539 if (idx == PIC_UPPER_INDEX)
540 event_id <<= sparc_pmu->upper_shift;
541 else
542 event_id <<= sparc_pmu->lower_shift;
543 return event_id;
544 }
545
546 static u64 mask_for_index(int idx)
547 {
548 return event_encoding(sparc_pmu->event_mask, idx);
549 }
550
551 static u64 nop_for_index(int idx)
552 {
553 return event_encoding(idx == PIC_UPPER_INDEX ?
554 sparc_pmu->upper_nop :
555 sparc_pmu->lower_nop, idx);
556 }
557
558 static inline void sparc_pmu_enable_event(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc, int idx)
559 {
560 u64 enc, val, mask = mask_for_index(idx);
561
562 enc = perf_event_get_enc(cpuc->events[idx]);
563
564 val = cpuc->pcr;
565 val &= ~mask;
566 val |= event_encoding(enc, idx);
567 cpuc->pcr = val;
568
569 pcr_ops->write(cpuc->pcr);
570 }
571
572 static inline void sparc_pmu_disable_event(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc, int idx)
573 {
574 u64 mask = mask_for_index(idx);
575 u64 nop = nop_for_index(idx);
576 u64 val;
577
578 val = cpuc->pcr;
579 val &= ~mask;
580 val |= nop;
581 cpuc->pcr = val;
582
583 pcr_ops->write(cpuc->pcr);
584 }
585
586 static u32 read_pmc(int idx)
587 {
588 u64 val;
589
590 read_pic(val);
591 if (idx == PIC_UPPER_INDEX)
592 val >>= 32;
593
594 return val & 0xffffffff;
595 }
596
597 static void write_pmc(int idx, u64 val)
598 {
599 u64 shift, mask, pic;
600
601 shift = 0;
602 if (idx == PIC_UPPER_INDEX)
603 shift = 32;
604
605 mask = ((u64) 0xffffffff) << shift;
606 val <<= shift;
607
608 read_pic(pic);
609 pic &= ~mask;
610 pic |= val;
611 write_pic(pic);
612 }
613
614 static u64 sparc_perf_event_update(struct perf_event *event,
615 struct hw_perf_event *hwc, int idx)
616 {
617 int shift = 64 - 32;
618 u64 prev_raw_count, new_raw_count;
619 s64 delta;
620
621 again:
622 prev_raw_count = local64_read(&hwc->prev_count);
623 new_raw_count = read_pmc(idx);
624
625 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
626 new_raw_count) != prev_raw_count)
627 goto again;
628
629 delta = (new_raw_count << shift) - (prev_raw_count << shift);
630 delta >>= shift;
631
632 local64_add(delta, &event->count);
633 local64_sub(delta, &hwc->period_left);
634
635 return new_raw_count;
636 }
637
638 static int sparc_perf_event_set_period(struct perf_event *event,
639 struct hw_perf_event *hwc, int idx)
640 {
641 s64 left = local64_read(&hwc->period_left);
642 s64 period = hwc->sample_period;
643 int ret = 0;
644
645 if (unlikely(left <= -period)) {
646 left = period;
647 local64_set(&hwc->period_left, left);
648 hwc->last_period = period;
649 ret = 1;
650 }
651
652 if (unlikely(left <= 0)) {
653 left += period;
654 local64_set(&hwc->period_left, left);
655 hwc->last_period = period;
656 ret = 1;
657 }
658 if (left > MAX_PERIOD)
659 left = MAX_PERIOD;
660
661 local64_set(&hwc->prev_count, (u64)-left);
662
663 write_pmc(idx, (u64)(-left) & 0xffffffff);
664
665 perf_event_update_userpage(event);
666
667 return ret;
668 }
669
670 /* If performance event entries have been added, move existing
671 * events around (if necessary) and then assign new entries to
672 * counters.
673 */
674 static u64 maybe_change_configuration(struct cpu_hw_events *cpuc, u64 pcr)
675 {
676 int i;
677
678 if (!cpuc->n_added)
679 goto out;
680
681 /* Read in the counters which are moving. */
682 for (i = 0; i < cpuc->n_events; i++) {
683 struct perf_event *cp = cpuc->event[i];
684
685 if (cpuc->current_idx[i] != PIC_NO_INDEX &&
686 cpuc->current_idx[i] != cp->hw.idx) {
687 sparc_perf_event_update(cp, &cp->hw,
688 cpuc->current_idx[i]);
689 cpuc->current_idx[i] = PIC_NO_INDEX;
690 }
691 }
692
693 /* Assign to counters all unassigned events. */
694 for (i = 0; i < cpuc->n_events; i++) {
695 struct perf_event *cp = cpuc->event[i];
696 struct hw_perf_event *hwc = &cp->hw;
697 int idx = hwc->idx;
698 u64 enc;
699
700 if (cpuc->current_idx[i] != PIC_NO_INDEX)
701 continue;
702
703 sparc_perf_event_set_period(cp, hwc, idx);
704 cpuc->current_idx[i] = idx;
705
706 enc = perf_event_get_enc(cpuc->events[i]);
707 pcr &= ~mask_for_index(idx);
708 if (hwc->state & PERF_HES_STOPPED)
709 pcr |= nop_for_index(idx);
710 else
711 pcr |= event_encoding(enc, idx);
712 }
713 out:
714 return pcr;
715 }
716
717 static void sparc_pmu_enable(struct pmu *pmu)
718 {
719 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
720 u64 pcr;
721
722 if (cpuc->enabled)
723 return;
724
725 cpuc->enabled = 1;
726 barrier();
727
728 pcr = cpuc->pcr;
729 if (!cpuc->n_events) {
730 pcr = 0;
731 } else {
732 pcr = maybe_change_configuration(cpuc, pcr);
733
734 /* We require that all of the events have the same
735 * configuration, so just fetch the settings from the
736 * first entry.
737 */
738 cpuc->pcr = pcr | cpuc->event[0]->hw.config_base;
739 }
740
741 pcr_ops->write(cpuc->pcr);
742 }
743
744 static void sparc_pmu_disable(struct pmu *pmu)
745 {
746 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
747 u64 val;
748
749 if (!cpuc->enabled)
750 return;
751
752 cpuc->enabled = 0;
753 cpuc->n_added = 0;
754
755 val = cpuc->pcr;
756 val &= ~(PCR_UTRACE | PCR_STRACE |
757 sparc_pmu->hv_bit | sparc_pmu->irq_bit);
758 cpuc->pcr = val;
759
760 pcr_ops->write(cpuc->pcr);
761 }
762
763 static int active_event_index(struct cpu_hw_events *cpuc,
764 struct perf_event *event)
765 {
766 int i;
767
768 for (i = 0; i < cpuc->n_events; i++) {
769 if (cpuc->event[i] == event)
770 break;
771 }
772 BUG_ON(i == cpuc->n_events);
773 return cpuc->current_idx[i];
774 }
775
776 static void sparc_pmu_start(struct perf_event *event, int flags)
777 {
778 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
779 int idx = active_event_index(cpuc, event);
780
781 if (flags & PERF_EF_RELOAD) {
782 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
783 sparc_perf_event_set_period(event, &event->hw, idx);
784 }
785
786 event->hw.state = 0;
787
788 sparc_pmu_enable_event(cpuc, &event->hw, idx);
789 }
790
791 static void sparc_pmu_stop(struct perf_event *event, int flags)
792 {
793 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
794 int idx = active_event_index(cpuc, event);
795
796 if (!(event->hw.state & PERF_HES_STOPPED)) {
797 sparc_pmu_disable_event(cpuc, &event->hw, idx);
798 event->hw.state |= PERF_HES_STOPPED;
799 }
800
801 if (!(event->hw.state & PERF_HES_UPTODATE) && (flags & PERF_EF_UPDATE)) {
802 sparc_perf_event_update(event, &event->hw, idx);
803 event->hw.state |= PERF_HES_UPTODATE;
804 }
805 }
806
807 static void sparc_pmu_del(struct perf_event *event, int _flags)
808 {
809 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
810 unsigned long flags;
811 int i;
812
813 local_irq_save(flags);
814 perf_pmu_disable(event->pmu);
815
816 for (i = 0; i < cpuc->n_events; i++) {
817 if (event == cpuc->event[i]) {
818 /* Absorb the final count and turn off the
819 * event.
820 */
821 sparc_pmu_stop(event, PERF_EF_UPDATE);
822
823 /* Shift remaining entries down into
824 * the existing slot.
825 */
826 while (++i < cpuc->n_events) {
827 cpuc->event[i - 1] = cpuc->event[i];
828 cpuc->events[i - 1] = cpuc->events[i];
829 cpuc->current_idx[i - 1] =
830 cpuc->current_idx[i];
831 }
832
833 perf_event_update_userpage(event);
834
835 cpuc->n_events--;
836 break;
837 }
838 }
839
840 perf_pmu_enable(event->pmu);
841 local_irq_restore(flags);
842 }
843
844 static void sparc_pmu_read(struct perf_event *event)
845 {
846 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
847 int idx = active_event_index(cpuc, event);
848 struct hw_perf_event *hwc = &event->hw;
849
850 sparc_perf_event_update(event, hwc, idx);
851 }
852
853 static atomic_t active_events = ATOMIC_INIT(0);
854 static DEFINE_MUTEX(pmc_grab_mutex);
855
856 static void perf_stop_nmi_watchdog(void *unused)
857 {
858 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
859
860 stop_nmi_watchdog(NULL);
861 cpuc->pcr = pcr_ops->read();
862 }
863
864 void perf_event_grab_pmc(void)
865 {
866 if (atomic_inc_not_zero(&active_events))
867 return;
868
869 mutex_lock(&pmc_grab_mutex);
870 if (atomic_read(&active_events) == 0) {
871 if (atomic_read(&nmi_active) > 0) {
872 on_each_cpu(perf_stop_nmi_watchdog, NULL, 1);
873 BUG_ON(atomic_read(&nmi_active) != 0);
874 }
875 atomic_inc(&active_events);
876 }
877 mutex_unlock(&pmc_grab_mutex);
878 }
879
880 void perf_event_release_pmc(void)
881 {
882 if (atomic_dec_and_mutex_lock(&active_events, &pmc_grab_mutex)) {
883 if (atomic_read(&nmi_active) == 0)
884 on_each_cpu(start_nmi_watchdog, NULL, 1);
885 mutex_unlock(&pmc_grab_mutex);
886 }
887 }
888
889 static const struct perf_event_map *sparc_map_cache_event(u64 config)
890 {
891 unsigned int cache_type, cache_op, cache_result;
892 const struct perf_event_map *pmap;
893
894 if (!sparc_pmu->cache_map)
895 return ERR_PTR(-ENOENT);
896
897 cache_type = (config >> 0) & 0xff;
898 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
899 return ERR_PTR(-EINVAL);
900
901 cache_op = (config >> 8) & 0xff;
902 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
903 return ERR_PTR(-EINVAL);
904
905 cache_result = (config >> 16) & 0xff;
906 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
907 return ERR_PTR(-EINVAL);
908
909 pmap = &((*sparc_pmu->cache_map)[cache_type][cache_op][cache_result]);
910
911 if (pmap->encoding == CACHE_OP_UNSUPPORTED)
912 return ERR_PTR(-ENOENT);
913
914 if (pmap->encoding == CACHE_OP_NONSENSE)
915 return ERR_PTR(-EINVAL);
916
917 return pmap;
918 }
919
920 static void hw_perf_event_destroy(struct perf_event *event)
921 {
922 perf_event_release_pmc();
923 }
924
925 /* Make sure all events can be scheduled into the hardware at
926 * the same time. This is simplified by the fact that we only
927 * need to support 2 simultaneous HW events.
928 *
929 * As a side effect, the evts[]->hw.idx values will be assigned
930 * on success. These are pending indexes. When the events are
931 * actually programmed into the chip, these values will propagate
932 * to the per-cpu cpuc->current_idx[] slots, see the code in
933 * maybe_change_configuration() for details.
934 */
935 static int sparc_check_constraints(struct perf_event **evts,
936 unsigned long *events, int n_ev)
937 {
938 u8 msk0 = 0, msk1 = 0;
939 int idx0 = 0;
940
941 /* This case is possible when we are invoked from
942 * hw_perf_group_sched_in().
943 */
944 if (!n_ev)
945 return 0;
946
947 if (n_ev > MAX_HWEVENTS)
948 return -1;
949
950 msk0 = perf_event_get_msk(events[0]);
951 if (n_ev == 1) {
952 if (msk0 & PIC_LOWER)
953 idx0 = 1;
954 goto success;
955 }
956 BUG_ON(n_ev != 2);
957 msk1 = perf_event_get_msk(events[1]);
958
959 /* If both events can go on any counter, OK. */
960 if (msk0 == (PIC_UPPER | PIC_LOWER) &&
961 msk1 == (PIC_UPPER | PIC_LOWER))
962 goto success;
963
964 /* If one event is limited to a specific counter,
965 * and the other can go on both, OK.
966 */
967 if ((msk0 == PIC_UPPER || msk0 == PIC_LOWER) &&
968 msk1 == (PIC_UPPER | PIC_LOWER)) {
969 if (msk0 & PIC_LOWER)
970 idx0 = 1;
971 goto success;
972 }
973
974 if ((msk1 == PIC_UPPER || msk1 == PIC_LOWER) &&
975 msk0 == (PIC_UPPER | PIC_LOWER)) {
976 if (msk1 & PIC_UPPER)
977 idx0 = 1;
978 goto success;
979 }
980
981 /* If the events are fixed to different counters, OK. */
982 if ((msk0 == PIC_UPPER && msk1 == PIC_LOWER) ||
983 (msk0 == PIC_LOWER && msk1 == PIC_UPPER)) {
984 if (msk0 & PIC_LOWER)
985 idx0 = 1;
986 goto success;
987 }
988
989 /* Otherwise, there is a conflict. */
990 return -1;
991
992 success:
993 evts[0]->hw.idx = idx0;
994 if (n_ev == 2)
995 evts[1]->hw.idx = idx0 ^ 1;
996 return 0;
997 }
998
999 static int check_excludes(struct perf_event **evts, int n_prev, int n_new)
1000 {
1001 int eu = 0, ek = 0, eh = 0;
1002 struct perf_event *event;
1003 int i, n, first;
1004
1005 n = n_prev + n_new;
1006 if (n <= 1)
1007 return 0;
1008
1009 first = 1;
1010 for (i = 0; i < n; i++) {
1011 event = evts[i];
1012 if (first) {
1013 eu = event->attr.exclude_user;
1014 ek = event->attr.exclude_kernel;
1015 eh = event->attr.exclude_hv;
1016 first = 0;
1017 } else if (event->attr.exclude_user != eu ||
1018 event->attr.exclude_kernel != ek ||
1019 event->attr.exclude_hv != eh) {
1020 return -EAGAIN;
1021 }
1022 }
1023
1024 return 0;
1025 }
1026
1027 static int collect_events(struct perf_event *group, int max_count,
1028 struct perf_event *evts[], unsigned long *events,
1029 int *current_idx)
1030 {
1031 struct perf_event *event;
1032 int n = 0;
1033
1034 if (!is_software_event(group)) {
1035 if (n >= max_count)
1036 return -1;
1037 evts[n] = group;
1038 events[n] = group->hw.event_base;
1039 current_idx[n++] = PIC_NO_INDEX;
1040 }
1041 list_for_each_entry(event, &group->sibling_list, group_entry) {
1042 if (!is_software_event(event) &&
1043 event->state != PERF_EVENT_STATE_OFF) {
1044 if (n >= max_count)
1045 return -1;
1046 evts[n] = event;
1047 events[n] = event->hw.event_base;
1048 current_idx[n++] = PIC_NO_INDEX;
1049 }
1050 }
1051 return n;
1052 }
1053
1054 static int sparc_pmu_add(struct perf_event *event, int ef_flags)
1055 {
1056 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1057 int n0, ret = -EAGAIN;
1058 unsigned long flags;
1059
1060 local_irq_save(flags);
1061 perf_pmu_disable(event->pmu);
1062
1063 n0 = cpuc->n_events;
1064 if (n0 >= MAX_HWEVENTS)
1065 goto out;
1066
1067 cpuc->event[n0] = event;
1068 cpuc->events[n0] = event->hw.event_base;
1069 cpuc->current_idx[n0] = PIC_NO_INDEX;
1070
1071 event->hw.state = PERF_HES_UPTODATE;
1072 if (!(ef_flags & PERF_EF_START))
1073 event->hw.state |= PERF_HES_STOPPED;
1074
1075 /*
1076 * If group events scheduling transaction was started,
1077 * skip the schedulability test here, it will be performed
1078 * at commit time(->commit_txn) as a whole
1079 */
1080 if (cpuc->group_flag & PERF_EVENT_TXN)
1081 goto nocheck;
1082
1083 if (check_excludes(cpuc->event, n0, 1))
1084 goto out;
1085 if (sparc_check_constraints(cpuc->event, cpuc->events, n0 + 1))
1086 goto out;
1087
1088 nocheck:
1089 cpuc->n_events++;
1090 cpuc->n_added++;
1091
1092 ret = 0;
1093 out:
1094 perf_pmu_enable(event->pmu);
1095 local_irq_restore(flags);
1096 return ret;
1097 }
1098
1099 static int sparc_pmu_event_init(struct perf_event *event)
1100 {
1101 struct perf_event_attr *attr = &event->attr;
1102 struct perf_event *evts[MAX_HWEVENTS];
1103 struct hw_perf_event *hwc = &event->hw;
1104 unsigned long events[MAX_HWEVENTS];
1105 int current_idx_dmy[MAX_HWEVENTS];
1106 const struct perf_event_map *pmap;
1107 int n;
1108
1109 if (atomic_read(&nmi_active) < 0)
1110 return -ENODEV;
1111
1112 /* does not support taken branch sampling */
1113 if (has_branch_stack(event))
1114 return -EOPNOTSUPP;
1115
1116 switch (attr->type) {
1117 case PERF_TYPE_HARDWARE:
1118 if (attr->config >= sparc_pmu->max_events)
1119 return -EINVAL;
1120 pmap = sparc_pmu->event_map(attr->config);
1121 break;
1122
1123 case PERF_TYPE_HW_CACHE:
1124 pmap = sparc_map_cache_event(attr->config);
1125 if (IS_ERR(pmap))
1126 return PTR_ERR(pmap);
1127 break;
1128
1129 case PERF_TYPE_RAW:
1130 pmap = NULL;
1131 break;
1132
1133 default:
1134 return -ENOENT;
1135
1136 }
1137
1138 if (pmap) {
1139 hwc->event_base = perf_event_encode(pmap);
1140 } else {
1141 /*
1142 * User gives us "(encoding << 16) | pic_mask" for
1143 * PERF_TYPE_RAW events.
1144 */
1145 hwc->event_base = attr->config;
1146 }
1147
1148 /* We save the enable bits in the config_base. */
1149 hwc->config_base = sparc_pmu->irq_bit;
1150 if (!attr->exclude_user)
1151 hwc->config_base |= PCR_UTRACE;
1152 if (!attr->exclude_kernel)
1153 hwc->config_base |= PCR_STRACE;
1154 if (!attr->exclude_hv)
1155 hwc->config_base |= sparc_pmu->hv_bit;
1156
1157 n = 0;
1158 if (event->group_leader != event) {
1159 n = collect_events(event->group_leader,
1160 MAX_HWEVENTS - 1,
1161 evts, events, current_idx_dmy);
1162 if (n < 0)
1163 return -EINVAL;
1164 }
1165 events[n] = hwc->event_base;
1166 evts[n] = event;
1167
1168 if (check_excludes(evts, n, 1))
1169 return -EINVAL;
1170
1171 if (sparc_check_constraints(evts, events, n + 1))
1172 return -EINVAL;
1173
1174 hwc->idx = PIC_NO_INDEX;
1175
1176 /* Try to do all error checking before this point, as unwinding
1177 * state after grabbing the PMC is difficult.
1178 */
1179 perf_event_grab_pmc();
1180 event->destroy = hw_perf_event_destroy;
1181
1182 if (!hwc->sample_period) {
1183 hwc->sample_period = MAX_PERIOD;
1184 hwc->last_period = hwc->sample_period;
1185 local64_set(&hwc->period_left, hwc->sample_period);
1186 }
1187
1188 return 0;
1189 }
1190
1191 /*
1192 * Start group events scheduling transaction
1193 * Set the flag to make pmu::enable() not perform the
1194 * schedulability test, it will be performed at commit time
1195 */
1196 static void sparc_pmu_start_txn(struct pmu *pmu)
1197 {
1198 struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events);
1199
1200 perf_pmu_disable(pmu);
1201 cpuhw->group_flag |= PERF_EVENT_TXN;
1202 }
1203
1204 /*
1205 * Stop group events scheduling transaction
1206 * Clear the flag and pmu::enable() will perform the
1207 * schedulability test.
1208 */
1209 static void sparc_pmu_cancel_txn(struct pmu *pmu)
1210 {
1211 struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events);
1212
1213 cpuhw->group_flag &= ~PERF_EVENT_TXN;
1214 perf_pmu_enable(pmu);
1215 }
1216
1217 /*
1218 * Commit group events scheduling transaction
1219 * Perform the group schedulability test as a whole
1220 * Return 0 if success
1221 */
1222 static int sparc_pmu_commit_txn(struct pmu *pmu)
1223 {
1224 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1225 int n;
1226
1227 if (!sparc_pmu)
1228 return -EINVAL;
1229
1230 cpuc = &__get_cpu_var(cpu_hw_events);
1231 n = cpuc->n_events;
1232 if (check_excludes(cpuc->event, 0, n))
1233 return -EINVAL;
1234 if (sparc_check_constraints(cpuc->event, cpuc->events, n))
1235 return -EAGAIN;
1236
1237 cpuc->group_flag &= ~PERF_EVENT_TXN;
1238 perf_pmu_enable(pmu);
1239 return 0;
1240 }
1241
1242 static struct pmu pmu = {
1243 .pmu_enable = sparc_pmu_enable,
1244 .pmu_disable = sparc_pmu_disable,
1245 .event_init = sparc_pmu_event_init,
1246 .add = sparc_pmu_add,
1247 .del = sparc_pmu_del,
1248 .start = sparc_pmu_start,
1249 .stop = sparc_pmu_stop,
1250 .read = sparc_pmu_read,
1251 .start_txn = sparc_pmu_start_txn,
1252 .cancel_txn = sparc_pmu_cancel_txn,
1253 .commit_txn = sparc_pmu_commit_txn,
1254 };
1255
1256 void perf_event_print_debug(void)
1257 {
1258 unsigned long flags;
1259 u64 pcr, pic;
1260 int cpu;
1261
1262 if (!sparc_pmu)
1263 return;
1264
1265 local_irq_save(flags);
1266
1267 cpu = smp_processor_id();
1268
1269 pcr = pcr_ops->read();
1270 read_pic(pic);
1271
1272 pr_info("\n");
1273 pr_info("CPU#%d: PCR[%016llx] PIC[%016llx]\n",
1274 cpu, pcr, pic);
1275
1276 local_irq_restore(flags);
1277 }
1278
1279 static int __kprobes perf_event_nmi_handler(struct notifier_block *self,
1280 unsigned long cmd, void *__args)
1281 {
1282 struct die_args *args = __args;
1283 struct perf_sample_data data;
1284 struct cpu_hw_events *cpuc;
1285 struct pt_regs *regs;
1286 int i;
1287
1288 if (!atomic_read(&active_events))
1289 return NOTIFY_DONE;
1290
1291 switch (cmd) {
1292 case DIE_NMI:
1293 break;
1294
1295 default:
1296 return NOTIFY_DONE;
1297 }
1298
1299 regs = args->regs;
1300
1301 cpuc = &__get_cpu_var(cpu_hw_events);
1302
1303 /* If the PMU has the TOE IRQ enable bits, we need to do a
1304 * dummy write to the %pcr to clear the overflow bits and thus
1305 * the interrupt.
1306 *
1307 * Do this before we peek at the counters to determine
1308 * overflow so we don't lose any events.
1309 */
1310 if (sparc_pmu->irq_bit)
1311 pcr_ops->write(cpuc->pcr);
1312
1313 for (i = 0; i < cpuc->n_events; i++) {
1314 struct perf_event *event = cpuc->event[i];
1315 int idx = cpuc->current_idx[i];
1316 struct hw_perf_event *hwc;
1317 u64 val;
1318
1319 hwc = &event->hw;
1320 val = sparc_perf_event_update(event, hwc, idx);
1321 if (val & (1ULL << 31))
1322 continue;
1323
1324 perf_sample_data_init(&data, 0, hwc->last_period);
1325 if (!sparc_perf_event_set_period(event, hwc, idx))
1326 continue;
1327
1328 if (perf_event_overflow(event, &data, regs))
1329 sparc_pmu_stop(event, 0);
1330 }
1331
1332 return NOTIFY_STOP;
1333 }
1334
1335 static __read_mostly struct notifier_block perf_event_nmi_notifier = {
1336 .notifier_call = perf_event_nmi_handler,
1337 };
1338
1339 static bool __init supported_pmu(void)
1340 {
1341 if (!strcmp(sparc_pmu_type, "ultra3") ||
1342 !strcmp(sparc_pmu_type, "ultra3+") ||
1343 !strcmp(sparc_pmu_type, "ultra3i") ||
1344 !strcmp(sparc_pmu_type, "ultra4+")) {
1345 sparc_pmu = &ultra3_pmu;
1346 return true;
1347 }
1348 if (!strcmp(sparc_pmu_type, "niagara")) {
1349 sparc_pmu = &niagara1_pmu;
1350 return true;
1351 }
1352 if (!strcmp(sparc_pmu_type, "niagara2") ||
1353 !strcmp(sparc_pmu_type, "niagara3")) {
1354 sparc_pmu = &niagara2_pmu;
1355 return true;
1356 }
1357 return false;
1358 }
1359
1360 int __init init_hw_perf_events(void)
1361 {
1362 pr_info("Performance events: ");
1363
1364 if (!supported_pmu()) {
1365 pr_cont("No support for PMU type '%s'\n", sparc_pmu_type);
1366 return 0;
1367 }
1368
1369 pr_cont("Supported PMU type is '%s'\n", sparc_pmu_type);
1370
1371 perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1372 register_die_notifier(&perf_event_nmi_notifier);
1373
1374 return 0;
1375 }
1376 early_initcall(init_hw_perf_events);
1377
1378 void perf_callchain_kernel(struct perf_callchain_entry *entry,
1379 struct pt_regs *regs)
1380 {
1381 unsigned long ksp, fp;
1382 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1383 int graph = 0;
1384 #endif
1385
1386 stack_trace_flush();
1387
1388 perf_callchain_store(entry, regs->tpc);
1389
1390 ksp = regs->u_regs[UREG_I6];
1391 fp = ksp + STACK_BIAS;
1392 do {
1393 struct sparc_stackf *sf;
1394 struct pt_regs *regs;
1395 unsigned long pc;
1396
1397 if (!kstack_valid(current_thread_info(), fp))
1398 break;
1399
1400 sf = (struct sparc_stackf *) fp;
1401 regs = (struct pt_regs *) (sf + 1);
1402
1403 if (kstack_is_trap_frame(current_thread_info(), regs)) {
1404 if (user_mode(regs))
1405 break;
1406 pc = regs->tpc;
1407 fp = regs->u_regs[UREG_I6] + STACK_BIAS;
1408 } else {
1409 pc = sf->callers_pc;
1410 fp = (unsigned long)sf->fp + STACK_BIAS;
1411 }
1412 perf_callchain_store(entry, pc);
1413 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1414 if ((pc + 8UL) == (unsigned long) &return_to_handler) {
1415 int index = current->curr_ret_stack;
1416 if (current->ret_stack && index >= graph) {
1417 pc = current->ret_stack[index - graph].ret;
1418 perf_callchain_store(entry, pc);
1419 graph++;
1420 }
1421 }
1422 #endif
1423 } while (entry->nr < PERF_MAX_STACK_DEPTH);
1424 }
1425
1426 static void perf_callchain_user_64(struct perf_callchain_entry *entry,
1427 struct pt_regs *regs)
1428 {
1429 unsigned long ufp;
1430
1431 ufp = regs->u_regs[UREG_I6] + STACK_BIAS;
1432 do {
1433 struct sparc_stackf *usf, sf;
1434 unsigned long pc;
1435
1436 usf = (struct sparc_stackf *) ufp;
1437 if (__copy_from_user_inatomic(&sf, usf, sizeof(sf)))
1438 break;
1439
1440 pc = sf.callers_pc;
1441 ufp = (unsigned long)sf.fp + STACK_BIAS;
1442 perf_callchain_store(entry, pc);
1443 } while (entry->nr < PERF_MAX_STACK_DEPTH);
1444 }
1445
1446 static void perf_callchain_user_32(struct perf_callchain_entry *entry,
1447 struct pt_regs *regs)
1448 {
1449 unsigned long ufp;
1450
1451 ufp = regs->u_regs[UREG_I6] & 0xffffffffUL;
1452 do {
1453 struct sparc_stackf32 *usf, sf;
1454 unsigned long pc;
1455
1456 usf = (struct sparc_stackf32 *) ufp;
1457 if (__copy_from_user_inatomic(&sf, usf, sizeof(sf)))
1458 break;
1459
1460 pc = sf.callers_pc;
1461 ufp = (unsigned long)sf.fp;
1462 perf_callchain_store(entry, pc);
1463 } while (entry->nr < PERF_MAX_STACK_DEPTH);
1464 }
1465
1466 void
1467 perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
1468 {
1469 perf_callchain_store(entry, regs->tpc);
1470
1471 if (!current->mm)
1472 return;
1473
1474 flushw_user();
1475 if (test_thread_flag(TIF_32BIT))
1476 perf_callchain_user_32(entry, regs);
1477 else
1478 perf_callchain_user_64(entry, regs);
1479 }
Linux ARM platform port for MOXA ART SoC