drivers/gpu/drm/radeon/radeon_legacy_encoders.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "drm_crtc_helper.h"
  28 #include "radeon_drm.h"
  29 #include "radeon.h"
  30 #include "atom.h"
  31 #include <linux/backlight.h>
  32 #ifdef CONFIG_PMAC_BACKLIGHT
  33 #include <asm/backlight.h>
  34 #endif
  35
  36 static void radeon_legacy_encoder_disable(struct drm_encoder *encoder)
  37 {
  38         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  39         struct drm_encoder_helper_funcs *encoder_funcs;
  40
  41         encoder_funcs = encoder->helper_private;
  42         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
  43         radeon_encoder->active_device = 0;
  44 }
  45
  46 static void radeon_legacy_lvds_update(struct drm_encoder *encoder, int mode)
  47 {
  48         struct drm_device *dev = encoder->dev;
  49         struct radeon_device *rdev = dev->dev_private;
  50         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  51         uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man;
  52         int panel_pwr_delay = 2000;
  53         bool is_mac = false;
  54         uint8_t backlight_level;
  55         DRM_DEBUG_KMS("\n");
  56
  57         lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
  58         backlight_level = (lvds_gen_cntl >> RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
  59
  60         if (radeon_encoder->enc_priv) {
  61                 if (rdev->is_atom_bios) {
  62                         struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
  63                         panel_pwr_delay = lvds->panel_pwr_delay;
  64                         if (lvds->bl_dev)
  65                                 backlight_level = lvds->backlight_level;
  66                 } else {
  67                         struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
  68                         panel_pwr_delay = lvds->panel_pwr_delay;
  69                         if (lvds->bl_dev)
  70                                 backlight_level = lvds->backlight_level;
  71                 }
  72         }
  73
  74         /* macs (and possibly some x86 oem systems?) wire up LVDS strangely
  75          * Taken from radeonfb.
  76          */
  77         if ((rdev->mode_info.connector_table == CT_IBOOK) ||
  78             (rdev->mode_info.connector_table == CT_POWERBOOK_EXTERNAL) ||
  79             (rdev->mode_info.connector_table == CT_POWERBOOK_INTERNAL) ||
  80             (rdev->mode_info.connector_table == CT_POWERBOOK_VGA))
  81                 is_mac = true;
  82
  83         switch (mode) {
  84         case DRM_MODE_DPMS_ON:
  85                 disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN);
  86                 disp_pwr_man |= RADEON_AUTO_PWRUP_EN;
  87                 WREG32(RADEON_DISP_PWR_MAN, disp_pwr_man);
  88                 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
  89                 lvds_pll_cntl |= RADEON_LVDS_PLL_EN;
  90                 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
  91                 mdelay(1);
  92
  93                 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
  94                 lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET;
  95                 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
  96
  97                 lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS |
  98                                    RADEON_LVDS_BL_MOD_LEVEL_MASK);
  99                 lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_EN |
 100                                   RADEON_LVDS_DIGON | RADEON_LVDS_BLON |
 101                                   (backlight_level << RADEON_LVDS_BL_MOD_LEVEL_SHIFT));
 102                 if (is_mac)
 103                         lvds_gen_cntl |= RADEON_LVDS_BL_MOD_EN;
 104                 mdelay(panel_pwr_delay);
 105                 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
 106                 break;
 107         case DRM_MODE_DPMS_STANDBY:
 108         case DRM_MODE_DPMS_SUSPEND:
 109         case DRM_MODE_DPMS_OFF:
 110                 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
 111                 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
 112                 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
 113                 if (is_mac) {
 114                         lvds_gen_cntl &= ~RADEON_LVDS_BL_MOD_EN;
 115                         WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
 116                         lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_EN);
 117                 } else {
 118                         WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
 119                         lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON);
 120                 }
 121                 mdelay(panel_pwr_delay);
 122                 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
 123                 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
 124                 mdelay(panel_pwr_delay);
 125                 break;
 126         }
 127
 128         if (rdev->is_atom_bios)
 129                 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 130         else
 131                 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 132
 133 }
 134
 135 static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
 136 {
 137         struct radeon_device *rdev = encoder->dev->dev_private;
 138         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 139         DRM_DEBUG("\n");
 140
 141         if (radeon_encoder->enc_priv) {
 142                 if (rdev->is_atom_bios) {
 143                         struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
 144                         lvds->dpms_mode = mode;
 145                 } else {
 146                         struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
 147                         lvds->dpms_mode = mode;
 148                 }
 149         }
 150
 151         radeon_legacy_lvds_update(encoder, mode);
 152 }
 153
 154 static void radeon_legacy_lvds_prepare(struct drm_encoder *encoder)
 155 {
 156         struct radeon_device *rdev = encoder->dev->dev_private;
 157
 158         if (rdev->is_atom_bios)
 159                 radeon_atom_output_lock(encoder, true);
 160         else
 161                 radeon_combios_output_lock(encoder, true);
 162         radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_OFF);
 163 }
 164
 165 static void radeon_legacy_lvds_commit(struct drm_encoder *encoder)
 166 {
 167         struct radeon_device *rdev = encoder->dev->dev_private;
 168
 169         radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_ON);
 170         if (rdev->is_atom_bios)
 171                 radeon_atom_output_lock(encoder, false);
 172         else
 173                 radeon_combios_output_lock(encoder, false);
 174 }
 175
 176 static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder,
 177                                         struct drm_display_mode *mode,
 178                                         struct drm_display_mode *adjusted_mode)
 179 {
 180         struct drm_device *dev = encoder->dev;
 181         struct radeon_device *rdev = dev->dev_private;
 182         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 183         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 184         uint32_t lvds_pll_cntl, lvds_gen_cntl, lvds_ss_gen_cntl;
 185
 186         DRM_DEBUG_KMS("\n");
 187
 188         lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
 189         lvds_pll_cntl &= ~RADEON_LVDS_PLL_EN;
 190
 191         lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
 192         if (rdev->is_atom_bios) {
 193                 /* LVDS_GEN_CNTL parameters are computed in LVDSEncoderControl
 194                  * need to call that on resume to set up the reg properly.
 195                  */
 196                 radeon_encoder->pixel_clock = adjusted_mode->clock;
 197                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
 198                 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
 199         } else {
 200                 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
 201                 if (lvds) {
 202                         DRM_DEBUG_KMS("bios LVDS_GEN_CNTL: 0x%x\n", lvds->lvds_gen_cntl);
 203                         lvds_gen_cntl = lvds->lvds_gen_cntl;
 204                         lvds_ss_gen_cntl &= ~((0xf << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
 205                                               (0xf << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
 206                         lvds_ss_gen_cntl |= ((lvds->panel_digon_delay << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
 207                                              (lvds->panel_blon_delay << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
 208                 } else
 209                         lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
 210         }
 211         lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
 212         lvds_gen_cntl &= ~(RADEON_LVDS_ON |
 213                            RADEON_LVDS_BLON |
 214                            RADEON_LVDS_EN |
 215                            RADEON_LVDS_RST_FM);
 216
 217         if (ASIC_IS_R300(rdev))
 218                 lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK);
 219
 220         if (radeon_crtc->crtc_id == 0) {
 221                 if (ASIC_IS_R300(rdev)) {
 222                         if (radeon_encoder->rmx_type != RMX_OFF)
 223                                 lvds_pll_cntl |= R300_LVDS_SRC_SEL_RMX;
 224                 } else
 225                         lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2;
 226         } else {
 227                 if (ASIC_IS_R300(rdev))
 228                         lvds_pll_cntl |= R300_LVDS_SRC_SEL_CRTC2;
 229                 else
 230                         lvds_gen_cntl |= RADEON_LVDS_SEL_CRTC2;
 231         }
 232
 233         WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
 234         WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
 235         WREG32(RADEON_LVDS_SS_GEN_CNTL, lvds_ss_gen_cntl);
 236
 237         if (rdev->family == CHIP_RV410)
 238                 WREG32(RADEON_CLOCK_CNTL_INDEX, 0);
 239
 240         if (rdev->is_atom_bios)
 241                 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 242         else
 243                 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 244 }
 245
 246 static bool radeon_legacy_mode_fixup(struct drm_encoder *encoder,
 247                                      const struct drm_display_mode *mode,
 248                                      struct drm_display_mode *adjusted_mode)
 249 {
 250         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 251
 252         /* set the active encoder to connector routing */
 253         radeon_encoder_set_active_device(encoder);
 254         drm_mode_set_crtcinfo(adjusted_mode, 0);
 255
 256         /* get the native mode for LVDS */
 257         if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
 258                 radeon_panel_mode_fixup(encoder, adjusted_mode);
 259
 260         return true;
 261 }
 262
 263 static const struct drm_encoder_helper_funcs radeon_legacy_lvds_helper_funcs = {
 264         .dpms = radeon_legacy_lvds_dpms,
 265         .mode_fixup = radeon_legacy_mode_fixup,
 266         .prepare = radeon_legacy_lvds_prepare,
 267         .mode_set = radeon_legacy_lvds_mode_set,
 268         .commit = radeon_legacy_lvds_commit,
 269         .disable = radeon_legacy_encoder_disable,
 270 };
 271
 272 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
 273
 274 #define MAX_RADEON_LEVEL 0xFF
 275
 276 struct radeon_backlight_privdata {
 277         struct radeon_encoder *encoder;
 278         uint8_t negative;
 279 };
 280
 281 static uint8_t radeon_legacy_lvds_level(struct backlight_device *bd)
 282 {
 283         struct radeon_backlight_privdata *pdata = bl_get_data(bd);
 284         uint8_t level;
 285
 286         /* Convert brightness to hardware level */
 287         if (bd->props.brightness < 0)
 288                 level = 0;
 289         else if (bd->props.brightness > MAX_RADEON_LEVEL)
 290                 level = MAX_RADEON_LEVEL;
 291         else
 292                 level = bd->props.brightness;
 293
 294         if (pdata->negative)
 295                 level = MAX_RADEON_LEVEL - level;
 296
 297         return level;
 298 }
 299
 300 static int radeon_legacy_backlight_update_status(struct backlight_device *bd)
 301 {
 302         struct radeon_backlight_privdata *pdata = bl_get_data(bd);
 303         struct radeon_encoder *radeon_encoder = pdata->encoder;
 304         struct drm_device *dev = radeon_encoder->base.dev;
 305         struct radeon_device *rdev = dev->dev_private;
 306         int dpms_mode = DRM_MODE_DPMS_ON;
 307
 308         if (radeon_encoder->enc_priv) {
 309                 if (rdev->is_atom_bios) {
 310                         struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
 311                         dpms_mode = lvds->dpms_mode;
 312                         lvds->backlight_level = radeon_legacy_lvds_level(bd);
 313                 } else {
 314                         struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
 315                         dpms_mode = lvds->dpms_mode;
 316                         lvds->backlight_level = radeon_legacy_lvds_level(bd);
 317                 }
 318         }
 319
 320         if (bd->props.brightness > 0)
 321                 radeon_legacy_lvds_update(&radeon_encoder->base, dpms_mode);
 322         else
 323                 radeon_legacy_lvds_update(&radeon_encoder->base, DRM_MODE_DPMS_OFF);
 324
 325         return 0;
 326 }
 327
 328 static int radeon_legacy_backlight_get_brightness(struct backlight_device *bd)
 329 {
 330         struct radeon_backlight_privdata *pdata = bl_get_data(bd);
 331         struct radeon_encoder *radeon_encoder = pdata->encoder;
 332         struct drm_device *dev = radeon_encoder->base.dev;
 333         struct radeon_device *rdev = dev->dev_private;
 334         uint8_t backlight_level;
 335
 336         backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >>
 337                            RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
 338
 339         return pdata->negative ? MAX_RADEON_LEVEL - backlight_level : backlight_level;
 340 }
 341
 342 static const struct backlight_ops radeon_backlight_ops = {
 343         .get_brightness = radeon_legacy_backlight_get_brightness,
 344         .update_status  = radeon_legacy_backlight_update_status,
 345 };
 346
 347 void radeon_legacy_backlight_init(struct radeon_encoder *radeon_encoder,
 348                                   struct drm_connector *drm_connector)
 349 {
 350         struct drm_device *dev = radeon_encoder->base.dev;
 351         struct radeon_device *rdev = dev->dev_private;
 352         struct backlight_device *bd;
 353         struct backlight_properties props;
 354         struct radeon_backlight_privdata *pdata;
 355         uint8_t backlight_level;
 356
 357         if (!radeon_encoder->enc_priv)
 358                 return;
 359
 360 #ifdef CONFIG_PMAC_BACKLIGHT
 361         if (!pmac_has_backlight_type("ati") &&
 362             !pmac_has_backlight_type("mnca"))
 363                 return;
 364 #endif
 365
 366         pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL);
 367         if (!pdata) {
 368                 DRM_ERROR("Memory allocation failed\n");
 369                 goto error;
 370         }
 371
 372         memset(&props, 0, sizeof(props));
 373         props.max_brightness = MAX_RADEON_LEVEL;
 374         props.type = BACKLIGHT_RAW;
 375         bd = backlight_device_register("radeon_bl", &drm_connector->kdev,
 376                                        pdata, &radeon_backlight_ops, &props);
 377         if (IS_ERR(bd)) {
 378                 DRM_ERROR("Backlight registration failed\n");
 379                 goto error;
 380         }
 381
 382         pdata->encoder = radeon_encoder;
 383
 384         backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >>
 385                            RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
 386
 387         /* First, try to detect backlight level sense based on the assumption
 388          * that firmware set it up at full brightness
 389          */
 390         if (backlight_level == 0)
 391                 pdata->negative = true;
 392         else if (backlight_level == 0xff)
 393                 pdata->negative = false;
 394         else {
 395                 /* XXX hack... maybe some day we can figure out in what direction
 396                  * backlight should work on a given panel?
 397                  */
 398                 pdata->negative = (rdev->family != CHIP_RV200 &&
 399                                    rdev->family != CHIP_RV250 &&
 400                                    rdev->family != CHIP_RV280 &&
 401                                    rdev->family != CHIP_RV350);
 402
 403 #ifdef CONFIG_PMAC_BACKLIGHT
 404                 pdata->negative = (pdata->negative ||
 405                                    of_machine_is_compatible("PowerBook4,3") ||
 406                                    of_machine_is_compatible("PowerBook6,3") ||
 407                                    of_machine_is_compatible("PowerBook6,5"));
 408 #endif
 409         }
 410
 411         if (rdev->is_atom_bios) {
 412                 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
 413                 lvds->bl_dev = bd;
 414         } else {
 415                 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
 416                 lvds->bl_dev = bd;
 417         }
 418
 419         bd->props.brightness = radeon_legacy_backlight_get_brightness(bd);
 420         bd->props.power = FB_BLANK_UNBLANK;
 421         backlight_update_status(bd);
 422
 423         DRM_INFO("radeon legacy LVDS backlight initialized\n");
 424
 425         return;
 426
 427 error:
 428         kfree(pdata);
 429         return;
 430 }
 431
 432 static void radeon_legacy_backlight_exit(struct radeon_encoder *radeon_encoder)
 433 {
 434         struct drm_device *dev = radeon_encoder->base.dev;
 435         struct radeon_device *rdev = dev->dev_private;
 436         struct backlight_device *bd = NULL;
 437
 438         if (!radeon_encoder->enc_priv)
 439                 return;
 440
 441         if (rdev->is_atom_bios) {
 442                 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
 443                 bd = lvds->bl_dev;
 444                 lvds->bl_dev = NULL;
 445         } else {
 446                 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
 447                 bd = lvds->bl_dev;
 448                 lvds->bl_dev = NULL;
 449         }
 450
 451         if (bd) {
 452                 struct radeon_legacy_backlight_privdata *pdata;
 453
 454                 pdata = bl_get_data(bd);
 455                 backlight_device_unregister(bd);
 456                 kfree(pdata);
 457
 458                 DRM_INFO("radeon legacy LVDS backlight unloaded\n");
 459         }
 460 }
 461
 462 #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
 463
 464 void radeon_legacy_backlight_init(struct radeon_encoder *encoder)
 465 {
 466 }
 467
 468 static void radeon_legacy_backlight_exit(struct radeon_encoder *encoder)
 469 {
 470 }
 471
 472 #endif
 473
 474
 475 static void radeon_lvds_enc_destroy(struct drm_encoder *encoder)
 476 {
 477         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 478
 479         if (radeon_encoder->enc_priv) {
 480                 radeon_legacy_backlight_exit(radeon_encoder);
 481                 kfree(radeon_encoder->enc_priv);
 482         }
 483         drm_encoder_cleanup(encoder);
 484         kfree(radeon_encoder);
 485 }
 486
 487 static const struct drm_encoder_funcs radeon_legacy_lvds_enc_funcs = {
 488         .destroy = radeon_lvds_enc_destroy,
 489 };
 490
 491 static void radeon_legacy_primary_dac_dpms(struct drm_encoder *encoder, int mode)
 492 {
 493         struct drm_device *dev = encoder->dev;
 494         struct radeon_device *rdev = dev->dev_private;
 495         uint32_t crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
 496         uint32_t dac_cntl = RREG32(RADEON_DAC_CNTL);
 497         uint32_t dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
 498
 499         DRM_DEBUG_KMS("\n");
 500
 501         switch (mode) {
 502         case DRM_MODE_DPMS_ON:
 503                 crtc_ext_cntl |= RADEON_CRTC_CRT_ON;
 504                 dac_cntl &= ~RADEON_DAC_PDWN;
 505                 dac_macro_cntl &= ~(RADEON_DAC_PDWN_R |
 506                                     RADEON_DAC_PDWN_G |
 507                                     RADEON_DAC_PDWN_B);
 508                 break;
 509         case DRM_MODE_DPMS_STANDBY:
 510         case DRM_MODE_DPMS_SUSPEND:
 511         case DRM_MODE_DPMS_OFF:
 512                 crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON;
 513                 dac_cntl |= RADEON_DAC_PDWN;
 514                 dac_macro_cntl |= (RADEON_DAC_PDWN_R |
 515                                    RADEON_DAC_PDWN_G |
 516                                    RADEON_DAC_PDWN_B);
 517                 break;
 518         }
 519
 520         WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
 521         WREG32(RADEON_DAC_CNTL, dac_cntl);
 522         WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
 523
 524         if (rdev->is_atom_bios)
 525                 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 526         else
 527                 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 528
 529 }
 530
 531 static void radeon_legacy_primary_dac_prepare(struct drm_encoder *encoder)
 532 {
 533         struct radeon_device *rdev = encoder->dev->dev_private;
 534
 535         if (rdev->is_atom_bios)
 536                 radeon_atom_output_lock(encoder, true);
 537         else
 538                 radeon_combios_output_lock(encoder, true);
 539         radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
 540 }
 541
 542 static void radeon_legacy_primary_dac_commit(struct drm_encoder *encoder)
 543 {
 544         struct radeon_device *rdev = encoder->dev->dev_private;
 545
 546         radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_ON);
 547
 548         if (rdev->is_atom_bios)
 549                 radeon_atom_output_lock(encoder, false);
 550         else
 551                 radeon_combios_output_lock(encoder, false);
 552 }
 553
 554 static void radeon_legacy_primary_dac_mode_set(struct drm_encoder *encoder,
 555                                                struct drm_display_mode *mode,
 556                                                struct drm_display_mode *adjusted_mode)
 557 {
 558         struct drm_device *dev = encoder->dev;
 559         struct radeon_device *rdev = dev->dev_private;
 560         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 561         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 562         uint32_t disp_output_cntl, dac_cntl, dac2_cntl, dac_macro_cntl;
 563
 564         DRM_DEBUG_KMS("\n");
 565
 566         if (radeon_crtc->crtc_id == 0) {
 567                 if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) {
 568                         disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
 569                                 ~(RADEON_DISP_DAC_SOURCE_MASK);
 570                         WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
 571                 } else {
 572                         dac2_cntl = RREG32(RADEON_DAC_CNTL2)  & ~(RADEON_DAC2_DAC_CLK_SEL);
 573                         WREG32(RADEON_DAC_CNTL2, dac2_cntl);
 574                 }
 575         } else {
 576                 if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) {
 577                         disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
 578                                 ~(RADEON_DISP_DAC_SOURCE_MASK);
 579                         disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2;
 580                         WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
 581                 } else {
 582                         dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC_CLK_SEL;
 583                         WREG32(RADEON_DAC_CNTL2, dac2_cntl);
 584                 }
 585         }
 586
 587         dac_cntl = (RADEON_DAC_MASK_ALL |
 588                     RADEON_DAC_VGA_ADR_EN |
 589                     /* TODO 6-bits */
 590                     RADEON_DAC_8BIT_EN);
 591
 592         WREG32_P(RADEON_DAC_CNTL,
 593                        dac_cntl,
 594                        RADEON_DAC_RANGE_CNTL |
 595                        RADEON_DAC_BLANKING);
 596
 597         if (radeon_encoder->enc_priv) {
 598                 struct radeon_encoder_primary_dac *p_dac = (struct radeon_encoder_primary_dac *)radeon_encoder->enc_priv;
 599                 dac_macro_cntl = p_dac->ps2_pdac_adj;
 600         } else
 601                 dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
 602         dac_macro_cntl |= RADEON_DAC_PDWN_R | RADEON_DAC_PDWN_G | RADEON_DAC_PDWN_B;
 603         WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
 604
 605         if (rdev->is_atom_bios)
 606                 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 607         else
 608                 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 609 }
 610
 611 static enum drm_connector_status radeon_legacy_primary_dac_detect(struct drm_encoder *encoder,
 612                                                                   struct drm_connector *connector)
 613 {
 614         struct drm_device *dev = encoder->dev;
 615         struct radeon_device *rdev = dev->dev_private;
 616         uint32_t vclk_ecp_cntl, crtc_ext_cntl;
 617         uint32_t dac_ext_cntl, dac_cntl, dac_macro_cntl, tmp;
 618         enum drm_connector_status found = connector_status_disconnected;
 619         bool color = true;
 620
 621         /* save the regs we need */
 622         vclk_ecp_cntl = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
 623         crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
 624         dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
 625         dac_cntl = RREG32(RADEON_DAC_CNTL);
 626         dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
 627
 628         tmp = vclk_ecp_cntl &
 629                 ~(RADEON_PIXCLK_ALWAYS_ONb | RADEON_PIXCLK_DAC_ALWAYS_ONb);
 630         WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
 631
 632         tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON;
 633         WREG32(RADEON_CRTC_EXT_CNTL, tmp);
 634
 635         tmp = RADEON_DAC_FORCE_BLANK_OFF_EN |
 636                 RADEON_DAC_FORCE_DATA_EN;
 637
 638         if (color)
 639                 tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
 640         else
 641                 tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
 642
 643         if (ASIC_IS_R300(rdev))
 644                 tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
 645         else
 646                 tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
 647
 648         WREG32(RADEON_DAC_EXT_CNTL, tmp);
 649
 650         tmp = dac_cntl & ~(RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_PDWN);
 651         tmp |= RADEON_DAC_RANGE_CNTL_PS2 | RADEON_DAC_CMP_EN;
 652         WREG32(RADEON_DAC_CNTL, tmp);
 653
 654         tmp = dac_macro_cntl;
 655         tmp &= ~(RADEON_DAC_PDWN_R |
 656                  RADEON_DAC_PDWN_G |
 657                  RADEON_DAC_PDWN_B);
 658
 659         WREG32(RADEON_DAC_MACRO_CNTL, tmp);
 660
 661         mdelay(2);
 662
 663         if (RREG32(RADEON_DAC_CNTL) & RADEON_DAC_CMP_OUTPUT)
 664                 found = connector_status_connected;
 665
 666         /* restore the regs we used */
 667         WREG32(RADEON_DAC_CNTL, dac_cntl);
 668         WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
 669         WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
 670         WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
 671         WREG32_PLL(RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl);
 672
 673         return found;
 674 }
 675
 676 static const struct drm_encoder_helper_funcs radeon_legacy_primary_dac_helper_funcs = {
 677         .dpms = radeon_legacy_primary_dac_dpms,
 678         .mode_fixup = radeon_legacy_mode_fixup,
 679         .prepare = radeon_legacy_primary_dac_prepare,
 680         .mode_set = radeon_legacy_primary_dac_mode_set,
 681         .commit = radeon_legacy_primary_dac_commit,
 682         .detect = radeon_legacy_primary_dac_detect,
 683         .disable = radeon_legacy_encoder_disable,
 684 };
 685
 686
 687 static const struct drm_encoder_funcs radeon_legacy_primary_dac_enc_funcs = {
 688         .destroy = radeon_enc_destroy,
 689 };
 690
 691 static void radeon_legacy_tmds_int_dpms(struct drm_encoder *encoder, int mode)
 692 {
 693         struct drm_device *dev = encoder->dev;
 694         struct radeon_device *rdev = dev->dev_private;
 695         uint32_t fp_gen_cntl = RREG32(RADEON_FP_GEN_CNTL);
 696         DRM_DEBUG_KMS("\n");
 697
 698         switch (mode) {
 699         case DRM_MODE_DPMS_ON:
 700                 fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
 701                 break;
 702         case DRM_MODE_DPMS_STANDBY:
 703         case DRM_MODE_DPMS_SUSPEND:
 704         case DRM_MODE_DPMS_OFF:
 705                 fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
 706                 break;
 707         }
 708
 709         WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
 710
 711         if (rdev->is_atom_bios)
 712                 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 713         else
 714                 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 715
 716 }
 717
 718 static void radeon_legacy_tmds_int_prepare(struct drm_encoder *encoder)
 719 {
 720         struct radeon_device *rdev = encoder->dev->dev_private;
 721
 722         if (rdev->is_atom_bios)
 723                 radeon_atom_output_lock(encoder, true);
 724         else
 725                 radeon_combios_output_lock(encoder, true);
 726         radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_OFF);
 727 }
 728
 729 static void radeon_legacy_tmds_int_commit(struct drm_encoder *encoder)
 730 {
 731         struct radeon_device *rdev = encoder->dev->dev_private;
 732
 733         radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_ON);
 734
 735         if (rdev->is_atom_bios)
 736                 radeon_atom_output_lock(encoder, true);
 737         else
 738                 radeon_combios_output_lock(encoder, true);
 739 }
 740
 741 static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder,
 742                                             struct drm_display_mode *mode,
 743                                             struct drm_display_mode *adjusted_mode)
 744 {
 745         struct drm_device *dev = encoder->dev;
 746         struct radeon_device *rdev = dev->dev_private;
 747         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 748         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 749         uint32_t tmp, tmds_pll_cntl, tmds_transmitter_cntl, fp_gen_cntl;
 750         int i;
 751
 752         DRM_DEBUG_KMS("\n");
 753
 754         tmp = tmds_pll_cntl = RREG32(RADEON_TMDS_PLL_CNTL);
 755         tmp &= 0xfffff;
 756         if (rdev->family == CHIP_RV280) {
 757                 /* bit 22 of TMDS_PLL_CNTL is read-back inverted */
 758                 tmp ^= (1 << 22);
 759                 tmds_pll_cntl ^= (1 << 22);
 760         }
 761
 762         if (radeon_encoder->enc_priv) {
 763                 struct radeon_encoder_int_tmds *tmds = (struct radeon_encoder_int_tmds *)radeon_encoder->enc_priv;
 764
 765                 for (i = 0; i < 4; i++) {
 766                         if (tmds->tmds_pll[i].freq == 0)
 767                                 break;
 768                         if ((uint32_t)(mode->clock / 10) < tmds->tmds_pll[i].freq) {
 769                                 tmp = tmds->tmds_pll[i].value ;
 770                                 break;
 771                         }
 772                 }
 773         }
 774
 775         if (ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV280)) {
 776                 if (tmp & 0xfff00000)
 777                         tmds_pll_cntl = tmp;
 778                 else {
 779                         tmds_pll_cntl &= 0xfff00000;
 780                         tmds_pll_cntl |= tmp;
 781                 }
 782         } else
 783                 tmds_pll_cntl = tmp;
 784
 785         tmds_transmitter_cntl = RREG32(RADEON_TMDS_TRANSMITTER_CNTL) &
 786                 ~(RADEON_TMDS_TRANSMITTER_PLLRST);
 787
 788     if (rdev->family == CHIP_R200 ||
 789         rdev->family == CHIP_R100 ||
 790         ASIC_IS_R300(rdev))
 791             tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN);
 792     else /* RV chips got this bit reversed */
 793             tmds_transmitter_cntl |= RADEON_TMDS_TRANSMITTER_PLLEN;
 794
 795     fp_gen_cntl = (RREG32(RADEON_FP_GEN_CNTL) |
 796                    (RADEON_FP_CRTC_DONT_SHADOW_VPAR |
 797                     RADEON_FP_CRTC_DONT_SHADOW_HEND));
 798
 799     fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
 800
 801     fp_gen_cntl &= ~(RADEON_FP_RMX_HVSYNC_CONTROL_EN |
 802                      RADEON_FP_DFP_SYNC_SEL |
 803                      RADEON_FP_CRT_SYNC_SEL |
 804                      RADEON_FP_CRTC_LOCK_8DOT |
 805                      RADEON_FP_USE_SHADOW_EN |
 806                      RADEON_FP_CRTC_USE_SHADOW_VEND |
 807                      RADEON_FP_CRT_SYNC_ALT);
 808
 809     if (1) /*  FIXME rgbBits == 8 */
 810             fp_gen_cntl |= RADEON_FP_PANEL_FORMAT;  /* 24 bit format */
 811     else
 812             fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */
 813
 814     if (radeon_crtc->crtc_id == 0) {
 815             if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) {
 816                     fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
 817                     if (radeon_encoder->rmx_type != RMX_OFF)
 818                             fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
 819                     else
 820                             fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
 821             } else
 822                     fp_gen_cntl &= ~RADEON_FP_SEL_CRTC2;
 823     } else {
 824             if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) {
 825                     fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
 826                     fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC2;
 827             } else
 828                     fp_gen_cntl |= RADEON_FP_SEL_CRTC2;
 829     }
 830
 831     WREG32(RADEON_TMDS_PLL_CNTL, tmds_pll_cntl);
 832     WREG32(RADEON_TMDS_TRANSMITTER_CNTL, tmds_transmitter_cntl);
 833     WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
 834
 835         if (rdev->is_atom_bios)
 836                 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 837         else
 838                 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 839 }
 840
 841 static const struct drm_encoder_helper_funcs radeon_legacy_tmds_int_helper_funcs = {
 842         .dpms = radeon_legacy_tmds_int_dpms,
 843         .mode_fixup = radeon_legacy_mode_fixup,
 844         .prepare = radeon_legacy_tmds_int_prepare,
 845         .mode_set = radeon_legacy_tmds_int_mode_set,
 846         .commit = radeon_legacy_tmds_int_commit,
 847         .disable = radeon_legacy_encoder_disable,
 848 };
 849
 850
 851 static const struct drm_encoder_funcs radeon_legacy_tmds_int_enc_funcs = {
 852         .destroy = radeon_enc_destroy,
 853 };
 854
 855 static void radeon_legacy_tmds_ext_dpms(struct drm_encoder *encoder, int mode)
 856 {
 857         struct drm_device *dev = encoder->dev;
 858         struct radeon_device *rdev = dev->dev_private;
 859         uint32_t fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
 860         DRM_DEBUG_KMS("\n");
 861
 862         switch (mode) {
 863         case DRM_MODE_DPMS_ON:
 864                 fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN;
 865                 fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
 866                 break;
 867         case DRM_MODE_DPMS_STANDBY:
 868         case DRM_MODE_DPMS_SUSPEND:
 869         case DRM_MODE_DPMS_OFF:
 870                 fp2_gen_cntl |= RADEON_FP2_BLANK_EN;
 871                 fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
 872                 break;
 873         }
 874
 875         WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
 876
 877         if (rdev->is_atom_bios)
 878                 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 879         else
 880                 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 881
 882 }
 883
 884 static void radeon_legacy_tmds_ext_prepare(struct drm_encoder *encoder)
 885 {
 886         struct radeon_device *rdev = encoder->dev->dev_private;
 887
 888         if (rdev->is_atom_bios)
 889                 radeon_atom_output_lock(encoder, true);
 890         else
 891                 radeon_combios_output_lock(encoder, true);
 892         radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_OFF);
 893 }
 894
 895 static void radeon_legacy_tmds_ext_commit(struct drm_encoder *encoder)
 896 {
 897         struct radeon_device *rdev = encoder->dev->dev_private;
 898         radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_ON);
 899
 900         if (rdev->is_atom_bios)
 901                 radeon_atom_output_lock(encoder, false);
 902         else
 903                 radeon_combios_output_lock(encoder, false);
 904 }
 905
 906 static void radeon_legacy_tmds_ext_mode_set(struct drm_encoder *encoder,
 907                                             struct drm_display_mode *mode,
 908                                             struct drm_display_mode *adjusted_mode)
 909 {
 910         struct drm_device *dev = encoder->dev;
 911         struct radeon_device *rdev = dev->dev_private;
 912         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 913         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 914         uint32_t fp2_gen_cntl;
 915
 916         DRM_DEBUG_KMS("\n");
 917
 918         if (rdev->is_atom_bios) {
 919                 radeon_encoder->pixel_clock = adjusted_mode->clock;
 920                 atombios_dvo_setup(encoder, ATOM_ENABLE);
 921                 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
 922         } else {
 923                 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
 924
 925                 if (1) /*  FIXME rgbBits == 8 */
 926                         fp2_gen_cntl |= RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */
 927                 else
 928                         fp2_gen_cntl &= ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */
 929
 930                 fp2_gen_cntl &= ~(RADEON_FP2_ON |
 931                                   RADEON_FP2_DVO_EN |
 932                                   RADEON_FP2_DVO_RATE_SEL_SDR);
 933
 934                 /* XXX: these are oem specific */
 935                 if (ASIC_IS_R300(rdev)) {
 936                         if ((dev->pdev->device == 0x4850) &&
 937                             (dev->pdev->subsystem_vendor == 0x1028) &&
 938                             (dev->pdev->subsystem_device == 0x2001)) /* Dell Inspiron 8600 */
 939                                 fp2_gen_cntl |= R300_FP2_DVO_CLOCK_MODE_SINGLE;
 940                         else
 941                                 fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN | R300_FP2_DVO_CLOCK_MODE_SINGLE;
 942
 943                         /*if (mode->clock > 165000)
 944                           fp2_gen_cntl |= R300_FP2_DVO_DUAL_CHANNEL_EN;*/
 945                 }
 946                 if (!radeon_combios_external_tmds_setup(encoder))
 947                         radeon_external_tmds_setup(encoder);
 948         }
 949
 950         if (radeon_crtc->crtc_id == 0) {
 951                 if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) {
 952                         fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
 953                         if (radeon_encoder->rmx_type != RMX_OFF)
 954                                 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX;
 955                         else
 956                                 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC1;
 957                 } else
 958                         fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2;
 959         } else {
 960                 if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) {
 961                         fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
 962                         fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
 963                 } else
 964                         fp2_gen_cntl |= RADEON_FP2_SRC_SEL_CRTC2;
 965         }
 966
 967         WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
 968
 969         if (rdev->is_atom_bios)
 970                 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 971         else
 972                 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 973 }
 974
 975 static void radeon_ext_tmds_enc_destroy(struct drm_encoder *encoder)
 976 {
 977         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 978         /* don't destroy the i2c bus record here, this will be done in radeon_i2c_fini */
 979         kfree(radeon_encoder->enc_priv);
 980         drm_encoder_cleanup(encoder);
 981         kfree(radeon_encoder);
 982 }
 983
 984 static const struct drm_encoder_helper_funcs radeon_legacy_tmds_ext_helper_funcs = {
 985         .dpms = radeon_legacy_tmds_ext_dpms,
 986         .mode_fixup = radeon_legacy_mode_fixup,
 987         .prepare = radeon_legacy_tmds_ext_prepare,
 988         .mode_set = radeon_legacy_tmds_ext_mode_set,
 989         .commit = radeon_legacy_tmds_ext_commit,
 990         .disable = radeon_legacy_encoder_disable,
 991 };
 992
 993
 994 static const struct drm_encoder_funcs radeon_legacy_tmds_ext_enc_funcs = {
 995         .destroy = radeon_ext_tmds_enc_destroy,
 996 };
 997
 998 static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode)
 999 {
1000         struct drm_device *dev = encoder->dev;
1001         struct radeon_device *rdev = dev->dev_private;
1002         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1003         uint32_t fp2_gen_cntl = 0, crtc2_gen_cntl = 0, tv_dac_cntl = 0;
1004         uint32_t tv_master_cntl = 0;
1005         bool is_tv;
1006         DRM_DEBUG_KMS("\n");
1007
1008         is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
1009
1010         if (rdev->family == CHIP_R200)
1011                 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
1012         else {
1013                 if (is_tv)
1014                         tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
1015                 else
1016                         crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1017                 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1018         }
1019
1020         switch (mode) {
1021         case DRM_MODE_DPMS_ON:
1022                 if (rdev->family == CHIP_R200) {
1023                         fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
1024                 } else {
1025                         if (is_tv)
1026                                 tv_master_cntl |= RADEON_TV_ON;
1027                         else
1028                                 crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON;
1029
1030                         if (rdev->family == CHIP_R420 ||
1031                             rdev->family == CHIP_R423 ||
1032                             rdev->family == CHIP_RV410)
1033                                 tv_dac_cntl &= ~(R420_TV_DAC_RDACPD |
1034                                                  R420_TV_DAC_GDACPD |
1035                                                  R420_TV_DAC_BDACPD |
1036                                                  RADEON_TV_DAC_BGSLEEP);
1037                         else
1038                                 tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD |
1039                                                  RADEON_TV_DAC_GDACPD |
1040                                                  RADEON_TV_DAC_BDACPD |
1041                                                  RADEON_TV_DAC_BGSLEEP);
1042                 }
1043                 break;
1044         case DRM_MODE_DPMS_STANDBY:
1045         case DRM_MODE_DPMS_SUSPEND:
1046         case DRM_MODE_DPMS_OFF:
1047                 if (rdev->family == CHIP_R200)
1048                         fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
1049                 else {
1050                         if (is_tv)
1051                                 tv_master_cntl &= ~RADEON_TV_ON;
1052                         else
1053                                 crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
1054
1055                         if (rdev->family == CHIP_R420 ||
1056                             rdev->family == CHIP_R423 ||
1057                             rdev->family == CHIP_RV410)
1058                                 tv_dac_cntl |= (R420_TV_DAC_RDACPD |
1059                                                 R420_TV_DAC_GDACPD |
1060                                                 R420_TV_DAC_BDACPD |
1061                                                 RADEON_TV_DAC_BGSLEEP);
1062                         else
1063                                 tv_dac_cntl |= (RADEON_TV_DAC_RDACPD |
1064                                                 RADEON_TV_DAC_GDACPD |
1065                                                 RADEON_TV_DAC_BDACPD |
1066                                                 RADEON_TV_DAC_BGSLEEP);
1067                 }
1068                 break;
1069         }
1070
1071         if (rdev->family == CHIP_R200) {
1072                 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
1073         } else {
1074                 if (is_tv)
1075                         WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
1076                 else
1077                         WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1078                 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1079         }
1080
1081         if (rdev->is_atom_bios)
1082                 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1083         else
1084                 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1085
1086 }
1087
1088 static void radeon_legacy_tv_dac_prepare(struct drm_encoder *encoder)
1089 {
1090         struct radeon_device *rdev = encoder->dev->dev_private;
1091
1092         if (rdev->is_atom_bios)
1093                 radeon_atom_output_lock(encoder, true);
1094         else
1095                 radeon_combios_output_lock(encoder, true);
1096         radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
1097 }
1098
1099 static void radeon_legacy_tv_dac_commit(struct drm_encoder *encoder)
1100 {
1101         struct radeon_device *rdev = encoder->dev->dev_private;
1102
1103         radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_ON);
1104
1105         if (rdev->is_atom_bios)
1106                 radeon_atom_output_lock(encoder, true);
1107         else
1108                 radeon_combios_output_lock(encoder, true);
1109 }
1110
1111 static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
1112                 struct drm_display_mode *mode,
1113                 struct drm_display_mode *adjusted_mode)
1114 {
1115         struct drm_device *dev = encoder->dev;
1116         struct radeon_device *rdev = dev->dev_private;
1117         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1118         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1119         struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
1120         uint32_t tv_dac_cntl, gpiopad_a = 0, dac2_cntl, disp_output_cntl = 0;
1121         uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0, disp_tv_out_cntl = 0;
1122         bool is_tv = false;
1123
1124         DRM_DEBUG_KMS("\n");
1125
1126         is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
1127
1128         if (rdev->family != CHIP_R200) {
1129                 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1130                 if (rdev->family == CHIP_R420 ||
1131                     rdev->family == CHIP_R423 ||
1132                     rdev->family == CHIP_RV410) {
1133                         tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
1134                                          RADEON_TV_DAC_BGADJ_MASK |
1135                                          R420_TV_DAC_DACADJ_MASK |
1136                                          R420_TV_DAC_RDACPD |
1137                                          R420_TV_DAC_GDACPD |
1138                                          R420_TV_DAC_BDACPD |
1139                                          R420_TV_DAC_TVENABLE);
1140                 } else {
1141                         tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
1142                                          RADEON_TV_DAC_BGADJ_MASK |
1143                                          RADEON_TV_DAC_DACADJ_MASK |
1144                                          RADEON_TV_DAC_RDACPD |
1145                                          RADEON_TV_DAC_GDACPD |
1146                                          RADEON_TV_DAC_BDACPD);
1147                 }
1148
1149                 tv_dac_cntl |= RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD;
1150
1151                 if (is_tv) {
1152                         if (tv_dac->tv_std == TV_STD_NTSC ||
1153                             tv_dac->tv_std == TV_STD_NTSC_J ||
1154                             tv_dac->tv_std == TV_STD_PAL_M ||
1155                             tv_dac->tv_std == TV_STD_PAL_60)
1156                                 tv_dac_cntl |= tv_dac->ntsc_tvdac_adj;
1157                         else
1158                                 tv_dac_cntl |= tv_dac->pal_tvdac_adj;
1159
1160                         if (tv_dac->tv_std == TV_STD_NTSC ||
1161                             tv_dac->tv_std == TV_STD_NTSC_J)
1162                                 tv_dac_cntl |= RADEON_TV_DAC_STD_NTSC;
1163                         else
1164                                 tv_dac_cntl |= RADEON_TV_DAC_STD_PAL;
1165                 } else
1166                         tv_dac_cntl |= (RADEON_TV_DAC_STD_PS2 |
1167                                         tv_dac->ps2_tvdac_adj);
1168
1169                 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1170         }
1171
1172         if (ASIC_IS_R300(rdev)) {
1173                 gpiopad_a = RREG32(RADEON_GPIOPAD_A) | 1;
1174                 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1175         } else if (rdev->family != CHIP_R200)
1176                 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
1177         else if (rdev->family == CHIP_R200)
1178                 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
1179
1180         if (rdev->family >= CHIP_R200)
1181                 disp_tv_out_cntl = RREG32(RADEON_DISP_TV_OUT_CNTL);
1182
1183         if (is_tv) {
1184                 uint32_t dac_cntl;
1185
1186                 dac_cntl = RREG32(RADEON_DAC_CNTL);
1187                 dac_cntl &= ~RADEON_DAC_TVO_EN;
1188                 WREG32(RADEON_DAC_CNTL, dac_cntl);
1189
1190                 if (ASIC_IS_R300(rdev))
1191                         gpiopad_a = RREG32(RADEON_GPIOPAD_A) & ~1;
1192
1193                 dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~RADEON_DAC2_DAC2_CLK_SEL;
1194                 if (radeon_crtc->crtc_id == 0) {
1195                         if (ASIC_IS_R300(rdev)) {
1196                                 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1197                                 disp_output_cntl |= (RADEON_DISP_TVDAC_SOURCE_CRTC |
1198                                                      RADEON_DISP_TV_SOURCE_CRTC);
1199                         }
1200                         if (rdev->family >= CHIP_R200) {
1201                                 disp_tv_out_cntl &= ~RADEON_DISP_TV_PATH_SRC_CRTC2;
1202                         } else {
1203                                 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
1204                         }
1205                 } else {
1206                         if (ASIC_IS_R300(rdev)) {
1207                                 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1208                                 disp_output_cntl |= RADEON_DISP_TV_SOURCE_CRTC;
1209                         }
1210                         if (rdev->family >= CHIP_R200) {
1211                                 disp_tv_out_cntl |= RADEON_DISP_TV_PATH_SRC_CRTC2;
1212                         } else {
1213                                 disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
1214                         }
1215                 }
1216                 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
1217         } else {
1218
1219                 dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC2_CLK_SEL;
1220
1221                 if (radeon_crtc->crtc_id == 0) {
1222                         if (ASIC_IS_R300(rdev)) {
1223                                 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1224                                 disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC;
1225                         } else if (rdev->family == CHIP_R200) {
1226                                 fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
1227                                                   RADEON_FP2_DVO_RATE_SEL_SDR);
1228                         } else
1229                                 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
1230                 } else {
1231                         if (ASIC_IS_R300(rdev)) {
1232                                 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1233                                 disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1234                         } else if (rdev->family == CHIP_R200) {
1235                                 fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
1236                                                   RADEON_FP2_DVO_RATE_SEL_SDR);
1237                                 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
1238                         } else
1239                                 disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
1240                 }
1241                 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
1242         }
1243
1244         if (ASIC_IS_R300(rdev)) {
1245                 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1246                 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1247         } else if (rdev->family != CHIP_R200)
1248                 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1249         else if (rdev->family == CHIP_R200)
1250                 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
1251
1252         if (rdev->family >= CHIP_R200)
1253                 WREG32(RADEON_DISP_TV_OUT_CNTL, disp_tv_out_cntl);
1254
1255         if (is_tv)
1256                 radeon_legacy_tv_mode_set(encoder, mode, adjusted_mode);
1257
1258         if (rdev->is_atom_bios)
1259                 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1260         else
1261                 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1262
1263 }
1264
1265 static bool r300_legacy_tv_detect(struct drm_encoder *encoder,
1266                                   struct drm_connector *connector)
1267 {
1268         struct drm_device *dev = encoder->dev;
1269         struct radeon_device *rdev = dev->dev_private;
1270         uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
1271         uint32_t disp_output_cntl, gpiopad_a, tmp;
1272         bool found = false;
1273
1274         /* save regs needed */
1275         gpiopad_a = RREG32(RADEON_GPIOPAD_A);
1276         dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1277         crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1278         dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
1279         tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1280         disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1281
1282         WREG32_P(RADEON_GPIOPAD_A, 0, ~1);
1283
1284         WREG32(RADEON_DAC_CNTL2, RADEON_DAC2_DAC2_CLK_SEL);
1285
1286         WREG32(RADEON_CRTC2_GEN_CNTL,
1287                RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_VSYNC_TRISTAT);
1288
1289         tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
1290         tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1291         WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
1292
1293         WREG32(RADEON_DAC_EXT_CNTL,
1294                RADEON_DAC2_FORCE_BLANK_OFF_EN |
1295                RADEON_DAC2_FORCE_DATA_EN |
1296                RADEON_DAC_FORCE_DATA_SEL_RGB |
1297                (0xec << RADEON_DAC_FORCE_DATA_SHIFT));
1298
1299         WREG32(RADEON_TV_DAC_CNTL,
1300                RADEON_TV_DAC_STD_NTSC |
1301                (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
1302                (6 << RADEON_TV_DAC_DACADJ_SHIFT));
1303
1304         RREG32(RADEON_TV_DAC_CNTL);
1305         mdelay(4);
1306
1307         WREG32(RADEON_TV_DAC_CNTL,
1308                RADEON_TV_DAC_NBLANK |
1309                RADEON_TV_DAC_NHOLD |
1310                RADEON_TV_MONITOR_DETECT_EN |
1311                RADEON_TV_DAC_STD_NTSC |
1312                (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
1313                (6 << RADEON_TV_DAC_DACADJ_SHIFT));
1314
1315         RREG32(RADEON_TV_DAC_CNTL);
1316         mdelay(6);
1317
1318         tmp = RREG32(RADEON_TV_DAC_CNTL);
1319         if ((tmp & RADEON_TV_DAC_GDACDET) != 0) {
1320                 found = true;
1321                 DRM_DEBUG_KMS("S-video TV connection detected\n");
1322         } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
1323                 found = true;
1324                 DRM_DEBUG_KMS("Composite TV connection detected\n");
1325         }
1326
1327         WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1328         WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
1329         WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1330         WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1331         WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1332         WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1333         return found;
1334 }
1335
1336 static bool radeon_legacy_tv_detect(struct drm_encoder *encoder,
1337                                     struct drm_connector *connector)
1338 {
1339         struct drm_device *dev = encoder->dev;
1340         struct radeon_device *rdev = dev->dev_private;
1341         uint32_t tv_dac_cntl, dac_cntl2;
1342         uint32_t config_cntl, tv_pre_dac_mux_cntl, tv_master_cntl, tmp;
1343         bool found = false;
1344
1345         if (ASIC_IS_R300(rdev))
1346                 return r300_legacy_tv_detect(encoder, connector);
1347
1348         dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1349         tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
1350         tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1351         config_cntl = RREG32(RADEON_CONFIG_CNTL);
1352         tv_pre_dac_mux_cntl = RREG32(RADEON_TV_PRE_DAC_MUX_CNTL);
1353
1354         tmp = dac_cntl2 & ~RADEON_DAC2_DAC2_CLK_SEL;
1355         WREG32(RADEON_DAC_CNTL2, tmp);
1356
1357         tmp = tv_master_cntl | RADEON_TV_ON;
1358         tmp &= ~(RADEON_TV_ASYNC_RST |
1359                  RADEON_RESTART_PHASE_FIX |
1360                  RADEON_CRT_FIFO_CE_EN |
1361                  RADEON_TV_FIFO_CE_EN |
1362                  RADEON_RE_SYNC_NOW_SEL_MASK);
1363         tmp |= RADEON_TV_FIFO_ASYNC_RST | RADEON_CRT_ASYNC_RST;
1364         WREG32(RADEON_TV_MASTER_CNTL, tmp);
1365
1366         tmp = RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD |
1367                 RADEON_TV_MONITOR_DETECT_EN | RADEON_TV_DAC_STD_NTSC |
1368                 (8 << RADEON_TV_DAC_BGADJ_SHIFT);
1369
1370         if (config_cntl & RADEON_CFG_ATI_REV_ID_MASK)
1371                 tmp |= (4 << RADEON_TV_DAC_DACADJ_SHIFT);
1372         else
1373                 tmp |= (8 << RADEON_TV_DAC_DACADJ_SHIFT);
1374         WREG32(RADEON_TV_DAC_CNTL, tmp);
1375
1376         tmp = RADEON_C_GRN_EN | RADEON_CMP_BLU_EN |
1377                 RADEON_RED_MX_FORCE_DAC_DATA |
1378                 RADEON_GRN_MX_FORCE_DAC_DATA |
1379                 RADEON_BLU_MX_FORCE_DAC_DATA |
1380                 (0x109 << RADEON_TV_FORCE_DAC_DATA_SHIFT);
1381         WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tmp);
1382
1383         mdelay(3);
1384         tmp = RREG32(RADEON_TV_DAC_CNTL);
1385         if (tmp & RADEON_TV_DAC_GDACDET) {
1386                 found = true;
1387                 DRM_DEBUG_KMS("S-video TV connection detected\n");
1388         } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
1389                 found = true;
1390                 DRM_DEBUG_KMS("Composite TV connection detected\n");
1391         }
1392
1393         WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tv_pre_dac_mux_cntl);
1394         WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1395         WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
1396         WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1397         return found;
1398 }
1399
1400 static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder *encoder,
1401                                                              struct drm_connector *connector)
1402 {
1403         struct drm_device *dev = encoder->dev;
1404         struct radeon_device *rdev = dev->dev_private;
1405         uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
1406         uint32_t disp_hw_debug, disp_output_cntl, gpiopad_a, pixclks_cntl, tmp;
1407         enum drm_connector_status found = connector_status_disconnected;
1408         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1409         struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
1410         bool color = true;
1411         struct drm_crtc *crtc;
1412
1413         /* find out if crtc2 is in use or if this encoder is using it */
1414         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1415                 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1416                 if ((radeon_crtc->crtc_id == 1) && crtc->enabled) {
1417                         if (encoder->crtc != crtc) {
1418                                 return connector_status_disconnected;
1419                         }
1420                 }
1421         }
1422
1423         if (connector->connector_type == DRM_MODE_CONNECTOR_SVIDEO ||
1424             connector->connector_type == DRM_MODE_CONNECTOR_Composite ||
1425             connector->connector_type == DRM_MODE_CONNECTOR_9PinDIN) {
1426                 bool tv_detect;
1427
1428                 if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT))
1429                         return connector_status_disconnected;
1430
1431                 tv_detect = radeon_legacy_tv_detect(encoder, connector);
1432                 if (tv_detect && tv_dac)
1433                         found = connector_status_connected;
1434                 return found;
1435         }
1436
1437         /* don't probe if the encoder is being used for something else not CRT related */
1438         if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_CRT_SUPPORT)) {
1439                 DRM_INFO("not detecting due to %08x\n", radeon_encoder->active_device);
1440                 return connector_status_disconnected;
1441         }
1442
1443         /* save the regs we need */
1444         pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
1445         gpiopad_a = ASIC_IS_R300(rdev) ? RREG32(RADEON_GPIOPAD_A) : 0;
1446         disp_output_cntl = ASIC_IS_R300(rdev) ? RREG32(RADEON_DISP_OUTPUT_CNTL) : 0;
1447         disp_hw_debug = ASIC_IS_R300(rdev) ? 0 : RREG32(RADEON_DISP_HW_DEBUG);
1448         crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1449         tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1450         dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
1451         dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1452
1453         tmp = pixclks_cntl & ~(RADEON_PIX2CLK_ALWAYS_ONb
1454                                | RADEON_PIX2CLK_DAC_ALWAYS_ONb);
1455         WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
1456
1457         if (ASIC_IS_R300(rdev))
1458                 WREG32_P(RADEON_GPIOPAD_A, 1, ~1);
1459
1460         tmp = crtc2_gen_cntl & ~RADEON_CRTC2_PIX_WIDTH_MASK;
1461         tmp |= RADEON_CRTC2_CRT2_ON |
1462                 (2 << RADEON_CRTC2_PIX_WIDTH_SHIFT);
1463
1464         WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
1465
1466         if (ASIC_IS_R300(rdev)) {
1467                 tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
1468                 tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1469                 WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
1470         } else {
1471                 tmp = disp_hw_debug & ~RADEON_CRT2_DISP1_SEL;
1472                 WREG32(RADEON_DISP_HW_DEBUG, tmp);
1473         }
1474
1475         tmp = RADEON_TV_DAC_NBLANK |
1476                 RADEON_TV_DAC_NHOLD |
1477                 RADEON_TV_MONITOR_DETECT_EN |
1478                 RADEON_TV_DAC_STD_PS2;
1479
1480         WREG32(RADEON_TV_DAC_CNTL, tmp);
1481
1482         tmp = RADEON_DAC2_FORCE_BLANK_OFF_EN |
1483                 RADEON_DAC2_FORCE_DATA_EN;
1484
1485         if (color)
1486                 tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
1487         else
1488                 tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
1489
1490         if (ASIC_IS_R300(rdev))
1491                 tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
1492         else
1493                 tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
1494
1495         WREG32(RADEON_DAC_EXT_CNTL, tmp);
1496
1497         tmp = dac_cntl2 | RADEON_DAC2_DAC2_CLK_SEL | RADEON_DAC2_CMP_EN;
1498         WREG32(RADEON_DAC_CNTL2, tmp);
1499
1500         mdelay(10);
1501
1502         if (ASIC_IS_R300(rdev)) {
1503                 if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUT_B)
1504                         found = connector_status_connected;
1505         } else {
1506                 if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUTPUT)
1507                         found = connector_status_connected;
1508         }
1509
1510         /* restore regs we used */
1511         WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1512         WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
1513         WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1514         WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1515
1516         if (ASIC_IS_R300(rdev)) {
1517                 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1518                 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1519         } else {
1520                 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1521         }
1522         WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
1523
1524         return found;
1525
1526 }
1527
1528 static const struct drm_encoder_helper_funcs radeon_legacy_tv_dac_helper_funcs = {
1529         .dpms = radeon_legacy_tv_dac_dpms,
1530         .mode_fixup = radeon_legacy_mode_fixup,
1531         .prepare = radeon_legacy_tv_dac_prepare,
1532         .mode_set = radeon_legacy_tv_dac_mode_set,
1533         .commit = radeon_legacy_tv_dac_commit,
1534         .detect = radeon_legacy_tv_dac_detect,
1535         .disable = radeon_legacy_encoder_disable,
1536 };
1537
1538
1539 static const struct drm_encoder_funcs radeon_legacy_tv_dac_enc_funcs = {
1540         .destroy = radeon_enc_destroy,
1541 };
1542
1543
1544 static struct radeon_encoder_int_tmds *radeon_legacy_get_tmds_info(struct radeon_encoder *encoder)
1545 {
1546         struct drm_device *dev = encoder->base.dev;
1547         struct radeon_device *rdev = dev->dev_private;
1548         struct radeon_encoder_int_tmds *tmds = NULL;
1549         bool ret;
1550
1551         tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
1552
1553         if (!tmds)
1554                 return NULL;
1555
1556         if (rdev->is_atom_bios)
1557                 ret = radeon_atombios_get_tmds_info(encoder, tmds);
1558         else
1559                 ret = radeon_legacy_get_tmds_info_from_combios(encoder, tmds);
1560
1561         if (ret == false)
1562                 radeon_legacy_get_tmds_info_from_table(encoder, tmds);
1563
1564         return tmds;
1565 }
1566
1567 static struct radeon_encoder_ext_tmds *radeon_legacy_get_ext_tmds_info(struct radeon_encoder *encoder)
1568 {
1569         struct drm_device *dev = encoder->base.dev;
1570         struct radeon_device *rdev = dev->dev_private;
1571         struct radeon_encoder_ext_tmds *tmds = NULL;
1572         bool ret;
1573
1574         if (rdev->is_atom_bios)
1575                 return NULL;
1576
1577         tmds = kzalloc(sizeof(struct radeon_encoder_ext_tmds), GFP_KERNEL);
1578
1579         if (!tmds)
1580                 return NULL;
1581
1582         ret = radeon_legacy_get_ext_tmds_info_from_combios(encoder, tmds);
1583
1584         if (ret == false)
1585                 radeon_legacy_get_ext_tmds_info_from_table(encoder, tmds);
1586
1587         return tmds;
1588 }
1589
1590 void
1591 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum, uint32_t supported_device)
1592 {
1593         struct radeon_device *rdev = dev->dev_private;
1594         struct drm_encoder *encoder;
1595         struct radeon_encoder *radeon_encoder;
1596
1597         /* see if we already added it */
1598         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1599                 radeon_encoder = to_radeon_encoder(encoder);
1600                 if (radeon_encoder->encoder_enum == encoder_enum) {
1601                         radeon_encoder->devices |= supported_device;
1602                         return;
1603                 }
1604
1605         }
1606
1607         /* add a new one */
1608         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1609         if (!radeon_encoder)
1610                 return;
1611
1612         encoder = &radeon_encoder->base;
1613         if (rdev->flags & RADEON_SINGLE_CRTC)
1614                 encoder->possible_crtcs = 0x1;
1615         else
1616                 encoder->possible_crtcs = 0x3;
1617
1618         radeon_encoder->enc_priv = NULL;
1619
1620         radeon_encoder->encoder_enum = encoder_enum;
1621         radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1622         radeon_encoder->devices = supported_device;
1623         radeon_encoder->rmx_type = RMX_OFF;
1624
1625         switch (radeon_encoder->encoder_id) {
1626         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1627                 encoder->possible_crtcs = 0x1;
1628                 drm_encoder_init(dev, encoder, &radeon_legacy_lvds_enc_funcs, DRM_MODE_ENCODER_LVDS);
1629                 drm_encoder_helper_add(encoder, &radeon_legacy_lvds_helper_funcs);
1630                 if (rdev->is_atom_bios)
1631                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1632                 else
1633                         radeon_encoder->enc_priv = radeon_combios_get_lvds_info(radeon_encoder);
1634                 radeon_encoder->rmx_type = RMX_FULL;
1635                 break;
1636         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1637                 drm_encoder_init(dev, encoder, &radeon_legacy_tmds_int_enc_funcs, DRM_MODE_ENCODER_TMDS);
1638                 drm_encoder_helper_add(encoder, &radeon_legacy_tmds_int_helper_funcs);
1639                 radeon_encoder->enc_priv = radeon_legacy_get_tmds_info(radeon_encoder);
1640                 break;
1641         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1642                 drm_encoder_init(dev, encoder, &radeon_legacy_primary_dac_enc_funcs, DRM_MODE_ENCODER_DAC);
1643                 drm_encoder_helper_add(encoder, &radeon_legacy_primary_dac_helper_funcs);
1644                 if (rdev->is_atom_bios)
1645                         radeon_encoder->enc_priv = radeon_atombios_get_primary_dac_info(radeon_encoder);
1646                 else
1647                         radeon_encoder->enc_priv = radeon_combios_get_primary_dac_info(radeon_encoder);
1648                 break;
1649         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1650                 drm_encoder_init(dev, encoder, &radeon_legacy_tv_dac_enc_funcs, DRM_MODE_ENCODER_TVDAC);
1651                 drm_encoder_helper_add(encoder, &radeon_legacy_tv_dac_helper_funcs);
1652                 if (rdev->is_atom_bios)
1653                         radeon_encoder->enc_priv = radeon_atombios_get_tv_dac_info(radeon_encoder);
1654                 else
1655                         radeon_encoder->enc_priv = radeon_combios_get_tv_dac_info(radeon_encoder);
1656                 break;
1657         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1658                 drm_encoder_init(dev, encoder, &radeon_legacy_tmds_ext_enc_funcs, DRM_MODE_ENCODER_TMDS);
1659                 drm_encoder_helper_add(encoder, &radeon_legacy_tmds_ext_helper_funcs);
1660                 if (!rdev->is_atom_bios)
1661                         radeon_encoder->enc_priv = radeon_legacy_get_ext_tmds_info(radeon_encoder);
1662                 break;
1663         }
1664 }