2 * AT86RF230/RF231 driver
4 * Copyright (C) 2009-2012 Siemens AG
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2
8 * as published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
20 * Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
21 * Alexander Smirnov <alex.bluesman.smirnov@gmail.com>
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/interrupt.h>
26 #include <linux/gpio.h>
27 #include <linux/delay.h>
28 #include <linux/mutex.h>
29 #include <linux/workqueue.h>
30 #include <linux/spinlock.h>
31 #include <linux/spi/spi.h>
32 #include <linux/spi/at86rf230.h>
33 #include <linux/skbuff.h>
35 #include <net/mac802154.h>
36 #include <net/wpan-phy.h>
38 struct at86rf230_local
{
39 struct spi_device
*spi
;
40 int rstn
, slp_tr
, dig2
;
48 struct work_struct irqwork
;
49 struct completion tx_complete
;
51 struct ieee802154_dev
*dev
;
58 #define RG_TRX_STATUS (0x01)
59 #define SR_TRX_STATUS 0x01, 0x1f, 0
60 #define SR_RESERVED_01_3 0x01, 0x20, 5
61 #define SR_CCA_STATUS 0x01, 0x40, 6
62 #define SR_CCA_DONE 0x01, 0x80, 7
63 #define RG_TRX_STATE (0x02)
64 #define SR_TRX_CMD 0x02, 0x1f, 0
65 #define SR_TRAC_STATUS 0x02, 0xe0, 5
66 #define RG_TRX_CTRL_0 (0x03)
67 #define SR_CLKM_CTRL 0x03, 0x07, 0
68 #define SR_CLKM_SHA_SEL 0x03, 0x08, 3
69 #define SR_PAD_IO_CLKM 0x03, 0x30, 4
70 #define SR_PAD_IO 0x03, 0xc0, 6
71 #define RG_TRX_CTRL_1 (0x04)
72 #define SR_IRQ_POLARITY 0x04, 0x01, 0
73 #define SR_IRQ_MASK_MODE 0x04, 0x02, 1
74 #define SR_SPI_CMD_MODE 0x04, 0x0c, 2
75 #define SR_RX_BL_CTRL 0x04, 0x10, 4
76 #define SR_TX_AUTO_CRC_ON 0x04, 0x20, 5
77 #define SR_IRQ_2_EXT_EN 0x04, 0x40, 6
78 #define SR_PA_EXT_EN 0x04, 0x80, 7
79 #define RG_PHY_TX_PWR (0x05)
80 #define SR_TX_PWR 0x05, 0x0f, 0
81 #define SR_PA_LT 0x05, 0x30, 4
82 #define SR_PA_BUF_LT 0x05, 0xc0, 6
83 #define RG_PHY_RSSI (0x06)
84 #define SR_RSSI 0x06, 0x1f, 0
85 #define SR_RND_VALUE 0x06, 0x60, 5
86 #define SR_RX_CRC_VALID 0x06, 0x80, 7
87 #define RG_PHY_ED_LEVEL (0x07)
88 #define SR_ED_LEVEL 0x07, 0xff, 0
89 #define RG_PHY_CC_CCA (0x08)
90 #define SR_CHANNEL 0x08, 0x1f, 0
91 #define SR_CCA_MODE 0x08, 0x60, 5
92 #define SR_CCA_REQUEST 0x08, 0x80, 7
93 #define RG_CCA_THRES (0x09)
94 #define SR_CCA_ED_THRES 0x09, 0x0f, 0
95 #define SR_RESERVED_09_1 0x09, 0xf0, 4
96 #define RG_RX_CTRL (0x0a)
97 #define SR_PDT_THRES 0x0a, 0x0f, 0
98 #define SR_RESERVED_0a_1 0x0a, 0xf0, 4
99 #define RG_SFD_VALUE (0x0b)
100 #define SR_SFD_VALUE 0x0b, 0xff, 0
101 #define RG_TRX_CTRL_2 (0x0c)
102 #define SR_OQPSK_DATA_RATE 0x0c, 0x03, 0
103 #define SR_RESERVED_0c_2 0x0c, 0x7c, 2
104 #define SR_RX_SAFE_MODE 0x0c, 0x80, 7
105 #define RG_ANT_DIV (0x0d)
106 #define SR_ANT_CTRL 0x0d, 0x03, 0
107 #define SR_ANT_EXT_SW_EN 0x0d, 0x04, 2
108 #define SR_ANT_DIV_EN 0x0d, 0x08, 3
109 #define SR_RESERVED_0d_2 0x0d, 0x70, 4
110 #define SR_ANT_SEL 0x0d, 0x80, 7
111 #define RG_IRQ_MASK (0x0e)
112 #define SR_IRQ_MASK 0x0e, 0xff, 0
113 #define RG_IRQ_STATUS (0x0f)
114 #define SR_IRQ_0_PLL_LOCK 0x0f, 0x01, 0
115 #define SR_IRQ_1_PLL_UNLOCK 0x0f, 0x02, 1
116 #define SR_IRQ_2_RX_START 0x0f, 0x04, 2
117 #define SR_IRQ_3_TRX_END 0x0f, 0x08, 3
118 #define SR_IRQ_4_CCA_ED_DONE 0x0f, 0x10, 4
119 #define SR_IRQ_5_AMI 0x0f, 0x20, 5
120 #define SR_IRQ_6_TRX_UR 0x0f, 0x40, 6
121 #define SR_IRQ_7_BAT_LOW 0x0f, 0x80, 7
122 #define RG_VREG_CTRL (0x10)
123 #define SR_RESERVED_10_6 0x10, 0x03, 0
124 #define SR_DVDD_OK 0x10, 0x04, 2
125 #define SR_DVREG_EXT 0x10, 0x08, 3
126 #define SR_RESERVED_10_3 0x10, 0x30, 4
127 #define SR_AVDD_OK 0x10, 0x40, 6
128 #define SR_AVREG_EXT 0x10, 0x80, 7
129 #define RG_BATMON (0x11)
130 #define SR_BATMON_VTH 0x11, 0x0f, 0
131 #define SR_BATMON_HR 0x11, 0x10, 4
132 #define SR_BATMON_OK 0x11, 0x20, 5
133 #define SR_RESERVED_11_1 0x11, 0xc0, 6
134 #define RG_XOSC_CTRL (0x12)
135 #define SR_XTAL_TRIM 0x12, 0x0f, 0
136 #define SR_XTAL_MODE 0x12, 0xf0, 4
137 #define RG_RX_SYN (0x15)
138 #define SR_RX_PDT_LEVEL 0x15, 0x0f, 0
139 #define SR_RESERVED_15_2 0x15, 0x70, 4
140 #define SR_RX_PDT_DIS 0x15, 0x80, 7
141 #define RG_XAH_CTRL_1 (0x17)
142 #define SR_RESERVED_17_8 0x17, 0x01, 0
143 #define SR_AACK_PROM_MODE 0x17, 0x02, 1
144 #define SR_AACK_ACK_TIME 0x17, 0x04, 2
145 #define SR_RESERVED_17_5 0x17, 0x08, 3
146 #define SR_AACK_UPLD_RES_FT 0x17, 0x10, 4
147 #define SR_AACK_FLTR_RES_FT 0x17, 0x20, 5
148 #define SR_RESERVED_17_2 0x17, 0x40, 6
149 #define SR_RESERVED_17_1 0x17, 0x80, 7
150 #define RG_FTN_CTRL (0x18)
151 #define SR_RESERVED_18_2 0x18, 0x7f, 0
152 #define SR_FTN_START 0x18, 0x80, 7
153 #define RG_PLL_CF (0x1a)
154 #define SR_RESERVED_1a_2 0x1a, 0x7f, 0
155 #define SR_PLL_CF_START 0x1a, 0x80, 7
156 #define RG_PLL_DCU (0x1b)
157 #define SR_RESERVED_1b_3 0x1b, 0x3f, 0
158 #define SR_RESERVED_1b_2 0x1b, 0x40, 6
159 #define SR_PLL_DCU_START 0x1b, 0x80, 7
160 #define RG_PART_NUM (0x1c)
161 #define SR_PART_NUM 0x1c, 0xff, 0
162 #define RG_VERSION_NUM (0x1d)
163 #define SR_VERSION_NUM 0x1d, 0xff, 0
164 #define RG_MAN_ID_0 (0x1e)
165 #define SR_MAN_ID_0 0x1e, 0xff, 0
166 #define RG_MAN_ID_1 (0x1f)
167 #define SR_MAN_ID_1 0x1f, 0xff, 0
168 #define RG_SHORT_ADDR_0 (0x20)
169 #define SR_SHORT_ADDR_0 0x20, 0xff, 0
170 #define RG_SHORT_ADDR_1 (0x21)
171 #define SR_SHORT_ADDR_1 0x21, 0xff, 0
172 #define RG_PAN_ID_0 (0x22)
173 #define SR_PAN_ID_0 0x22, 0xff, 0
174 #define RG_PAN_ID_1 (0x23)
175 #define SR_PAN_ID_1 0x23, 0xff, 0
176 #define RG_IEEE_ADDR_0 (0x24)
177 #define SR_IEEE_ADDR_0 0x24, 0xff, 0
178 #define RG_IEEE_ADDR_1 (0x25)
179 #define SR_IEEE_ADDR_1 0x25, 0xff, 0
180 #define RG_IEEE_ADDR_2 (0x26)
181 #define SR_IEEE_ADDR_2 0x26, 0xff, 0
182 #define RG_IEEE_ADDR_3 (0x27)
183 #define SR_IEEE_ADDR_3 0x27, 0xff, 0
184 #define RG_IEEE_ADDR_4 (0x28)
185 #define SR_IEEE_ADDR_4 0x28, 0xff, 0
186 #define RG_IEEE_ADDR_5 (0x29)
187 #define SR_IEEE_ADDR_5 0x29, 0xff, 0
188 #define RG_IEEE_ADDR_6 (0x2a)
189 #define SR_IEEE_ADDR_6 0x2a, 0xff, 0
190 #define RG_IEEE_ADDR_7 (0x2b)
191 #define SR_IEEE_ADDR_7 0x2b, 0xff, 0
192 #define RG_XAH_CTRL_0 (0x2c)
193 #define SR_SLOTTED_OPERATION 0x2c, 0x01, 0
194 #define SR_MAX_CSMA_RETRIES 0x2c, 0x0e, 1
195 #define SR_MAX_FRAME_RETRIES 0x2c, 0xf0, 4
196 #define RG_CSMA_SEED_0 (0x2d)
197 #define SR_CSMA_SEED_0 0x2d, 0xff, 0
198 #define RG_CSMA_SEED_1 (0x2e)
199 #define SR_CSMA_SEED_1 0x2e, 0x07, 0
200 #define SR_AACK_I_AM_COORD 0x2e, 0x08, 3
201 #define SR_AACK_DIS_ACK 0x2e, 0x10, 4
202 #define SR_AACK_SET_PD 0x2e, 0x20, 5
203 #define SR_AACK_FVN_MODE 0x2e, 0xc0, 6
204 #define RG_CSMA_BE (0x2f)
205 #define SR_MIN_BE 0x2f, 0x0f, 0
206 #define SR_MAX_BE 0x2f, 0xf0, 4
209 #define CMD_REG_MASK 0x3f
210 #define CMD_WRITE 0x40
213 #define IRQ_BAT_LOW (1 << 7)
214 #define IRQ_TRX_UR (1 << 6)
215 #define IRQ_AMI (1 << 5)
216 #define IRQ_CCA_ED (1 << 4)
217 #define IRQ_TRX_END (1 << 3)
218 #define IRQ_RX_START (1 << 2)
219 #define IRQ_PLL_UNL (1 << 1)
220 #define IRQ_PLL_LOCK (1 << 0)
222 #define STATE_P_ON 0x00 /* BUSY */
223 #define STATE_BUSY_RX 0x01
224 #define STATE_BUSY_TX 0x02
225 #define STATE_FORCE_TRX_OFF 0x03
226 #define STATE_FORCE_TX_ON 0x04 /* IDLE */
227 /* 0x05 */ /* INVALID_PARAMETER */
228 #define STATE_RX_ON 0x06
229 /* 0x07 */ /* SUCCESS */
230 #define STATE_TRX_OFF 0x08
231 #define STATE_TX_ON 0x09
232 /* 0x0a - 0x0e */ /* 0x0a - UNSUPPORTED_ATTRIBUTE */
233 #define STATE_SLEEP 0x0F
234 #define STATE_BUSY_RX_AACK 0x11
235 #define STATE_BUSY_TX_ARET 0x12
236 #define STATE_BUSY_RX_AACK_ON 0x16
237 #define STATE_BUSY_TX_ARET_ON 0x19
238 #define STATE_RX_ON_NOCLK 0x1C
239 #define STATE_RX_AACK_ON_NOCLK 0x1D
240 #define STATE_BUSY_RX_AACK_NOCLK 0x1E
241 #define STATE_TRANSITION_IN_PROGRESS 0x1F
244 __at86rf230_write(struct at86rf230_local
*lp
, u8 addr
, u8 data
)
248 struct spi_message msg
;
249 struct spi_transfer xfer
= {
254 buf
[0] = (addr
& CMD_REG_MASK
) | CMD_REG
| CMD_WRITE
;
256 dev_vdbg(&lp
->spi
->dev
, "buf[0] = %02x\n", buf
[0]);
257 dev_vdbg(&lp
->spi
->dev
, "buf[1] = %02x\n", buf
[1]);
258 spi_message_init(&msg
);
259 spi_message_add_tail(&xfer
, &msg
);
261 status
= spi_sync(lp
->spi
, &msg
);
262 dev_vdbg(&lp
->spi
->dev
, "status = %d\n", status
);
266 dev_vdbg(&lp
->spi
->dev
, "status = %d\n", status
);
267 dev_vdbg(&lp
->spi
->dev
, "buf[0] = %02x\n", buf
[0]);
268 dev_vdbg(&lp
->spi
->dev
, "buf[1] = %02x\n", buf
[1]);
274 __at86rf230_read_subreg(struct at86rf230_local
*lp
,
275 u8 addr
, u8 mask
, int shift
, u8
*data
)
279 struct spi_message msg
;
280 struct spi_transfer xfer
= {
286 buf
[0] = (addr
& CMD_REG_MASK
) | CMD_REG
;
288 dev_vdbg(&lp
->spi
->dev
, "buf[0] = %02x\n", buf
[0]);
289 spi_message_init(&msg
);
290 spi_message_add_tail(&xfer
, &msg
);
292 status
= spi_sync(lp
->spi
, &msg
);
293 dev_vdbg(&lp
->spi
->dev
, "status = %d\n", status
);
297 dev_vdbg(&lp
->spi
->dev
, "status = %d\n", status
);
298 dev_vdbg(&lp
->spi
->dev
, "buf[0] = %02x\n", buf
[0]);
299 dev_vdbg(&lp
->spi
->dev
, "buf[1] = %02x\n", buf
[1]);
308 at86rf230_read_subreg(struct at86rf230_local
*lp
,
309 u8 addr
, u8 mask
, int shift
, u8
*data
)
313 mutex_lock(&lp
->bmux
);
314 status
= __at86rf230_read_subreg(lp
, addr
, mask
, shift
, data
);
315 mutex_unlock(&lp
->bmux
);
321 at86rf230_write_subreg(struct at86rf230_local
*lp
,
322 u8 addr
, u8 mask
, int shift
, u8 data
)
327 mutex_lock(&lp
->bmux
);
328 status
= __at86rf230_read_subreg(lp
, addr
, 0xff, 0, &val
);
333 val
|= (data
<< shift
) & mask
;
335 status
= __at86rf230_write(lp
, addr
, val
);
337 mutex_unlock(&lp
->bmux
);
343 at86rf230_write_fbuf(struct at86rf230_local
*lp
, u8
*data
, u8 len
)
347 struct spi_message msg
;
348 struct spi_transfer xfer_head
= {
353 struct spi_transfer xfer_buf
= {
358 mutex_lock(&lp
->bmux
);
359 buf
[0] = CMD_WRITE
| CMD_FB
;
360 buf
[1] = len
+ 2; /* 2 bytes for CRC that isn't written */
362 dev_vdbg(&lp
->spi
->dev
, "buf[0] = %02x\n", buf
[0]);
363 dev_vdbg(&lp
->spi
->dev
, "buf[1] = %02x\n", buf
[1]);
365 spi_message_init(&msg
);
366 spi_message_add_tail(&xfer_head
, &msg
);
367 spi_message_add_tail(&xfer_buf
, &msg
);
369 status
= spi_sync(lp
->spi
, &msg
);
370 dev_vdbg(&lp
->spi
->dev
, "status = %d\n", status
);
374 dev_vdbg(&lp
->spi
->dev
, "status = %d\n", status
);
375 dev_vdbg(&lp
->spi
->dev
, "buf[0] = %02x\n", buf
[0]);
376 dev_vdbg(&lp
->spi
->dev
, "buf[1] = %02x\n", buf
[1]);
378 mutex_unlock(&lp
->bmux
);
383 at86rf230_read_fbuf(struct at86rf230_local
*lp
, u8
*data
, u8
*len
, u8
*lqi
)
387 struct spi_message msg
;
388 struct spi_transfer xfer_head
= {
393 struct spi_transfer xfer_head1
= {
398 struct spi_transfer xfer_buf
= {
403 mutex_lock(&lp
->bmux
);
408 spi_message_init(&msg
);
409 spi_message_add_tail(&xfer_head
, &msg
);
411 status
= spi_sync(lp
->spi
, &msg
);
412 dev_vdbg(&lp
->spi
->dev
, "status = %d\n", status
);
414 xfer_buf
.len
= *(buf
+ 1) + 1;
420 spi_message_init(&msg
);
421 spi_message_add_tail(&xfer_head1
, &msg
);
422 spi_message_add_tail(&xfer_buf
, &msg
);
424 status
= spi_sync(lp
->spi
, &msg
);
429 dev_vdbg(&lp
->spi
->dev
, "status = %d\n", status
);
430 dev_vdbg(&lp
->spi
->dev
, "buf[0] = %02x\n", buf
[0]);
431 dev_vdbg(&lp
->spi
->dev
, "buf[1] = %02x\n", buf
[1]);
434 if (lqi
&& (*len
> lp
->buf
[1]))
435 *lqi
= data
[lp
->buf
[1]];
437 mutex_unlock(&lp
->bmux
);
443 at86rf230_ed(struct ieee802154_dev
*dev
, u8
*level
)
452 at86rf230_state(struct ieee802154_dev
*dev
, int state
)
454 struct at86rf230_local
*lp
= dev
->priv
;
461 if (state
== STATE_FORCE_TX_ON
)
462 desired_status
= STATE_TX_ON
;
463 else if (state
== STATE_FORCE_TRX_OFF
)
464 desired_status
= STATE_TRX_OFF
;
466 desired_status
= state
;
469 rc
= at86rf230_read_subreg(lp
, SR_TRX_STATUS
, &val
);
472 } while (val
== STATE_TRANSITION_IN_PROGRESS
);
474 if (val
== desired_status
)
477 /* state is equal to phy states */
478 rc
= at86rf230_write_subreg(lp
, SR_TRX_CMD
, state
);
483 rc
= at86rf230_read_subreg(lp
, SR_TRX_STATUS
, &val
);
486 } while (val
== STATE_TRANSITION_IN_PROGRESS
);
489 if (val
== desired_status
)
492 pr_err("unexpected state change: %d, asked for %d\n", val
, state
);
496 pr_err("error: %d\n", rc
);
501 at86rf230_start(struct ieee802154_dev
*dev
)
503 struct at86rf230_local
*lp
= dev
->priv
;
506 rc
= at86rf230_write_subreg(lp
, SR_RX_SAFE_MODE
, 1);
510 return at86rf230_state(dev
, STATE_RX_ON
);
514 at86rf230_stop(struct ieee802154_dev
*dev
)
516 at86rf230_state(dev
, STATE_FORCE_TRX_OFF
);
520 at86rf230_channel(struct ieee802154_dev
*dev
, int page
, int channel
)
522 struct at86rf230_local
*lp
= dev
->priv
;
527 if (page
!= 0 || channel
< 11 || channel
> 26) {
532 rc
= at86rf230_write_subreg(lp
, SR_CHANNEL
, channel
);
533 msleep(1); /* Wait for PLL */
534 dev
->phy
->current_channel
= channel
;
540 at86rf230_xmit(struct ieee802154_dev
*dev
, struct sk_buff
*skb
)
542 struct at86rf230_local
*lp
= dev
->priv
;
546 spin_lock(&lp
->lock
);
547 if (lp
->irq_disabled
) {
548 spin_unlock(&lp
->lock
);
551 spin_unlock(&lp
->lock
);
555 rc
= at86rf230_state(dev
, STATE_FORCE_TX_ON
);
559 spin_lock_irqsave(&lp
->lock
, flags
);
561 INIT_COMPLETION(lp
->tx_complete
);
562 spin_unlock_irqrestore(&lp
->lock
, flags
);
564 rc
= at86rf230_write_fbuf(lp
, skb
->data
, skb
->len
);
568 rc
= at86rf230_write_subreg(lp
, SR_TRX_CMD
, STATE_BUSY_TX
);
572 rc
= wait_for_completion_interruptible(&lp
->tx_complete
);
576 rc
= at86rf230_start(dev
);
581 at86rf230_start(dev
);
583 pr_err("error: %d\n", rc
);
585 spin_lock_irqsave(&lp
->lock
, flags
);
587 spin_unlock_irqrestore(&lp
->lock
, flags
);
592 static int at86rf230_rx(struct at86rf230_local
*lp
)
594 u8 len
= 128, lqi
= 0;
597 skb
= alloc_skb(len
, GFP_KERNEL
);
602 if (at86rf230_read_fbuf(lp
, skb_put(skb
, len
), &len
, &lqi
))
608 skb_trim(skb
, len
- 2); /* We do not put CRC into the frame */
610 ieee802154_rx_irqsafe(lp
->dev
, skb
, lqi
);
612 dev_dbg(&lp
->spi
->dev
, "READ_FBUF: %d %x\n", len
, lqi
);
616 pr_debug("received frame is too small\n");
622 static struct ieee802154_ops at86rf230_ops
= {
623 .owner
= THIS_MODULE
,
624 .xmit
= at86rf230_xmit
,
626 .set_channel
= at86rf230_channel
,
627 .start
= at86rf230_start
,
628 .stop
= at86rf230_stop
,
631 static void at86rf230_irqwork(struct work_struct
*work
)
633 struct at86rf230_local
*lp
=
634 container_of(work
, struct at86rf230_local
, irqwork
);
639 rc
= at86rf230_read_subreg(lp
, RG_IRQ_STATUS
, 0xff, 0, &val
);
642 status
&= ~IRQ_PLL_LOCK
; /* ignore */
643 status
&= ~IRQ_RX_START
; /* ignore */
644 status
&= ~IRQ_AMI
; /* ignore */
645 status
&= ~IRQ_TRX_UR
; /* FIXME: possibly handle ???*/
647 if (status
& IRQ_TRX_END
) {
648 spin_lock_irqsave(&lp
->lock
, flags
);
649 status
&= ~IRQ_TRX_END
;
652 spin_unlock_irqrestore(&lp
->lock
, flags
);
653 complete(&lp
->tx_complete
);
655 spin_unlock_irqrestore(&lp
->lock
, flags
);
660 spin_lock_irqsave(&lp
->lock
, flags
);
661 lp
->irq_disabled
= 0;
662 spin_unlock_irqrestore(&lp
->lock
, flags
);
664 enable_irq(lp
->spi
->irq
);
667 static irqreturn_t
at86rf230_isr(int irq
, void *data
)
669 struct at86rf230_local
*lp
= data
;
671 disable_irq_nosync(irq
);
673 spin_lock(&lp
->lock
);
674 lp
->irq_disabled
= 1;
675 spin_unlock(&lp
->lock
);
677 schedule_work(&lp
->irqwork
);
683 static int at86rf230_hw_init(struct at86rf230_local
*lp
)
688 rc
= at86rf230_read_subreg(lp
, SR_TRX_STATUS
, &status
);
692 dev_info(&lp
->spi
->dev
, "Status: %02x\n", status
);
693 if (status
== STATE_P_ON
) {
694 rc
= at86rf230_write_subreg(lp
, SR_TRX_CMD
, STATE_TRX_OFF
);
698 rc
= at86rf230_read_subreg(lp
, SR_TRX_STATUS
, &status
);
701 dev_info(&lp
->spi
->dev
, "Status: %02x\n", status
);
704 rc
= at86rf230_write_subreg(lp
, SR_IRQ_MASK
, 0xff); /* IRQ_TRX_UR |
713 /* CLKM changes are applied immediately */
714 rc
= at86rf230_write_subreg(lp
, SR_CLKM_SHA_SEL
, 0x00);
719 rc
= at86rf230_write_subreg(lp
, SR_CLKM_CTRL
, 0x00);
722 /* Wait the next SLEEP cycle */
725 rc
= at86rf230_write_subreg(lp
, SR_TRX_CMD
, STATE_TX_ON
);
730 rc
= at86rf230_read_subreg(lp
, SR_TRX_STATUS
, &status
);
733 dev_info(&lp
->spi
->dev
, "Status: %02x\n", status
);
735 rc
= at86rf230_read_subreg(lp
, SR_DVDD_OK
, &status
);
739 dev_err(&lp
->spi
->dev
, "DVDD error\n");
743 rc
= at86rf230_read_subreg(lp
, SR_AVDD_OK
, &status
);
747 dev_err(&lp
->spi
->dev
, "AVDD error\n");
754 static int at86rf230_suspend(struct spi_device
*spi
, pm_message_t message
)
759 static int at86rf230_resume(struct spi_device
*spi
)
764 static int at86rf230_fill_data(struct spi_device
*spi
)
766 struct at86rf230_local
*lp
= spi_get_drvdata(spi
);
767 struct at86rf230_platform_data
*pdata
= spi
->dev
.platform_data
;
770 dev_err(&spi
->dev
, "no platform_data\n");
774 lp
->rstn
= pdata
->rstn
;
775 lp
->slp_tr
= pdata
->slp_tr
;
776 lp
->dig2
= pdata
->dig2
;
781 static int __devinit
at86rf230_probe(struct spi_device
*spi
)
783 struct ieee802154_dev
*dev
;
784 struct at86rf230_local
*lp
;
785 u8 man_id_0
, man_id_1
;
791 dev_err(&spi
->dev
, "no IRQ specified\n");
795 dev
= ieee802154_alloc_device(sizeof(*lp
), &at86rf230_ops
);
805 dev
->parent
= &spi
->dev
;
806 dev
->extra_tx_headroom
= 0;
807 /* We do support only 2.4 Ghz */
808 dev
->phy
->channels_supported
[0] = 0x7FFF800;
809 dev
->flags
= IEEE802154_HW_OMIT_CKSUM
;
811 mutex_init(&lp
->bmux
);
812 INIT_WORK(&lp
->irqwork
, at86rf230_irqwork
);
813 spin_lock_init(&lp
->lock
);
814 init_completion(&lp
->tx_complete
);
816 spi_set_drvdata(spi
, lp
);
818 rc
= at86rf230_fill_data(spi
);
822 rc
= gpio_request(lp
->rstn
, "rstn");
826 if (gpio_is_valid(lp
->slp_tr
)) {
827 rc
= gpio_request(lp
->slp_tr
, "slp_tr");
832 rc
= gpio_direction_output(lp
->rstn
, 1);
836 if (gpio_is_valid(lp
->slp_tr
)) {
837 rc
= gpio_direction_output(lp
->slp_tr
, 0);
844 gpio_set_value(lp
->rstn
, 0);
846 gpio_set_value(lp
->rstn
, 1);
849 rc
= at86rf230_read_subreg(lp
, SR_MAN_ID_0
, &man_id_0
);
852 rc
= at86rf230_read_subreg(lp
, SR_MAN_ID_1
, &man_id_1
);
856 if (man_id_1
!= 0x00 || man_id_0
!= 0x1f) {
857 dev_err(&spi
->dev
, "Non-Atmel dev found (MAN_ID %02x %02x)\n",
863 rc
= at86rf230_read_subreg(lp
, SR_PART_NUM
, &lp
->part
);
867 rc
= at86rf230_read_subreg(lp
, SR_VERSION_NUM
, &lp
->vers
);
874 /* supported = 1; FIXME: should be easy to support; */
885 dev_info(&spi
->dev
, "Detected %s chip version %d\n", chip
, lp
->vers
);
891 rc
= at86rf230_hw_init(lp
);
895 rc
= request_irq(spi
->irq
, at86rf230_isr
, IRQF_SHARED
,
896 dev_name(&spi
->dev
), lp
);
900 rc
= ieee802154_register_device(lp
->dev
);
906 ieee802154_unregister_device(lp
->dev
);
908 free_irq(spi
->irq
, lp
);
909 flush_work(&lp
->irqwork
);
911 if (gpio_is_valid(lp
->slp_tr
))
912 gpio_free(lp
->slp_tr
);
917 spi_set_drvdata(spi
, NULL
);
918 mutex_destroy(&lp
->bmux
);
919 ieee802154_free_device(lp
->dev
);
923 static int __devexit
at86rf230_remove(struct spi_device
*spi
)
925 struct at86rf230_local
*lp
= spi_get_drvdata(spi
);
927 ieee802154_unregister_device(lp
->dev
);
929 free_irq(spi
->irq
, lp
);
930 flush_work(&lp
->irqwork
);
932 if (gpio_is_valid(lp
->slp_tr
))
933 gpio_free(lp
->slp_tr
);
936 spi_set_drvdata(spi
, NULL
);
937 mutex_destroy(&lp
->bmux
);
938 ieee802154_free_device(lp
->dev
);
940 dev_dbg(&spi
->dev
, "unregistered at86rf230\n");
944 static struct spi_driver at86rf230_driver
= {
947 .owner
= THIS_MODULE
,
949 .probe
= at86rf230_probe
,
950 .remove
= __devexit_p(at86rf230_remove
),
951 .suspend
= at86rf230_suspend
,
952 .resume
= at86rf230_resume
,
955 static int __init
at86rf230_init(void)
957 return spi_register_driver(&at86rf230_driver
);
959 module_init(at86rf230_init
);
961 static void __exit
at86rf230_exit(void)
963 spi_unregister_driver(&at86rf230_driver
);
965 module_exit(at86rf230_exit
);
967 MODULE_DESCRIPTION("AT86RF230 Transceiver Driver");
968 MODULE_LICENSE("GPL v2");