drivers/media/video/s5p-fimc/fimc-core.h

   1 /*
   2  * Copyright (C) 2010 - 2012 Samsung Electronics Co., Ltd.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #ifndef FIMC_CORE_H_
  10 #define FIMC_CORE_H_
  11
  12 /*#define DEBUG*/
  13
  14 #include <linux/platform_device.h>
  15 #include <linux/sched.h>
  16 #include <linux/spinlock.h>
  17 #include <linux/types.h>
  18 #include <linux/videodev2.h>
  19 #include <linux/io.h>
  20 #include <asm/sizes.h>
  21
  22 #include <media/media-entity.h>
  23 #include <media/videobuf2-core.h>
  24 #include <media/v4l2-ctrls.h>
  25 #include <media/v4l2-device.h>
  26 #include <media/v4l2-mem2mem.h>
  27 #include <media/v4l2-mediabus.h>
  28 #include <media/s5p_fimc.h>
  29
  30 #define dbg(fmt, args...) \
  31         pr_debug("%s:%d: " fmt "\n", __func__, __LINE__, ##args)
  32
  33 /* Time to wait for next frame VSYNC interrupt while stopping operation. */
  34 #define FIMC_SHUTDOWN_TIMEOUT   ((100*HZ)/1000)
  35 #define MAX_FIMC_CLOCKS         2
  36 #define FIMC_MODULE_NAME        "s5p-fimc"
  37 #define FIMC_MAX_DEVS           4
  38 #define FIMC_MAX_OUT_BUFS       4
  39 #define SCALER_MAX_HRATIO       64
  40 #define SCALER_MAX_VRATIO       64
  41 #define DMA_MIN_SIZE            8
  42 #define FIMC_CAMIF_MAX_HEIGHT   0x2000
  43
  44 /* indices to the clocks array */
  45 enum {
  46         CLK_BUS,
  47         CLK_GATE,
  48 };
  49
  50 enum fimc_dev_flags {
  51         ST_LPM,
  52         /* m2m node */
  53         ST_M2M_RUN,
  54         ST_M2M_PEND,
  55         ST_M2M_SUSPENDING,
  56         ST_M2M_SUSPENDED,
  57         /* capture node */
  58         ST_CAPT_PEND,
  59         ST_CAPT_RUN,
  60         ST_CAPT_STREAM,
  61         ST_CAPT_ISP_STREAM,
  62         ST_CAPT_SUSPENDED,
  63         ST_CAPT_SHUT,
  64         ST_CAPT_BUSY,
  65         ST_CAPT_APPLY_CFG,
  66         ST_CAPT_JPEG,
  67 };
  68
  69 #define fimc_m2m_active(dev) test_bit(ST_M2M_RUN, &(dev)->state)
  70 #define fimc_m2m_pending(dev) test_bit(ST_M2M_PEND, &(dev)->state)
  71
  72 #define fimc_capture_running(dev) test_bit(ST_CAPT_RUN, &(dev)->state)
  73 #define fimc_capture_pending(dev) test_bit(ST_CAPT_PEND, &(dev)->state)
  74 #define fimc_capture_busy(dev) test_bit(ST_CAPT_BUSY, &(dev)->state)
  75
  76 enum fimc_datapath {
  77         FIMC_IO_NONE,
  78         FIMC_IO_CAMERA,
  79         FIMC_IO_DMA,
  80         FIMC_IO_LCDFIFO,
  81         FIMC_IO_WRITEBACK,
  82         FIMC_IO_ISP,
  83 };
  84
  85 enum fimc_color_fmt {
  86         FIMC_FMT_RGB444 = 0x10,
  87         FIMC_FMT_RGB555,
  88         FIMC_FMT_RGB565,
  89         FIMC_FMT_RGB666,
  90         FIMC_FMT_RGB888,
  91         FIMC_FMT_RGB30_LOCAL,
  92         FIMC_FMT_YCBCR420 = 0x20,
  93         FIMC_FMT_YCBYCR422,
  94         FIMC_FMT_YCRYCB422,
  95         FIMC_FMT_CBYCRY422,
  96         FIMC_FMT_CRYCBY422,
  97         FIMC_FMT_YCBCR444_LOCAL,
  98         FIMC_FMT_JPEG = 0x40,
  99         FIMC_FMT_RAW8 = 0x80,
 100         FIMC_FMT_RAW10,
 101         FIMC_FMT_RAW12,
 102 };
 103
 104 #define fimc_fmt_is_rgb(x) (!!((x) & 0x10))
 105 #define fimc_fmt_is_jpeg(x) (!!((x) & 0x40))
 106
 107 #define IS_M2M(__strt) ((__strt) == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE || \
 108                         __strt == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
 109
 110 /* The hardware context state. */
 111 #define FIMC_PARAMS             (1 << 0)
 112 #define FIMC_SRC_FMT            (1 << 3)
 113 #define FIMC_DST_FMT            (1 << 4)
 114 #define FIMC_COMPOSE            (1 << 5)
 115 #define FIMC_CTX_M2M            (1 << 16)
 116 #define FIMC_CTX_CAP            (1 << 17)
 117 #define FIMC_CTX_SHUT           (1 << 18)
 118
 119 /* Image conversion flags */
 120 #define FIMC_IN_DMA_ACCESS_TILED        (1 << 0)
 121 #define FIMC_IN_DMA_ACCESS_LINEAR       (0 << 0)
 122 #define FIMC_OUT_DMA_ACCESS_TILED       (1 << 1)
 123 #define FIMC_OUT_DMA_ACCESS_LINEAR      (0 << 1)
 124 #define FIMC_SCAN_MODE_PROGRESSIVE      (0 << 2)
 125 #define FIMC_SCAN_MODE_INTERLACED       (1 << 2)
 126 /*
 127  * YCbCr data dynamic range for RGB-YUV color conversion.
 128  * Y/Cb/Cr: (0 ~ 255) */
 129 #define FIMC_COLOR_RANGE_WIDE           (0 << 3)
 130 /* Y (16 ~ 235), Cb/Cr (16 ~ 240) */
 131 #define FIMC_COLOR_RANGE_NARROW         (1 << 3)
 132
 133 /**
 134  * struct fimc_fmt - the driver's internal color format data
 135  * @mbus_code: Media Bus pixel code, -1 if not applicable
 136  * @name: format description
 137  * @fourcc: the fourcc code for this format, 0 if not applicable
 138  * @color: the corresponding fimc_color_fmt
 139  * @memplanes: number of physically non-contiguous data planes
 140  * @colplanes: number of physically contiguous data planes
 141  * @depth: per plane driver's private 'number of bits per pixel'
 142  * @flags: flags indicating which operation mode format applies to
 143  */
 144 struct fimc_fmt {
 145         enum v4l2_mbus_pixelcode mbus_code;
 146         char    *name;
 147         u32     fourcc;
 148         u32     color;
 149         u16     memplanes;
 150         u16     colplanes;
 151         u8      depth[VIDEO_MAX_PLANES];
 152         u16     flags;
 153 #define FMT_FLAGS_CAM           (1 << 0)
 154 #define FMT_FLAGS_M2M_IN        (1 << 1)
 155 #define FMT_FLAGS_M2M_OUT       (1 << 2)
 156 #define FMT_FLAGS_M2M           (1 << 1 | 1 << 2)
 157 #define FMT_HAS_ALPHA           (1 << 3)
 158 };
 159
 160 /**
 161  * struct fimc_dma_offset - pixel offset information for DMA
 162  * @y_h:        y value horizontal offset
 163  * @y_v:        y value vertical offset
 164  * @cb_h:       cb value horizontal offset
 165  * @cb_v:       cb value vertical offset
 166  * @cr_h:       cr value horizontal offset
 167  * @cr_v:       cr value vertical offset
 168  */
 169 struct fimc_dma_offset {
 170         int     y_h;
 171         int     y_v;
 172         int     cb_h;
 173         int     cb_v;
 174         int     cr_h;
 175         int     cr_v;
 176 };
 177
 178 /**
 179  * struct fimc_effect - color effect information
 180  * @type:       effect type
 181  * @pat_cb:     cr value when type is "arbitrary"
 182  * @pat_cr:     cr value when type is "arbitrary"
 183  */
 184 struct fimc_effect {
 185         u32     type;
 186         u8      pat_cb;
 187         u8      pat_cr;
 188 };
 189
 190 /**
 191  * struct fimc_scaler - the configuration data for FIMC inetrnal scaler
 192  * @scaleup_h:          flag indicating scaling up horizontally
 193  * @scaleup_v:          flag indicating scaling up vertically
 194  * @copy_mode:          flag indicating transparent DMA transfer (no scaling
 195  *                      and color format conversion)
 196  * @enabled:            flag indicating if the scaler is used
 197  * @hfactor:            horizontal shift factor
 198  * @vfactor:            vertical shift factor
 199  * @pre_hratio:         horizontal ratio of the prescaler
 200  * @pre_vratio:         vertical ratio of the prescaler
 201  * @pre_dst_width:      the prescaler's destination width
 202  * @pre_dst_height:     the prescaler's destination height
 203  * @main_hratio:        the main scaler's horizontal ratio
 204  * @main_vratio:        the main scaler's vertical ratio
 205  * @real_width:         source pixel (width - offset)
 206  * @real_height:        source pixel (height - offset)
 207  */
 208 struct fimc_scaler {
 209         unsigned int scaleup_h:1;
 210         unsigned int scaleup_v:1;
 211         unsigned int copy_mode:1;
 212         unsigned int enabled:1;
 213         u32     hfactor;
 214         u32     vfactor;
 215         u32     pre_hratio;
 216         u32     pre_vratio;
 217         u32     pre_dst_width;
 218         u32     pre_dst_height;
 219         u32     main_hratio;
 220         u32     main_vratio;
 221         u32     real_width;
 222         u32     real_height;
 223 };
 224
 225 /**
 226  * struct fimc_addr - the FIMC physical address set for DMA
 227  * @y:   luminance plane physical address
 228  * @cb:  Cb plane physical address
 229  * @cr:  Cr plane physical address
 230  */
 231 struct fimc_addr {
 232         u32     y;
 233         u32     cb;
 234         u32     cr;
 235 };
 236
 237 /**
 238  * struct fimc_vid_buffer - the driver's video buffer
 239  * @vb:    v4l videobuf buffer
 240  * @list:  linked list structure for buffer queue
 241  * @paddr: precalculated physical address set
 242  * @index: buffer index for the output DMA engine
 243  */
 244 struct fimc_vid_buffer {
 245         struct vb2_buffer       vb;
 246         struct list_head        list;
 247         struct fimc_addr        paddr;
 248         int                     index;
 249 };
 250
 251 /**
 252  * struct fimc_frame - source/target frame properties
 253  * @f_width:    image full width (virtual screen size)
 254  * @f_height:   image full height (virtual screen size)
 255  * @o_width:    original image width as set by S_FMT
 256  * @o_height:   original image height as set by S_FMT
 257  * @offs_h:     image horizontal pixel offset
 258  * @offs_v:     image vertical pixel offset
 259  * @width:      image pixel width
 260  * @height:     image pixel weight
 261  * @payload:    image size in bytes (w x h x bpp)
 262  * @paddr:      image frame buffer physical addresses
 263  * @dma_offset: DMA offset in bytes
 264  * @fmt:        fimc color format pointer
 265  */
 266 struct fimc_frame {
 267         u32     f_width;
 268         u32     f_height;
 269         u32     o_width;
 270         u32     o_height;
 271         u32     offs_h;
 272         u32     offs_v;
 273         u32     width;
 274         u32     height;
 275         unsigned long           payload[VIDEO_MAX_PLANES];
 276         struct fimc_addr        paddr;
 277         struct fimc_dma_offset  dma_offset;
 278         struct fimc_fmt         *fmt;
 279         u8                      alpha;
 280 };
 281
 282 /**
 283  * struct fimc_m2m_device - v4l2 memory-to-memory device data
 284  * @vfd: the video device node for v4l2 m2m mode
 285  * @m2m_dev: v4l2 memory-to-memory device data
 286  * @ctx: hardware context data
 287  * @refcnt: the reference counter
 288  */
 289 struct fimc_m2m_device {
 290         struct video_device     *vfd;
 291         struct v4l2_m2m_dev     *m2m_dev;
 292         struct fimc_ctx         *ctx;
 293         int                     refcnt;
 294 };
 295
 296 #define FIMC_SD_PAD_SINK        0
 297 #define FIMC_SD_PAD_SOURCE      1
 298 #define FIMC_SD_PADS_NUM        2
 299
 300 /**
 301  * struct fimc_vid_cap - camera capture device information
 302  * @ctx: hardware context data
 303  * @vfd: video device node for camera capture mode
 304  * @subdev: subdev exposing the FIMC processing block
 305  * @vd_pad: fimc video capture node pad
 306  * @sd_pads: fimc video processing block pads
 307  * @mf: media bus format at the FIMC camera input (and the scaler output) pad
 308  * @pending_buf_q: the pending buffer queue head
 309  * @active_buf_q: the queue head of buffers scheduled in hardware
 310  * @vbq: the capture am video buffer queue
 311  * @active_buf_cnt: number of video buffers scheduled in hardware
 312  * @buf_index: index for managing the output DMA buffers
 313  * @frame_count: the frame counter for statistics
 314  * @reqbufs_count: the number of buffers requested in REQBUFS ioctl
 315  * @input_index: input (camera sensor) index
 316  * @refcnt: driver's private reference counter
 317  * @input: capture input type, grp_id of the attached subdev
 318  * @user_subdev_api: true if subdevs are not configured by the host driver
 319  */
 320 struct fimc_vid_cap {
 321         struct fimc_ctx                 *ctx;
 322         struct vb2_alloc_ctx            *alloc_ctx;
 323         struct video_device             *vfd;
 324         struct v4l2_subdev              subdev;
 325         struct media_pad                vd_pad;
 326         struct v4l2_mbus_framefmt       mf;
 327         struct media_pad                sd_pads[FIMC_SD_PADS_NUM];
 328         struct list_head                pending_buf_q;
 329         struct list_head                active_buf_q;
 330         struct vb2_queue                vbq;
 331         int                             active_buf_cnt;
 332         int                             buf_index;
 333         unsigned int                    frame_count;
 334         unsigned int                    reqbufs_count;
 335         int                             input_index;
 336         int                             refcnt;
 337         u32                             input;
 338         bool                            user_subdev_api;
 339 };
 340
 341 /**
 342  *  struct fimc_pix_limit - image pixel size limits in various IP configurations
 343  *
 344  *  @scaler_en_w: max input pixel width when the scaler is enabled
 345  *  @scaler_dis_w: max input pixel width when the scaler is disabled
 346  *  @in_rot_en_h: max input width with the input rotator is on
 347  *  @in_rot_dis_w: max input width with the input rotator is off
 348  *  @out_rot_en_w: max output width with the output rotator on
 349  *  @out_rot_dis_w: max output width with the output rotator off
 350  */
 351 struct fimc_pix_limit {
 352         u16 scaler_en_w;
 353         u16 scaler_dis_w;
 354         u16 in_rot_en_h;
 355         u16 in_rot_dis_w;
 356         u16 out_rot_en_w;
 357         u16 out_rot_dis_w;
 358 };
 359
 360 /**
 361  * struct fimc_variant - FIMC device variant information
 362  * @pix_hoff: indicate whether horizontal offset is in pixels or in bytes
 363  * @has_inp_rot: set if has input rotator
 364  * @has_out_rot: set if has output rotator
 365  * @has_cistatus2: 1 if CISTATUS2 register is present in this IP revision
 366  * @has_mainscaler_ext: 1 if extended mainscaler ratios in CIEXTEN register
 367  *                       are present in this IP revision
 368  * @has_cam_if: set if this instance has a camera input interface
 369  * @pix_limit: pixel size constraints for the scaler
 370  * @min_inp_pixsize: minimum input pixel size
 371  * @min_out_pixsize: minimum output pixel size
 372  * @hor_offs_align: horizontal pixel offset aligment
 373  * @min_vsize_align: minimum vertical pixel size alignment
 374  * @out_buf_count: the number of buffers in output DMA sequence
 375  */
 376 struct fimc_variant {
 377         unsigned int    pix_hoff:1;
 378         unsigned int    has_inp_rot:1;
 379         unsigned int    has_out_rot:1;
 380         unsigned int    has_cistatus2:1;
 381         unsigned int    has_mainscaler_ext:1;
 382         unsigned int    has_cam_if:1;
 383         unsigned int    has_alpha:1;
 384         struct fimc_pix_limit *pix_limit;
 385         u16             min_inp_pixsize;
 386         u16             min_out_pixsize;
 387         u16             hor_offs_align;
 388         u16             min_vsize_align;
 389         u16             out_buf_count;
 390 };
 391
 392 /**
 393  * struct fimc_drvdata - per device type driver data
 394  * @variant: variant information for this device
 395  * @num_entities: number of fimc instances available in a SoC
 396  * @lclk_frequency: local bus clock frequency
 397  */
 398 struct fimc_drvdata {
 399         struct fimc_variant *variant[FIMC_MAX_DEVS];
 400         int num_entities;
 401         unsigned long lclk_frequency;
 402 };
 403
 404 #define fimc_get_drvdata(_pdev) \
 405         ((struct fimc_drvdata *) platform_get_device_id(_pdev)->driver_data)
 406
 407 struct fimc_ctx;
 408
 409 /**
 410  * struct fimc_dev - abstraction for FIMC entity
 411  * @slock:      the spinlock protecting this data structure
 412  * @lock:       the mutex protecting this data structure
 413  * @pdev:       pointer to the FIMC platform device
 414  * @pdata:      pointer to the device platform data
 415  * @variant:    the IP variant information
 416  * @id:         FIMC device index (0..FIMC_MAX_DEVS)
 417  * @clock:      clocks required for FIMC operation
 418  * @regs:       the mapped hardware registers
 419  * @irq_queue:  interrupt handler waitqueue
 420  * @v4l2_dev:   root v4l2_device
 421  * @m2m:        memory-to-memory V4L2 device information
 422  * @vid_cap:    camera capture device information
 423  * @state:      flags used to synchronize m2m and capture mode operation
 424  * @alloc_ctx:  videobuf2 memory allocator context
 425  * @pipeline:   fimc video capture pipeline data structure
 426  */
 427 struct fimc_dev {
 428         spinlock_t                      slock;
 429         struct mutex                    lock;
 430         struct platform_device          *pdev;
 431         struct s5p_platform_fimc        *pdata;
 432         struct fimc_variant             *variant;
 433         u16                             id;
 434         struct clk                      *clock[MAX_FIMC_CLOCKS];
 435         void __iomem                    *regs;
 436         wait_queue_head_t               irq_queue;
 437         struct v4l2_device              *v4l2_dev;
 438         struct fimc_m2m_device          m2m;
 439         struct fimc_vid_cap             vid_cap;
 440         unsigned long                   state;
 441         struct vb2_alloc_ctx            *alloc_ctx;
 442         struct fimc_pipeline            pipeline;
 443 };
 444
 445 /**
 446  * struct fimc_ctrls - v4l2 controls structure
 447  * @handler: the control handler
 448  * @colorfx: image effect control
 449  * @colorfx_cbcr: Cb/Cr coefficients control
 450  * @rotate: image rotation control
 451  * @hflip: horizontal flip control
 452  * @vflip: vertical flip control
 453  * @alpha: RGB alpha control
 454  * @ready: true if @handler is initialized
 455  */
 456 struct fimc_ctrls {
 457         struct v4l2_ctrl_handler handler;
 458         struct {
 459                 struct v4l2_ctrl *colorfx;
 460                 struct v4l2_ctrl *colorfx_cbcr;
 461         };
 462         struct v4l2_ctrl *rotate;
 463         struct v4l2_ctrl *hflip;
 464         struct v4l2_ctrl *vflip;
 465         struct v4l2_ctrl *alpha;
 466         bool ready;
 467 };
 468
 469 /**
 470  * fimc_ctx - the device context data
 471  * @s_frame:            source frame properties
 472  * @d_frame:            destination frame properties
 473  * @out_order_1p:       output 1-plane YCBCR order
 474  * @out_order_2p:       output 2-plane YCBCR order
 475  * @in_order_1p         input 1-plane YCBCR order
 476  * @in_order_2p:        input 2-plane YCBCR order
 477  * @in_path:            input mode (DMA or camera)
 478  * @out_path:           output mode (DMA or FIFO)
 479  * @scaler:             image scaler properties
 480  * @effect:             image effect
 481  * @rotation:           image clockwise rotation in degrees
 482  * @hflip:              indicates image horizontal flip if set
 483  * @vflip:              indicates image vertical flip if set
 484  * @flags:              additional flags for image conversion
 485  * @state:              flags to keep track of user configuration
 486  * @fimc_dev:           the FIMC device this context applies to
 487  * @m2m_ctx:            memory-to-memory device context
 488  * @fh:                 v4l2 file handle
 489  * @ctrls:              v4l2 controls structure
 490  */
 491 struct fimc_ctx {
 492         struct fimc_frame       s_frame;
 493         struct fimc_frame       d_frame;
 494         u32                     out_order_1p;
 495         u32                     out_order_2p;
 496         u32                     in_order_1p;
 497         u32                     in_order_2p;
 498         enum fimc_datapath      in_path;
 499         enum fimc_datapath      out_path;
 500         struct fimc_scaler      scaler;
 501         struct fimc_effect      effect;
 502         int                     rotation;
 503         unsigned int            hflip:1;
 504         unsigned int            vflip:1;
 505         u32                     flags;
 506         u32                     state;
 507         struct fimc_dev         *fimc_dev;
 508         struct v4l2_m2m_ctx     *m2m_ctx;
 509         struct v4l2_fh          fh;
 510         struct fimc_ctrls       ctrls;
 511 };
 512
 513 #define fh_to_ctx(__fh) container_of(__fh, struct fimc_ctx, fh)
 514
 515 static inline void set_frame_bounds(struct fimc_frame *f, u32 width, u32 height)
 516 {
 517         f->o_width  = width;
 518         f->o_height = height;
 519         f->f_width  = width;
 520         f->f_height = height;
 521 }
 522
 523 static inline void set_frame_crop(struct fimc_frame *f,
 524                                   u32 left, u32 top, u32 width, u32 height)
 525 {
 526         f->offs_h = left;
 527         f->offs_v = top;
 528         f->width  = width;
 529         f->height = height;
 530 }
 531
 532 static inline u32 fimc_get_format_depth(struct fimc_fmt *ff)
 533 {
 534         u32 i, depth = 0;
 535
 536         if (ff != NULL)
 537                 for (i = 0; i < ff->colplanes; i++)
 538                         depth += ff->depth[i];
 539         return depth;
 540 }
 541
 542 static inline bool fimc_capture_active(struct fimc_dev *fimc)
 543 {
 544         unsigned long flags;
 545         bool ret;
 546
 547         spin_lock_irqsave(&fimc->slock, flags);
 548         ret = !!(fimc->state & (1 << ST_CAPT_RUN) ||
 549                  fimc->state & (1 << ST_CAPT_PEND));
 550         spin_unlock_irqrestore(&fimc->slock, flags);
 551         return ret;
 552 }
 553
 554 static inline void fimc_ctx_state_set(u32 state, struct fimc_ctx *ctx)
 555 {
 556         unsigned long flags;
 557
 558         spin_lock_irqsave(&ctx->fimc_dev->slock, flags);
 559         ctx->state |= state;
 560         spin_unlock_irqrestore(&ctx->fimc_dev->slock, flags);
 561 }
 562
 563 static inline bool fimc_ctx_state_is_set(u32 mask, struct fimc_ctx *ctx)
 564 {
 565         unsigned long flags;
 566         bool ret;
 567
 568         spin_lock_irqsave(&ctx->fimc_dev->slock, flags);
 569         ret = (ctx->state & mask) == mask;
 570         spin_unlock_irqrestore(&ctx->fimc_dev->slock, flags);
 571         return ret;
 572 }
 573
 574 static inline int tiled_fmt(struct fimc_fmt *fmt)
 575 {
 576         return fmt->fourcc == V4L2_PIX_FMT_NV12MT;
 577 }
 578
 579 /* Return the alpha component bit mask */
 580 static inline int fimc_get_alpha_mask(struct fimc_fmt *fmt)
 581 {
 582         switch (fmt->color) {
 583         case FIMC_FMT_RGB444:   return 0x0f;
 584         case FIMC_FMT_RGB555:   return 0x01;
 585         case FIMC_FMT_RGB888:   return 0xff;
 586         default:                return 0;
 587         };
 588 }
 589
 590 static inline struct fimc_frame *ctx_get_frame(struct fimc_ctx *ctx,
 591                                                enum v4l2_buf_type type)
 592 {
 593         struct fimc_frame *frame;
 594
 595         if (V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE == type) {
 596                 if (fimc_ctx_state_is_set(FIMC_CTX_M2M, ctx))
 597                         frame = &ctx->s_frame;
 598                 else
 599                         return ERR_PTR(-EINVAL);
 600         } else if (V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE == type) {
 601                 frame = &ctx->d_frame;
 602         } else {
 603                 v4l2_err(ctx->fimc_dev->v4l2_dev,
 604                         "Wrong buffer/video queue type (%d)\n", type);
 605                 return ERR_PTR(-EINVAL);
 606         }
 607
 608         return frame;
 609 }
 610
 611 /* -----------------------------------------------------*/
 612 /* fimc-core.c */
 613 int fimc_vidioc_enum_fmt_mplane(struct file *file, void *priv,
 614                                 struct v4l2_fmtdesc *f);
 615 int fimc_ctrls_create(struct fimc_ctx *ctx);
 616 void fimc_ctrls_delete(struct fimc_ctx *ctx);
 617 void fimc_ctrls_activate(struct fimc_ctx *ctx, bool active);
 618 void fimc_alpha_ctrl_update(struct fimc_ctx *ctx);
 619 int fimc_fill_format(struct fimc_frame *frame, struct v4l2_format *f);
 620 void fimc_adjust_mplane_format(struct fimc_fmt *fmt, u32 width, u32 height,
 621                                struct v4l2_pix_format_mplane *pix);
 622 struct fimc_fmt *fimc_find_format(const u32 *pixelformat, const u32 *mbus_code,
 623                                   unsigned int mask, int index);
 624 struct fimc_fmt *fimc_get_format(unsigned int index);
 625
 626 int fimc_check_scaler_ratio(struct fimc_ctx *ctx, int sw, int sh,
 627                             int dw, int dh, int rotation);
 628 int fimc_set_scaler_info(struct fimc_ctx *ctx);
 629 int fimc_prepare_config(struct fimc_ctx *ctx, u32 flags);
 630 int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb,
 631                       struct fimc_frame *frame, struct fimc_addr *paddr);
 632 void fimc_prepare_dma_offset(struct fimc_ctx *ctx, struct fimc_frame *f);
 633 void fimc_set_yuv_order(struct fimc_ctx *ctx);
 634 void fimc_fill_frame(struct fimc_frame *frame, struct v4l2_format *f);
 635 void fimc_capture_irq_handler(struct fimc_dev *fimc, int deq_buf);
 636
 637 int fimc_register_m2m_device(struct fimc_dev *fimc,
 638                              struct v4l2_device *v4l2_dev);
 639 void fimc_unregister_m2m_device(struct fimc_dev *fimc);
 640 int fimc_register_driver(void);
 641 void fimc_unregister_driver(void);
 642
 643 /* -----------------------------------------------------*/
 644 /* fimc-m2m.c */
 645 void fimc_m2m_job_finish(struct fimc_ctx *ctx, int vb_state);
 646
 647 /* -----------------------------------------------------*/
 648 /* fimc-capture.c                                       */
 649 int fimc_initialize_capture_subdev(struct fimc_dev *fimc);
 650 void fimc_unregister_capture_subdev(struct fimc_dev *fimc);
 651 int fimc_capture_ctrls_create(struct fimc_dev *fimc);
 652 void fimc_sensor_notify(struct v4l2_subdev *sd, unsigned int notification,
 653                         void *arg);
 654 int fimc_capture_suspend(struct fimc_dev *fimc);
 655 int fimc_capture_resume(struct fimc_dev *fimc);
 656
 657 /*
 658  * Buffer list manipulation functions. Must be called with fimc.slock held.
 659  */
 660
 661 /**
 662  * fimc_active_queue_add - add buffer to the capture active buffers queue
 663  * @buf: buffer to add to the active buffers list
 664  */
 665 static inline void fimc_active_queue_add(struct fimc_vid_cap *vid_cap,
 666                                          struct fimc_vid_buffer *buf)
 667 {
 668         list_add_tail(&buf->list, &vid_cap->active_buf_q);
 669         vid_cap->active_buf_cnt++;
 670 }
 671
 672 /**
 673  * fimc_active_queue_pop - pop buffer from the capture active buffers queue
 674  *
 675  * The caller must assure the active_buf_q list is not empty.
 676  */
 677 static inline struct fimc_vid_buffer *fimc_active_queue_pop(
 678                                     struct fimc_vid_cap *vid_cap)
 679 {
 680         struct fimc_vid_buffer *buf;
 681         buf = list_entry(vid_cap->active_buf_q.next,
 682                          struct fimc_vid_buffer, list);
 683         list_del(&buf->list);
 684         vid_cap->active_buf_cnt--;
 685         return buf;
 686 }
 687
 688 /**
 689  * fimc_pending_queue_add - add buffer to the capture pending buffers queue
 690  * @buf: buffer to add to the pending buffers list
 691  */
 692 static inline void fimc_pending_queue_add(struct fimc_vid_cap *vid_cap,
 693                                           struct fimc_vid_buffer *buf)
 694 {
 695         list_add_tail(&buf->list, &vid_cap->pending_buf_q);
 696 }
 697
 698 /**
 699  * fimc_pending_queue_pop - pop buffer from the capture pending buffers queue
 700  *
 701  * The caller must assure the pending_buf_q list is not empty.
 702  */
 703 static inline struct fimc_vid_buffer *fimc_pending_queue_pop(
 704                                      struct fimc_vid_cap *vid_cap)
 705 {
 706         struct fimc_vid_buffer *buf;
 707         buf = list_entry(vid_cap->pending_buf_q.next,
 708                         struct fimc_vid_buffer, list);
 709         list_del(&buf->list);
 710         return buf;
 711 }
 712
 713 #endif /* FIMC_CORE_H_ */