1 /*****************************************************************************
2 * Copyright 2004 - 2009 Broadcom Corporation. All rights reserved.
4 * Unless you and Broadcom execute a separate written software license
5 * agreement governing use of this software, this software is licensed to you
6 * under the terms of the GNU General Public License version 2, available at
7 * http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
9 * Notwithstanding the above, under no circumstances may you combine this
10 * software in any way with any other Broadcom software provided under a
11 * license other than the GPL, without Broadcom's express prior written
13 *****************************************************************************/
15 /* ---- Include Files ---------------------------------------------------- */
16 #include <linux/module.h>
17 #include <linux/types.h>
18 #include <linux/init.h>
19 #include <linux/kernel.h>
20 #include <linux/slab.h>
21 #include <linux/string.h>
22 #include <linux/ioport.h>
23 #include <linux/device.h>
24 #include <linux/delay.h>
25 #include <linux/err.h>
27 #include <linux/platform_device.h>
28 #include <linux/mtd/mtd.h>
29 #include <linux/mtd/nand.h>
30 #include <linux/mtd/nand_ecc.h>
31 #include <linux/mtd/partitions.h>
33 #include <asm/mach-types.h>
35 #include <mach/reg_nand.h>
36 #include <mach/reg_umi.h>
38 #include "nand_bcm_umi.h"
40 #include <mach/memory_settings.h>
44 #include <linux/dma-mapping.h>
45 #include <linux/completion.h>
47 /* ---- External Variable Declarations ----------------------------------- */
48 /* ---- External Function Prototypes ------------------------------------- */
49 /* ---- Public Variables ------------------------------------------------- */
50 /* ---- Private Constants and Types -------------------------------------- */
51 static const __devinitconst
char gBanner
[] = KERN_INFO \
52 "BCM UMI MTD NAND Driver: 1.00\n";
55 static uint8_t scan_ff_pattern
[] = { 0xff };
57 static struct nand_bbt_descr largepage_bbt
= {
61 .pattern
= scan_ff_pattern
66 ** Preallocate a buffer to avoid having to do this every dma operation.
67 ** This is the size of the preallocated coherent DMA buffer.
70 #define DMA_MIN_BUFLEN 512
71 #define DMA_MAX_BUFLEN PAGE_SIZE
72 #define USE_DIRECT_IO(len) (((len) < DMA_MIN_BUFLEN) || \
73 ((len) > DMA_MAX_BUFLEN))
76 * The current NAND data space goes from 0x80001900 to 0x80001FFF,
77 * which is only 0x700 = 1792 bytes long. This is too small for 2K, 4K page
78 * size NAND flash. Need to break the DMA down to multiple 1Ks.
80 * Need to make sure REG_NAND_DATA_PADDR + DMA_MAX_LEN < 0x80002000
82 #define DMA_MAX_LEN 1024
85 #define DMA_MIN_BUFLEN 0
86 #define DMA_MAX_BUFLEN 0
87 #define USE_DIRECT_IO(len) 1
89 /* ---- Private Function Prototypes -------------------------------------- */
90 static void bcm_umi_nand_read_buf(struct mtd_info
*mtd
, u_char
* buf
, int len
);
91 static void bcm_umi_nand_write_buf(struct mtd_info
*mtd
, const u_char
* buf
,
94 /* ---- Private Variables ------------------------------------------------ */
95 static struct mtd_info
*board_mtd
;
96 static void __iomem
*bcm_umi_io_base
;
98 static dma_addr_t physPtr
;
99 static struct completion nand_comp
;
101 /* ---- Private Functions ------------------------------------------------ */
103 #include "bcm_umi_bch.c"
105 #include "bcm_umi_hamming.c"
110 /* Handler called when the DMA finishes. */
111 static void nand_dma_handler(DMA_Device_t dev
, int reason
, void *userData
)
113 complete(&nand_comp
);
116 static int nand_dma_init(void)
120 rc
= dma_set_device_handler(DMA_DEVICE_NAND_MEM_TO_MEM
,
121 nand_dma_handler
, NULL
);
123 printk(KERN_ERR
"dma_set_device_handler failed: %d\n", rc
);
128 dma_alloc_coherent(NULL
, DMA_MAX_BUFLEN
, &physPtr
, GFP_KERNEL
);
129 if (virtPtr
== NULL
) {
130 printk(KERN_ERR
"NAND - Failed to allocate memory for DMA buffer\n");
137 static void nand_dma_term(void)
140 dma_free_coherent(NULL
, DMA_MAX_BUFLEN
, virtPtr
, physPtr
);
143 static void nand_dma_read(void *buf
, int len
)
151 panic("nand_dma_read: virtPtr == NULL\n");
153 if ((void *)physPtr
== NULL
)
154 panic("nand_dma_read: physPtr == NULL\n");
156 hndl
= dma_request_channel(DMA_DEVICE_NAND_MEM_TO_MEM
);
159 "nand_dma_read: unable to allocate dma channel: %d\n",
164 while (len_left
> 0) {
165 if (len_left
> DMA_MAX_LEN
) {
166 tmp_len
= DMA_MAX_LEN
;
167 len_left
-= DMA_MAX_LEN
;
173 init_completion(&nand_comp
);
174 dma_transfer_mem_to_mem(hndl
, REG_NAND_DATA_PADDR
,
175 physPtr
+ offset
, tmp_len
);
176 wait_for_completion(&nand_comp
);
181 dma_free_channel(hndl
);
184 memcpy(buf
, virtPtr
, len
);
187 static void nand_dma_write(const void *buf
, int len
)
195 panic("nand_dma_write: buf == NULL\n");
198 panic("nand_dma_write: virtPtr == NULL\n");
200 if ((void *)physPtr
== NULL
)
201 panic("nand_dma_write: physPtr == NULL\n");
203 memcpy(virtPtr
, buf
, len
);
206 hndl
= dma_request_channel(DMA_DEVICE_NAND_MEM_TO_MEM
);
209 "nand_dma_write: unable to allocate dma channel: %d\n",
214 while (len_left
> 0) {
215 if (len_left
> DMA_MAX_LEN
) {
216 tmp_len
= DMA_MAX_LEN
;
217 len_left
-= DMA_MAX_LEN
;
223 init_completion(&nand_comp
);
224 dma_transfer_mem_to_mem(hndl
, physPtr
+ offset
,
225 REG_NAND_DATA_PADDR
, tmp_len
);
226 wait_for_completion(&nand_comp
);
231 dma_free_channel(hndl
);
236 static int nand_dev_ready(struct mtd_info
*mtd
)
238 return nand_bcm_umi_dev_ready();
241 /****************************************************************************
243 * bcm_umi_nand_inithw
245 * This routine does the necessary hardware (board-specific)
246 * initializations. This includes setting up the timings, etc.
248 ***************************************************************************/
249 int bcm_umi_nand_inithw(void)
251 /* Configure nand timing parameters */
252 REG_UMI_NAND_TCR
&= ~0x7ffff;
253 REG_UMI_NAND_TCR
|= HW_CFG_NAND_TCR
;
255 #if !defined(CONFIG_MTD_NAND_BCM_UMI_HWCS)
256 /* enable software control of CS */
257 REG_UMI_NAND_TCR
|= REG_UMI_NAND_TCR_CS_SWCTRL
;
260 /* keep NAND chip select asserted */
261 REG_UMI_NAND_RCSR
|= REG_UMI_NAND_RCSR_CS_ASSERTED
;
263 REG_UMI_NAND_TCR
&= ~REG_UMI_NAND_TCR_WORD16
;
264 /* enable writes to flash */
265 REG_UMI_MMD_ICR
|= REG_UMI_MMD_ICR_FLASH_WP
;
267 writel(NAND_CMD_RESET
, bcm_umi_io_base
+ REG_NAND_CMD_OFFSET
);
268 nand_bcm_umi_wait_till_ready();
271 nand_bcm_umi_bch_config_ecc(NAND_ECC_NUM_BYTES
);
277 /* Used to turn latch the proper register for access. */
278 static void bcm_umi_nand_hwcontrol(struct mtd_info
*mtd
, int cmd
,
281 /* send command to hardware */
282 struct nand_chip
*chip
= mtd
->priv
;
283 if (ctrl
& NAND_CTRL_CHANGE
) {
284 if (ctrl
& NAND_CLE
) {
285 chip
->IO_ADDR_W
= bcm_umi_io_base
+ REG_NAND_CMD_OFFSET
;
288 if (ctrl
& NAND_ALE
) {
290 bcm_umi_io_base
+ REG_NAND_ADDR_OFFSET
;
293 chip
->IO_ADDR_W
= bcm_umi_io_base
+ REG_NAND_DATA8_OFFSET
;
297 /* Send command to chip directly */
298 if (cmd
!= NAND_CMD_NONE
)
299 writeb(cmd
, chip
->IO_ADDR_W
);
302 static void bcm_umi_nand_write_buf(struct mtd_info
*mtd
, const u_char
* buf
,
305 if (USE_DIRECT_IO(len
)) {
306 /* Do it the old way if the buffer is small or too large.
307 * Probably quicker than starting and checking dma. */
309 struct nand_chip
*this = mtd
->priv
;
311 for (i
= 0; i
< len
; i
++)
312 writeb(buf
[i
], this->IO_ADDR_W
);
316 nand_dma_write(buf
, len
);
320 static void bcm_umi_nand_read_buf(struct mtd_info
*mtd
, u_char
* buf
, int len
)
322 if (USE_DIRECT_IO(len
)) {
324 struct nand_chip
*this = mtd
->priv
;
326 for (i
= 0; i
< len
; i
++)
327 buf
[i
] = readb(this->IO_ADDR_R
);
331 nand_dma_read(buf
, len
);
335 static uint8_t readbackbuf
[NAND_MAX_PAGESIZE
];
336 static int bcm_umi_nand_verify_buf(struct mtd_info
*mtd
, const u_char
* buf
,
340 * Try to readback page with ECC correction. This is necessary
341 * for MLC parts which may have permanently stuck bits.
343 struct nand_chip
*chip
= mtd
->priv
;
344 int ret
= chip
->ecc
.read_page(mtd
, chip
, readbackbuf
, 0, 0);
348 if (memcmp(readbackbuf
, buf
, len
) == 0)
356 static int __devinit
bcm_umi_nand_probe(struct platform_device
*pdev
)
358 struct nand_chip
*this;
364 /* Allocate memory for MTD device structure and private data */
366 kmalloc(sizeof(struct mtd_info
) + sizeof(struct nand_chip
),
370 "Unable to allocate NAND MTD device structure.\n");
374 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
381 /* map physical address */
382 bcm_umi_io_base
= ioremap(r
->start
, resource_size(r
));
384 if (!bcm_umi_io_base
) {
385 printk(KERN_ERR
"ioremap to access BCM UMI NAND chip failed\n");
390 /* Get pointer to private data */
391 this = (struct nand_chip
*)(&board_mtd
[1]);
393 /* Initialize structures */
394 memset((char *)board_mtd
, 0, sizeof(struct mtd_info
));
395 memset((char *)this, 0, sizeof(struct nand_chip
));
397 /* Link the private data with the MTD structure */
398 board_mtd
->priv
= this;
400 /* Initialize the NAND hardware. */
401 if (bcm_umi_nand_inithw() < 0) {
402 printk(KERN_ERR
"BCM UMI NAND chip could not be initialized\n");
407 /* Set address of NAND IO lines */
408 this->IO_ADDR_W
= bcm_umi_io_base
+ REG_NAND_DATA8_OFFSET
;
409 this->IO_ADDR_R
= bcm_umi_io_base
+ REG_NAND_DATA8_OFFSET
;
411 /* Set command delay time, see datasheet for correct value */
412 this->chip_delay
= 0;
413 /* Assign the device ready function, if available */
414 this->dev_ready
= nand_dev_ready
;
417 this->write_buf
= bcm_umi_nand_write_buf
;
418 this->read_buf
= bcm_umi_nand_read_buf
;
419 this->verify_buf
= bcm_umi_nand_verify_buf
;
421 this->cmd_ctrl
= bcm_umi_nand_hwcontrol
;
422 this->ecc
.mode
= NAND_ECC_HW
;
423 this->ecc
.size
= 512;
424 this->ecc
.bytes
= NAND_ECC_NUM_BYTES
;
426 this->ecc
.read_page
= bcm_umi_bch_read_page_hwecc
;
427 this->ecc
.write_page
= bcm_umi_bch_write_page_hwecc
;
429 this->ecc
.correct
= nand_correct_data512
;
430 this->ecc
.calculate
= bcm_umi_hamming_get_hw_ecc
;
431 this->ecc
.hwctl
= bcm_umi_hamming_enable_hwecc
;
435 err
= nand_dma_init();
440 /* Figure out the size of the device that we have.
441 * We need to do this to figure out which ECC
442 * layout we'll be using.
445 err
= nand_scan_ident(board_mtd
, 1, NULL
);
447 printk(KERN_ERR
"nand_scan failed: %d\n", err
);
451 /* Now that we know the nand size, we can setup the ECC layout */
453 switch (board_mtd
->writesize
) { /* writesize is the pagesize */
455 this->ecc
.layout
= &nand_hw_eccoob_4096
;
458 this->ecc
.layout
= &nand_hw_eccoob_2048
;
461 this->ecc
.layout
= &nand_hw_eccoob_512
;
465 printk(KERN_ERR
"NAND - Unrecognized pagesize: %d\n",
466 board_mtd
->writesize
);
473 if (board_mtd
->writesize
> 512) {
474 if (this->bbt_options
& NAND_BBT_USE_FLASH
)
475 largepage_bbt
.options
= NAND_BBT_SCAN2NDPAGE
;
476 this->badblock_pattern
= &largepage_bbt
;
479 this->ecc
.strength
= 8;
483 /* Now finish off the scan, now that ecc.layout has been initialized. */
485 err
= nand_scan_tail(board_mtd
);
487 printk(KERN_ERR
"nand_scan failed: %d\n", err
);
491 /* Register the partitions */
492 board_mtd
->name
= "bcm_umi-nand";
493 mtd_device_parse_register(board_mtd
, NULL
, NULL
, NULL
, 0);
498 iounmap(bcm_umi_io_base
);
504 static int bcm_umi_nand_remove(struct platform_device
*pdev
)
510 /* Release resources, unregister device */
511 nand_release(board_mtd
);
513 /* unmap physical address */
514 iounmap(bcm_umi_io_base
);
516 /* Free the MTD device structure */
523 static int bcm_umi_nand_suspend(struct platform_device
*pdev
,
526 printk(KERN_ERR
"MTD NAND suspend is being called\n");
530 static int bcm_umi_nand_resume(struct platform_device
*pdev
)
532 printk(KERN_ERR
"MTD NAND resume is being called\n");
536 #define bcm_umi_nand_suspend NULL
537 #define bcm_umi_nand_resume NULL
540 static struct platform_driver nand_driver
= {
543 .owner
= THIS_MODULE
,
545 .probe
= bcm_umi_nand_probe
,
546 .remove
= bcm_umi_nand_remove
,
547 .suspend
= bcm_umi_nand_suspend
,
548 .resume
= bcm_umi_nand_resume
,
551 module_platform_driver(nand_driver
);
553 MODULE_LICENSE("GPL");
554 MODULE_AUTHOR("Broadcom");
555 MODULE_DESCRIPTION("BCM UMI MTD NAND driver");