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initial commit with v3.6.7
[linux-3.6.7-moxart.git] / drivers / net / ethernet / qlogic / netxen / netxen_nic.h
blobeb3dfdbb642b18bb7ba34da39fd7de7411cb616b
1 /*
2 * Copyright (C) 2003 - 2009 NetXen, Inc.
3 * Copyright (C) 2009 - QLogic Corporation.
4 * All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
19 * MA 02111-1307, USA.
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called "COPYING".
23 *
24 */
25
26 #ifndef _NETXEN_NIC_H_
27 #define _NETXEN_NIC_H_
28
29 #include <linux/module.h>
30 #include <linux/kernel.h>
31 #include <linux/types.h>
32 #include <linux/ioport.h>
33 #include <linux/pci.h>
34 #include <linux/netdevice.h>
35 #include <linux/etherdevice.h>
36 #include <linux/ip.h>
37 #include <linux/in.h>
38 #include <linux/tcp.h>
39 #include <linux/skbuff.h>
40 #include <linux/firmware.h>
41
42 #include <linux/ethtool.h>
43 #include <linux/mii.h>
44 #include <linux/timer.h>
45
46 #include <linux/vmalloc.h>
47
48 #include <asm/io.h>
49 #include <asm/byteorder.h>
50
51 #include "netxen_nic_hdr.h"
52 #include "netxen_nic_hw.h"
53
54 #define _NETXEN_NIC_LINUX_MAJOR 4
55 #define _NETXEN_NIC_LINUX_MINOR 0
56 #define _NETXEN_NIC_LINUX_SUBVERSION 80
57 #define NETXEN_NIC_LINUX_VERSIONID "4.0.80"
58
59 #define NETXEN_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c))
60 #define _major(v) (((v) >> 24) & 0xff)
61 #define _minor(v) (((v) >> 16) & 0xff)
62 #define _build(v) ((v) & 0xffff)
63
64 /* version in image has weird encoding:
65 * 7:0 - major
66 * 15:8 - minor
67 * 31:16 - build (little endian)
68 */
69 #define NETXEN_DECODE_VERSION(v) \
70 NETXEN_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16))
71
72 #define NETXEN_NUM_FLASH_SECTORS (64)
73 #define NETXEN_FLASH_SECTOR_SIZE (64 * 1024)
74 #define NETXEN_FLASH_TOTAL_SIZE (NETXEN_NUM_FLASH_SECTORS \
75 * NETXEN_FLASH_SECTOR_SIZE)
76
77 #define RCV_DESC_RINGSIZE(rds_ring) \
78 (sizeof(struct rcv_desc) * (rds_ring)->num_desc)
79 #define RCV_BUFF_RINGSIZE(rds_ring) \
80 (sizeof(struct netxen_rx_buffer) * rds_ring->num_desc)
81 #define STATUS_DESC_RINGSIZE(sds_ring) \
82 (sizeof(struct status_desc) * (sds_ring)->num_desc)
83 #define TX_BUFF_RINGSIZE(tx_ring) \
84 (sizeof(struct netxen_cmd_buffer) * tx_ring->num_desc)
85 #define TX_DESC_RINGSIZE(tx_ring) \
86 (sizeof(struct cmd_desc_type0) * tx_ring->num_desc)
87
88 #define find_diff_among(a,b,range) ((a)<(b)?((b)-(a)):((b)+(range)-(a)))
89
90 #define NETXEN_RCV_PRODUCER_OFFSET 0
91 #define NETXEN_RCV_PEG_DB_ID 2
92 #define NETXEN_HOST_DUMMY_DMA_SIZE 1024
93 #define FLASH_SUCCESS 0
94
95 #define ADDR_IN_WINDOW1(off) \
96 ((off > NETXEN_CRB_PCIX_HOST2) && (off < NETXEN_CRB_MAX)) ? 1 : 0
97
98 #define ADDR_IN_RANGE(addr, low, high) \
99 (((addr) < (high)) && ((addr) >= (low)))
100
101 /*
102 * normalize a 64MB crb address to 32MB PCI window
103 * To use NETXEN_CRB_NORMALIZE, window _must_ be set to 1
104 */
105 #define NETXEN_CRB_NORMAL(reg) \
106 ((reg) - NETXEN_CRB_PCIX_HOST2 + NETXEN_CRB_PCIX_HOST)
107
108 #define NETXEN_CRB_NORMALIZE(adapter, reg) \
109 pci_base_offset(adapter, NETXEN_CRB_NORMAL(reg))
110
111 #define DB_NORMALIZE(adapter, off) \
112 (adapter->ahw.db_base + (off))
113
114 #define NX_P2_C0 0x24
115 #define NX_P2_C1 0x25
116 #define NX_P3_A0 0x30
117 #define NX_P3_A2 0x30
118 #define NX_P3_B0 0x40
119 #define NX_P3_B1 0x41
120 #define NX_P3_B2 0x42
121 #define NX_P3P_A0 0x50
122
123 #define NX_IS_REVISION_P2(REVISION) (REVISION <= NX_P2_C1)
124 #define NX_IS_REVISION_P3(REVISION) (REVISION >= NX_P3_A0)
125 #define NX_IS_REVISION_P3P(REVISION) (REVISION >= NX_P3P_A0)
126
127 #define FIRST_PAGE_GROUP_START 0
128 #define FIRST_PAGE_GROUP_END 0x100000
129
130 #define SECOND_PAGE_GROUP_START 0x6000000
131 #define SECOND_PAGE_GROUP_END 0x68BC000
132
133 #define THIRD_PAGE_GROUP_START 0x70E4000
134 #define THIRD_PAGE_GROUP_END 0x8000000
135
136 #define FIRST_PAGE_GROUP_SIZE FIRST_PAGE_GROUP_END - FIRST_PAGE_GROUP_START
137 #define SECOND_PAGE_GROUP_SIZE SECOND_PAGE_GROUP_END - SECOND_PAGE_GROUP_START
138 #define THIRD_PAGE_GROUP_SIZE THIRD_PAGE_GROUP_END - THIRD_PAGE_GROUP_START
139
140 #define P2_MAX_MTU (8000)
141 #define P3_MAX_MTU (9600)
142 #define NX_ETHERMTU 1500
143 #define NX_MAX_ETHERHDR 32 /* This contains some padding */
144
145 #define NX_P2_RX_BUF_MAX_LEN 1760
146 #define NX_P3_RX_BUF_MAX_LEN (NX_MAX_ETHERHDR + NX_ETHERMTU)
147 #define NX_P2_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P2_MAX_MTU)
148 #define NX_P3_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P3_MAX_MTU)
149 #define NX_CT_DEFAULT_RX_BUF_LEN 2048
150 #define NX_LRO_BUFFER_EXTRA 2048
151
152 #define NX_RX_LRO_BUFFER_LENGTH (8060)
153
154 /*
155 * Maximum number of ring contexts
156 */
157 #define MAX_RING_CTX 1
158
159 /* Opcodes to be used with the commands */
160 #define TX_ETHER_PKT 0x01
161 #define TX_TCP_PKT 0x02
162 #define TX_UDP_PKT 0x03
163 #define TX_IP_PKT 0x04
164 #define TX_TCP_LSO 0x05
165 #define TX_TCP_LSO6 0x06
166 #define TX_IPSEC 0x07
167 #define TX_IPSEC_CMD 0x0a
168 #define TX_TCPV6_PKT 0x0b
169 #define TX_UDPV6_PKT 0x0c
170
171 /* The following opcodes are for internal consumption. */
172 #define NETXEN_CONTROL_OP 0x10
173 #define PEGNET_REQUEST 0x11
174
175 #define MAX_NUM_CARDS 4
176
177 #define NETXEN_MAX_FRAGS_PER_TX 14
178 #define MAX_TSO_HEADER_DESC 2
179 #define MGMT_CMD_DESC_RESV 4
180 #define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + MAX_TSO_HEADER_DESC \
181 + MGMT_CMD_DESC_RESV)
182 #define NX_MAX_TX_TIMEOUTS 2
183
184 /*
185 * Following are the states of the Phantom. Phantom will set them and
186 * Host will read to check if the fields are correct.
187 */
188 #define PHAN_INITIALIZE_START 0xff00
189 #define PHAN_INITIALIZE_FAILED 0xffff
190 #define PHAN_INITIALIZE_COMPLETE 0xff01
191
192 /* Host writes the following to notify that it has done the init-handshake */
193 #define PHAN_INITIALIZE_ACK 0xf00f
194
195 #define NUM_RCV_DESC_RINGS 3
196 #define NUM_STS_DESC_RINGS 4
197
198 #define RCV_RING_NORMAL 0
199 #define RCV_RING_JUMBO 1
200 #define RCV_RING_LRO 2
201
202 #define MIN_CMD_DESCRIPTORS 64
203 #define MIN_RCV_DESCRIPTORS 64
204 #define MIN_JUMBO_DESCRIPTORS 32
205
206 #define MAX_CMD_DESCRIPTORS 1024
207 #define MAX_RCV_DESCRIPTORS_1G 4096
208 #define MAX_RCV_DESCRIPTORS_10G 8192
209 #define MAX_JUMBO_RCV_DESCRIPTORS_1G 512
210 #define MAX_JUMBO_RCV_DESCRIPTORS_10G 1024
211 #define MAX_LRO_RCV_DESCRIPTORS 8
212
213 #define DEFAULT_RCV_DESCRIPTORS_1G 2048
214 #define DEFAULT_RCV_DESCRIPTORS_10G 4096
215
216 #define NETXEN_CTX_SIGNATURE 0xdee0
217 #define NETXEN_CTX_SIGNATURE_V2 0x0002dee0
218 #define NETXEN_CTX_RESET 0xbad0
219 #define NETXEN_CTX_D3_RESET 0xacc0
220 #define NETXEN_RCV_PRODUCER(ringid) (ringid)
221
222 #define PHAN_PEG_RCV_INITIALIZED 0xff01
223 #define PHAN_PEG_RCV_START_INITIALIZE 0xff00
224
225 #define get_next_index(index, length) \
226 (((index) + 1) & ((length) - 1))
227
228 #define get_index_range(index,length,count) \
229 (((index) + (count)) & ((length) - 1))
230
231 #define MPORT_SINGLE_FUNCTION_MODE 0x1111
232 #define MPORT_MULTI_FUNCTION_MODE 0x2222
233
234 #define NX_MAX_PCI_FUNC 8
235
236 /*
237 * NetXen host-peg signal message structure
238 *
239 * Bit 0-1 : peg_id => 0x2 for tx and 01 for rx
240 * Bit 2 : priv_id => must be 1
241 * Bit 3-17 : count => for doorbell
242 * Bit 18-27 : ctx_id => Context id
243 * Bit 28-31 : opcode
244 */
245
246 typedef u32 netxen_ctx_msg;
247
248 #define netxen_set_msg_peg_id(config_word, val) \
249 ((config_word) &= ~3, (config_word) |= val & 3)
250 #define netxen_set_msg_privid(config_word) \
251 ((config_word) |= 1 << 2)
252 #define netxen_set_msg_count(config_word, val) \
253 ((config_word) &= ~(0x7fff<<3), (config_word) |= (val & 0x7fff) << 3)
254 #define netxen_set_msg_ctxid(config_word, val) \
255 ((config_word) &= ~(0x3ff<<18), (config_word) |= (val & 0x3ff) << 18)
256 #define netxen_set_msg_opcode(config_word, val) \
257 ((config_word) &= ~(0xf<<28), (config_word) |= (val & 0xf) << 28)
258
259 struct netxen_rcv_ring {
260 __le64 addr;
261 __le32 size;
262 __le32 rsrvd;
263 };
264
265 struct netxen_sts_ring {
266 __le64 addr;
267 __le32 size;
268 __le16 msi_index;
269 __le16 rsvd;
270 } ;
271
272 struct netxen_ring_ctx {
273
274 /* one command ring */
275 __le64 cmd_consumer_offset;
276 __le64 cmd_ring_addr;
277 __le32 cmd_ring_size;
278 __le32 rsrvd;
279
280 /* three receive rings */
281 struct netxen_rcv_ring rcv_rings[NUM_RCV_DESC_RINGS];
282
283 __le64 sts_ring_addr;
284 __le32 sts_ring_size;
285
286 __le32 ctx_id;
287
288 __le64 rsrvd_2[3];
289 __le32 sts_ring_count;
290 __le32 rsrvd_3;
291 struct netxen_sts_ring sts_rings[NUM_STS_DESC_RINGS];
292
293 } __attribute__ ((aligned(64)));
294
295 /*
296 * Following data structures describe the descriptors that will be used.
297 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
298 * we are doing LSO (above the 1500 size packet) only.
299 */
300
301 /*
302 * The size of reference handle been changed to 16 bits to pass the MSS fields
303 * for the LSO packet
304 */
305
306 #define FLAGS_CHECKSUM_ENABLED 0x01
307 #define FLAGS_LSO_ENABLED 0x02
308 #define FLAGS_IPSEC_SA_ADD 0x04
309 #define FLAGS_IPSEC_SA_DELETE 0x08
310 #define FLAGS_VLAN_TAGGED 0x10
311 #define FLAGS_VLAN_OOB 0x40
312
313 #define netxen_set_tx_vlan_tci(cmd_desc, v) \
314 (cmd_desc)->vlan_TCI = cpu_to_le16(v);
315
316 #define netxen_set_cmd_desc_port(cmd_desc, var) \
317 ((cmd_desc)->port_ctxid |= ((var) & 0x0F))
318 #define netxen_set_cmd_desc_ctxid(cmd_desc, var) \
319 ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0))
320
321 #define netxen_set_tx_port(_desc, _port) \
322 (_desc)->port_ctxid = ((_port) & 0xf) | (((_port) << 4) & 0xf0)
323
324 #define netxen_set_tx_flags_opcode(_desc, _flags, _opcode) \
325 (_desc)->flags_opcode = \
326 cpu_to_le16(((_flags) & 0x7f) | (((_opcode) & 0x3f) << 7))
327
328 #define netxen_set_tx_frags_len(_desc, _frags, _len) \
329 (_desc)->nfrags__length = \
330 cpu_to_le32(((_frags) & 0xff) | (((_len) & 0xffffff) << 8))
331
332 struct cmd_desc_type0 {
333 u8 tcp_hdr_offset; /* For LSO only */
334 u8 ip_hdr_offset; /* For LSO only */
335 __le16 flags_opcode; /* 15:13 unused, 12:7 opcode, 6:0 flags */
336 __le32 nfrags__length; /* 31:8 total len, 7:0 frag count */
337
338 __le64 addr_buffer2;
339
340 __le16 reference_handle;
341 __le16 mss;
342 u8 port_ctxid; /* 7:4 ctxid 3:0 port */
343 u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */
344 __le16 conn_id; /* IPSec offoad only */
345
346 __le64 addr_buffer3;
347 __le64 addr_buffer1;
348
349 __le16 buffer_length[4];
350
351 __le64 addr_buffer4;
352
353 __le32 reserved2;
354 __le16 reserved;
355 __le16 vlan_TCI;
356
357 } __attribute__ ((aligned(64)));
358
359 /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
360 struct rcv_desc {
361 __le16 reference_handle;
362 __le16 reserved;
363 __le32 buffer_length; /* allocated buffer length (usually 2K) */
364 __le64 addr_buffer;
365 };
366
367 /* opcode field in status_desc */
368 #define NETXEN_NIC_SYN_OFFLOAD 0x03
369 #define NETXEN_NIC_RXPKT_DESC 0x04
370 #define NETXEN_OLD_RXPKT_DESC 0x3f
371 #define NETXEN_NIC_RESPONSE_DESC 0x05
372 #define NETXEN_NIC_LRO_DESC 0x12
373
374 /* for status field in status_desc */
375 #define STATUS_NEED_CKSUM (1)
376 #define STATUS_CKSUM_OK (2)
377
378 /* owner bits of status_desc */
379 #define STATUS_OWNER_HOST (0x1ULL << 56)
380 #define STATUS_OWNER_PHANTOM (0x2ULL << 56)
381
382 /* Status descriptor:
383 0-3 port, 4-7 status, 8-11 type, 12-27 total_length
384 28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset
385 53-55 desc_cnt, 56-57 owner, 58-63 opcode
386 */
387 #define netxen_get_sts_port(sts_data) \
388 ((sts_data) & 0x0F)
389 #define netxen_get_sts_status(sts_data) \
390 (((sts_data) >> 4) & 0x0F)
391 #define netxen_get_sts_type(sts_data) \
392 (((sts_data) >> 8) & 0x0F)
393 #define netxen_get_sts_totallength(sts_data) \
394 (((sts_data) >> 12) & 0xFFFF)
395 #define netxen_get_sts_refhandle(sts_data) \
396 (((sts_data) >> 28) & 0xFFFF)
397 #define netxen_get_sts_prot(sts_data) \
398 (((sts_data) >> 44) & 0x0F)
399 #define netxen_get_sts_pkt_offset(sts_data) \
400 (((sts_data) >> 48) & 0x1F)
401 #define netxen_get_sts_desc_cnt(sts_data) \
402 (((sts_data) >> 53) & 0x7)
403 #define netxen_get_sts_opcode(sts_data) \
404 (((sts_data) >> 58) & 0x03F)
405
406 #define netxen_get_lro_sts_refhandle(sts_data) \
407 ((sts_data) & 0x0FFFF)
408 #define netxen_get_lro_sts_length(sts_data) \
409 (((sts_data) >> 16) & 0x0FFFF)
410 #define netxen_get_lro_sts_l2_hdr_offset(sts_data) \
411 (((sts_data) >> 32) & 0x0FF)
412 #define netxen_get_lro_sts_l4_hdr_offset(sts_data) \
413 (((sts_data) >> 40) & 0x0FF)
414 #define netxen_get_lro_sts_timestamp(sts_data) \
415 (((sts_data) >> 48) & 0x1)
416 #define netxen_get_lro_sts_type(sts_data) \
417 (((sts_data) >> 49) & 0x7)
418 #define netxen_get_lro_sts_push_flag(sts_data) \
419 (((sts_data) >> 52) & 0x1)
420 #define netxen_get_lro_sts_seq_number(sts_data) \
421 ((sts_data) & 0x0FFFFFFFF)
422 #define netxen_get_lro_sts_mss(sts_data1) \
423 ((sts_data1 >> 32) & 0x0FFFF)
424
425
426 struct status_desc {
427 __le64 status_desc_data[2];
428 } __attribute__ ((aligned(16)));
429
430 /* UNIFIED ROMIMAGE *************************/
431 #define NX_UNI_DIR_SECT_PRODUCT_TBL 0x0
432 #define NX_UNI_DIR_SECT_BOOTLD 0x6
433 #define NX_UNI_DIR_SECT_FW 0x7
434
435 /*Offsets */
436 #define NX_UNI_CHIP_REV_OFF 10
437 #define NX_UNI_FLAGS_OFF 11
438 #define NX_UNI_BIOS_VERSION_OFF 12
439 #define NX_UNI_BOOTLD_IDX_OFF 27
440 #define NX_UNI_FIRMWARE_IDX_OFF 29
441
442 struct uni_table_desc{
443 uint32_t findex;
444 uint32_t num_entries;
445 uint32_t entry_size;
446 uint32_t reserved[5];
447 };
448
449 struct uni_data_desc{
450 uint32_t findex;
451 uint32_t size;
452 uint32_t reserved[5];
453 };
454
455 /* UNIFIED ROMIMAGE *************************/
456
457 /* The version of the main data structure */
458 #define NETXEN_BDINFO_VERSION 1
459
460 /* Magic number to let user know flash is programmed */
461 #define NETXEN_BDINFO_MAGIC 0x12345678
462
463 /* Max number of Gig ports on a Phantom board */
464 #define NETXEN_MAX_PORTS 4
465
466 #define NETXEN_BRDTYPE_P1_BD 0x0000
467 #define NETXEN_BRDTYPE_P1_SB 0x0001
468 #define NETXEN_BRDTYPE_P1_SMAX 0x0002
469 #define NETXEN_BRDTYPE_P1_SOCK 0x0003
470
471 #define NETXEN_BRDTYPE_P2_SOCK_31 0x0008
472 #define NETXEN_BRDTYPE_P2_SOCK_35 0x0009
473 #define NETXEN_BRDTYPE_P2_SB35_4G 0x000a
474 #define NETXEN_BRDTYPE_P2_SB31_10G 0x000b
475 #define NETXEN_BRDTYPE_P2_SB31_2G 0x000c
476
477 #define NETXEN_BRDTYPE_P2_SB31_10G_IMEZ 0x000d
478 #define NETXEN_BRDTYPE_P2_SB31_10G_HMEZ 0x000e
479 #define NETXEN_BRDTYPE_P2_SB31_10G_CX4 0x000f
480
481 #define NETXEN_BRDTYPE_P3_REF_QG 0x0021
482 #define NETXEN_BRDTYPE_P3_HMEZ 0x0022
483 #define NETXEN_BRDTYPE_P3_10G_CX4_LP 0x0023
484 #define NETXEN_BRDTYPE_P3_4_GB 0x0024
485 #define NETXEN_BRDTYPE_P3_IMEZ 0x0025
486 #define NETXEN_BRDTYPE_P3_10G_SFP_PLUS 0x0026
487 #define NETXEN_BRDTYPE_P3_10000_BASE_T 0x0027
488 #define NETXEN_BRDTYPE_P3_XG_LOM 0x0028
489 #define NETXEN_BRDTYPE_P3_4_GB_MM 0x0029
490 #define NETXEN_BRDTYPE_P3_10G_SFP_CT 0x002a
491 #define NETXEN_BRDTYPE_P3_10G_SFP_QT 0x002b
492 #define NETXEN_BRDTYPE_P3_10G_CX4 0x0031
493 #define NETXEN_BRDTYPE_P3_10G_XFP 0x0032
494 #define NETXEN_BRDTYPE_P3_10G_TP 0x0080
495
496 /* Flash memory map */
497 #define NETXEN_CRBINIT_START 0 /* crbinit section */
498 #define NETXEN_BRDCFG_START 0x4000 /* board config */
499 #define NETXEN_INITCODE_START 0x6000 /* pegtune code */
500 #define NETXEN_BOOTLD_START 0x10000 /* bootld */
501 #define NETXEN_IMAGE_START 0x43000 /* compressed image */
502 #define NETXEN_SECONDARY_START 0x200000 /* backup images */
503 #define NETXEN_PXE_START 0x3E0000 /* PXE boot rom */
504 #define NETXEN_USER_START 0x3E8000 /* Firmare info */
505 #define NETXEN_FIXED_START 0x3F0000 /* backup of crbinit */
506 #define NETXEN_USER_START_OLD NETXEN_PXE_START /* very old flash */
507
508 #define NX_OLD_MAC_ADDR_OFFSET (NETXEN_USER_START)
509 #define NX_FW_VERSION_OFFSET (NETXEN_USER_START+0x408)
510 #define NX_FW_SIZE_OFFSET (NETXEN_USER_START+0x40c)
511 #define NX_FW_MAC_ADDR_OFFSET (NETXEN_USER_START+0x418)
512 #define NX_FW_SERIAL_NUM_OFFSET (NETXEN_USER_START+0x81c)
513 #define NX_BIOS_VERSION_OFFSET (NETXEN_USER_START+0x83c)
514
515 #define NX_HDR_VERSION_OFFSET (NETXEN_BRDCFG_START)
516 #define NX_BRDTYPE_OFFSET (NETXEN_BRDCFG_START+0x8)
517 #define NX_FW_MAGIC_OFFSET (NETXEN_BRDCFG_START+0x128)
518
519 #define NX_FW_MIN_SIZE (0x3fffff)
520 #define NX_P2_MN_ROMIMAGE 0
521 #define NX_P3_CT_ROMIMAGE 1
522 #define NX_P3_MN_ROMIMAGE 2
523 #define NX_UNIFIED_ROMIMAGE 3
524 #define NX_FLASH_ROMIMAGE 4
525 #define NX_UNKNOWN_ROMIMAGE 0xff
526
527 #define NX_P2_MN_ROMIMAGE_NAME "nxromimg.bin"
528 #define NX_P3_CT_ROMIMAGE_NAME "nx3fwct.bin"
529 #define NX_P3_MN_ROMIMAGE_NAME "nx3fwmn.bin"
530 #define NX_UNIFIED_ROMIMAGE_NAME "phanfw.bin"
531 #define NX_FLASH_ROMIMAGE_NAME "flash"
532
533 extern char netxen_nic_driver_name[];
534
535 /* Number of status descriptors to handle per interrupt */
536 #define MAX_STATUS_HANDLE (64)
537
538 /*
539 * netxen_skb_frag{} is to contain mapping info for each SG list. This
540 * has to be freed when DMA is complete. This is part of netxen_tx_buffer{}.
541 */
542 struct netxen_skb_frag {
543 u64 dma;
544 u64 length;
545 };
546
547 struct netxen_recv_crb {
548 u32 crb_rcv_producer[NUM_RCV_DESC_RINGS];
549 u32 crb_sts_consumer[NUM_STS_DESC_RINGS];
550 u32 sw_int_mask[NUM_STS_DESC_RINGS];
551 };
552
553 /* Following defines are for the state of the buffers */
554 #define NETXEN_BUFFER_FREE 0
555 #define NETXEN_BUFFER_BUSY 1
556
557 /*
558 * There will be one netxen_buffer per skb packet. These will be
559 * used to save the dma info for pci_unmap_page()
560 */
561 struct netxen_cmd_buffer {
562 struct sk_buff *skb;
563 struct netxen_skb_frag frag_array[MAX_SKB_FRAGS + 1];
564 u32 frag_count;
565 };
566
567 /* In rx_buffer, we do not need multiple fragments as is a single buffer */
568 struct netxen_rx_buffer {
569 struct list_head list;
570 struct sk_buff *skb;
571 u64 dma;
572 u16 ref_handle;
573 u16 state;
574 };
575
576 /* Board types */
577 #define NETXEN_NIC_GBE 0x01
578 #define NETXEN_NIC_XGBE 0x02
579
580 /*
581 * One hardware_context{} per adapter
582 * contains interrupt info as well shared hardware info.
583 */
584 struct netxen_hardware_context {
585 void __iomem *pci_base0;
586 void __iomem *pci_base1;
587 void __iomem *pci_base2;
588 void __iomem *db_base;
589 void __iomem *ocm_win_crb;
590
591 unsigned long db_len;
592 unsigned long pci_len0;
593
594 u32 ocm_win;
595 u32 crb_win;
596
597 rwlock_t crb_lock;
598 spinlock_t mem_lock;
599
600 u8 cut_through;
601 u8 revision_id;
602 u8 pci_func;
603 u8 linkup;
604 u16 port_type;
605 u16 board_type;
606 };
607
608 #define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */
609 #define ETHERNET_FCS_SIZE 4
610
611 struct netxen_adapter_stats {
612 u64 xmitcalled;
613 u64 xmitfinished;
614 u64 rxdropped;
615 u64 txdropped;
616 u64 csummed;
617 u64 rx_pkts;
618 u64 lro_pkts;
619 u64 rxbytes;
620 u64 txbytes;
621 };
622
623 /*
624 * Rcv Descriptor Context. One such per Rcv Descriptor. There may
625 * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
626 */
627 struct nx_host_rds_ring {
628 u32 producer;
629 u32 num_desc;
630 u32 dma_size;
631 u32 skb_size;
632 u32 flags;
633 void __iomem *crb_rcv_producer;
634 struct rcv_desc *desc_head;
635 struct netxen_rx_buffer *rx_buf_arr;
636 struct list_head free_list;
637 spinlock_t lock;
638 dma_addr_t phys_addr;
639 };
640
641 struct nx_host_sds_ring {
642 u32 consumer;
643 u32 num_desc;
644 void __iomem *crb_sts_consumer;
645 void __iomem *crb_intr_mask;
646
647 struct status_desc *desc_head;
648 struct netxen_adapter *adapter;
649 struct napi_struct napi;
650 struct list_head free_list[NUM_RCV_DESC_RINGS];
651
652 int irq;
653
654 dma_addr_t phys_addr;
655 char name[IFNAMSIZ+4];
656 };
657
658 struct nx_host_tx_ring {
659 u32 producer;
660 __le32 *hw_consumer;
661 u32 sw_consumer;
662 void __iomem *crb_cmd_producer;
663 void __iomem *crb_cmd_consumer;
664 u32 num_desc;
665
666 struct netdev_queue *txq;
667
668 struct netxen_cmd_buffer *cmd_buf_arr;
669 struct cmd_desc_type0 *desc_head;
670 dma_addr_t phys_addr;
671 };
672
673 /*
674 * Receive context. There is one such structure per instance of the
675 * receive processing. Any state information that is relevant to
676 * the receive, and is must be in this structure. The global data may be
677 * present elsewhere.
678 */
679 struct netxen_recv_context {
680 u32 state;
681 u16 context_id;
682 u16 virt_port;
683
684 struct nx_host_rds_ring *rds_rings;
685 struct nx_host_sds_ring *sds_rings;
686
687 struct netxen_ring_ctx *hwctx;
688 dma_addr_t phys_addr;
689 };
690
691 struct _cdrp_cmd {
692 u32 cmd;
693 u32 arg1;
694 u32 arg2;
695 u32 arg3;
696 };
697
698 struct netxen_cmd_args {
699 struct _cdrp_cmd req;
700 struct _cdrp_cmd rsp;
701 };
702
703 /* New HW context creation */
704
705 #define NX_OS_CRB_RETRY_COUNT 4000
706 #define NX_CDRP_SIGNATURE_MAKE(pcifn, version) \
707 (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16))
708
709 #define NX_CDRP_CLEAR 0x00000000
710 #define NX_CDRP_CMD_BIT 0x80000000
711
712 /*
713 * All responses must have the NX_CDRP_CMD_BIT cleared
714 * in the crb NX_CDRP_CRB_OFFSET.
715 */
716 #define NX_CDRP_FORM_RSP(rsp) (rsp)
717 #define NX_CDRP_IS_RSP(rsp) (((rsp) & NX_CDRP_CMD_BIT) == 0)
718
719 #define NX_CDRP_RSP_OK 0x00000001
720 #define NX_CDRP_RSP_FAIL 0x00000002
721 #define NX_CDRP_RSP_TIMEOUT 0x00000003
722
723 /*
724 * All commands must have the NX_CDRP_CMD_BIT set in
725 * the crb NX_CDRP_CRB_OFFSET.
726 */
727 #define NX_CDRP_FORM_CMD(cmd) (NX_CDRP_CMD_BIT | (cmd))
728 #define NX_CDRP_IS_CMD(cmd) (((cmd) & NX_CDRP_CMD_BIT) != 0)
729
730 #define NX_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001
731 #define NX_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002
732 #define NX_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003
733 #define NX_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004
734 #define NX_CDRP_CMD_READ_MAX_RX_CTX 0x00000005
735 #define NX_CDRP_CMD_READ_MAX_TX_CTX 0x00000006
736 #define NX_CDRP_CMD_CREATE_RX_CTX 0x00000007
737 #define NX_CDRP_CMD_DESTROY_RX_CTX 0x00000008
738 #define NX_CDRP_CMD_CREATE_TX_CTX 0x00000009
739 #define NX_CDRP_CMD_DESTROY_TX_CTX 0x0000000a
740 #define NX_CDRP_CMD_SETUP_STATISTICS 0x0000000e
741 #define NX_CDRP_CMD_GET_STATISTICS 0x0000000f
742 #define NX_CDRP_CMD_DELETE_STATISTICS 0x00000010
743 #define NX_CDRP_CMD_SET_MTU 0x00000012
744 #define NX_CDRP_CMD_READ_PHY 0x00000013
745 #define NX_CDRP_CMD_WRITE_PHY 0x00000014
746 #define NX_CDRP_CMD_READ_HW_REG 0x00000015
747 #define NX_CDRP_CMD_GET_FLOW_CTL 0x00000016
748 #define NX_CDRP_CMD_SET_FLOW_CTL 0x00000017
749 #define NX_CDRP_CMD_READ_MAX_MTU 0x00000018
750 #define NX_CDRP_CMD_READ_MAX_LRO 0x00000019
751 #define NX_CDRP_CMD_CONFIGURE_TOE 0x0000001a
752 #define NX_CDRP_CMD_FUNC_ATTRIB 0x0000001b
753 #define NX_CDRP_CMD_READ_PEXQ_PARAMETERS 0x0000001c
754 #define NX_CDRP_CMD_GET_LIC_CAPABILITIES 0x0000001d
755 #define NX_CDRP_CMD_READ_MAX_LRO_PER_BOARD 0x0000001e
756 #define NX_CDRP_CMD_CONFIG_GBE_PORT 0x0000001f
757 #define NX_CDRP_CMD_MAX 0x00000020
758
759 #define NX_RCODE_SUCCESS 0
760 #define NX_RCODE_NO_HOST_MEM 1
761 #define NX_RCODE_NO_HOST_RESOURCE 2
762 #define NX_RCODE_NO_CARD_CRB 3
763 #define NX_RCODE_NO_CARD_MEM 4
764 #define NX_RCODE_NO_CARD_RESOURCE 5
765 #define NX_RCODE_INVALID_ARGS 6
766 #define NX_RCODE_INVALID_ACTION 7
767 #define NX_RCODE_INVALID_STATE 8
768 #define NX_RCODE_NOT_SUPPORTED 9
769 #define NX_RCODE_NOT_PERMITTED 10
770 #define NX_RCODE_NOT_READY 11
771 #define NX_RCODE_DOES_NOT_EXIST 12
772 #define NX_RCODE_ALREADY_EXISTS 13
773 #define NX_RCODE_BAD_SIGNATURE 14
774 #define NX_RCODE_CMD_NOT_IMPL 15
775 #define NX_RCODE_CMD_INVALID 16
776 #define NX_RCODE_TIMEOUT 17
777 #define NX_RCODE_CMD_FAILED 18
778 #define NX_RCODE_MAX_EXCEEDED 19
779 #define NX_RCODE_MAX 20
780
781 #define NX_DESTROY_CTX_RESET 0
782 #define NX_DESTROY_CTX_D3_RESET 1
783 #define NX_DESTROY_CTX_MAX 2
784
785 /*
786 * Capabilities
787 */
788 #define NX_CAP_BIT(class, bit) (1 << bit)
789 #define NX_CAP0_LEGACY_CONTEXT NX_CAP_BIT(0, 0)
790 #define NX_CAP0_MULTI_CONTEXT NX_CAP_BIT(0, 1)
791 #define NX_CAP0_LEGACY_MN NX_CAP_BIT(0, 2)
792 #define NX_CAP0_LEGACY_MS NX_CAP_BIT(0, 3)
793 #define NX_CAP0_CUT_THROUGH NX_CAP_BIT(0, 4)
794 #define NX_CAP0_LRO NX_CAP_BIT(0, 5)
795 #define NX_CAP0_LSO NX_CAP_BIT(0, 6)
796 #define NX_CAP0_JUMBO_CONTIGUOUS NX_CAP_BIT(0, 7)
797 #define NX_CAP0_LRO_CONTIGUOUS NX_CAP_BIT(0, 8)
798 #define NX_CAP0_HW_LRO NX_CAP_BIT(0, 10)
799 #define NX_CAP0_HW_LRO_MSS NX_CAP_BIT(0, 21)
800
801 /*
802 * Context state
803 */
804 #define NX_HOST_CTX_STATE_FREED 0
805 #define NX_HOST_CTX_STATE_ALLOCATED 1
806 #define NX_HOST_CTX_STATE_ACTIVE 2
807 #define NX_HOST_CTX_STATE_DISABLED 3
808 #define NX_HOST_CTX_STATE_QUIESCED 4
809 #define NX_HOST_CTX_STATE_MAX 5
810
811 /*
812 * Rx context
813 */
814
815 typedef struct {
816 __le64 host_phys_addr; /* Ring base addr */
817 __le32 ring_size; /* Ring entries */
818 __le16 msi_index;
819 __le16 rsvd; /* Padding */
820 } nx_hostrq_sds_ring_t;
821
822 typedef struct {
823 __le64 host_phys_addr; /* Ring base addr */
824 __le64 buff_size; /* Packet buffer size */
825 __le32 ring_size; /* Ring entries */
826 __le32 ring_kind; /* Class of ring */
827 } nx_hostrq_rds_ring_t;
828
829 typedef struct {
830 __le64 host_rsp_dma_addr; /* Response dma'd here */
831 __le32 capabilities[4]; /* Flag bit vector */
832 __le32 host_int_crb_mode; /* Interrupt crb usage */
833 __le32 host_rds_crb_mode; /* RDS crb usage */
834 /* These ring offsets are relative to data[0] below */
835 __le32 rds_ring_offset; /* Offset to RDS config */
836 __le32 sds_ring_offset; /* Offset to SDS config */
837 __le16 num_rds_rings; /* Count of RDS rings */
838 __le16 num_sds_rings; /* Count of SDS rings */
839 __le16 rsvd1; /* Padding */
840 __le16 rsvd2; /* Padding */
841 u8 reserved[128]; /* reserve space for future expansion*/
842 /* MUST BE 64-bit aligned.
843 The following is packed:
844 - N hostrq_rds_rings
845 - N hostrq_sds_rings */
846 char data[0];
847 } nx_hostrq_rx_ctx_t;
848
849 typedef struct {
850 __le32 host_producer_crb; /* Crb to use */
851 __le32 rsvd1; /* Padding */
852 } nx_cardrsp_rds_ring_t;
853
854 typedef struct {
855 __le32 host_consumer_crb; /* Crb to use */
856 __le32 interrupt_crb; /* Crb to use */
857 } nx_cardrsp_sds_ring_t;
858
859 typedef struct {
860 /* These ring offsets are relative to data[0] below */
861 __le32 rds_ring_offset; /* Offset to RDS config */
862 __le32 sds_ring_offset; /* Offset to SDS config */
863 __le32 host_ctx_state; /* Starting State */
864 __le32 num_fn_per_port; /* How many PCI fn share the port */
865 __le16 num_rds_rings; /* Count of RDS rings */
866 __le16 num_sds_rings; /* Count of SDS rings */
867 __le16 context_id; /* Handle for context */
868 u8 phys_port; /* Physical id of port */
869 u8 virt_port; /* Virtual/Logical id of port */
870 u8 reserved[128]; /* save space for future expansion */
871 /* MUST BE 64-bit aligned.
872 The following is packed:
873 - N cardrsp_rds_rings
874 - N cardrs_sds_rings */
875 char data[0];
876 } nx_cardrsp_rx_ctx_t;
877
878 #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \
879 (sizeof(HOSTRQ_RX) + \
880 (rds_rings)*(sizeof(nx_hostrq_rds_ring_t)) + \
881 (sds_rings)*(sizeof(nx_hostrq_sds_ring_t)))
882
883 #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \
884 (sizeof(CARDRSP_RX) + \
885 (rds_rings)*(sizeof(nx_cardrsp_rds_ring_t)) + \
886 (sds_rings)*(sizeof(nx_cardrsp_sds_ring_t)))
887
888 /*
889 * Tx context
890 */
891
892 typedef struct {
893 __le64 host_phys_addr; /* Ring base addr */
894 __le32 ring_size; /* Ring entries */
895 __le32 rsvd; /* Padding */
896 } nx_hostrq_cds_ring_t;
897
898 typedef struct {
899 __le64 host_rsp_dma_addr; /* Response dma'd here */
900 __le64 cmd_cons_dma_addr; /* */
901 __le64 dummy_dma_addr; /* */
902 __le32 capabilities[4]; /* Flag bit vector */
903 __le32 host_int_crb_mode; /* Interrupt crb usage */
904 __le32 rsvd1; /* Padding */
905 __le16 rsvd2; /* Padding */
906 __le16 interrupt_ctl;
907 __le16 msi_index;
908 __le16 rsvd3; /* Padding */
909 nx_hostrq_cds_ring_t cds_ring; /* Desc of cds ring */
910 u8 reserved[128]; /* future expansion */
911 } nx_hostrq_tx_ctx_t;
912
913 typedef struct {
914 __le32 host_producer_crb; /* Crb to use */
915 __le32 interrupt_crb; /* Crb to use */
916 } nx_cardrsp_cds_ring_t;
917
918 typedef struct {
919 __le32 host_ctx_state; /* Starting state */
920 __le16 context_id; /* Handle for context */
921 u8 phys_port; /* Physical id of port */
922 u8 virt_port; /* Virtual/Logical id of port */
923 nx_cardrsp_cds_ring_t cds_ring; /* Card cds settings */
924 u8 reserved[128]; /* future expansion */
925 } nx_cardrsp_tx_ctx_t;
926
927 #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX))
928 #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX))
929
930 /* CRB */
931
932 #define NX_HOST_RDS_CRB_MODE_UNIQUE 0
933 #define NX_HOST_RDS_CRB_MODE_SHARED 1
934 #define NX_HOST_RDS_CRB_MODE_CUSTOM 2
935 #define NX_HOST_RDS_CRB_MODE_MAX 3
936
937 #define NX_HOST_INT_CRB_MODE_UNIQUE 0
938 #define NX_HOST_INT_CRB_MODE_SHARED 1
939 #define NX_HOST_INT_CRB_MODE_NORX 2
940 #define NX_HOST_INT_CRB_MODE_NOTX 3
941 #define NX_HOST_INT_CRB_MODE_NORXTX 4
942
943
944 /* MAC */
945
946 #define MC_COUNT_P2 16
947 #define MC_COUNT_P3 38
948
949 #define NETXEN_MAC_NOOP 0
950 #define NETXEN_MAC_ADD 1
951 #define NETXEN_MAC_DEL 2
952
953 typedef struct nx_mac_list_s {
954 struct list_head list;
955 uint8_t mac_addr[ETH_ALEN+2];
956 } nx_mac_list_t;
957
958 struct nx_vlan_ip_list {
959 struct list_head list;
960 __be32 ip_addr;
961 };
962
963 /*
964 * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is
965 * adjusted based on configured MTU.
966 */
967 #define NETXEN_DEFAULT_INTR_COALESCE_RX_TIME_US 3
968 #define NETXEN_DEFAULT_INTR_COALESCE_RX_PACKETS 256
969 #define NETXEN_DEFAULT_INTR_COALESCE_TX_PACKETS 64
970 #define NETXEN_DEFAULT_INTR_COALESCE_TX_TIME_US 4
971
972 #define NETXEN_NIC_INTR_DEFAULT 0x04
973
974 typedef union {
975 struct {
976 uint16_t rx_packets;
977 uint16_t rx_time_us;
978 uint16_t tx_packets;
979 uint16_t tx_time_us;
980 } data;
981 uint64_t word;
982 } nx_nic_intr_coalesce_data_t;
983
984 typedef struct {
985 uint16_t stats_time_us;
986 uint16_t rate_sample_time;
987 uint16_t flags;
988 uint16_t rsvd_1;
989 uint32_t low_threshold;
990 uint32_t high_threshold;
991 nx_nic_intr_coalesce_data_t normal;
992 nx_nic_intr_coalesce_data_t low;
993 nx_nic_intr_coalesce_data_t high;
994 nx_nic_intr_coalesce_data_t irq;
995 } nx_nic_intr_coalesce_t;
996
997 #define NX_HOST_REQUEST 0x13
998 #define NX_NIC_REQUEST 0x14
999
1000 #define NX_MAC_EVENT 0x1
1001
1002 #define NX_IP_UP 2
1003 #define NX_IP_DOWN 3
1004
1005 /*
1006 * Driver --> Firmware
1007 */
1008 #define NX_NIC_H2C_OPCODE_START 0
1009 #define NX_NIC_H2C_OPCODE_CONFIG_RSS 1
1010 #define NX_NIC_H2C_OPCODE_CONFIG_RSS_TBL 2
1011 #define NX_NIC_H2C_OPCODE_CONFIG_INTR_COALESCE 3
1012 #define NX_NIC_H2C_OPCODE_CONFIG_LED 4
1013 #define NX_NIC_H2C_OPCODE_CONFIG_PROMISCUOUS 5
1014 #define NX_NIC_H2C_OPCODE_CONFIG_L2_MAC 6
1015 #define NX_NIC_H2C_OPCODE_LRO_REQUEST 7
1016 #define NX_NIC_H2C_OPCODE_GET_SNMP_STATS 8
1017 #define NX_NIC_H2C_OPCODE_PROXY_START_REQUEST 9
1018 #define NX_NIC_H2C_OPCODE_PROXY_STOP_REQUEST 10
1019 #define NX_NIC_H2C_OPCODE_PROXY_SET_MTU 11
1020 #define NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE 12
1021 #define NX_NIC_H2C_OPCODE_GET_FINGER_PRINT_REQUEST 13
1022 #define NX_NIC_H2C_OPCODE_INSTALL_LICENSE_REQUEST 14
1023 #define NX_NIC_H2C_OPCODE_GET_LICENSE_CAPABILITY_REQUEST 15
1024 #define NX_NIC_H2C_OPCODE_GET_NET_STATS 16
1025 #define NX_NIC_H2C_OPCODE_PROXY_UPDATE_P2V 17
1026 #define NX_NIC_H2C_OPCODE_CONFIG_IPADDR 18
1027 #define NX_NIC_H2C_OPCODE_CONFIG_LOOPBACK 19
1028 #define NX_NIC_H2C_OPCODE_PROXY_STOP_DONE 20
1029 #define NX_NIC_H2C_OPCODE_GET_LINKEVENT 21
1030 #define NX_NIC_C2C_OPCODE 22
1031 #define NX_NIC_H2C_OPCODE_CONFIG_BRIDGING 23
1032 #define NX_NIC_H2C_OPCODE_CONFIG_HW_LRO 24
1033 #define NX_NIC_H2C_OPCODE_LAST 25
1034
1035 /*
1036 * Firmware --> Driver
1037 */
1038
1039 #define NX_NIC_C2H_OPCODE_START 128
1040 #define NX_NIC_C2H_OPCODE_CONFIG_RSS_RESPONSE 129
1041 #define NX_NIC_C2H_OPCODE_CONFIG_RSS_TBL_RESPONSE 130
1042 #define NX_NIC_C2H_OPCODE_CONFIG_MAC_RESPONSE 131
1043 #define NX_NIC_C2H_OPCODE_CONFIG_PROMISCUOUS_RESPONSE 132
1044 #define NX_NIC_C2H_OPCODE_CONFIG_L2_MAC_RESPONSE 133
1045 #define NX_NIC_C2H_OPCODE_LRO_DELETE_RESPONSE 134
1046 #define NX_NIC_C2H_OPCODE_LRO_ADD_FAILURE_RESPONSE 135
1047 #define NX_NIC_C2H_OPCODE_GET_SNMP_STATS 136
1048 #define NX_NIC_C2H_OPCODE_GET_FINGER_PRINT_REPLY 137
1049 #define NX_NIC_C2H_OPCODE_INSTALL_LICENSE_REPLY 138
1050 #define NX_NIC_C2H_OPCODE_GET_LICENSE_CAPABILITIES_REPLY 139
1051 #define NX_NIC_C2H_OPCODE_GET_NET_STATS_RESPONSE 140
1052 #define NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 141
1053 #define NX_NIC_C2H_OPCODE_LAST 142
1054
1055 #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */
1056 #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */
1057 #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */
1058
1059 #define NX_NIC_LRO_REQUEST_FIRST 0
1060 #define NX_NIC_LRO_REQUEST_ADD_FLOW 1
1061 #define NX_NIC_LRO_REQUEST_DELETE_FLOW 2
1062 #define NX_NIC_LRO_REQUEST_TIMER 3
1063 #define NX_NIC_LRO_REQUEST_CLEANUP 4
1064 #define NX_NIC_LRO_REQUEST_ADD_FLOW_SCHEDULED 5
1065 #define NX_TOE_LRO_REQUEST_ADD_FLOW 6
1066 #define NX_TOE_LRO_REQUEST_ADD_FLOW_RESPONSE 7
1067 #define NX_TOE_LRO_REQUEST_DELETE_FLOW 8
1068 #define NX_TOE_LRO_REQUEST_DELETE_FLOW_RESPONSE 9
1069 #define NX_TOE_LRO_REQUEST_TIMER 10
1070 #define NX_NIC_LRO_REQUEST_LAST 11
1071
1072 #define NX_FW_CAPABILITY_LINK_NOTIFICATION (1 << 5)
1073 #define NX_FW_CAPABILITY_SWITCHING (1 << 6)
1074 #define NX_FW_CAPABILITY_PEXQ (1 << 7)
1075 #define NX_FW_CAPABILITY_BDG (1 << 8)
1076 #define NX_FW_CAPABILITY_FVLANTX (1 << 9)
1077 #define NX_FW_CAPABILITY_HW_LRO (1 << 10)
1078 #define NX_FW_CAPABILITY_GBE_LINK_CFG (1 << 11)
1079 #define NX_FW_CAPABILITY_MORE_CAPS (1 << 31)
1080 #define NX_FW_CAPABILITY_2_LRO_MAX_TCP_SEG (1 << 2)
1081
1082 /* module types */
1083 #define LINKEVENT_MODULE_NOT_PRESENT 1
1084 #define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2
1085 #define LINKEVENT_MODULE_OPTICAL_SRLR 3
1086 #define LINKEVENT_MODULE_OPTICAL_LRM 4
1087 #define LINKEVENT_MODULE_OPTICAL_SFP_1G 5
1088 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6
1089 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7
1090 #define LINKEVENT_MODULE_TWINAX 8
1091
1092 #define LINKSPEED_10GBPS 10000
1093 #define LINKSPEED_1GBPS 1000
1094 #define LINKSPEED_100MBPS 100
1095 #define LINKSPEED_10MBPS 10
1096
1097 #define LINKSPEED_ENCODED_10MBPS 0
1098 #define LINKSPEED_ENCODED_100MBPS 1
1099 #define LINKSPEED_ENCODED_1GBPS 2
1100
1101 #define LINKEVENT_AUTONEG_DISABLED 0
1102 #define LINKEVENT_AUTONEG_ENABLED 1
1103
1104 #define LINKEVENT_HALF_DUPLEX 0
1105 #define LINKEVENT_FULL_DUPLEX 1
1106
1107 #define LINKEVENT_LINKSPEED_MBPS 0
1108 #define LINKEVENT_LINKSPEED_ENCODED 1
1109
1110 #define AUTO_FW_RESET_ENABLED 0xEF10AF12
1111 #define AUTO_FW_RESET_DISABLED 0xDCBAAF12
1112
1113 /* firmware response header:
1114 * 63:58 - message type
1115 * 57:56 - owner
1116 * 55:53 - desc count
1117 * 52:48 - reserved
1118 * 47:40 - completion id
1119 * 39:32 - opcode
1120 * 31:16 - error code
1121 * 15:00 - reserved
1122 */
1123 #define netxen_get_nic_msgtype(msg_hdr) \
1124 ((msg_hdr >> 58) & 0x3F)
1125 #define netxen_get_nic_msg_compid(msg_hdr) \
1126 ((msg_hdr >> 40) & 0xFF)
1127 #define netxen_get_nic_msg_opcode(msg_hdr) \
1128 ((msg_hdr >> 32) & 0xFF)
1129 #define netxen_get_nic_msg_errcode(msg_hdr) \
1130 ((msg_hdr >> 16) & 0xFFFF)
1131
1132 typedef struct {
1133 union {
1134 struct {
1135 u64 hdr;
1136 u64 body[7];
1137 };
1138 u64 words[8];
1139 };
1140 } nx_fw_msg_t;
1141
1142 typedef struct {
1143 __le64 qhdr;
1144 __le64 req_hdr;
1145 __le64 words[6];
1146 } nx_nic_req_t;
1147
1148 typedef struct {
1149 u8 op;
1150 u8 tag;
1151 u8 mac_addr[6];
1152 } nx_mac_req_t;
1153
1154 #define MAX_PENDING_DESC_BLOCK_SIZE 64
1155
1156 #define NETXEN_NIC_MSI_ENABLED 0x02
1157 #define NETXEN_NIC_MSIX_ENABLED 0x04
1158 #define NETXEN_NIC_LRO_ENABLED 0x08
1159 #define NETXEN_NIC_LRO_DISABLED 0x00
1160 #define NETXEN_NIC_BRIDGE_ENABLED 0X10
1161 #define NETXEN_NIC_DIAG_ENABLED 0x20
1162 #define NETXEN_FW_RESET_OWNER 0x40
1163 #define NETXEN_FW_MSS_CAP 0x80
1164 #define NETXEN_IS_MSI_FAMILY(adapter) \
1165 ((adapter)->flags & (NETXEN_NIC_MSI_ENABLED | NETXEN_NIC_MSIX_ENABLED))
1166
1167 #define MSIX_ENTRIES_PER_ADAPTER NUM_STS_DESC_RINGS
1168 #define NETXEN_MSIX_TBL_SPACE 8192
1169 #define NETXEN_PCI_REG_MSIX_TBL 0x44
1170
1171 #define NETXEN_DB_MAPSIZE_BYTES 0x1000
1172
1173 #define NETXEN_NETDEV_WEIGHT 128
1174 #define NETXEN_ADAPTER_UP_MAGIC 777
1175 #define NETXEN_NIC_PEG_TUNE 0
1176
1177 #define __NX_FW_ATTACHED 0
1178 #define __NX_DEV_UP 1
1179 #define __NX_RESETTING 2
1180
1181 /* Mini Coredump FW supported version */
1182 #define NX_MD_SUPPORT_MAJOR 4
1183 #define NX_MD_SUPPORT_MINOR 0
1184 #define NX_MD_SUPPORT_SUBVERSION 579
1185
1186 #define LSW(x) ((uint16_t)(x))
1187 #define LSD(x) ((uint32_t)((uint64_t)(x)))
1188 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
1189
1190 /* Mini Coredump mask level */
1191 #define NX_DUMP_MASK_MIN 0x03
1192 #define NX_DUMP_MASK_DEF 0x1f
1193 #define NX_DUMP_MASK_MAX 0xff
1194
1195 /* Mini Coredump CDRP commands */
1196 #define NX_CDRP_CMD_TEMP_SIZE 0x0000002f
1197 #define NX_CDRP_CMD_GET_TEMP_HDR 0x00000030
1198
1199
1200 #define NX_DUMP_STATE_ARRAY_LEN 16
1201 #define NX_DUMP_CAP_SIZE_ARRAY_LEN 8
1202
1203 /* Mini Coredump sysfs entries flags*/
1204 #define NX_FORCE_FW_DUMP_KEY 0xdeadfeed
1205 #define NX_ENABLE_FW_DUMP 0xaddfeed
1206 #define NX_DISABLE_FW_DUMP 0xbadfeed
1207 #define NX_FORCE_FW_RESET 0xdeaddead
1208
1209
1210 /* Fw dump levels */
1211 static const u32 FW_DUMP_LEVELS[] = { 0x3, 0x7, 0xf, 0x1f, 0x3f, 0x7f, 0xff };
1212
1213 /* Flash read/write address */
1214 #define NX_FW_DUMP_REG1 0x00130060
1215 #define NX_FW_DUMP_REG2 0x001e0000
1216 #define NX_FLASH_SEM2_LK 0x0013C010
1217 #define NX_FLASH_SEM2_ULK 0x0013C014
1218 #define NX_FLASH_LOCK_ID 0x001B2100
1219 #define FLASH_ROM_WINDOW 0x42110030
1220 #define FLASH_ROM_DATA 0x42150000
1221
1222 /* Mini Coredump register read/write routine */
1223 #define NX_RD_DUMP_REG(addr, bar0, data) do { \
1224 writel((addr & 0xFFFF0000), (void __iomem *) (bar0 + \
1225 NX_FW_DUMP_REG1)); \
1226 readl((void __iomem *) (bar0 + NX_FW_DUMP_REG1)); \
1227 *data = readl((void __iomem *) (bar0 + NX_FW_DUMP_REG2 + \
1228 LSW(addr))); \
1229 } while (0)
1230
1231 #define NX_WR_DUMP_REG(addr, bar0, data) do { \
1232 writel((addr & 0xFFFF0000), (void __iomem *) (bar0 + \
1233 NX_FW_DUMP_REG1)); \
1234 readl((void __iomem *) (bar0 + NX_FW_DUMP_REG1)); \
1235 writel(data, (void __iomem *) (bar0 + NX_FW_DUMP_REG2 + LSW(addr)));\
1236 readl((void __iomem *) (bar0 + NX_FW_DUMP_REG2 + LSW(addr))); \
1237 } while (0)
1238
1239
1240 /*
1241 Entry Type Defines
1242 */
1243
1244 #define RDNOP 0
1245 #define RDCRB 1
1246 #define RDMUX 2
1247 #define QUEUE 3
1248 #define BOARD 4
1249 #define RDSRE 5
1250 #define RDOCM 6
1251 #define PREGS 7
1252 #define L1DTG 8
1253 #define L1ITG 9
1254 #define CACHE 10
1255
1256 #define L1DAT 11
1257 #define L1INS 12
1258 #define RDSTK 13
1259 #define RDCON 14
1260
1261 #define L2DTG 21
1262 #define L2ITG 22
1263 #define L2DAT 23
1264 #define L2INS 24
1265 #define RDOC3 25
1266
1267 #define MEMBK 32
1268
1269 #define RDROM 71
1270 #define RDMEM 72
1271 #define RDMN 73
1272
1273 #define INFOR 81
1274 #define CNTRL 98
1275
1276 #define TLHDR 99
1277 #define RDEND 255
1278
1279 #define PRIMQ 103
1280 #define SQG2Q 104
1281 #define SQG3Q 105
1282
1283 /*
1284 * Opcodes for Control Entries.
1285 * These Flags are bit fields.
1286 */
1287 #define NX_DUMP_WCRB 0x01
1288 #define NX_DUMP_RWCRB 0x02
1289 #define NX_DUMP_ANDCRB 0x04
1290 #define NX_DUMP_ORCRB 0x08
1291 #define NX_DUMP_POLLCRB 0x10
1292 #define NX_DUMP_RD_SAVE 0x20
1293 #define NX_DUMP_WRT_SAVED 0x40
1294 #define NX_DUMP_MOD_SAVE_ST 0x80
1295
1296 /* Driver Flags */
1297 #define NX_DUMP_SKIP 0x80 /* driver skipped this entry */
1298 #define NX_DUMP_SIZE_ERR 0x40 /*entry size vs capture size mismatch*/
1299
1300 #define NX_PCI_READ_32(ADDR) readl((ADDR))
1301 #define NX_PCI_WRITE_32(DATA, ADDR) writel(DATA, (ADDR))
1302
1303
1304
1305 struct netxen_minidump {
1306 u32 pos; /* position in the dump buffer */
1307 u8 fw_supports_md; /* FW supports Mini cordump */
1308 u8 has_valid_dump; /* indicates valid dump */
1309 u8 md_capture_mask; /* driver capture mask */
1310 u8 md_enabled; /* Turn Mini Coredump on/off */
1311 u32 md_dump_size; /* Total FW Mini Coredump size */
1312 u32 md_capture_size; /* FW dump capture size */
1313 u32 md_template_size; /* FW template size */
1314 u32 md_template_ver; /* FW template version */
1315 u64 md_timestamp; /* FW Mini dump timestamp */
1316 void *md_template; /* FW template will be stored */
1317 void *md_capture_buff; /* FW dump will be stored */
1318 };
1319
1320
1321
1322 struct netxen_minidump_template_hdr {
1323 u32 entry_type;
1324 u32 first_entry_offset;
1325 u32 size_of_template;
1326 u32 capture_mask;
1327 u32 num_of_entries;
1328 u32 version;
1329 u32 driver_timestamp;
1330 u32 checksum;
1331 u32 driver_capture_mask;
1332 u32 driver_info_word2;
1333 u32 driver_info_word3;
1334 u32 driver_info_word4;
1335 u32 saved_state_array[NX_DUMP_STATE_ARRAY_LEN];
1336 u32 capture_size_array[NX_DUMP_CAP_SIZE_ARRAY_LEN];
1337 u32 rsvd[0];
1338 };
1339
1340 /* Common Entry Header: Common to All Entry Types */
1341 /*
1342 * Driver Code is for driver to write some info about the entry.
1343 * Currently not used.
1344 */
1345
1346 struct netxen_common_entry_hdr {
1347 u32 entry_type;
1348 u32 entry_size;
1349 u32 entry_capture_size;
1350 union {
1351 struct {
1352 u8 entry_capture_mask;
1353 u8 entry_code;
1354 u8 driver_code;
1355 u8 driver_flags;
1356 };
1357 u32 entry_ctrl_word;
1358 };
1359 };
1360
1361
1362 /* Generic Entry Including Header */
1363 struct netxen_minidump_entry {
1364 struct netxen_common_entry_hdr hdr;
1365 u32 entry_data00;
1366 u32 entry_data01;
1367 u32 entry_data02;
1368 u32 entry_data03;
1369 u32 entry_data04;
1370 u32 entry_data05;
1371 u32 entry_data06;
1372 u32 entry_data07;
1373 };
1374
1375 /* Read ROM Header */
1376 struct netxen_minidump_entry_rdrom {
1377 struct netxen_common_entry_hdr h;
1378 union {
1379 struct {
1380 u32 select_addr_reg;
1381 };
1382 u32 rsvd_0;
1383 };
1384 union {
1385 struct {
1386 u8 addr_stride;
1387 u8 addr_cnt;
1388 u16 data_size;
1389 };
1390 u32 rsvd_1;
1391 };
1392 union {
1393 struct {
1394 u32 op_count;
1395 };
1396 u32 rsvd_2;
1397 };
1398 union {
1399 struct {
1400 u32 read_addr_reg;
1401 };
1402 u32 rsvd_3;
1403 };
1404 union {
1405 struct {
1406 u32 write_mask;
1407 };
1408 u32 rsvd_4;
1409 };
1410 union {
1411 struct {
1412 u32 read_mask;
1413 };
1414 u32 rsvd_5;
1415 };
1416 u32 read_addr;
1417 u32 read_data_size;
1418 };
1419
1420
1421 /* Read CRB and Control Entry Header */
1422 struct netxen_minidump_entry_crb {
1423 struct netxen_common_entry_hdr h;
1424 u32 addr;
1425 union {
1426 struct {
1427 u8 addr_stride;
1428 u8 state_index_a;
1429 u16 poll_timeout;
1430 };
1431 u32 addr_cntrl;
1432 };
1433 u32 data_size;
1434 u32 op_count;
1435 union {
1436 struct {
1437 u8 opcode;
1438 u8 state_index_v;
1439 u8 shl;
1440 u8 shr;
1441 };
1442 u32 control_value;
1443 };
1444 u32 value_1;
1445 u32 value_2;
1446 u32 value_3;
1447 };
1448
1449 /* Read Memory and MN Header */
1450 struct netxen_minidump_entry_rdmem {
1451 struct netxen_common_entry_hdr h;
1452 union {
1453 struct {
1454 u32 select_addr_reg;
1455 };
1456 u32 rsvd_0;
1457 };
1458 union {
1459 struct {
1460 u8 addr_stride;
1461 u8 addr_cnt;
1462 u16 data_size;
1463 };
1464 u32 rsvd_1;
1465 };
1466 union {
1467 struct {
1468 u32 op_count;
1469 };
1470 u32 rsvd_2;
1471 };
1472 union {
1473 struct {
1474 u32 read_addr_reg;
1475 };
1476 u32 rsvd_3;
1477 };
1478 union {
1479 struct {
1480 u32 cntrl_addr_reg;
1481 };
1482 u32 rsvd_4;
1483 };
1484 union {
1485 struct {
1486 u8 wr_byte0;
1487 u8 wr_byte1;
1488 u8 poll_mask;
1489 u8 poll_cnt;
1490 };
1491 u32 rsvd_5;
1492 };
1493 u32 read_addr;
1494 u32 read_data_size;
1495 };
1496
1497 /* Read Cache L1 and L2 Header */
1498 struct netxen_minidump_entry_cache {
1499 struct netxen_common_entry_hdr h;
1500 u32 tag_reg_addr;
1501 union {
1502 struct {
1503 u16 tag_value_stride;
1504 u16 init_tag_value;
1505 };
1506 u32 select_addr_cntrl;
1507 };
1508 u32 data_size;
1509 u32 op_count;
1510 u32 control_addr;
1511 union {
1512 struct {
1513 u16 write_value;
1514 u8 poll_mask;
1515 u8 poll_wait;
1516 };
1517 u32 control_value;
1518 };
1519 u32 read_addr;
1520 union {
1521 struct {
1522 u8 read_addr_stride;
1523 u8 read_addr_cnt;
1524 u16 rsvd_1;
1525 };
1526 u32 read_addr_cntrl;
1527 };
1528 };
1529
1530 /* Read OCM Header */
1531 struct netxen_minidump_entry_rdocm {
1532 struct netxen_common_entry_hdr h;
1533 u32 rsvd_0;
1534 union {
1535 struct {
1536 u32 rsvd_1;
1537 };
1538 u32 select_addr_cntrl;
1539 };
1540 u32 data_size;
1541 u32 op_count;
1542 u32 rsvd_2;
1543 u32 rsvd_3;
1544 u32 read_addr;
1545 union {
1546 struct {
1547 u32 read_addr_stride;
1548 };
1549 u32 read_addr_cntrl;
1550 };
1551 };
1552
1553 /* Read MUX Header */
1554 struct netxen_minidump_entry_mux {
1555 struct netxen_common_entry_hdr h;
1556 u32 select_addr;
1557 union {
1558 struct {
1559 u32 rsvd_0;
1560 };
1561 u32 select_addr_cntrl;
1562 };
1563 u32 data_size;
1564 u32 op_count;
1565 u32 select_value;
1566 u32 select_value_stride;
1567 u32 read_addr;
1568 u32 rsvd_1;
1569 };
1570
1571 /* Read Queue Header */
1572 struct netxen_minidump_entry_queue {
1573 struct netxen_common_entry_hdr h;
1574 u32 select_addr;
1575 union {
1576 struct {
1577 u16 queue_id_stride;
1578 u16 rsvd_0;
1579 };
1580 u32 select_addr_cntrl;
1581 };
1582 u32 data_size;
1583 u32 op_count;
1584 u32 rsvd_1;
1585 u32 rsvd_2;
1586 u32 read_addr;
1587 union {
1588 struct {
1589 u8 read_addr_stride;
1590 u8 read_addr_cnt;
1591 u16 rsvd_3;
1592 };
1593 u32 read_addr_cntrl;
1594 };
1595 };
1596
1597 struct netxen_dummy_dma {
1598 void *addr;
1599 dma_addr_t phys_addr;
1600 };
1601
1602 struct netxen_adapter {
1603 struct netxen_hardware_context ahw;
1604
1605 struct net_device *netdev;
1606 struct pci_dev *pdev;
1607 struct list_head mac_list;
1608 struct list_head vlan_ip_list;
1609
1610 spinlock_t tx_clean_lock;
1611
1612 u16 num_txd;
1613 u16 num_rxd;
1614 u16 num_jumbo_rxd;
1615 u16 num_lro_rxd;
1616
1617 u8 max_rds_rings;
1618 u8 max_sds_rings;
1619 u8 driver_mismatch;
1620 u8 msix_supported;
1621 u8 __pad;
1622 u8 pci_using_dac;
1623 u8 portnum;
1624 u8 physical_port;
1625
1626 u8 mc_enabled;
1627 u8 max_mc_count;
1628 u8 rss_supported;
1629 u8 link_changed;
1630 u8 fw_wait_cnt;
1631 u8 fw_fail_cnt;
1632 u8 tx_timeo_cnt;
1633 u8 need_fw_reset;
1634
1635 u8 has_link_events;
1636 u8 fw_type;
1637 u16 tx_context_id;
1638 u16 mtu;
1639 u16 is_up;
1640
1641 u16 link_speed;
1642 u16 link_duplex;
1643 u16 link_autoneg;
1644 u16 module_type;
1645
1646 u32 capabilities;
1647 u32 flags;
1648 u32 irq;
1649 u32 temp;
1650
1651 u32 int_vec_bit;
1652 u32 heartbit;
1653
1654 u8 mac_addr[ETH_ALEN];
1655
1656 struct netxen_adapter_stats stats;
1657
1658 struct netxen_recv_context recv_ctx;
1659 struct nx_host_tx_ring *tx_ring;
1660
1661 int (*macaddr_set) (struct netxen_adapter *, u8 *);
1662 int (*set_mtu) (struct netxen_adapter *, int);
1663 int (*set_promisc) (struct netxen_adapter *, u32);
1664 void (*set_multi) (struct net_device *);
1665 int (*phy_read) (struct netxen_adapter *, u32 reg, u32 *);
1666 int (*phy_write) (struct netxen_adapter *, u32 reg, u32 val);
1667 int (*init_port) (struct netxen_adapter *, int);
1668 int (*stop_port) (struct netxen_adapter *);
1669
1670 u32 (*crb_read)(struct netxen_adapter *, ulong);
1671 int (*crb_write)(struct netxen_adapter *, ulong, u32);
1672
1673 int (*pci_mem_read)(struct netxen_adapter *, u64, u64 *);
1674 int (*pci_mem_write)(struct netxen_adapter *, u64, u64);
1675
1676 int (*pci_set_window)(struct netxen_adapter *, u64, u32 *);
1677
1678 u32 (*io_read)(struct netxen_adapter *, void __iomem *);
1679 void (*io_write)(struct netxen_adapter *, void __iomem *, u32);
1680
1681 void __iomem *tgt_mask_reg;
1682 void __iomem *pci_int_reg;
1683 void __iomem *tgt_status_reg;
1684 void __iomem *crb_int_state_reg;
1685 void __iomem *isr_int_vec;
1686
1687 struct msix_entry msix_entries[MSIX_ENTRIES_PER_ADAPTER];
1688
1689 struct netxen_dummy_dma dummy_dma;
1690
1691 struct delayed_work fw_work;
1692
1693 struct work_struct tx_timeout_task;
1694
1695 nx_nic_intr_coalesce_t coal;
1696
1697 unsigned long state;
1698 __le32 file_prd_off; /*File fw product offset*/
1699 u32 fw_version;
1700 const struct firmware *fw;
1701 struct netxen_minidump mdump; /* mdump ptr */
1702 int fw_mdump_rdy; /* for mdump ready */
1703 };
1704
1705 int nx_fw_cmd_query_phy(struct netxen_adapter *adapter, u32 reg, u32 *val);
1706 int nx_fw_cmd_set_phy(struct netxen_adapter *adapter, u32 reg, u32 val);
1707
1708 #define NXRD32(adapter, off) \
1709 (adapter->crb_read(adapter, off))
1710 #define NXWR32(adapter, off, val) \
1711 (adapter->crb_write(adapter, off, val))
1712 #define NXRDIO(adapter, addr) \
1713 (adapter->io_read(adapter, addr))
1714 #define NXWRIO(adapter, addr, val) \
1715 (adapter->io_write(adapter, addr, val))
1716
1717 int netxen_pcie_sem_lock(struct netxen_adapter *, int, u32);
1718 void netxen_pcie_sem_unlock(struct netxen_adapter *, int);
1719
1720 #define netxen_rom_lock(a) \
1721 netxen_pcie_sem_lock((a), 2, NETXEN_ROM_LOCK_ID)
1722 #define netxen_rom_unlock(a) \
1723 netxen_pcie_sem_unlock((a), 2)
1724 #define netxen_phy_lock(a) \
1725 netxen_pcie_sem_lock((a), 3, NETXEN_PHY_LOCK_ID)
1726 #define netxen_phy_unlock(a) \
1727 netxen_pcie_sem_unlock((a), 3)
1728 #define netxen_api_lock(a) \
1729 netxen_pcie_sem_lock((a), 5, 0)
1730 #define netxen_api_unlock(a) \
1731 netxen_pcie_sem_unlock((a), 5)
1732 #define netxen_sw_lock(a) \
1733 netxen_pcie_sem_lock((a), 6, 0)
1734 #define netxen_sw_unlock(a) \
1735 netxen_pcie_sem_unlock((a), 6)
1736 #define crb_win_lock(a) \
1737 netxen_pcie_sem_lock((a), 7, NETXEN_CRB_WIN_LOCK_ID)
1738 #define crb_win_unlock(a) \
1739 netxen_pcie_sem_unlock((a), 7)
1740
1741 int netxen_nic_get_board_info(struct netxen_adapter *adapter);
1742 int netxen_nic_wol_supported(struct netxen_adapter *adapter);
1743
1744 /* Functions from netxen_nic_init.c */
1745 int netxen_init_dummy_dma(struct netxen_adapter *adapter);
1746 void netxen_free_dummy_dma(struct netxen_adapter *adapter);
1747
1748 int netxen_check_flash_fw_compatibility(struct netxen_adapter *adapter);
1749 int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val);
1750 int netxen_load_firmware(struct netxen_adapter *adapter);
1751 int netxen_need_fw_reset(struct netxen_adapter *adapter);
1752 void netxen_request_firmware(struct netxen_adapter *adapter);
1753 void netxen_release_firmware(struct netxen_adapter *adapter);
1754 int netxen_pinit_from_rom(struct netxen_adapter *adapter);
1755
1756 int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp);
1757 int netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
1758 u8 *bytes, size_t size);
1759 int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr,
1760 u8 *bytes, size_t size);
1761 int netxen_flash_unlock(struct netxen_adapter *adapter);
1762 int netxen_backup_crbinit(struct netxen_adapter *adapter);
1763 int netxen_flash_erase_secondary(struct netxen_adapter *adapter);
1764 int netxen_flash_erase_primary(struct netxen_adapter *adapter);
1765 void netxen_halt_pegs(struct netxen_adapter *adapter);
1766
1767 int netxen_rom_se(struct netxen_adapter *adapter, int addr);
1768
1769 int netxen_alloc_sw_resources(struct netxen_adapter *adapter);
1770 void netxen_free_sw_resources(struct netxen_adapter *adapter);
1771
1772 void netxen_setup_hwops(struct netxen_adapter *adapter);
1773 void __iomem *netxen_get_ioaddr(struct netxen_adapter *, u32);
1774
1775 int netxen_alloc_hw_resources(struct netxen_adapter *adapter);
1776 void netxen_free_hw_resources(struct netxen_adapter *adapter);
1777
1778 void netxen_release_rx_buffers(struct netxen_adapter *adapter);
1779 void netxen_release_tx_buffers(struct netxen_adapter *adapter);
1780
1781 int netxen_init_firmware(struct netxen_adapter *adapter);
1782 void netxen_nic_clear_stats(struct netxen_adapter *adapter);
1783 void netxen_watchdog_task(struct work_struct *work);
1784 void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid,
1785 struct nx_host_rds_ring *rds_ring);
1786 int netxen_process_cmd_ring(struct netxen_adapter *adapter);
1787 int netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max);
1788
1789 void netxen_p3_free_mac_list(struct netxen_adapter *adapter);
1790 int netxen_config_intr_coalesce(struct netxen_adapter *adapter);
1791 int netxen_config_rss(struct netxen_adapter *adapter, int enable);
1792 int netxen_config_ipaddr(struct netxen_adapter *adapter, __be32 ip, int cmd);
1793 int netxen_linkevent_request(struct netxen_adapter *adapter, int enable);
1794 void netxen_advert_link_change(struct netxen_adapter *adapter, int linkup);
1795 void netxen_pci_camqm_read_2M(struct netxen_adapter *, u64, u64 *);
1796 void netxen_pci_camqm_write_2M(struct netxen_adapter *, u64, u64);
1797
1798 int nx_fw_cmd_set_gbe_port(struct netxen_adapter *adapter,
1799 u32 speed, u32 duplex, u32 autoneg);
1800 int nx_fw_cmd_set_mtu(struct netxen_adapter *adapter, int mtu);
1801 int netxen_nic_change_mtu(struct net_device *netdev, int new_mtu);
1802 int netxen_config_hw_lro(struct netxen_adapter *adapter, int enable);
1803 int netxen_config_bridged_mode(struct netxen_adapter *adapter, int enable);
1804 int netxen_send_lro_cleanup(struct netxen_adapter *adapter);
1805 int netxen_setup_minidump(struct netxen_adapter *adapter);
1806 void netxen_dump_fw(struct netxen_adapter *adapter);
1807 void netxen_nic_update_cmd_producer(struct netxen_adapter *adapter,
1808 struct nx_host_tx_ring *tx_ring);
1809
1810 /* Functions from netxen_nic_main.c */
1811 int netxen_nic_reset_context(struct netxen_adapter *);
1812
1813 int nx_dev_request_reset(struct netxen_adapter *adapter);
1814
1815 /*
1816 * NetXen Board information
1817 */
1818
1819 #define NETXEN_MAX_SHORT_NAME 32
1820 struct netxen_brdinfo {
1821 int brdtype; /* type of board */
1822 long ports; /* max no of physical ports */
1823 char short_name[NETXEN_MAX_SHORT_NAME];
1824 };
1825
1826 struct netxen_dimm_cfg {
1827 u8 presence;
1828 u8 mem_type;
1829 u8 dimm_type;
1830 u32 size;
1831 };
1832
1833 static const struct netxen_brdinfo netxen_boards[] = {
1834 {NETXEN_BRDTYPE_P2_SB31_10G_CX4, 1, "XGb CX4"},
1835 {NETXEN_BRDTYPE_P2_SB31_10G_HMEZ, 1, "XGb HMEZ"},
1836 {NETXEN_BRDTYPE_P2_SB31_10G_IMEZ, 2, "XGb IMEZ"},
1837 {NETXEN_BRDTYPE_P2_SB31_10G, 1, "XGb XFP"},
1838 {NETXEN_BRDTYPE_P2_SB35_4G, 4, "Quad Gb"},
1839 {NETXEN_BRDTYPE_P2_SB31_2G, 2, "Dual Gb"},
1840 {NETXEN_BRDTYPE_P3_REF_QG, 4, "Reference Quad Gig "},
1841 {NETXEN_BRDTYPE_P3_HMEZ, 2, "Dual XGb HMEZ"},
1842 {NETXEN_BRDTYPE_P3_10G_CX4_LP, 2, "Dual XGb CX4 LP"},
1843 {NETXEN_BRDTYPE_P3_4_GB, 4, "Quad Gig LP"},
1844 {NETXEN_BRDTYPE_P3_IMEZ, 2, "Dual XGb IMEZ"},
1845 {NETXEN_BRDTYPE_P3_10G_SFP_PLUS, 2, "Dual XGb SFP+ LP"},
1846 {NETXEN_BRDTYPE_P3_10000_BASE_T, 1, "XGB 10G BaseT LP"},
1847 {NETXEN_BRDTYPE_P3_XG_LOM, 2, "Dual XGb LOM"},
1848 {NETXEN_BRDTYPE_P3_4_GB_MM, 4, "NX3031 Gigabit Ethernet"},
1849 {NETXEN_BRDTYPE_P3_10G_SFP_CT, 2, "NX3031 10 Gigabit Ethernet"},
1850 {NETXEN_BRDTYPE_P3_10G_SFP_QT, 2, "Quanta Dual XGb SFP+"},
1851 {NETXEN_BRDTYPE_P3_10G_CX4, 2, "Reference Dual CX4 Option"},
1852 {NETXEN_BRDTYPE_P3_10G_XFP, 1, "Reference Single XFP Option"}
1853 };
1854
1855 #define NUM_SUPPORTED_BOARDS ARRAY_SIZE(netxen_boards)
1856
1857 static inline void get_brd_name_by_type(u32 type, char *name)
1858 {
1859 int i, found = 0;
1860 for (i = 0; i < NUM_SUPPORTED_BOARDS; ++i) {
1861 if (netxen_boards[i].brdtype == type) {
1862 strcpy(name, netxen_boards[i].short_name);
1863 found = 1;
1864 break;
1865 }
1866
1867 }
1868 if (!found)
1869 name = "Unknown";
1870 }
1871
1872 static inline u32 netxen_tx_avail(struct nx_host_tx_ring *tx_ring)
1873 {
1874 smp_mb();
1875 return find_diff_among(tx_ring->producer,
1876 tx_ring->sw_consumer, tx_ring->num_desc);
1877
1878 }
1879
1880 int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, u64 *mac);
1881 int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, u64 *mac);
1882 extern void netxen_change_ringparam(struct netxen_adapter *adapter);
1883 extern int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr,
1884 int *valp);
1885
1886 extern const struct ethtool_ops netxen_nic_ethtool_ops;
1887
1888 #endif /* __NETXEN_NIC_H_ */
Linux ARM platform port for MOXA ART SoC