drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c

   1 /*******************************************************************************
   2   This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
   3   DWC Ether MAC 10/100/1000 Universal version 3.41a  has been used for
   4   developing this code.
   5
   6   This only implements the mac core functions for this chip.
   7
   8   Copyright (C) 2007-2009  STMicroelectronics Ltd
   9
  10   This program is free software; you can redistribute it and/or modify it
  11   under the terms and conditions of the GNU General Public License,
  12   version 2, as published by the Free Software Foundation.
  13
  14   This program is distributed in the hope it will be useful, but WITHOUT
  15   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17   more details.
  18
  19   You should have received a copy of the GNU General Public License along with
  20   this program; if not, write to the Free Software Foundation, Inc.,
  21   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  22
  23   The full GNU General Public License is included in this distribution in
  24   the file called "COPYING".
  25
  26   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  27 *******************************************************************************/
  28
  29 #include <linux/crc32.h>
  30 #include <linux/slab.h>
  31 #include <asm/io.h>
  32 #include "dwmac1000.h"
  33
  34 static void dwmac1000_core_init(void __iomem *ioaddr)
  35 {
  36         u32 value = readl(ioaddr + GMAC_CONTROL);
  37         value |= GMAC_CORE_INIT;
  38         writel(value, ioaddr + GMAC_CONTROL);
  39
  40         /* Mask GMAC interrupts */
  41         writel(0x207, ioaddr + GMAC_INT_MASK);
  42
  43 #ifdef STMMAC_VLAN_TAG_USED
  44         /* Tag detection without filtering */
  45         writel(0x0, ioaddr + GMAC_VLAN_TAG);
  46 #endif
  47 }
  48
  49 static int dwmac1000_rx_ipc_enable(void __iomem *ioaddr)
  50 {
  51         u32 value = readl(ioaddr + GMAC_CONTROL);
  52
  53         value |= GMAC_CONTROL_IPC;
  54         writel(value, ioaddr + GMAC_CONTROL);
  55
  56         value = readl(ioaddr + GMAC_CONTROL);
  57
  58         return !!(value & GMAC_CONTROL_IPC);
  59 }
  60
  61 static void dwmac1000_dump_regs(void __iomem *ioaddr)
  62 {
  63         int i;
  64         pr_info("\tDWMAC1000 regs (base addr = 0x%p)\n", ioaddr);
  65
  66         for (i = 0; i < 55; i++) {
  67                 int offset = i * 4;
  68                 pr_info("\tReg No. %d (offset 0x%x): 0x%08x\n", i,
  69                         offset, readl(ioaddr + offset));
  70         }
  71 }
  72
  73 static void dwmac1000_set_umac_addr(void __iomem *ioaddr, unsigned char *addr,
  74                                 unsigned int reg_n)
  75 {
  76         stmmac_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
  77                                 GMAC_ADDR_LOW(reg_n));
  78 }
  79
  80 static void dwmac1000_get_umac_addr(void __iomem *ioaddr, unsigned char *addr,
  81                                 unsigned int reg_n)
  82 {
  83         stmmac_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
  84                                 GMAC_ADDR_LOW(reg_n));
  85 }
  86
  87 static void dwmac1000_set_filter(struct net_device *dev, int id)
  88 {
  89         void __iomem *ioaddr = (void __iomem *) dev->base_addr;
  90         unsigned int value = 0;
  91         unsigned int perfect_addr_number;
  92
  93         CHIP_DBG(KERN_INFO "%s: # mcasts %d, # unicast %d\n",
  94                  __func__, netdev_mc_count(dev), netdev_uc_count(dev));
  95
  96         if (dev->flags & IFF_PROMISC)
  97                 value = GMAC_FRAME_FILTER_PR;
  98         else if ((netdev_mc_count(dev) > HASH_TABLE_SIZE)
  99                    || (dev->flags & IFF_ALLMULTI)) {
 100                 value = GMAC_FRAME_FILTER_PM;   /* pass all multi */
 101                 writel(0xffffffff, ioaddr + GMAC_HASH_HIGH);
 102                 writel(0xffffffff, ioaddr + GMAC_HASH_LOW);
 103         } else if (!netdev_mc_empty(dev)) {
 104                 u32 mc_filter[2];
 105                 struct netdev_hw_addr *ha;
 106
 107                 /* Hash filter for multicast */
 108                 value = GMAC_FRAME_FILTER_HMC;
 109
 110                 memset(mc_filter, 0, sizeof(mc_filter));
 111                 netdev_for_each_mc_addr(ha, dev) {
 112                         /* The upper 6 bits of the calculated CRC are used to
 113                            index the contens of the hash table */
 114                         int bit_nr =
 115                             bitrev32(~crc32_le(~0, ha->addr, 6)) >> 26;
 116                         /* The most significant bit determines the register to
 117                          * use (H/L) while the other 5 bits determine the bit
 118                          * within the register. */
 119                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
 120                 }
 121                 writel(mc_filter[0], ioaddr + GMAC_HASH_LOW);
 122                 writel(mc_filter[1], ioaddr + GMAC_HASH_HIGH);
 123         }
 124
 125         /* Extra 16 regs are available in cores newer than the 3.40. */
 126         if (id > DWMAC_CORE_3_40)
 127                 perfect_addr_number = GMAC_MAX_PERFECT_ADDRESSES;
 128         else
 129                 perfect_addr_number = GMAC_MAX_PERFECT_ADDRESSES / 2;
 130
 131         /* Handle multiple unicast addresses (perfect filtering)*/
 132         if (netdev_uc_count(dev) > perfect_addr_number)
 133                 /* Switch to promiscuous mode is more than 16 addrs
 134                    are required */
 135                 value |= GMAC_FRAME_FILTER_PR;
 136         else {
 137                 int reg = 1;
 138                 struct netdev_hw_addr *ha;
 139
 140                 netdev_for_each_uc_addr(ha, dev) {
 141                         dwmac1000_set_umac_addr(ioaddr, ha->addr, reg);
 142                         reg++;
 143                 }
 144         }
 145
 146 #ifdef FRAME_FILTER_DEBUG
 147         /* Enable Receive all mode (to debug filtering_fail errors) */
 148         value |= GMAC_FRAME_FILTER_RA;
 149 #endif
 150         writel(value, ioaddr + GMAC_FRAME_FILTER);
 151
 152         CHIP_DBG(KERN_INFO "\tFrame Filter reg: 0x%08x\n\tHash regs: "
 153             "HI 0x%08x, LO 0x%08x\n", readl(ioaddr + GMAC_FRAME_FILTER),
 154             readl(ioaddr + GMAC_HASH_HIGH), readl(ioaddr + GMAC_HASH_LOW));
 155 }
 156
 157 static void dwmac1000_flow_ctrl(void __iomem *ioaddr, unsigned int duplex,
 158                            unsigned int fc, unsigned int pause_time)
 159 {
 160         unsigned int flow = 0;
 161
 162         CHIP_DBG(KERN_DEBUG "GMAC Flow-Control:\n");
 163         if (fc & FLOW_RX) {
 164                 CHIP_DBG(KERN_DEBUG "\tReceive Flow-Control ON\n");
 165                 flow |= GMAC_FLOW_CTRL_RFE;
 166         }
 167         if (fc & FLOW_TX) {
 168                 CHIP_DBG(KERN_DEBUG "\tTransmit Flow-Control ON\n");
 169                 flow |= GMAC_FLOW_CTRL_TFE;
 170         }
 171
 172         if (duplex) {
 173                 CHIP_DBG(KERN_DEBUG "\tduplex mode: PAUSE %d\n", pause_time);
 174                 flow |= (pause_time << GMAC_FLOW_CTRL_PT_SHIFT);
 175         }
 176
 177         writel(flow, ioaddr + GMAC_FLOW_CTRL);
 178 }
 179
 180 static void dwmac1000_pmt(void __iomem *ioaddr, unsigned long mode)
 181 {
 182         unsigned int pmt = 0;
 183
 184         if (mode & WAKE_MAGIC) {
 185                 CHIP_DBG(KERN_DEBUG "GMAC: WOL Magic frame\n");
 186                 pmt |= power_down | magic_pkt_en;
 187         }
 188         if (mode & WAKE_UCAST) {
 189                 CHIP_DBG(KERN_DEBUG "GMAC: WOL on global unicast\n");
 190                 pmt |= global_unicast;
 191         }
 192
 193         writel(pmt, ioaddr + GMAC_PMT);
 194 }
 195
 196
 197 static int dwmac1000_irq_status(void __iomem *ioaddr)
 198 {
 199         u32 intr_status = readl(ioaddr + GMAC_INT_STATUS);
 200         int status = 0;
 201
 202         /* Not used events (e.g. MMC interrupts) are not handled. */
 203         if ((intr_status & mmc_tx_irq)) {
 204                 CHIP_DBG(KERN_INFO "GMAC: MMC tx interrupt: 0x%08x\n",
 205                     readl(ioaddr + GMAC_MMC_TX_INTR));
 206                 status |= core_mmc_tx_irq;
 207         }
 208         if (unlikely(intr_status & mmc_rx_irq)) {
 209                 CHIP_DBG(KERN_INFO "GMAC: MMC rx interrupt: 0x%08x\n",
 210                     readl(ioaddr + GMAC_MMC_RX_INTR));
 211                 status |= core_mmc_rx_irq;
 212         }
 213         if (unlikely(intr_status & mmc_rx_csum_offload_irq)) {
 214                 CHIP_DBG(KERN_INFO "GMAC: MMC rx csum offload: 0x%08x\n",
 215                     readl(ioaddr + GMAC_MMC_RX_CSUM_OFFLOAD));
 216                 status |= core_mmc_rx_csum_offload_irq;
 217         }
 218         if (unlikely(intr_status & pmt_irq)) {
 219                 CHIP_DBG(KERN_INFO "GMAC: received Magic frame\n");
 220                 /* clear the PMT bits 5 and 6 by reading the PMT
 221                  * status register. */
 222                 readl(ioaddr + GMAC_PMT);
 223                 status |= core_irq_receive_pmt_irq;
 224         }
 225         /* MAC trx/rx EEE LPI entry/exit interrupts */
 226         if (intr_status & lpiis_irq) {
 227                 /* Clean LPI interrupt by reading the Reg 12 */
 228                 u32 lpi_status = readl(ioaddr + LPI_CTRL_STATUS);
 229
 230                 if (lpi_status & LPI_CTRL_STATUS_TLPIEN) {
 231                         CHIP_DBG(KERN_INFO "GMAC TX entered in LPI\n");
 232                         status |= core_irq_tx_path_in_lpi_mode;
 233                 }
 234                 if (lpi_status & LPI_CTRL_STATUS_TLPIEX) {
 235                         CHIP_DBG(KERN_INFO "GMAC TX exit from LPI\n");
 236                         status |= core_irq_tx_path_exit_lpi_mode;
 237                 }
 238                 if (lpi_status & LPI_CTRL_STATUS_RLPIEN) {
 239                         CHIP_DBG(KERN_INFO "GMAC RX entered in LPI\n");
 240                         status |= core_irq_rx_path_in_lpi_mode;
 241                 }
 242                 if (lpi_status & LPI_CTRL_STATUS_RLPIEX) {
 243                         CHIP_DBG(KERN_INFO "GMAC RX exit from LPI\n");
 244                         status |= core_irq_rx_path_exit_lpi_mode;
 245                 }
 246         }
 247
 248         return status;
 249 }
 250
 251 static void  dwmac1000_set_eee_mode(void __iomem *ioaddr)
 252 {
 253         u32 value;
 254
 255         /* Enable the link status receive on RGMII, SGMII ore SMII
 256          * receive path and instruct the transmit to enter in LPI
 257          * state. */
 258         value = readl(ioaddr + LPI_CTRL_STATUS);
 259         value |= LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_LPITXA;
 260         writel(value, ioaddr + LPI_CTRL_STATUS);
 261 }
 262
 263 static void  dwmac1000_reset_eee_mode(void __iomem *ioaddr)
 264 {
 265         u32 value;
 266
 267         value = readl(ioaddr + LPI_CTRL_STATUS);
 268         value &= ~(LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_LPITXA);
 269         writel(value, ioaddr + LPI_CTRL_STATUS);
 270 }
 271
 272 static void  dwmac1000_set_eee_pls(void __iomem *ioaddr, int link)
 273 {
 274         u32 value;
 275
 276         value = readl(ioaddr + LPI_CTRL_STATUS);
 277
 278         if (link)
 279                 value |= LPI_CTRL_STATUS_PLS;
 280         else
 281                 value &= ~LPI_CTRL_STATUS_PLS;
 282
 283         writel(value, ioaddr + LPI_CTRL_STATUS);
 284 }
 285
 286 static void  dwmac1000_set_eee_timer(void __iomem *ioaddr, int ls, int tw)
 287 {
 288         int value = ((tw & 0xffff)) | ((ls & 0x7ff) << 16);
 289
 290         /* Program the timers in the LPI timer control register:
 291          * LS: minimum time (ms) for which the link
 292          *  status from PHY should be ok before transmitting
 293          *  the LPI pattern.
 294          * TW: minimum time (us) for which the core waits
 295          *  after it has stopped transmitting the LPI pattern.
 296          */
 297         writel(value, ioaddr + LPI_TIMER_CTRL);
 298 }
 299
 300 static const struct stmmac_ops dwmac1000_ops = {
 301         .core_init = dwmac1000_core_init,
 302         .rx_ipc = dwmac1000_rx_ipc_enable,
 303         .dump_regs = dwmac1000_dump_regs,
 304         .host_irq_status = dwmac1000_irq_status,
 305         .set_filter = dwmac1000_set_filter,
 306         .flow_ctrl = dwmac1000_flow_ctrl,
 307         .pmt = dwmac1000_pmt,
 308         .set_umac_addr = dwmac1000_set_umac_addr,
 309         .get_umac_addr = dwmac1000_get_umac_addr,
 310         .set_eee_mode =  dwmac1000_set_eee_mode,
 311         .reset_eee_mode =  dwmac1000_reset_eee_mode,
 312         .set_eee_timer =  dwmac1000_set_eee_timer,
 313         .set_eee_pls =  dwmac1000_set_eee_pls,
 314 };
 315
 316 struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr)
 317 {
 318         struct mac_device_info *mac;
 319         u32 hwid = readl(ioaddr + GMAC_VERSION);
 320
 321         mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL);
 322         if (!mac)
 323                 return NULL;
 324
 325         mac->mac = &dwmac1000_ops;
 326         mac->dma = &dwmac1000_dma_ops;
 327
 328         mac->link.port = GMAC_CONTROL_PS;
 329         mac->link.duplex = GMAC_CONTROL_DM;
 330         mac->link.speed = GMAC_CONTROL_FES;
 331         mac->mii.addr = GMAC_MII_ADDR;
 332         mac->mii.data = GMAC_MII_DATA;
 333         mac->synopsys_uid = hwid;
 334
 335         return mac;
 336 }