drivers/net/wireless/ath/ath9k/pci.c

   1 /*
   2  * Copyright (c) 2008-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  18
  19 #include <linux/nl80211.h>
  20 #include <linux/pci.h>
  21 #include <linux/pci-aspm.h>
  22 #include <linux/ath9k_platform.h>
  23 #include <linux/module.h>
  24 #include "ath9k.h"
  25
  26 static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = {
  27         { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI   */
  28         { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
  29         { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI   */
  30         { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI   */
  31         { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
  32         { PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */
  33         { PCI_VDEVICE(ATHEROS, 0x002C) }, /* PCI-E 802.11n bonded out */
  34         { PCI_VDEVICE(ATHEROS, 0x002D) }, /* PCI   */
  35         { PCI_VDEVICE(ATHEROS, 0x002E) }, /* PCI-E */
  36         { PCI_VDEVICE(ATHEROS, 0x0030) }, /* PCI-E  AR9300 */
  37         { PCI_VDEVICE(ATHEROS, 0x0032) }, /* PCI-E  AR9485 */
  38         { PCI_VDEVICE(ATHEROS, 0x0033) }, /* PCI-E  AR9580 */
  39         { PCI_VDEVICE(ATHEROS, 0x0034) }, /* PCI-E  AR9462 */
  40         { PCI_VDEVICE(ATHEROS, 0x0037) }, /* PCI-E  AR1111/AR9485 */
  41         { 0 }
  42 };
  43
  44
  45 /* return bus cachesize in 4B word units */
  46 static void ath_pci_read_cachesize(struct ath_common *common, int *csz)
  47 {
  48         struct ath_softc *sc = (struct ath_softc *) common->priv;
  49         u8 u8tmp;
  50
  51         pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE, &u8tmp);
  52         *csz = (int)u8tmp;
  53
  54         /*
  55          * This check was put in to avoid "unpleasant" consequences if
  56          * the bootrom has not fully initialized all PCI devices.
  57          * Sometimes the cache line size register is not set
  58          */
  59
  60         if (*csz == 0)
  61                 *csz = DEFAULT_CACHELINE >> 2;   /* Use the default size */
  62 }
  63
  64 static bool ath_pci_eeprom_read(struct ath_common *common, u32 off, u16 *data)
  65 {
  66         struct ath_softc *sc = (struct ath_softc *) common->priv;
  67         struct ath9k_platform_data *pdata = sc->dev->platform_data;
  68
  69         if (pdata) {
  70                 if (off >= (ARRAY_SIZE(pdata->eeprom_data))) {
  71                         ath_err(common,
  72                                 "%s: eeprom read failed, offset %08x is out of range\n",
  73                                 __func__, off);
  74                 }
  75
  76                 *data = pdata->eeprom_data[off];
  77         } else {
  78                 struct ath_hw *ah = (struct ath_hw *) common->ah;
  79
  80                 common->ops->read(ah, AR5416_EEPROM_OFFSET +
  81                                       (off << AR5416_EEPROM_S));
  82
  83                 if (!ath9k_hw_wait(ah,
  84                                    AR_EEPROM_STATUS_DATA,
  85                                    AR_EEPROM_STATUS_DATA_BUSY |
  86                                    AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
  87                                    AH_WAIT_TIMEOUT)) {
  88                         return false;
  89                 }
  90
  91                 *data = MS(common->ops->read(ah, AR_EEPROM_STATUS_DATA),
  92                            AR_EEPROM_STATUS_DATA_VAL);
  93         }
  94
  95         return true;
  96 }
  97
  98 static void ath_pci_extn_synch_enable(struct ath_common *common)
  99 {
 100         struct ath_softc *sc = (struct ath_softc *) common->priv;
 101         struct pci_dev *pdev = to_pci_dev(sc->dev);
 102         u8 lnkctl;
 103
 104         pci_read_config_byte(pdev, sc->sc_ah->caps.pcie_lcr_offset, &lnkctl);
 105         lnkctl |= PCI_EXP_LNKCTL_ES;
 106         pci_write_config_byte(pdev, sc->sc_ah->caps.pcie_lcr_offset, lnkctl);
 107 }
 108
 109 /* Need to be called after we discover btcoex capabilities */
 110 static void ath_pci_aspm_init(struct ath_common *common)
 111 {
 112         struct ath_softc *sc = (struct ath_softc *) common->priv;
 113         struct ath_hw *ah = sc->sc_ah;
 114         struct pci_dev *pdev = to_pci_dev(sc->dev);
 115         struct pci_dev *parent;
 116         int pos;
 117         u8 aspm;
 118
 119         if (!ah->is_pciexpress)
 120                 return;
 121
 122         pos = pci_pcie_cap(pdev);
 123         if (!pos)
 124                 return;
 125
 126         parent = pdev->bus->self;
 127         if (!parent)
 128                 return;
 129
 130         if ((ath9k_hw_get_btcoex_scheme(ah) != ATH_BTCOEX_CFG_NONE) &&
 131             (AR_SREV_9285(ah))) {
 132                 /* Bluetooth coexistance requires disabling ASPM for AR9285. */
 133                 pci_read_config_byte(pdev, pos + PCI_EXP_LNKCTL, &aspm);
 134                 aspm &= ~(PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
 135                 pci_write_config_byte(pdev, pos + PCI_EXP_LNKCTL, aspm);
 136
 137                 /*
 138                  * Both upstream and downstream PCIe components should
 139                  * have the same ASPM settings.
 140                  */
 141                 pos = pci_pcie_cap(parent);
 142                 pci_read_config_byte(parent, pos + PCI_EXP_LNKCTL, &aspm);
 143                 aspm &= ~(PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
 144                 pci_write_config_byte(parent, pos + PCI_EXP_LNKCTL, aspm);
 145
 146                 ath_info(common, "Disabling ASPM since BTCOEX is enabled\n");
 147                 return;
 148         }
 149
 150         pos = pci_pcie_cap(parent);
 151         pci_read_config_byte(parent, pos +  PCI_EXP_LNKCTL, &aspm);
 152         if (aspm & (PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1)) {
 153                 ah->aspm_enabled = true;
 154                 /* Initialize PCIe PM and SERDES registers. */
 155                 ath9k_hw_configpcipowersave(ah, false);
 156                 ath_info(common, "ASPM enabled: 0x%x\n", aspm);
 157         }
 158 }
 159
 160 static const struct ath_bus_ops ath_pci_bus_ops = {
 161         .ath_bus_type = ATH_PCI,
 162         .read_cachesize = ath_pci_read_cachesize,
 163         .eeprom_read = ath_pci_eeprom_read,
 164         .extn_synch_en = ath_pci_extn_synch_enable,
 165         .aspm_init = ath_pci_aspm_init,
 166 };
 167
 168 static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 169 {
 170         void __iomem *mem;
 171         struct ath_softc *sc;
 172         struct ieee80211_hw *hw;
 173         u8 csz;
 174         u32 val;
 175         int ret = 0;
 176         char hw_name[64];
 177
 178         if (pci_enable_device(pdev))
 179                 return -EIO;
 180
 181         ret =  pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
 182         if (ret) {
 183                 pr_err("32-bit DMA not available\n");
 184                 goto err_dma;
 185         }
 186
 187         ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
 188         if (ret) {
 189                 pr_err("32-bit DMA consistent DMA enable failed\n");
 190                 goto err_dma;
 191         }
 192
 193         /*
 194          * Cache line size is used to size and align various
 195          * structures used to communicate with the hardware.
 196          */
 197         pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
 198         if (csz == 0) {
 199                 /*
 200                  * Linux 2.4.18 (at least) writes the cache line size
 201                  * register as a 16-bit wide register which is wrong.
 202                  * We must have this setup properly for rx buffer
 203                  * DMA to work so force a reasonable value here if it
 204                  * comes up zero.
 205                  */
 206                 csz = L1_CACHE_BYTES / sizeof(u32);
 207                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
 208         }
 209         /*
 210          * The default setting of latency timer yields poor results,
 211          * set it to the value used by other systems. It may be worth
 212          * tweaking this setting more.
 213          */
 214         pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
 215
 216         pci_set_master(pdev);
 217
 218         /*
 219          * Disable the RETRY_TIMEOUT register (0x41) to keep
 220          * PCI Tx retries from interfering with C3 CPU state.
 221          */
 222         pci_read_config_dword(pdev, 0x40, &val);
 223         if ((val & 0x0000ff00) != 0)
 224                 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
 225
 226         ret = pci_request_region(pdev, 0, "ath9k");
 227         if (ret) {
 228                 dev_err(&pdev->dev, "PCI memory region reserve error\n");
 229                 ret = -ENODEV;
 230                 goto err_region;
 231         }
 232
 233         mem = pci_iomap(pdev, 0, 0);
 234         if (!mem) {
 235                 pr_err("PCI memory map error\n") ;
 236                 ret = -EIO;
 237                 goto err_iomap;
 238         }
 239
 240         hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
 241         if (!hw) {
 242                 dev_err(&pdev->dev, "No memory for ieee80211_hw\n");
 243                 ret = -ENOMEM;
 244                 goto err_alloc_hw;
 245         }
 246
 247         SET_IEEE80211_DEV(hw, &pdev->dev);
 248         pci_set_drvdata(pdev, hw);
 249
 250         sc = hw->priv;
 251         sc->hw = hw;
 252         sc->dev = &pdev->dev;
 253         sc->mem = mem;
 254
 255         /* Will be cleared in ath9k_start() */
 256         set_bit(SC_OP_INVALID, &sc->sc_flags);
 257
 258         ret = request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath9k", sc);
 259         if (ret) {
 260                 dev_err(&pdev->dev, "request_irq failed\n");
 261                 goto err_irq;
 262         }
 263
 264         sc->irq = pdev->irq;
 265
 266         ret = ath9k_init_device(id->device, sc, &ath_pci_bus_ops);
 267         if (ret) {
 268                 dev_err(&pdev->dev, "Failed to initialize device\n");
 269                 goto err_init;
 270         }
 271
 272         ath9k_hw_name(sc->sc_ah, hw_name, sizeof(hw_name));
 273         wiphy_info(hw->wiphy, "%s mem=0x%lx, irq=%d\n",
 274                    hw_name, (unsigned long)mem, pdev->irq);
 275
 276         return 0;
 277
 278 err_init:
 279         free_irq(sc->irq, sc);
 280 err_irq:
 281         ieee80211_free_hw(hw);
 282 err_alloc_hw:
 283         pci_iounmap(pdev, mem);
 284 err_iomap:
 285         pci_release_region(pdev, 0);
 286 err_region:
 287         /* Nothing */
 288 err_dma:
 289         pci_disable_device(pdev);
 290         return ret;
 291 }
 292
 293 static void ath_pci_remove(struct pci_dev *pdev)
 294 {
 295         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
 296         struct ath_softc *sc = hw->priv;
 297         void __iomem *mem = sc->mem;
 298
 299         if (!is_ath9k_unloaded)
 300                 sc->sc_ah->ah_flags |= AH_UNPLUGGED;
 301         ath9k_deinit_device(sc);
 302         free_irq(sc->irq, sc);
 303         ieee80211_free_hw(sc->hw);
 304
 305         pci_iounmap(pdev, mem);
 306         pci_disable_device(pdev);
 307         pci_release_region(pdev, 0);
 308 }
 309
 310 #ifdef CONFIG_PM
 311
 312 static int ath_pci_suspend(struct device *device)
 313 {
 314         struct pci_dev *pdev = to_pci_dev(device);
 315         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
 316         struct ath_softc *sc = hw->priv;
 317
 318         if (sc->wow_enabled)
 319                 return 0;
 320
 321         /* The device has to be moved to FULLSLEEP forcibly.
 322          * Otherwise the chip never moved to full sleep,
 323          * when no interface is up.
 324          */
 325         ath9k_stop_btcoex(sc);
 326         ath9k_hw_disable(sc->sc_ah);
 327         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
 328
 329         return 0;
 330 }
 331
 332 static int ath_pci_resume(struct device *device)
 333 {
 334         struct pci_dev *pdev = to_pci_dev(device);
 335         u32 val;
 336
 337         /*
 338          * Suspend/Resume resets the PCI configuration space, so we have to
 339          * re-disable the RETRY_TIMEOUT register (0x41) to keep
 340          * PCI Tx retries from interfering with C3 CPU state
 341          */
 342         pci_read_config_dword(pdev, 0x40, &val);
 343         if ((val & 0x0000ff00) != 0)
 344                 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
 345
 346         return 0;
 347 }
 348
 349 static const struct dev_pm_ops ath9k_pm_ops = {
 350         .suspend = ath_pci_suspend,
 351         .resume = ath_pci_resume,
 352         .freeze = ath_pci_suspend,
 353         .thaw = ath_pci_resume,
 354         .poweroff = ath_pci_suspend,
 355         .restore = ath_pci_resume,
 356 };
 357
 358 #define ATH9K_PM_OPS    (&ath9k_pm_ops)
 359
 360 #else /* !CONFIG_PM */
 361
 362 #define ATH9K_PM_OPS    NULL
 363
 364 #endif /* !CONFIG_PM */
 365
 366
 367 MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
 368
 369 static struct pci_driver ath_pci_driver = {
 370         .name       = "ath9k",
 371         .id_table   = ath_pci_id_table,
 372         .probe      = ath_pci_probe,
 373         .remove     = ath_pci_remove,
 374         .driver.pm  = ATH9K_PM_OPS,
 375 };
 376
 377 int ath_pci_init(void)
 378 {
 379         return pci_register_driver(&ath_pci_driver);
 380 }
 381
 382 void ath_pci_exit(void)
 383 {
 384         pci_unregister_driver(&ath_pci_driver);
 385 }