drivers/staging/ipack/devices/scc2698.h

   1 /*
   2  * scc2698.h
   3  *
   4  * driver for the IPOCTAL boards
   5  * Copyright (c) 2009 Nicolas Serafini, EIC2 SA
   6  * Copyright (c) 2010,2011 Samuel Iglesias Gonsalvez <siglesia@cern.ch>, CERN
   7  * Copyright (c) 2012 Samuel Iglesias Gonsalvez <siglesias@igalia.com>, Igalia
   8  *
   9  * This program is free software; you can redistribute it and/or modify it
  10  * under the terms of the GNU General Public License as published by the Free
  11  * Software Foundation; version 2 of the License.
  12  */
  13
  14 #ifndef SCC2698_H_
  15 #define SCC2698_H_
  16
  17 /*
  18  * struct scc2698_channel - Channel access to scc2698 IO
  19  *
  20  * dn value are only spacer.
  21  *
  22  */
  23 struct scc2698_channel {
  24         union {
  25                 struct {
  26                         unsigned char d0, mr;  /* Mode register 1/2*/
  27                         unsigned char d1, sr;  /* Status register */
  28                         unsigned char d2, r1;  /* reserved */
  29                         unsigned char d3, rhr; /* Receive holding register (R) */
  30                         unsigned char junk[8]; /* other crap for block control */
  31                 } r; /* Read access */
  32                 struct {
  33                         unsigned char d0, mr;  /* Mode register 1/2 */
  34                         unsigned char d1, csr; /* Clock select register */
  35                         unsigned char d2, cr;  /* Command register */
  36                         unsigned char d3, thr; /* Transmit holding register */
  37                         unsigned char junk[8]; /* other crap for block control */
  38                 } w; /* Write access */
  39         } u;
  40 };
  41
  42 /*
  43  * struct scc2698_block - Block access to scc2698 IO
  44  *
  45  * The scc2698 contain 4 block.
  46  * Each block containt two channel a and b.
  47  * dn value are only spacer.
  48  *
  49  */
  50 struct scc2698_block {
  51         union {
  52                 struct {
  53                         unsigned char d0, mra;  /* Mode register 1/2 (a) */
  54                         unsigned char d1, sra;  /* Status register (a) */
  55                         unsigned char d2, r1;   /* reserved */
  56                         unsigned char d3, rhra; /* Receive holding register (a) */
  57                         unsigned char d4, ipcr; /* Input port change register of block */
  58                         unsigned char d5, isr;  /* Interrupt status register of block */
  59                         unsigned char d6, ctur; /* Counter timer upper register of block */
  60                         unsigned char d7, ctlr; /* Counter timer lower register of block */
  61                         unsigned char d8, mrb;  /* Mode register 1/2 (b) */
  62                         unsigned char d9, srb;  /* Status register (b) */
  63                         unsigned char da, r2;   /* reserved */
  64                         unsigned char db, rhrb; /* Receive holding register (b) */
  65                         unsigned char dc, r3;   /* reserved */
  66                         unsigned char dd, ip;   /* Input port register of block */
  67                         unsigned char de, ctg;  /* Start counter timer of block */
  68                         unsigned char df, cts;  /* Stop counter timer of block */
  69                 } r; /* Read access */
  70                 struct {
  71                         unsigned char d0, mra;  /* Mode register 1/2 (a) */
  72                         unsigned char d1, csra; /* Clock select register (a) */
  73                         unsigned char d2, cra;  /* Command register (a) */
  74                         unsigned char d3, thra; /* Transmit holding register (a) */
  75                         unsigned char d4, acr;  /* Auxiliary control register of block */
  76                         unsigned char d5, imr;  /* Interrupt mask register of block  */
  77                         unsigned char d6, ctu;  /* Counter timer upper register of block */
  78                         unsigned char d7, ctl;  /* Counter timer lower register of block */
  79                         unsigned char d8, mrb;  /* Mode register 1/2 (b) */
  80                         unsigned char d9, csrb; /* Clock select register (a) */
  81                         unsigned char da, crb;  /* Command register (b) */
  82                         unsigned char db, thrb; /* Transmit holding register (b) */
  83                         unsigned char dc, r1;   /* reserved */
  84                         unsigned char dd, opcr; /* Output port configuration register of block */
  85                         unsigned char de, r2;   /* reserved */
  86                         unsigned char df, r3;   /* reserved */
  87                 } w; /* Write access */
  88         } u;
  89 } ;
  90
  91 #define MR1_CHRL_5_BITS             (0x0 << 0)
  92 #define MR1_CHRL_6_BITS             (0x1 << 0)
  93 #define MR1_CHRL_7_BITS             (0x2 << 0)
  94 #define MR1_CHRL_8_BITS             (0x3 << 0)
  95 #define MR1_PARITY_EVEN             (0x1 << 2)
  96 #define MR1_PARITY_ODD              (0x0 << 2)
  97 #define MR1_PARITY_ON               (0x0 << 3)
  98 #define MR1_PARITY_FORCE            (0x1 << 3)
  99 #define MR1_PARITY_OFF              (0x2 << 3)
 100 #define MR1_PARITY_SPECIAL          (0x3 << 3)
 101 #define MR1_ERROR_CHAR              (0x0 << 5)
 102 #define MR1_ERROR_BLOCK             (0x1 << 5)
 103 #define MR1_RxINT_RxRDY             (0x0 << 6)
 104 #define MR1_RxINT_FFULL             (0x1 << 6)
 105 #define MR1_RxRTS_CONTROL_ON        (0x1 << 7)
 106 #define MR1_RxRTS_CONTROL_OFF       (0x0 << 7)
 107
 108 #define MR2_STOP_BITS_LENGTH_1      (0x7 << 0)
 109 #define MR2_STOP_BITS_LENGTH_2      (0xF << 0)
 110 #define MR2_CTS_ENABLE_TX_ON        (0x1 << 4)
 111 #define MR2_CTS_ENABLE_TX_OFF       (0x0 << 4)
 112 #define MR2_TxRTS_CONTROL_ON        (0x1 << 5)
 113 #define MR2_TxRTS_CONTROL_OFF       (0x0 << 5)
 114 #define MR2_CH_MODE_NORMAL          (0x0 << 6)
 115 #define MR2_CH_MODE_ECHO            (0x1 << 6)
 116 #define MR2_CH_MODE_LOCAL           (0x2 << 6)
 117 #define MR2_CH_MODE_REMOTE          (0x3 << 6)
 118
 119 #define CR_ENABLE_RX                (0x1 << 0)
 120 #define CR_DISABLE_RX               (0x1 << 1)
 121 #define CR_ENABLE_TX                (0x1 << 2)
 122 #define CR_DISABLE_TX               (0x1 << 3)
 123 #define CR_CMD_RESET_MR             (0x1 << 4)
 124 #define CR_CMD_RESET_RX             (0x2 << 4)
 125 #define CR_CMD_RESET_TX             (0x3 << 4)
 126 #define CR_CMD_RESET_ERR_STATUS     (0x4 << 4)
 127 #define CR_CMD_RESET_BREAK_CHANGE   (0x5 << 4)
 128 #define CR_CMD_START_BREAK          (0x6 << 4)
 129 #define CR_CMD_STOP_BREAK           (0x7 << 4)
 130 #define CR_CMD_ASSERT_RTSN          (0x8 << 4)
 131 #define CR_CMD_NEGATE_RTSN          (0x9 << 4)
 132 #define CR_CMD_SET_TIMEOUT_MODE     (0xA << 4)
 133 #define CR_CMD_DISABLE_TIMEOUT_MODE (0xC << 4)
 134
 135 #define SR_RX_READY                 (0x1 << 0)
 136 #define SR_FIFO_FULL                (0x1 << 1)
 137 #define SR_TX_READY                 (0x1 << 2)
 138 #define SR_TX_EMPTY                 (0x1 << 3)
 139 #define SR_OVERRUN_ERROR            (0x1 << 4)
 140 #define SR_PARITY_ERROR             (0x1 << 5)
 141 #define SR_FRAMING_ERROR            (0x1 << 6)
 142 #define SR_RECEIVED_BREAK           (0x1 << 7)
 143
 144 #define SR_ERROR                    (0xF0)
 145
 146 #define ACR_DELTA_IP0_IRQ_EN        (0x1 << 0)
 147 #define ACR_DELTA_IP1_IRQ_EN        (0x1 << 1)
 148 #define ACR_DELTA_IP2_IRQ_EN        (0x1 << 2)
 149 #define ACR_DELTA_IP3_IRQ_EN        (0x1 << 3)
 150 #define ACR_CT_Mask                 (0x7 << 4)
 151 #define ACR_CExt                    (0x0 << 4)
 152 #define ACR_CTxCA                   (0x1 << 4)
 153 #define ACR_CTxCB                   (0x2 << 4)
 154 #define ACR_CClk16                  (0x3 << 4)
 155 #define ACR_TExt                    (0x4 << 4)
 156 #define ACR_TExt16                  (0x5 << 4)
 157 #define ACR_TClk                    (0x6 << 4)
 158 #define ACR_TClk16                  (0x7 << 4)
 159 #define ACR_BRG_SET1                (0x0 << 7)
 160 #define ACR_BRG_SET2                (0x1 << 7)
 161
 162 #define TX_CLK_75                   (0x0 << 0)
 163 #define TX_CLK_110                  (0x1 << 0)
 164 #define TX_CLK_38400                (0x2 << 0)
 165 #define TX_CLK_150                  (0x3 << 0)
 166 #define TX_CLK_300                  (0x4 << 0)
 167 #define TX_CLK_600                  (0x5 << 0)
 168 #define TX_CLK_1200                 (0x6 << 0)
 169 #define TX_CLK_2000                 (0x7 << 0)
 170 #define TX_CLK_2400                 (0x8 << 0)
 171 #define TX_CLK_4800                 (0x9 << 0)
 172 #define TX_CLK_1800                 (0xA << 0)
 173 #define TX_CLK_9600                 (0xB << 0)
 174 #define TX_CLK_19200                (0xC << 0)
 175 #define RX_CLK_75                   (0x0 << 4)
 176 #define RX_CLK_110                  (0x1 << 4)
 177 #define RX_CLK_38400                (0x2 << 4)
 178 #define RX_CLK_150                  (0x3 << 4)
 179 #define RX_CLK_300                  (0x4 << 4)
 180 #define RX_CLK_600                  (0x5 << 4)
 181 #define RX_CLK_1200                 (0x6 << 4)
 182 #define RX_CLK_2000                 (0x7 << 4)
 183 #define RX_CLK_2400                 (0x8 << 4)
 184 #define RX_CLK_4800                 (0x9 << 4)
 185 #define RX_CLK_1800                 (0xA << 4)
 186 #define RX_CLK_9600                 (0xB << 4)
 187 #define RX_CLK_19200                (0xC << 4)
 188
 189 #define OPCR_MPOa_RTSN              (0x0 << 0)
 190 #define OPCR_MPOa_C_TO              (0x1 << 0)
 191 #define OPCR_MPOa_TxC1X             (0x2 << 0)
 192 #define OPCR_MPOa_TxC16X            (0x3 << 0)
 193 #define OPCR_MPOa_RxC1X             (0x4 << 0)
 194 #define OPCR_MPOa_RxC16X            (0x5 << 0)
 195 #define OPCR_MPOa_TxRDY             (0x6 << 0)
 196 #define OPCR_MPOa_RxRDY_FF          (0x7 << 0)
 197
 198 #define OPCR_MPOb_RTSN              (0x0 << 4)
 199 #define OPCR_MPOb_C_TO              (0x1 << 4)
 200 #define OPCR_MPOb_TxC1X             (0x2 << 4)
 201 #define OPCR_MPOb_TxC16X            (0x3 << 4)
 202 #define OPCR_MPOb_RxC1X             (0x4 << 4)
 203 #define OPCR_MPOb_RxC16X            (0x5 << 4)
 204 #define OPCR_MPOb_TxRDY             (0x6 << 4)
 205 #define OPCR_MPOb_RxRDY_FF          (0x7 << 4)
 206
 207 #define OPCR_MPP_INPUT              (0x0 << 7)
 208 #define OPCR_MPP_OUTPUT             (0x1 << 7)
 209
 210 #define IMR_TxRDY_A                 (0x1 << 0)
 211 #define IMR_RxRDY_FFULL_A           (0x1 << 1)
 212 #define IMR_DELTA_BREAK_A           (0x1 << 2)
 213 #define IMR_COUNTER_READY           (0x1 << 3)
 214 #define IMR_TxRDY_B                 (0x1 << 4)
 215 #define IMR_RxRDY_FFULL_B           (0x1 << 5)
 216 #define IMR_DELTA_BREAK_B           (0x1 << 6)
 217 #define IMR_INPUT_PORT_CHANGE       (0x1 << 7)
 218
 219 #define ISR_TxRDY_A                 (0x1 << 0)
 220 #define ISR_RxRDY_FFULL_A           (0x1 << 1)
 221 #define ISR_DELTA_BREAK_A           (0x1 << 2)
 222 #define ISR_COUNTER_READY           (0x1 << 3)
 223 #define ISR_TxRDY_B                 (0x1 << 4)
 224 #define ISR_RxRDY_FFULL_B           (0x1 << 5)
 225 #define ISR_DELTA_BREAK_B           (0x1 << 6)
 226 #define ISR_INPUT_PORT_CHANGE       (0x1 << 7)
 227
 228 #endif /* SCC2698_H_ */