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initial commit with v3.6.7
[linux-3.6.7-moxart.git] / drivers / tty / serial / 8250 / 8250_pci.c
blob6b8fcb48f3fb70a5364b84ca2b42fb2d0799399c
1 /*
2 * Probe module for 8250/16550-type PCI serial ports.
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King, All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
11 */
12 #include <linux/module.h>
13 #include <linux/init.h>
14 #include <linux/pci.h>
15 #include <linux/string.h>
16 #include <linux/kernel.h>
17 #include <linux/slab.h>
18 #include <linux/delay.h>
19 #include <linux/tty.h>
20 #include <linux/serial_reg.h>
21 #include <linux/serial_core.h>
22 #include <linux/8250_pci.h>
23 #include <linux/bitops.h>
24
25 #include <asm/byteorder.h>
26 #include <asm/io.h>
27
28 #include "8250.h"
29
30 #undef SERIAL_DEBUG_PCI
31
32 /*
33 * init function returns:
34 * > 0 - number of ports
35 * = 0 - use board->num_ports
36 * < 0 - error
37 */
38 struct pci_serial_quirk {
39 u32 vendor;
40 u32 device;
41 u32 subvendor;
42 u32 subdevice;
43 int (*probe)(struct pci_dev *dev);
44 int (*init)(struct pci_dev *dev);
45 int (*setup)(struct serial_private *,
46 const struct pciserial_board *,
47 struct uart_port *, int);
48 void (*exit)(struct pci_dev *dev);
49 };
50
51 #define PCI_NUM_BAR_RESOURCES 6
52
53 struct serial_private {
54 struct pci_dev *dev;
55 unsigned int nr;
56 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
57 struct pci_serial_quirk *quirk;
58 int line[0];
59 };
60
61 static int pci_default_setup(struct serial_private*,
62 const struct pciserial_board*, struct uart_port*, int);
63
64 static void moan_device(const char *str, struct pci_dev *dev)
65 {
66 printk(KERN_WARNING
67 "%s: %s\n"
68 "Please send the output of lspci -vv, this\n"
69 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
70 "manufacturer and name of serial board or\n"
71 "modem board to rmk+serial@arm.linux.org.uk.\n",
72 pci_name(dev), str, dev->vendor, dev->device,
73 dev->subsystem_vendor, dev->subsystem_device);
74 }
75
76 static int
77 setup_port(struct serial_private *priv, struct uart_port *port,
78 int bar, int offset, int regshift)
79 {
80 struct pci_dev *dev = priv->dev;
81 unsigned long base, len;
82
83 if (bar >= PCI_NUM_BAR_RESOURCES)
84 return -EINVAL;
85
86 base = pci_resource_start(dev, bar);
87
88 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
89 len = pci_resource_len(dev, bar);
90
91 if (!priv->remapped_bar[bar])
92 priv->remapped_bar[bar] = ioremap_nocache(base, len);
93 if (!priv->remapped_bar[bar])
94 return -ENOMEM;
95
96 port->iotype = UPIO_MEM;
97 port->iobase = 0;
98 port->mapbase = base + offset;
99 port->membase = priv->remapped_bar[bar] + offset;
100 port->regshift = regshift;
101 } else {
102 port->iotype = UPIO_PORT;
103 port->iobase = base + offset;
104 port->mapbase = 0;
105 port->membase = NULL;
106 port->regshift = 0;
107 }
108 return 0;
109 }
110
111 /*
112 * ADDI-DATA GmbH communication cards <info@addi-data.com>
113 */
114 static int addidata_apci7800_setup(struct serial_private *priv,
115 const struct pciserial_board *board,
116 struct uart_port *port, int idx)
117 {
118 unsigned int bar = 0, offset = board->first_offset;
119 bar = FL_GET_BASE(board->flags);
120
121 if (idx < 2) {
122 offset += idx * board->uart_offset;
123 } else if ((idx >= 2) && (idx < 4)) {
124 bar += 1;
125 offset += ((idx - 2) * board->uart_offset);
126 } else if ((idx >= 4) && (idx < 6)) {
127 bar += 2;
128 offset += ((idx - 4) * board->uart_offset);
129 } else if (idx >= 6) {
130 bar += 3;
131 offset += ((idx - 6) * board->uart_offset);
132 }
133
134 return setup_port(priv, port, bar, offset, board->reg_shift);
135 }
136
137 /*
138 * AFAVLAB uses a different mixture of BARs and offsets
139 * Not that ugly ;) -- HW
140 */
141 static int
142 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
143 struct uart_port *port, int idx)
144 {
145 unsigned int bar, offset = board->first_offset;
146
147 bar = FL_GET_BASE(board->flags);
148 if (idx < 4)
149 bar += idx;
150 else {
151 bar = 4;
152 offset += (idx - 4) * board->uart_offset;
153 }
154
155 return setup_port(priv, port, bar, offset, board->reg_shift);
156 }
157
158 /*
159 * HP's Remote Management Console. The Diva chip came in several
160 * different versions. N-class, L2000 and A500 have two Diva chips, each
161 * with 3 UARTs (the third UART on the second chip is unused). Superdome
162 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
163 * one Diva chip, but it has been expanded to 5 UARTs.
164 */
165 static int pci_hp_diva_init(struct pci_dev *dev)
166 {
167 int rc = 0;
168
169 switch (dev->subsystem_device) {
170 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
171 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
172 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
173 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
174 rc = 3;
175 break;
176 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
177 rc = 2;
178 break;
179 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
180 rc = 4;
181 break;
182 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
183 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
184 rc = 1;
185 break;
186 }
187
188 return rc;
189 }
190
191 /*
192 * HP's Diva chip puts the 4th/5th serial port further out, and
193 * some serial ports are supposed to be hidden on certain models.
194 */
195 static int
196 pci_hp_diva_setup(struct serial_private *priv,
197 const struct pciserial_board *board,
198 struct uart_port *port, int idx)
199 {
200 unsigned int offset = board->first_offset;
201 unsigned int bar = FL_GET_BASE(board->flags);
202
203 switch (priv->dev->subsystem_device) {
204 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
205 if (idx == 3)
206 idx++;
207 break;
208 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
209 if (idx > 0)
210 idx++;
211 if (idx > 2)
212 idx++;
213 break;
214 }
215 if (idx > 2)
216 offset = 0x18;
217
218 offset += idx * board->uart_offset;
219
220 return setup_port(priv, port, bar, offset, board->reg_shift);
221 }
222
223 /*
224 * Added for EKF Intel i960 serial boards
225 */
226 static int pci_inteli960ni_init(struct pci_dev *dev)
227 {
228 unsigned long oldval;
229
230 if (!(dev->subsystem_device & 0x1000))
231 return -ENODEV;
232
233 /* is firmware started? */
234 pci_read_config_dword(dev, 0x44, (void *)&oldval);
235 if (oldval == 0x00001000L) { /* RESET value */
236 printk(KERN_DEBUG "Local i960 firmware missing");
237 return -ENODEV;
238 }
239 return 0;
240 }
241
242 /*
243 * Some PCI serial cards using the PLX 9050 PCI interface chip require
244 * that the card interrupt be explicitly enabled or disabled. This
245 * seems to be mainly needed on card using the PLX which also use I/O
246 * mapped memory.
247 */
248 static int pci_plx9050_init(struct pci_dev *dev)
249 {
250 u8 irq_config;
251 void __iomem *p;
252
253 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
254 moan_device("no memory in bar 0", dev);
255 return 0;
256 }
257
258 irq_config = 0x41;
259 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
260 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
261 irq_config = 0x43;
262
263 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
264 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
265 /*
266 * As the megawolf cards have the int pins active
267 * high, and have 2 UART chips, both ints must be
268 * enabled on the 9050. Also, the UARTS are set in
269 * 16450 mode by default, so we have to enable the
270 * 16C950 'enhanced' mode so that we can use the
271 * deep FIFOs
272 */
273 irq_config = 0x5b;
274 /*
275 * enable/disable interrupts
276 */
277 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
278 if (p == NULL)
279 return -ENOMEM;
280 writel(irq_config, p + 0x4c);
281
282 /*
283 * Read the register back to ensure that it took effect.
284 */
285 readl(p + 0x4c);
286 iounmap(p);
287
288 return 0;
289 }
290
291 static void __devexit pci_plx9050_exit(struct pci_dev *dev)
292 {
293 u8 __iomem *p;
294
295 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
296 return;
297
298 /*
299 * disable interrupts
300 */
301 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
302 if (p != NULL) {
303 writel(0, p + 0x4c);
304
305 /*
306 * Read the register back to ensure that it took effect.
307 */
308 readl(p + 0x4c);
309 iounmap(p);
310 }
311 }
312
313 #define NI8420_INT_ENABLE_REG 0x38
314 #define NI8420_INT_ENABLE_BIT 0x2000
315
316 static void __devexit pci_ni8420_exit(struct pci_dev *dev)
317 {
318 void __iomem *p;
319 unsigned long base, len;
320 unsigned int bar = 0;
321
322 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
323 moan_device("no memory in bar", dev);
324 return;
325 }
326
327 base = pci_resource_start(dev, bar);
328 len = pci_resource_len(dev, bar);
329 p = ioremap_nocache(base, len);
330 if (p == NULL)
331 return;
332
333 /* Disable the CPU Interrupt */
334 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
335 p + NI8420_INT_ENABLE_REG);
336 iounmap(p);
337 }
338
339
340 /* MITE registers */
341 #define MITE_IOWBSR1 0xc4
342 #define MITE_IOWCR1 0xf4
343 #define MITE_LCIMR1 0x08
344 #define MITE_LCIMR2 0x10
345
346 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
347
348 static void __devexit pci_ni8430_exit(struct pci_dev *dev)
349 {
350 void __iomem *p;
351 unsigned long base, len;
352 unsigned int bar = 0;
353
354 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
355 moan_device("no memory in bar", dev);
356 return;
357 }
358
359 base = pci_resource_start(dev, bar);
360 len = pci_resource_len(dev, bar);
361 p = ioremap_nocache(base, len);
362 if (p == NULL)
363 return;
364
365 /* Disable the CPU Interrupt */
366 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
367 iounmap(p);
368 }
369
370 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
371 static int
372 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
373 struct uart_port *port, int idx)
374 {
375 unsigned int bar, offset = board->first_offset;
376
377 bar = 0;
378
379 if (idx < 4) {
380 /* first four channels map to 0, 0x100, 0x200, 0x300 */
381 offset += idx * board->uart_offset;
382 } else if (idx < 8) {
383 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
384 offset += idx * board->uart_offset + 0xC00;
385 } else /* we have only 8 ports on PMC-OCTALPRO */
386 return 1;
387
388 return setup_port(priv, port, bar, offset, board->reg_shift);
389 }
390
391 /*
392 * This does initialization for PMC OCTALPRO cards:
393 * maps the device memory, resets the UARTs (needed, bc
394 * if the module is removed and inserted again, the card
395 * is in the sleep mode) and enables global interrupt.
396 */
397
398 /* global control register offset for SBS PMC-OctalPro */
399 #define OCT_REG_CR_OFF 0x500
400
401 static int sbs_init(struct pci_dev *dev)
402 {
403 u8 __iomem *p;
404
405 p = pci_ioremap_bar(dev, 0);
406
407 if (p == NULL)
408 return -ENOMEM;
409 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
410 writeb(0x10, p + OCT_REG_CR_OFF);
411 udelay(50);
412 writeb(0x0, p + OCT_REG_CR_OFF);
413
414 /* Set bit-2 (INTENABLE) of Control Register */
415 writeb(0x4, p + OCT_REG_CR_OFF);
416 iounmap(p);
417
418 return 0;
419 }
420
421 /*
422 * Disables the global interrupt of PMC-OctalPro
423 */
424
425 static void __devexit sbs_exit(struct pci_dev *dev)
426 {
427 u8 __iomem *p;
428
429 p = pci_ioremap_bar(dev, 0);
430 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
431 if (p != NULL)
432 writeb(0, p + OCT_REG_CR_OFF);
433 iounmap(p);
434 }
435
436 /*
437 * SIIG serial cards have an PCI interface chip which also controls
438 * the UART clocking frequency. Each UART can be clocked independently
439 * (except cards equipped with 4 UARTs) and initial clocking settings
440 * are stored in the EEPROM chip. It can cause problems because this
441 * version of serial driver doesn't support differently clocked UART's
442 * on single PCI card. To prevent this, initialization functions set
443 * high frequency clocking for all UART's on given card. It is safe (I
444 * hope) because it doesn't touch EEPROM settings to prevent conflicts
445 * with other OSes (like M$ DOS).
446 *
447 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
448 *
449 * There is two family of SIIG serial cards with different PCI
450 * interface chip and different configuration methods:
451 * - 10x cards have control registers in IO and/or memory space;
452 * - 20x cards have control registers in standard PCI configuration space.
453 *
454 * Note: all 10x cards have PCI device ids 0x10..
455 * all 20x cards have PCI device ids 0x20..
456 *
457 * There are also Quartet Serial cards which use Oxford Semiconductor
458 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
459 *
460 * Note: some SIIG cards are probed by the parport_serial object.
461 */
462
463 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
464 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
465
466 static int pci_siig10x_init(struct pci_dev *dev)
467 {
468 u16 data;
469 void __iomem *p;
470
471 switch (dev->device & 0xfff8) {
472 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
473 data = 0xffdf;
474 break;
475 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
476 data = 0xf7ff;
477 break;
478 default: /* 1S1P, 4S */
479 data = 0xfffb;
480 break;
481 }
482
483 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
484 if (p == NULL)
485 return -ENOMEM;
486
487 writew(readw(p + 0x28) & data, p + 0x28);
488 readw(p + 0x28);
489 iounmap(p);
490 return 0;
491 }
492
493 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
494 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
495
496 static int pci_siig20x_init(struct pci_dev *dev)
497 {
498 u8 data;
499
500 /* Change clock frequency for the first UART. */
501 pci_read_config_byte(dev, 0x6f, &data);
502 pci_write_config_byte(dev, 0x6f, data & 0xef);
503
504 /* If this card has 2 UART, we have to do the same with second UART. */
505 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
506 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
507 pci_read_config_byte(dev, 0x73, &data);
508 pci_write_config_byte(dev, 0x73, data & 0xef);
509 }
510 return 0;
511 }
512
513 static int pci_siig_init(struct pci_dev *dev)
514 {
515 unsigned int type = dev->device & 0xff00;
516
517 if (type == 0x1000)
518 return pci_siig10x_init(dev);
519 else if (type == 0x2000)
520 return pci_siig20x_init(dev);
521
522 moan_device("Unknown SIIG card", dev);
523 return -ENODEV;
524 }
525
526 static int pci_siig_setup(struct serial_private *priv,
527 const struct pciserial_board *board,
528 struct uart_port *port, int idx)
529 {
530 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
531
532 if (idx > 3) {
533 bar = 4;
534 offset = (idx - 4) * 8;
535 }
536
537 return setup_port(priv, port, bar, offset, 0);
538 }
539
540 /*
541 * Timedia has an explosion of boards, and to avoid the PCI table from
542 * growing *huge*, we use this function to collapse some 70 entries
543 * in the PCI table into one, for sanity's and compactness's sake.
544 */
545 static const unsigned short timedia_single_port[] = {
546 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
547 };
548
549 static const unsigned short timedia_dual_port[] = {
550 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
551 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
552 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
553 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
554 0xD079, 0
555 };
556
557 static const unsigned short timedia_quad_port[] = {
558 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
559 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
560 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
561 0xB157, 0
562 };
563
564 static const unsigned short timedia_eight_port[] = {
565 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
566 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
567 };
568
569 static const struct timedia_struct {
570 int num;
571 const unsigned short *ids;
572 } timedia_data[] = {
573 { 1, timedia_single_port },
574 { 2, timedia_dual_port },
575 { 4, timedia_quad_port },
576 { 8, timedia_eight_port }
577 };
578
579 /*
580 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
581 * listing them individually, this driver merely grabs them all with
582 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
583 * and should be left free to be claimed by parport_serial instead.
584 */
585 static int pci_timedia_probe(struct pci_dev *dev)
586 {
587 /*
588 * Check the third digit of the subdevice ID
589 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
590 */
591 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
592 dev_info(&dev->dev,
593 "ignoring Timedia subdevice %04x for parport_serial\n",
594 dev->subsystem_device);
595 return -ENODEV;
596 }
597
598 return 0;
599 }
600
601 static int pci_timedia_init(struct pci_dev *dev)
602 {
603 const unsigned short *ids;
604 int i, j;
605
606 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
607 ids = timedia_data[i].ids;
608 for (j = 0; ids[j]; j++)
609 if (dev->subsystem_device == ids[j])
610 return timedia_data[i].num;
611 }
612 return 0;
613 }
614
615 /*
616 * Timedia/SUNIX uses a mixture of BARs and offsets
617 * Ugh, this is ugly as all hell --- TYT
618 */
619 static int
620 pci_timedia_setup(struct serial_private *priv,
621 const struct pciserial_board *board,
622 struct uart_port *port, int idx)
623 {
624 unsigned int bar = 0, offset = board->first_offset;
625
626 switch (idx) {
627 case 0:
628 bar = 0;
629 break;
630 case 1:
631 offset = board->uart_offset;
632 bar = 0;
633 break;
634 case 2:
635 bar = 1;
636 break;
637 case 3:
638 offset = board->uart_offset;
639 /* FALLTHROUGH */
640 case 4: /* BAR 2 */
641 case 5: /* BAR 3 */
642 case 6: /* BAR 4 */
643 case 7: /* BAR 5 */
644 bar = idx - 2;
645 }
646
647 return setup_port(priv, port, bar, offset, board->reg_shift);
648 }
649
650 /*
651 * Some Titan cards are also a little weird
652 */
653 static int
654 titan_400l_800l_setup(struct serial_private *priv,
655 const struct pciserial_board *board,
656 struct uart_port *port, int idx)
657 {
658 unsigned int bar, offset = board->first_offset;
659
660 switch (idx) {
661 case 0:
662 bar = 1;
663 break;
664 case 1:
665 bar = 2;
666 break;
667 default:
668 bar = 4;
669 offset = (idx - 2) * board->uart_offset;
670 }
671
672 return setup_port(priv, port, bar, offset, board->reg_shift);
673 }
674
675 static int pci_xircom_init(struct pci_dev *dev)
676 {
677 msleep(100);
678 return 0;
679 }
680
681 static int pci_ni8420_init(struct pci_dev *dev)
682 {
683 void __iomem *p;
684 unsigned long base, len;
685 unsigned int bar = 0;
686
687 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
688 moan_device("no memory in bar", dev);
689 return 0;
690 }
691
692 base = pci_resource_start(dev, bar);
693 len = pci_resource_len(dev, bar);
694 p = ioremap_nocache(base, len);
695 if (p == NULL)
696 return -ENOMEM;
697
698 /* Enable CPU Interrupt */
699 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
700 p + NI8420_INT_ENABLE_REG);
701
702 iounmap(p);
703 return 0;
704 }
705
706 #define MITE_IOWBSR1_WSIZE 0xa
707 #define MITE_IOWBSR1_WIN_OFFSET 0x800
708 #define MITE_IOWBSR1_WENAB (1 << 7)
709 #define MITE_LCIMR1_IO_IE_0 (1 << 24)
710 #define MITE_LCIMR2_SET_CPU_IE (1 << 31)
711 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
712
713 static int pci_ni8430_init(struct pci_dev *dev)
714 {
715 void __iomem *p;
716 unsigned long base, len;
717 u32 device_window;
718 unsigned int bar = 0;
719
720 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
721 moan_device("no memory in bar", dev);
722 return 0;
723 }
724
725 base = pci_resource_start(dev, bar);
726 len = pci_resource_len(dev, bar);
727 p = ioremap_nocache(base, len);
728 if (p == NULL)
729 return -ENOMEM;
730
731 /* Set device window address and size in BAR0 */
732 device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
733 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
734 writel(device_window, p + MITE_IOWBSR1);
735
736 /* Set window access to go to RAMSEL IO address space */
737 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
738 p + MITE_IOWCR1);
739
740 /* Enable IO Bus Interrupt 0 */
741 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
742
743 /* Enable CPU Interrupt */
744 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
745
746 iounmap(p);
747 return 0;
748 }
749
750 /* UART Port Control Register */
751 #define NI8430_PORTCON 0x0f
752 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
753
754 static int
755 pci_ni8430_setup(struct serial_private *priv,
756 const struct pciserial_board *board,
757 struct uart_port *port, int idx)
758 {
759 void __iomem *p;
760 unsigned long base, len;
761 unsigned int bar, offset = board->first_offset;
762
763 if (idx >= board->num_ports)
764 return 1;
765
766 bar = FL_GET_BASE(board->flags);
767 offset += idx * board->uart_offset;
768
769 base = pci_resource_start(priv->dev, bar);
770 len = pci_resource_len(priv->dev, bar);
771 p = ioremap_nocache(base, len);
772
773 /* enable the transceiver */
774 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
775 p + offset + NI8430_PORTCON);
776
777 iounmap(p);
778
779 return setup_port(priv, port, bar, offset, board->reg_shift);
780 }
781
782 static int pci_netmos_9900_setup(struct serial_private *priv,
783 const struct pciserial_board *board,
784 struct uart_port *port, int idx)
785 {
786 unsigned int bar;
787
788 if ((priv->dev->subsystem_device & 0xff00) == 0x3000) {
789 /* netmos apparently orders BARs by datasheet layout, so serial
790 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
791 */
792 bar = 3 * idx;
793
794 return setup_port(priv, port, bar, 0, board->reg_shift);
795 } else {
796 return pci_default_setup(priv, board, port, idx);
797 }
798 }
799
800 /* the 99xx series comes with a range of device IDs and a variety
801 * of capabilities:
802 *
803 * 9900 has varying capabilities and can cascade to sub-controllers
804 * (cascading should be purely internal)
805 * 9904 is hardwired with 4 serial ports
806 * 9912 and 9922 are hardwired with 2 serial ports
807 */
808 static int pci_netmos_9900_numports(struct pci_dev *dev)
809 {
810 unsigned int c = dev->class;
811 unsigned int pi;
812 unsigned short sub_serports;
813
814 pi = (c & 0xff);
815
816 if (pi == 2) {
817 return 1;
818 } else if ((pi == 0) &&
819 (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
820 /* two possibilities: 0x30ps encodes number of parallel and
821 * serial ports, or 0x1000 indicates *something*. This is not
822 * immediately obvious, since the 2s1p+4s configuration seems
823 * to offer all functionality on functions 0..2, while still
824 * advertising the same function 3 as the 4s+2s1p config.
825 */
826 sub_serports = dev->subsystem_device & 0xf;
827 if (sub_serports > 0) {
828 return sub_serports;
829 } else {
830 printk(KERN_NOTICE "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
831 return 0;
832 }
833 }
834
835 moan_device("unknown NetMos/Mostech program interface", dev);
836 return 0;
837 }
838
839 static int pci_netmos_init(struct pci_dev *dev)
840 {
841 /* subdevice 0x00PS means <P> parallel, <S> serial */
842 unsigned int num_serial = dev->subsystem_device & 0xf;
843
844 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
845 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
846 return 0;
847
848 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
849 dev->subsystem_device == 0x0299)
850 return 0;
851
852 switch (dev->device) { /* FALLTHROUGH on all */
853 case PCI_DEVICE_ID_NETMOS_9904:
854 case PCI_DEVICE_ID_NETMOS_9912:
855 case PCI_DEVICE_ID_NETMOS_9922:
856 case PCI_DEVICE_ID_NETMOS_9900:
857 num_serial = pci_netmos_9900_numports(dev);
858 break;
859
860 default:
861 if (num_serial == 0 ) {
862 moan_device("unknown NetMos/Mostech device", dev);
863 }
864 }
865
866 if (num_serial == 0)
867 return -ENODEV;
868
869 return num_serial;
870 }
871
872 /*
873 * These chips are available with optionally one parallel port and up to
874 * two serial ports. Unfortunately they all have the same product id.
875 *
876 * Basic configuration is done over a region of 32 I/O ports. The base
877 * ioport is called INTA or INTC, depending on docs/other drivers.
878 *
879 * The region of the 32 I/O ports is configured in POSIO0R...
880 */
881
882 /* registers */
883 #define ITE_887x_MISCR 0x9c
884 #define ITE_887x_INTCBAR 0x78
885 #define ITE_887x_UARTBAR 0x7c
886 #define ITE_887x_PS0BAR 0x10
887 #define ITE_887x_POSIO0 0x60
888
889 /* I/O space size */
890 #define ITE_887x_IOSIZE 32
891 /* I/O space size (bits 26-24; 8 bytes = 011b) */
892 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
893 /* I/O space size (bits 26-24; 32 bytes = 101b) */
894 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
895 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
896 #define ITE_887x_POSIO_SPEED (3 << 29)
897 /* enable IO_Space bit */
898 #define ITE_887x_POSIO_ENABLE (1 << 31)
899
900 static int pci_ite887x_init(struct pci_dev *dev)
901 {
902 /* inta_addr are the configuration addresses of the ITE */
903 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
904 0x200, 0x280, 0 };
905 int ret, i, type;
906 struct resource *iobase = NULL;
907 u32 miscr, uartbar, ioport;
908
909 /* search for the base-ioport */
910 i = 0;
911 while (inta_addr[i] && iobase == NULL) {
912 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
913 "ite887x");
914 if (iobase != NULL) {
915 /* write POSIO0R - speed | size | ioport */
916 pci_write_config_dword(dev, ITE_887x_POSIO0,
917 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
918 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
919 /* write INTCBAR - ioport */
920 pci_write_config_dword(dev, ITE_887x_INTCBAR,
921 inta_addr[i]);
922 ret = inb(inta_addr[i]);
923 if (ret != 0xff) {
924 /* ioport connected */
925 break;
926 }
927 release_region(iobase->start, ITE_887x_IOSIZE);
928 iobase = NULL;
929 }
930 i++;
931 }
932
933 if (!inta_addr[i]) {
934 printk(KERN_ERR "ite887x: could not find iobase\n");
935 return -ENODEV;
936 }
937
938 /* start of undocumented type checking (see parport_pc.c) */
939 type = inb(iobase->start + 0x18) & 0x0f;
940
941 switch (type) {
942 case 0x2: /* ITE8871 (1P) */
943 case 0xa: /* ITE8875 (1P) */
944 ret = 0;
945 break;
946 case 0xe: /* ITE8872 (2S1P) */
947 ret = 2;
948 break;
949 case 0x6: /* ITE8873 (1S) */
950 ret = 1;
951 break;
952 case 0x8: /* ITE8874 (2S) */
953 ret = 2;
954 break;
955 default:
956 moan_device("Unknown ITE887x", dev);
957 ret = -ENODEV;
958 }
959
960 /* configure all serial ports */
961 for (i = 0; i < ret; i++) {
962 /* read the I/O port from the device */
963 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
964 &ioport);
965 ioport &= 0x0000FF00; /* the actual base address */
966 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
967 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
968 ITE_887x_POSIO_IOSIZE_8 | ioport);
969
970 /* write the ioport to the UARTBAR */
971 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
972 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
973 uartbar |= (ioport << (16 * i)); /* set the ioport */
974 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
975
976 /* get current config */
977 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
978 /* disable interrupts (UARTx_Routing[3:0]) */
979 miscr &= ~(0xf << (12 - 4 * i));
980 /* activate the UART (UARTx_En) */
981 miscr |= 1 << (23 - i);
982 /* write new config with activated UART */
983 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
984 }
985
986 if (ret <= 0) {
987 /* the device has no UARTs if we get here */
988 release_region(iobase->start, ITE_887x_IOSIZE);
989 }
990
991 return ret;
992 }
993
994 static void __devexit pci_ite887x_exit(struct pci_dev *dev)
995 {
996 u32 ioport;
997 /* the ioport is bit 0-15 in POSIO0R */
998 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
999 ioport &= 0xffff;
1000 release_region(ioport, ITE_887x_IOSIZE);
1001 }
1002
1003 /*
1004 * Oxford Semiconductor Inc.
1005 * Check that device is part of the Tornado range of devices, then determine
1006 * the number of ports available on the device.
1007 */
1008 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1009 {
1010 u8 __iomem *p;
1011 unsigned long deviceID;
1012 unsigned int number_uarts = 0;
1013
1014 /* OxSemi Tornado devices are all 0xCxxx */
1015 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1016 (dev->device & 0xF000) != 0xC000)
1017 return 0;
1018
1019 p = pci_iomap(dev, 0, 5);
1020 if (p == NULL)
1021 return -ENOMEM;
1022
1023 deviceID = ioread32(p);
1024 /* Tornado device */
1025 if (deviceID == 0x07000200) {
1026 number_uarts = ioread8(p + 4);
1027 printk(KERN_DEBUG
1028 "%d ports detected on Oxford PCI Express device\n",
1029 number_uarts);
1030 }
1031 pci_iounmap(dev, p);
1032 return number_uarts;
1033 }
1034
1035 static int
1036 pci_default_setup(struct serial_private *priv,
1037 const struct pciserial_board *board,
1038 struct uart_port *port, int idx)
1039 {
1040 unsigned int bar, offset = board->first_offset, maxnr;
1041
1042 bar = FL_GET_BASE(board->flags);
1043 if (board->flags & FL_BASE_BARS)
1044 bar += idx;
1045 else
1046 offset += idx * board->uart_offset;
1047
1048 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1049 (board->reg_shift + 3);
1050
1051 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1052 return 1;
1053
1054 return setup_port(priv, port, bar, offset, board->reg_shift);
1055 }
1056
1057 static int
1058 ce4100_serial_setup(struct serial_private *priv,
1059 const struct pciserial_board *board,
1060 struct uart_port *port, int idx)
1061 {
1062 int ret;
1063
1064 ret = setup_port(priv, port, 0, 0, board->reg_shift);
1065 port->iotype = UPIO_MEM32;
1066 port->type = PORT_XSCALE;
1067 port->flags = (port->flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1068 port->regshift = 2;
1069
1070 return ret;
1071 }
1072
1073 static int
1074 pci_omegapci_setup(struct serial_private *priv,
1075 const struct pciserial_board *board,
1076 struct uart_port *port, int idx)
1077 {
1078 return setup_port(priv, port, 2, idx * 8, 0);
1079 }
1080
1081 static int skip_tx_en_setup(struct serial_private *priv,
1082 const struct pciserial_board *board,
1083 struct uart_port *port, int idx)
1084 {
1085 port->flags |= UPF_NO_TXEN_TEST;
1086 printk(KERN_DEBUG "serial8250: skipping TxEn test for device "
1087 "[%04x:%04x] subsystem [%04x:%04x]\n",
1088 priv->dev->vendor,
1089 priv->dev->device,
1090 priv->dev->subsystem_vendor,
1091 priv->dev->subsystem_device);
1092
1093 return pci_default_setup(priv, board, port, idx);
1094 }
1095
1096 static void kt_handle_break(struct uart_port *p)
1097 {
1098 struct uart_8250_port *up =
1099 container_of(p, struct uart_8250_port, port);
1100 /*
1101 * On receipt of a BI, serial device in Intel ME (Intel
1102 * management engine) needs to have its fifos cleared for sane
1103 * SOL (Serial Over Lan) output.
1104 */
1105 serial8250_clear_and_reinit_fifos(up);
1106 }
1107
1108 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1109 {
1110 struct uart_8250_port *up =
1111 container_of(p, struct uart_8250_port, port);
1112 unsigned int val;
1113
1114 /*
1115 * When the Intel ME (management engine) gets reset its serial
1116 * port registers could return 0 momentarily. Functions like
1117 * serial8250_console_write, read and save the IER, perform
1118 * some operation and then restore it. In order to avoid
1119 * setting IER register inadvertently to 0, if the value read
1120 * is 0, double check with ier value in uart_8250_port and use
1121 * that instead. up->ier should be the same value as what is
1122 * currently configured.
1123 */
1124 val = inb(p->iobase + offset);
1125 if (offset == UART_IER) {
1126 if (val == 0)
1127 val = up->ier;
1128 }
1129 return val;
1130 }
1131
1132 static int kt_serial_setup(struct serial_private *priv,
1133 const struct pciserial_board *board,
1134 struct uart_port *port, int idx)
1135 {
1136 port->flags |= UPF_BUG_THRE;
1137 port->serial_in = kt_serial_in;
1138 port->handle_break = kt_handle_break;
1139 return skip_tx_en_setup(priv, board, port, idx);
1140 }
1141
1142 static int pci_eg20t_init(struct pci_dev *dev)
1143 {
1144 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1145 return -ENODEV;
1146 #else
1147 return 0;
1148 #endif
1149 }
1150
1151 static int
1152 pci_xr17c154_setup(struct serial_private *priv,
1153 const struct pciserial_board *board,
1154 struct uart_port *port, int idx)
1155 {
1156 port->flags |= UPF_EXAR_EFR;
1157 return pci_default_setup(priv, board, port, idx);
1158 }
1159
1160 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1161 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1162 #define PCI_DEVICE_ID_OCTPRO 0x0001
1163 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
1164 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
1165 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
1166 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
1167 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
1168 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
1169 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
1170 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1171 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1172 #define PCI_DEVICE_ID_TITAN_200I 0x8028
1173 #define PCI_DEVICE_ID_TITAN_400I 0x8048
1174 #define PCI_DEVICE_ID_TITAN_800I 0x8088
1175 #define PCI_DEVICE_ID_TITAN_800EH 0xA007
1176 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1177 #define PCI_DEVICE_ID_TITAN_400EH 0xA009
1178 #define PCI_DEVICE_ID_TITAN_100E 0xA010
1179 #define PCI_DEVICE_ID_TITAN_200E 0xA012
1180 #define PCI_DEVICE_ID_TITAN_400E 0xA013
1181 #define PCI_DEVICE_ID_TITAN_800E 0xA014
1182 #define PCI_DEVICE_ID_TITAN_200EI 0xA016
1183 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017
1184 #define PCI_DEVICE_ID_TITAN_400V3 0xA310
1185 #define PCI_DEVICE_ID_TITAN_410V3 0xA312
1186 #define PCI_DEVICE_ID_TITAN_800V3 0xA314
1187 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315
1188 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
1189 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
1190 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
1191 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1192
1193 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1194 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1195
1196 /*
1197 * Master list of serial port init/setup/exit quirks.
1198 * This does not describe the general nature of the port.
1199 * (ie, baud base, number and location of ports, etc)
1200 *
1201 * This list is ordered alphabetically by vendor then device.
1202 * Specific entries must come before more generic entries.
1203 */
1204 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1205 /*
1206 * ADDI-DATA GmbH communication cards <info@addi-data.com>
1207 */
1208 {
1209 .vendor = PCI_VENDOR_ID_ADDIDATA_OLD,
1210 .device = PCI_DEVICE_ID_ADDIDATA_APCI7800,
1211 .subvendor = PCI_ANY_ID,
1212 .subdevice = PCI_ANY_ID,
1213 .setup = addidata_apci7800_setup,
1214 },
1215 /*
1216 * AFAVLAB cards - these may be called via parport_serial
1217 * It is not clear whether this applies to all products.
1218 */
1219 {
1220 .vendor = PCI_VENDOR_ID_AFAVLAB,
1221 .device = PCI_ANY_ID,
1222 .subvendor = PCI_ANY_ID,
1223 .subdevice = PCI_ANY_ID,
1224 .setup = afavlab_setup,
1225 },
1226 /*
1227 * HP Diva
1228 */
1229 {
1230 .vendor = PCI_VENDOR_ID_HP,
1231 .device = PCI_DEVICE_ID_HP_DIVA,
1232 .subvendor = PCI_ANY_ID,
1233 .subdevice = PCI_ANY_ID,
1234 .init = pci_hp_diva_init,
1235 .setup = pci_hp_diva_setup,
1236 },
1237 /*
1238 * Intel
1239 */
1240 {
1241 .vendor = PCI_VENDOR_ID_INTEL,
1242 .device = PCI_DEVICE_ID_INTEL_80960_RP,
1243 .subvendor = 0xe4bf,
1244 .subdevice = PCI_ANY_ID,
1245 .init = pci_inteli960ni_init,
1246 .setup = pci_default_setup,
1247 },
1248 {
1249 .vendor = PCI_VENDOR_ID_INTEL,
1250 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
1251 .subvendor = PCI_ANY_ID,
1252 .subdevice = PCI_ANY_ID,
1253 .setup = skip_tx_en_setup,
1254 },
1255 {
1256 .vendor = PCI_VENDOR_ID_INTEL,
1257 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
1258 .subvendor = PCI_ANY_ID,
1259 .subdevice = PCI_ANY_ID,
1260 .setup = skip_tx_en_setup,
1261 },
1262 {
1263 .vendor = PCI_VENDOR_ID_INTEL,
1264 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
1265 .subvendor = PCI_ANY_ID,
1266 .subdevice = PCI_ANY_ID,
1267 .setup = skip_tx_en_setup,
1268 },
1269 {
1270 .vendor = PCI_VENDOR_ID_INTEL,
1271 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
1272 .subvendor = PCI_ANY_ID,
1273 .subdevice = PCI_ANY_ID,
1274 .setup = ce4100_serial_setup,
1275 },
1276 {
1277 .vendor = PCI_VENDOR_ID_INTEL,
1278 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
1279 .subvendor = PCI_ANY_ID,
1280 .subdevice = PCI_ANY_ID,
1281 .setup = kt_serial_setup,
1282 },
1283 /*
1284 * ITE
1285 */
1286 {
1287 .vendor = PCI_VENDOR_ID_ITE,
1288 .device = PCI_DEVICE_ID_ITE_8872,
1289 .subvendor = PCI_ANY_ID,
1290 .subdevice = PCI_ANY_ID,
1291 .init = pci_ite887x_init,
1292 .setup = pci_default_setup,
1293 .exit = __devexit_p(pci_ite887x_exit),
1294 },
1295 /*
1296 * National Instruments
1297 */
1298 {
1299 .vendor = PCI_VENDOR_ID_NI,
1300 .device = PCI_DEVICE_ID_NI_PCI23216,
1301 .subvendor = PCI_ANY_ID,
1302 .subdevice = PCI_ANY_ID,
1303 .init = pci_ni8420_init,
1304 .setup = pci_default_setup,
1305 .exit = __devexit_p(pci_ni8420_exit),
1306 },
1307 {
1308 .vendor = PCI_VENDOR_ID_NI,
1309 .device = PCI_DEVICE_ID_NI_PCI2328,
1310 .subvendor = PCI_ANY_ID,
1311 .subdevice = PCI_ANY_ID,
1312 .init = pci_ni8420_init,
1313 .setup = pci_default_setup,
1314 .exit = __devexit_p(pci_ni8420_exit),
1315 },
1316 {
1317 .vendor = PCI_VENDOR_ID_NI,
1318 .device = PCI_DEVICE_ID_NI_PCI2324,
1319 .subvendor = PCI_ANY_ID,
1320 .subdevice = PCI_ANY_ID,
1321 .init = pci_ni8420_init,
1322 .setup = pci_default_setup,
1323 .exit = __devexit_p(pci_ni8420_exit),
1324 },
1325 {
1326 .vendor = PCI_VENDOR_ID_NI,
1327 .device = PCI_DEVICE_ID_NI_PCI2322,
1328 .subvendor = PCI_ANY_ID,
1329 .subdevice = PCI_ANY_ID,
1330 .init = pci_ni8420_init,
1331 .setup = pci_default_setup,
1332 .exit = __devexit_p(pci_ni8420_exit),
1333 },
1334 {
1335 .vendor = PCI_VENDOR_ID_NI,
1336 .device = PCI_DEVICE_ID_NI_PCI2324I,
1337 .subvendor = PCI_ANY_ID,
1338 .subdevice = PCI_ANY_ID,
1339 .init = pci_ni8420_init,
1340 .setup = pci_default_setup,
1341 .exit = __devexit_p(pci_ni8420_exit),
1342 },
1343 {
1344 .vendor = PCI_VENDOR_ID_NI,
1345 .device = PCI_DEVICE_ID_NI_PCI2322I,
1346 .subvendor = PCI_ANY_ID,
1347 .subdevice = PCI_ANY_ID,
1348 .init = pci_ni8420_init,
1349 .setup = pci_default_setup,
1350 .exit = __devexit_p(pci_ni8420_exit),
1351 },
1352 {
1353 .vendor = PCI_VENDOR_ID_NI,
1354 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
1355 .subvendor = PCI_ANY_ID,
1356 .subdevice = PCI_ANY_ID,
1357 .init = pci_ni8420_init,
1358 .setup = pci_default_setup,
1359 .exit = __devexit_p(pci_ni8420_exit),
1360 },
1361 {
1362 .vendor = PCI_VENDOR_ID_NI,
1363 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
1364 .subvendor = PCI_ANY_ID,
1365 .subdevice = PCI_ANY_ID,
1366 .init = pci_ni8420_init,
1367 .setup = pci_default_setup,
1368 .exit = __devexit_p(pci_ni8420_exit),
1369 },
1370 {
1371 .vendor = PCI_VENDOR_ID_NI,
1372 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
1373 .subvendor = PCI_ANY_ID,
1374 .subdevice = PCI_ANY_ID,
1375 .init = pci_ni8420_init,
1376 .setup = pci_default_setup,
1377 .exit = __devexit_p(pci_ni8420_exit),
1378 },
1379 {
1380 .vendor = PCI_VENDOR_ID_NI,
1381 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
1382 .subvendor = PCI_ANY_ID,
1383 .subdevice = PCI_ANY_ID,
1384 .init = pci_ni8420_init,
1385 .setup = pci_default_setup,
1386 .exit = __devexit_p(pci_ni8420_exit),
1387 },
1388 {
1389 .vendor = PCI_VENDOR_ID_NI,
1390 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
1391 .subvendor = PCI_ANY_ID,
1392 .subdevice = PCI_ANY_ID,
1393 .init = pci_ni8420_init,
1394 .setup = pci_default_setup,
1395 .exit = __devexit_p(pci_ni8420_exit),
1396 },
1397 {
1398 .vendor = PCI_VENDOR_ID_NI,
1399 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
1400 .subvendor = PCI_ANY_ID,
1401 .subdevice = PCI_ANY_ID,
1402 .init = pci_ni8420_init,
1403 .setup = pci_default_setup,
1404 .exit = __devexit_p(pci_ni8420_exit),
1405 },
1406 {
1407 .vendor = PCI_VENDOR_ID_NI,
1408 .device = PCI_ANY_ID,
1409 .subvendor = PCI_ANY_ID,
1410 .subdevice = PCI_ANY_ID,
1411 .init = pci_ni8430_init,
1412 .setup = pci_ni8430_setup,
1413 .exit = __devexit_p(pci_ni8430_exit),
1414 },
1415 /*
1416 * Panacom
1417 */
1418 {
1419 .vendor = PCI_VENDOR_ID_PANACOM,
1420 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
1421 .subvendor = PCI_ANY_ID,
1422 .subdevice = PCI_ANY_ID,
1423 .init = pci_plx9050_init,
1424 .setup = pci_default_setup,
1425 .exit = __devexit_p(pci_plx9050_exit),
1426 },
1427 {
1428 .vendor = PCI_VENDOR_ID_PANACOM,
1429 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
1430 .subvendor = PCI_ANY_ID,
1431 .subdevice = PCI_ANY_ID,
1432 .init = pci_plx9050_init,
1433 .setup = pci_default_setup,
1434 .exit = __devexit_p(pci_plx9050_exit),
1435 },
1436 /*
1437 * PLX
1438 */
1439 {
1440 .vendor = PCI_VENDOR_ID_PLX,
1441 .device = PCI_DEVICE_ID_PLX_9030,
1442 .subvendor = PCI_SUBVENDOR_ID_PERLE,
1443 .subdevice = PCI_ANY_ID,
1444 .setup = pci_default_setup,
1445 },
1446 {
1447 .vendor = PCI_VENDOR_ID_PLX,
1448 .device = PCI_DEVICE_ID_PLX_9050,
1449 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
1450 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
1451 .init = pci_plx9050_init,
1452 .setup = pci_default_setup,
1453 .exit = __devexit_p(pci_plx9050_exit),
1454 },
1455 {
1456 .vendor = PCI_VENDOR_ID_PLX,
1457 .device = PCI_DEVICE_ID_PLX_9050,
1458 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
1459 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
1460 .init = pci_plx9050_init,
1461 .setup = pci_default_setup,
1462 .exit = __devexit_p(pci_plx9050_exit),
1463 },
1464 {
1465 .vendor = PCI_VENDOR_ID_PLX,
1466 .device = PCI_DEVICE_ID_PLX_9050,
1467 .subvendor = PCI_VENDOR_ID_PLX,
1468 .subdevice = PCI_SUBDEVICE_ID_UNKNOWN_0x1584,
1469 .init = pci_plx9050_init,
1470 .setup = pci_default_setup,
1471 .exit = __devexit_p(pci_plx9050_exit),
1472 },
1473 {
1474 .vendor = PCI_VENDOR_ID_PLX,
1475 .device = PCI_DEVICE_ID_PLX_ROMULUS,
1476 .subvendor = PCI_VENDOR_ID_PLX,
1477 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
1478 .init = pci_plx9050_init,
1479 .setup = pci_default_setup,
1480 .exit = __devexit_p(pci_plx9050_exit),
1481 },
1482 /*
1483 * SBS Technologies, Inc., PMC-OCTALPRO 232
1484 */
1485 {
1486 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1487 .device = PCI_DEVICE_ID_OCTPRO,
1488 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1489 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
1490 .init = sbs_init,
1491 .setup = sbs_setup,
1492 .exit = __devexit_p(sbs_exit),
1493 },
1494 /*
1495 * SBS Technologies, Inc., PMC-OCTALPRO 422
1496 */
1497 {
1498 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1499 .device = PCI_DEVICE_ID_OCTPRO,
1500 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1501 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
1502 .init = sbs_init,
1503 .setup = sbs_setup,
1504 .exit = __devexit_p(sbs_exit),
1505 },
1506 /*
1507 * SBS Technologies, Inc., P-Octal 232
1508 */
1509 {
1510 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1511 .device = PCI_DEVICE_ID_OCTPRO,
1512 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1513 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
1514 .init = sbs_init,
1515 .setup = sbs_setup,
1516 .exit = __devexit_p(sbs_exit),
1517 },
1518 /*
1519 * SBS Technologies, Inc., P-Octal 422
1520 */
1521 {
1522 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1523 .device = PCI_DEVICE_ID_OCTPRO,
1524 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1525 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
1526 .init = sbs_init,
1527 .setup = sbs_setup,
1528 .exit = __devexit_p(sbs_exit),
1529 },
1530 /*
1531 * SIIG cards - these may be called via parport_serial
1532 */
1533 {
1534 .vendor = PCI_VENDOR_ID_SIIG,
1535 .device = PCI_ANY_ID,
1536 .subvendor = PCI_ANY_ID,
1537 .subdevice = PCI_ANY_ID,
1538 .init = pci_siig_init,
1539 .setup = pci_siig_setup,
1540 },
1541 /*
1542 * Titan cards
1543 */
1544 {
1545 .vendor = PCI_VENDOR_ID_TITAN,
1546 .device = PCI_DEVICE_ID_TITAN_400L,
1547 .subvendor = PCI_ANY_ID,
1548 .subdevice = PCI_ANY_ID,
1549 .setup = titan_400l_800l_setup,
1550 },
1551 {
1552 .vendor = PCI_VENDOR_ID_TITAN,
1553 .device = PCI_DEVICE_ID_TITAN_800L,
1554 .subvendor = PCI_ANY_ID,
1555 .subdevice = PCI_ANY_ID,
1556 .setup = titan_400l_800l_setup,
1557 },
1558 /*
1559 * Timedia cards
1560 */
1561 {
1562 .vendor = PCI_VENDOR_ID_TIMEDIA,
1563 .device = PCI_DEVICE_ID_TIMEDIA_1889,
1564 .subvendor = PCI_VENDOR_ID_TIMEDIA,
1565 .subdevice = PCI_ANY_ID,
1566 .probe = pci_timedia_probe,
1567 .init = pci_timedia_init,
1568 .setup = pci_timedia_setup,
1569 },
1570 {
1571 .vendor = PCI_VENDOR_ID_TIMEDIA,
1572 .device = PCI_ANY_ID,
1573 .subvendor = PCI_ANY_ID,
1574 .subdevice = PCI_ANY_ID,
1575 .setup = pci_timedia_setup,
1576 },
1577 /*
1578 * Exar cards
1579 */
1580 {
1581 .vendor = PCI_VENDOR_ID_EXAR,
1582 .device = PCI_DEVICE_ID_EXAR_XR17C152,
1583 .subvendor = PCI_ANY_ID,
1584 .subdevice = PCI_ANY_ID,
1585 .setup = pci_xr17c154_setup,
1586 },
1587 {
1588 .vendor = PCI_VENDOR_ID_EXAR,
1589 .device = PCI_DEVICE_ID_EXAR_XR17C154,
1590 .subvendor = PCI_ANY_ID,
1591 .subdevice = PCI_ANY_ID,
1592 .setup = pci_xr17c154_setup,
1593 },
1594 {
1595 .vendor = PCI_VENDOR_ID_EXAR,
1596 .device = PCI_DEVICE_ID_EXAR_XR17C158,
1597 .subvendor = PCI_ANY_ID,
1598 .subdevice = PCI_ANY_ID,
1599 .setup = pci_xr17c154_setup,
1600 },
1601 /*
1602 * Xircom cards
1603 */
1604 {
1605 .vendor = PCI_VENDOR_ID_XIRCOM,
1606 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
1607 .subvendor = PCI_ANY_ID,
1608 .subdevice = PCI_ANY_ID,
1609 .init = pci_xircom_init,
1610 .setup = pci_default_setup,
1611 },
1612 /*
1613 * Netmos cards - these may be called via parport_serial
1614 */
1615 {
1616 .vendor = PCI_VENDOR_ID_NETMOS,
1617 .device = PCI_ANY_ID,
1618 .subvendor = PCI_ANY_ID,
1619 .subdevice = PCI_ANY_ID,
1620 .init = pci_netmos_init,
1621 .setup = pci_netmos_9900_setup,
1622 },
1623 /*
1624 * For Oxford Semiconductor Tornado based devices
1625 */
1626 {
1627 .vendor = PCI_VENDOR_ID_OXSEMI,
1628 .device = PCI_ANY_ID,
1629 .subvendor = PCI_ANY_ID,
1630 .subdevice = PCI_ANY_ID,
1631 .init = pci_oxsemi_tornado_init,
1632 .setup = pci_default_setup,
1633 },
1634 {
1635 .vendor = PCI_VENDOR_ID_MAINPINE,
1636 .device = PCI_ANY_ID,
1637 .subvendor = PCI_ANY_ID,
1638 .subdevice = PCI_ANY_ID,
1639 .init = pci_oxsemi_tornado_init,
1640 .setup = pci_default_setup,
1641 },
1642 {
1643 .vendor = PCI_VENDOR_ID_DIGI,
1644 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
1645 .subvendor = PCI_SUBVENDOR_ID_IBM,
1646 .subdevice = PCI_ANY_ID,
1647 .init = pci_oxsemi_tornado_init,
1648 .setup = pci_default_setup,
1649 },
1650 {
1651 .vendor = PCI_VENDOR_ID_INTEL,
1652 .device = 0x8811,
1653 .subvendor = PCI_ANY_ID,
1654 .subdevice = PCI_ANY_ID,
1655 .init = pci_eg20t_init,
1656 .setup = pci_default_setup,
1657 },
1658 {
1659 .vendor = PCI_VENDOR_ID_INTEL,
1660 .device = 0x8812,
1661 .subvendor = PCI_ANY_ID,
1662 .subdevice = PCI_ANY_ID,
1663 .init = pci_eg20t_init,
1664 .setup = pci_default_setup,
1665 },
1666 {
1667 .vendor = PCI_VENDOR_ID_INTEL,
1668 .device = 0x8813,
1669 .subvendor = PCI_ANY_ID,
1670 .subdevice = PCI_ANY_ID,
1671 .init = pci_eg20t_init,
1672 .setup = pci_default_setup,
1673 },
1674 {
1675 .vendor = PCI_VENDOR_ID_INTEL,
1676 .device = 0x8814,
1677 .subvendor = PCI_ANY_ID,
1678 .subdevice = PCI_ANY_ID,
1679 .init = pci_eg20t_init,
1680 .setup = pci_default_setup,
1681 },
1682 {
1683 .vendor = 0x10DB,
1684 .device = 0x8027,
1685 .subvendor = PCI_ANY_ID,
1686 .subdevice = PCI_ANY_ID,
1687 .init = pci_eg20t_init,
1688 .setup = pci_default_setup,
1689 },
1690 {
1691 .vendor = 0x10DB,
1692 .device = 0x8028,
1693 .subvendor = PCI_ANY_ID,
1694 .subdevice = PCI_ANY_ID,
1695 .init = pci_eg20t_init,
1696 .setup = pci_default_setup,
1697 },
1698 {
1699 .vendor = 0x10DB,
1700 .device = 0x8029,
1701 .subvendor = PCI_ANY_ID,
1702 .subdevice = PCI_ANY_ID,
1703 .init = pci_eg20t_init,
1704 .setup = pci_default_setup,
1705 },
1706 {
1707 .vendor = 0x10DB,
1708 .device = 0x800C,
1709 .subvendor = PCI_ANY_ID,
1710 .subdevice = PCI_ANY_ID,
1711 .init = pci_eg20t_init,
1712 .setup = pci_default_setup,
1713 },
1714 {
1715 .vendor = 0x10DB,
1716 .device = 0x800D,
1717 .subvendor = PCI_ANY_ID,
1718 .subdevice = PCI_ANY_ID,
1719 .init = pci_eg20t_init,
1720 .setup = pci_default_setup,
1721 },
1722 /*
1723 * Cronyx Omega PCI (PLX-chip based)
1724 */
1725 {
1726 .vendor = PCI_VENDOR_ID_PLX,
1727 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
1728 .subvendor = PCI_ANY_ID,
1729 .subdevice = PCI_ANY_ID,
1730 .setup = pci_omegapci_setup,
1731 },
1732 /*
1733 * Default "match everything" terminator entry
1734 */
1735 {
1736 .vendor = PCI_ANY_ID,
1737 .device = PCI_ANY_ID,
1738 .subvendor = PCI_ANY_ID,
1739 .subdevice = PCI_ANY_ID,
1740 .setup = pci_default_setup,
1741 }
1742 };
1743
1744 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
1745 {
1746 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
1747 }
1748
1749 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
1750 {
1751 struct pci_serial_quirk *quirk;
1752
1753 for (quirk = pci_serial_quirks; ; quirk++)
1754 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
1755 quirk_id_matches(quirk->device, dev->device) &&
1756 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
1757 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
1758 break;
1759 return quirk;
1760 }
1761
1762 static inline int get_pci_irq(struct pci_dev *dev,
1763 const struct pciserial_board *board)
1764 {
1765 if (board->flags & FL_NOIRQ)
1766 return 0;
1767 else
1768 return dev->irq;
1769 }
1770
1771 /*
1772 * This is the configuration table for all of the PCI serial boards
1773 * which we support. It is directly indexed by the pci_board_num_t enum
1774 * value, which is encoded in the pci_device_id PCI probe table's
1775 * driver_data member.
1776 *
1777 * The makeup of these names are:
1778 * pbn_bn{_bt}_n_baud{_offsetinhex}
1779 *
1780 * bn = PCI BAR number
1781 * bt = Index using PCI BARs
1782 * n = number of serial ports
1783 * baud = baud rate
1784 * offsetinhex = offset for each sequential port (in hex)
1785 *
1786 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
1787 *
1788 * Please note: in theory if n = 1, _bt infix should make no difference.
1789 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
1790 */
1791 enum pci_board_num_t {
1792 pbn_default = 0,
1793
1794 pbn_b0_1_115200,
1795 pbn_b0_2_115200,
1796 pbn_b0_4_115200,
1797 pbn_b0_5_115200,
1798 pbn_b0_8_115200,
1799
1800 pbn_b0_1_921600,
1801 pbn_b0_2_921600,
1802 pbn_b0_4_921600,
1803
1804 pbn_b0_2_1130000,
1805
1806 pbn_b0_4_1152000,
1807
1808 pbn_b0_2_1843200,
1809 pbn_b0_4_1843200,
1810
1811 pbn_b0_2_1843200_200,
1812 pbn_b0_4_1843200_200,
1813 pbn_b0_8_1843200_200,
1814
1815 pbn_b0_1_4000000,
1816
1817 pbn_b0_bt_1_115200,
1818 pbn_b0_bt_2_115200,
1819 pbn_b0_bt_4_115200,
1820 pbn_b0_bt_8_115200,
1821
1822 pbn_b0_bt_1_460800,
1823 pbn_b0_bt_2_460800,
1824 pbn_b0_bt_4_460800,
1825
1826 pbn_b0_bt_1_921600,
1827 pbn_b0_bt_2_921600,
1828 pbn_b0_bt_4_921600,
1829 pbn_b0_bt_8_921600,
1830
1831 pbn_b1_1_115200,
1832 pbn_b1_2_115200,
1833 pbn_b1_4_115200,
1834 pbn_b1_8_115200,
1835 pbn_b1_16_115200,
1836
1837 pbn_b1_1_921600,
1838 pbn_b1_2_921600,
1839 pbn_b1_4_921600,
1840 pbn_b1_8_921600,
1841
1842 pbn_b1_2_1250000,
1843
1844 pbn_b1_bt_1_115200,
1845 pbn_b1_bt_2_115200,
1846 pbn_b1_bt_4_115200,
1847
1848 pbn_b1_bt_2_921600,
1849
1850 pbn_b1_1_1382400,
1851 pbn_b1_2_1382400,
1852 pbn_b1_4_1382400,
1853 pbn_b1_8_1382400,
1854
1855 pbn_b2_1_115200,
1856 pbn_b2_2_115200,
1857 pbn_b2_4_115200,
1858 pbn_b2_8_115200,
1859
1860 pbn_b2_1_460800,
1861 pbn_b2_4_460800,
1862 pbn_b2_8_460800,
1863 pbn_b2_16_460800,
1864
1865 pbn_b2_1_921600,
1866 pbn_b2_4_921600,
1867 pbn_b2_8_921600,
1868
1869 pbn_b2_8_1152000,
1870
1871 pbn_b2_bt_1_115200,
1872 pbn_b2_bt_2_115200,
1873 pbn_b2_bt_4_115200,
1874
1875 pbn_b2_bt_2_921600,
1876 pbn_b2_bt_4_921600,
1877
1878 pbn_b3_2_115200,
1879 pbn_b3_4_115200,
1880 pbn_b3_8_115200,
1881
1882 pbn_b4_bt_2_921600,
1883 pbn_b4_bt_4_921600,
1884 pbn_b4_bt_8_921600,
1885
1886 /*
1887 * Board-specific versions.
1888 */
1889 pbn_panacom,
1890 pbn_panacom2,
1891 pbn_panacom4,
1892 pbn_exsys_4055,
1893 pbn_plx_romulus,
1894 pbn_oxsemi,
1895 pbn_oxsemi_1_4000000,
1896 pbn_oxsemi_2_4000000,
1897 pbn_oxsemi_4_4000000,
1898 pbn_oxsemi_8_4000000,
1899 pbn_intel_i960,
1900 pbn_sgi_ioc3,
1901 pbn_computone_4,
1902 pbn_computone_6,
1903 pbn_computone_8,
1904 pbn_sbsxrsio,
1905 pbn_exar_XR17C152,
1906 pbn_exar_XR17C154,
1907 pbn_exar_XR17C158,
1908 pbn_exar_ibm_saturn,
1909 pbn_pasemi_1682M,
1910 pbn_ni8430_2,
1911 pbn_ni8430_4,
1912 pbn_ni8430_8,
1913 pbn_ni8430_16,
1914 pbn_ADDIDATA_PCIe_1_3906250,
1915 pbn_ADDIDATA_PCIe_2_3906250,
1916 pbn_ADDIDATA_PCIe_4_3906250,
1917 pbn_ADDIDATA_PCIe_8_3906250,
1918 pbn_ce4100_1_115200,
1919 pbn_omegapci,
1920 pbn_NETMOS9900_2s_115200,
1921 };
1922
1923 /*
1924 * uart_offset - the space between channels
1925 * reg_shift - describes how the UART registers are mapped
1926 * to PCI memory by the card.
1927 * For example IER register on SBS, Inc. PMC-OctPro is located at
1928 * offset 0x10 from the UART base, while UART_IER is defined as 1
1929 * in include/linux/serial_reg.h,
1930 * see first lines of serial_in() and serial_out() in 8250.c
1931 */
1932
1933 static struct pciserial_board pci_boards[] __devinitdata = {
1934 [pbn_default] = {
1935 .flags = FL_BASE0,
1936 .num_ports = 1,
1937 .base_baud = 115200,
1938 .uart_offset = 8,
1939 },
1940 [pbn_b0_1_115200] = {
1941 .flags = FL_BASE0,
1942 .num_ports = 1,
1943 .base_baud = 115200,
1944 .uart_offset = 8,
1945 },
1946 [pbn_b0_2_115200] = {
1947 .flags = FL_BASE0,
1948 .num_ports = 2,
1949 .base_baud = 115200,
1950 .uart_offset = 8,
1951 },
1952 [pbn_b0_4_115200] = {
1953 .flags = FL_BASE0,
1954 .num_ports = 4,
1955 .base_baud = 115200,
1956 .uart_offset = 8,
1957 },
1958 [pbn_b0_5_115200] = {
1959 .flags = FL_BASE0,
1960 .num_ports = 5,
1961 .base_baud = 115200,
1962 .uart_offset = 8,
1963 },
1964 [pbn_b0_8_115200] = {
1965 .flags = FL_BASE0,
1966 .num_ports = 8,
1967 .base_baud = 115200,
1968 .uart_offset = 8,
1969 },
1970 [pbn_b0_1_921600] = {
1971 .flags = FL_BASE0,
1972 .num_ports = 1,
1973 .base_baud = 921600,
1974 .uart_offset = 8,
1975 },
1976 [pbn_b0_2_921600] = {
1977 .flags = FL_BASE0,
1978 .num_ports = 2,
1979 .base_baud = 921600,
1980 .uart_offset = 8,
1981 },
1982 [pbn_b0_4_921600] = {
1983 .flags = FL_BASE0,
1984 .num_ports = 4,
1985 .base_baud = 921600,
1986 .uart_offset = 8,
1987 },
1988
1989 [pbn_b0_2_1130000] = {
1990 .flags = FL_BASE0,
1991 .num_ports = 2,
1992 .base_baud = 1130000,
1993 .uart_offset = 8,
1994 },
1995
1996 [pbn_b0_4_1152000] = {
1997 .flags = FL_BASE0,
1998 .num_ports = 4,
1999 .base_baud = 1152000,
2000 .uart_offset = 8,
2001 },
2002
2003 [pbn_b0_2_1843200] = {
2004 .flags = FL_BASE0,
2005 .num_ports = 2,
2006 .base_baud = 1843200,
2007 .uart_offset = 8,
2008 },
2009 [pbn_b0_4_1843200] = {
2010 .flags = FL_BASE0,
2011 .num_ports = 4,
2012 .base_baud = 1843200,
2013 .uart_offset = 8,
2014 },
2015
2016 [pbn_b0_2_1843200_200] = {
2017 .flags = FL_BASE0,
2018 .num_ports = 2,
2019 .base_baud = 1843200,
2020 .uart_offset = 0x200,
2021 },
2022 [pbn_b0_4_1843200_200] = {
2023 .flags = FL_BASE0,
2024 .num_ports = 4,
2025 .base_baud = 1843200,
2026 .uart_offset = 0x200,
2027 },
2028 [pbn_b0_8_1843200_200] = {
2029 .flags = FL_BASE0,
2030 .num_ports = 8,
2031 .base_baud = 1843200,
2032 .uart_offset = 0x200,
2033 },
2034 [pbn_b0_1_4000000] = {
2035 .flags = FL_BASE0,
2036 .num_ports = 1,
2037 .base_baud = 4000000,
2038 .uart_offset = 8,
2039 },
2040
2041 [pbn_b0_bt_1_115200] = {
2042 .flags = FL_BASE0|FL_BASE_BARS,
2043 .num_ports = 1,
2044 .base_baud = 115200,
2045 .uart_offset = 8,
2046 },
2047 [pbn_b0_bt_2_115200] = {
2048 .flags = FL_BASE0|FL_BASE_BARS,
2049 .num_ports = 2,
2050 .base_baud = 115200,
2051 .uart_offset = 8,
2052 },
2053 [pbn_b0_bt_4_115200] = {
2054 .flags = FL_BASE0|FL_BASE_BARS,
2055 .num_ports = 4,
2056 .base_baud = 115200,
2057 .uart_offset = 8,
2058 },
2059 [pbn_b0_bt_8_115200] = {
2060 .flags = FL_BASE0|FL_BASE_BARS,
2061 .num_ports = 8,
2062 .base_baud = 115200,
2063 .uart_offset = 8,
2064 },
2065
2066 [pbn_b0_bt_1_460800] = {
2067 .flags = FL_BASE0|FL_BASE_BARS,
2068 .num_ports = 1,
2069 .base_baud = 460800,
2070 .uart_offset = 8,
2071 },
2072 [pbn_b0_bt_2_460800] = {
2073 .flags = FL_BASE0|FL_BASE_BARS,
2074 .num_ports = 2,
2075 .base_baud = 460800,
2076 .uart_offset = 8,
2077 },
2078 [pbn_b0_bt_4_460800] = {
2079 .flags = FL_BASE0|FL_BASE_BARS,
2080 .num_ports = 4,
2081 .base_baud = 460800,
2082 .uart_offset = 8,
2083 },
2084
2085 [pbn_b0_bt_1_921600] = {
2086 .flags = FL_BASE0|FL_BASE_BARS,
2087 .num_ports = 1,
2088 .base_baud = 921600,
2089 .uart_offset = 8,
2090 },
2091 [pbn_b0_bt_2_921600] = {
2092 .flags = FL_BASE0|FL_BASE_BARS,
2093 .num_ports = 2,
2094 .base_baud = 921600,
2095 .uart_offset = 8,
2096 },
2097 [pbn_b0_bt_4_921600] = {
2098 .flags = FL_BASE0|FL_BASE_BARS,
2099 .num_ports = 4,
2100 .base_baud = 921600,
2101 .uart_offset = 8,
2102 },
2103 [pbn_b0_bt_8_921600] = {
2104 .flags = FL_BASE0|FL_BASE_BARS,
2105 .num_ports = 8,
2106 .base_baud = 921600,
2107 .uart_offset = 8,
2108 },
2109
2110 [pbn_b1_1_115200] = {
2111 .flags = FL_BASE1,
2112 .num_ports = 1,
2113 .base_baud = 115200,
2114 .uart_offset = 8,
2115 },
2116 [pbn_b1_2_115200] = {
2117 .flags = FL_BASE1,
2118 .num_ports = 2,
2119 .base_baud = 115200,
2120 .uart_offset = 8,
2121 },
2122 [pbn_b1_4_115200] = {
2123 .flags = FL_BASE1,
2124 .num_ports = 4,
2125 .base_baud = 115200,
2126 .uart_offset = 8,
2127 },
2128 [pbn_b1_8_115200] = {
2129 .flags = FL_BASE1,
2130 .num_ports = 8,
2131 .base_baud = 115200,
2132 .uart_offset = 8,
2133 },
2134 [pbn_b1_16_115200] = {
2135 .flags = FL_BASE1,
2136 .num_ports = 16,
2137 .base_baud = 115200,
2138 .uart_offset = 8,
2139 },
2140
2141 [pbn_b1_1_921600] = {
2142 .flags = FL_BASE1,
2143 .num_ports = 1,
2144 .base_baud = 921600,
2145 .uart_offset = 8,
2146 },
2147 [pbn_b1_2_921600] = {
2148 .flags = FL_BASE1,
2149 .num_ports = 2,
2150 .base_baud = 921600,
2151 .uart_offset = 8,
2152 },
2153 [pbn_b1_4_921600] = {
2154 .flags = FL_BASE1,
2155 .num_ports = 4,
2156 .base_baud = 921600,
2157 .uart_offset = 8,
2158 },
2159 [pbn_b1_8_921600] = {
2160 .flags = FL_BASE1,
2161 .num_ports = 8,
2162 .base_baud = 921600,
2163 .uart_offset = 8,
2164 },
2165 [pbn_b1_2_1250000] = {
2166 .flags = FL_BASE1,
2167 .num_ports = 2,
2168 .base_baud = 1250000,
2169 .uart_offset = 8,
2170 },
2171
2172 [pbn_b1_bt_1_115200] = {
2173 .flags = FL_BASE1|FL_BASE_BARS,
2174 .num_ports = 1,
2175 .base_baud = 115200,
2176 .uart_offset = 8,
2177 },
2178 [pbn_b1_bt_2_115200] = {
2179 .flags = FL_BASE1|FL_BASE_BARS,
2180 .num_ports = 2,
2181 .base_baud = 115200,
2182 .uart_offset = 8,
2183 },
2184 [pbn_b1_bt_4_115200] = {
2185 .flags = FL_BASE1|FL_BASE_BARS,
2186 .num_ports = 4,
2187 .base_baud = 115200,
2188 .uart_offset = 8,
2189 },
2190
2191 [pbn_b1_bt_2_921600] = {
2192 .flags = FL_BASE1|FL_BASE_BARS,
2193 .num_ports = 2,
2194 .base_baud = 921600,
2195 .uart_offset = 8,
2196 },
2197
2198 [pbn_b1_1_1382400] = {
2199 .flags = FL_BASE1,
2200 .num_ports = 1,
2201 .base_baud = 1382400,
2202 .uart_offset = 8,
2203 },
2204 [pbn_b1_2_1382400] = {
2205 .flags = FL_BASE1,
2206 .num_ports = 2,
2207 .base_baud = 1382400,
2208 .uart_offset = 8,
2209 },
2210 [pbn_b1_4_1382400] = {
2211 .flags = FL_BASE1,
2212 .num_ports = 4,
2213 .base_baud = 1382400,
2214 .uart_offset = 8,
2215 },
2216 [pbn_b1_8_1382400] = {
2217 .flags = FL_BASE1,
2218 .num_ports = 8,
2219 .base_baud = 1382400,
2220 .uart_offset = 8,
2221 },
2222
2223 [pbn_b2_1_115200] = {
2224 .flags = FL_BASE2,
2225 .num_ports = 1,
2226 .base_baud = 115200,
2227 .uart_offset = 8,
2228 },
2229 [pbn_b2_2_115200] = {
2230 .flags = FL_BASE2,
2231 .num_ports = 2,
2232 .base_baud = 115200,
2233 .uart_offset = 8,
2234 },
2235 [pbn_b2_4_115200] = {
2236 .flags = FL_BASE2,
2237 .num_ports = 4,
2238 .base_baud = 115200,
2239 .uart_offset = 8,
2240 },
2241 [pbn_b2_8_115200] = {
2242 .flags = FL_BASE2,
2243 .num_ports = 8,
2244 .base_baud = 115200,
2245 .uart_offset = 8,
2246 },
2247
2248 [pbn_b2_1_460800] = {
2249 .flags = FL_BASE2,
2250 .num_ports = 1,
2251 .base_baud = 460800,
2252 .uart_offset = 8,
2253 },
2254 [pbn_b2_4_460800] = {
2255 .flags = FL_BASE2,
2256 .num_ports = 4,
2257 .base_baud = 460800,
2258 .uart_offset = 8,
2259 },
2260 [pbn_b2_8_460800] = {
2261 .flags = FL_BASE2,
2262 .num_ports = 8,
2263 .base_baud = 460800,
2264 .uart_offset = 8,
2265 },
2266 [pbn_b2_16_460800] = {
2267 .flags = FL_BASE2,
2268 .num_ports = 16,
2269 .base_baud = 460800,
2270 .uart_offset = 8,
2271 },
2272
2273 [pbn_b2_1_921600] = {
2274 .flags = FL_BASE2,
2275 .num_ports = 1,
2276 .base_baud = 921600,
2277 .uart_offset = 8,
2278 },
2279 [pbn_b2_4_921600] = {
2280 .flags = FL_BASE2,
2281 .num_ports = 4,
2282 .base_baud = 921600,
2283 .uart_offset = 8,
2284 },
2285 [pbn_b2_8_921600] = {
2286 .flags = FL_BASE2,
2287 .num_ports = 8,
2288 .base_baud = 921600,
2289 .uart_offset = 8,
2290 },
2291
2292 [pbn_b2_8_1152000] = {
2293 .flags = FL_BASE2,
2294 .num_ports = 8,
2295 .base_baud = 1152000,
2296 .uart_offset = 8,
2297 },
2298
2299 [pbn_b2_bt_1_115200] = {
2300 .flags = FL_BASE2|FL_BASE_BARS,
2301 .num_ports = 1,
2302 .base_baud = 115200,
2303 .uart_offset = 8,
2304 },
2305 [pbn_b2_bt_2_115200] = {
2306 .flags = FL_BASE2|FL_BASE_BARS,
2307 .num_ports = 2,
2308 .base_baud = 115200,
2309 .uart_offset = 8,
2310 },
2311 [pbn_b2_bt_4_115200] = {
2312 .flags = FL_BASE2|FL_BASE_BARS,
2313 .num_ports = 4,
2314 .base_baud = 115200,
2315 .uart_offset = 8,
2316 },
2317
2318 [pbn_b2_bt_2_921600] = {
2319 .flags = FL_BASE2|FL_BASE_BARS,
2320 .num_ports = 2,
2321 .base_baud = 921600,
2322 .uart_offset = 8,
2323 },
2324 [pbn_b2_bt_4_921600] = {
2325 .flags = FL_BASE2|FL_BASE_BARS,
2326 .num_ports = 4,
2327 .base_baud = 921600,
2328 .uart_offset = 8,
2329 },
2330
2331 [pbn_b3_2_115200] = {
2332 .flags = FL_BASE3,
2333 .num_ports = 2,
2334 .base_baud = 115200,
2335 .uart_offset = 8,
2336 },
2337 [pbn_b3_4_115200] = {
2338 .flags = FL_BASE3,
2339 .num_ports = 4,
2340 .base_baud = 115200,
2341 .uart_offset = 8,
2342 },
2343 [pbn_b3_8_115200] = {
2344 .flags = FL_BASE3,
2345 .num_ports = 8,
2346 .base_baud = 115200,
2347 .uart_offset = 8,
2348 },
2349
2350 [pbn_b4_bt_2_921600] = {
2351 .flags = FL_BASE4,
2352 .num_ports = 2,
2353 .base_baud = 921600,
2354 .uart_offset = 8,
2355 },
2356 [pbn_b4_bt_4_921600] = {
2357 .flags = FL_BASE4,
2358 .num_ports = 4,
2359 .base_baud = 921600,
2360 .uart_offset = 8,
2361 },
2362 [pbn_b4_bt_8_921600] = {
2363 .flags = FL_BASE4,
2364 .num_ports = 8,
2365 .base_baud = 921600,
2366 .uart_offset = 8,
2367 },
2368
2369 /*
2370 * Entries following this are board-specific.
2371 */
2372
2373 /*
2374 * Panacom - IOMEM
2375 */
2376 [pbn_panacom] = {
2377 .flags = FL_BASE2,
2378 .num_ports = 2,
2379 .base_baud = 921600,
2380 .uart_offset = 0x400,
2381 .reg_shift = 7,
2382 },
2383 [pbn_panacom2] = {
2384 .flags = FL_BASE2|FL_BASE_BARS,
2385 .num_ports = 2,
2386 .base_baud = 921600,
2387 .uart_offset = 0x400,
2388 .reg_shift = 7,
2389 },
2390 [pbn_panacom4] = {
2391 .flags = FL_BASE2|FL_BASE_BARS,
2392 .num_ports = 4,
2393 .base_baud = 921600,
2394 .uart_offset = 0x400,
2395 .reg_shift = 7,
2396 },
2397
2398 [pbn_exsys_4055] = {
2399 .flags = FL_BASE2,
2400 .num_ports = 4,
2401 .base_baud = 115200,
2402 .uart_offset = 8,
2403 },
2404
2405 /* I think this entry is broken - the first_offset looks wrong --rmk */
2406 [pbn_plx_romulus] = {
2407 .flags = FL_BASE2,
2408 .num_ports = 4,
2409 .base_baud = 921600,
2410 .uart_offset = 8 << 2,
2411 .reg_shift = 2,
2412 .first_offset = 0x03,
2413 },
2414
2415 /*
2416 * This board uses the size of PCI Base region 0 to
2417 * signal now many ports are available
2418 */
2419 [pbn_oxsemi] = {
2420 .flags = FL_BASE0|FL_REGION_SZ_CAP,
2421 .num_ports = 32,
2422 .base_baud = 115200,
2423 .uart_offset = 8,
2424 },
2425 [pbn_oxsemi_1_4000000] = {
2426 .flags = FL_BASE0,
2427 .num_ports = 1,
2428 .base_baud = 4000000,
2429 .uart_offset = 0x200,
2430 .first_offset = 0x1000,
2431 },
2432 [pbn_oxsemi_2_4000000] = {
2433 .flags = FL_BASE0,
2434 .num_ports = 2,
2435 .base_baud = 4000000,
2436 .uart_offset = 0x200,
2437 .first_offset = 0x1000,
2438 },
2439 [pbn_oxsemi_4_4000000] = {
2440 .flags = FL_BASE0,
2441 .num_ports = 4,
2442 .base_baud = 4000000,
2443 .uart_offset = 0x200,
2444 .first_offset = 0x1000,
2445 },
2446 [pbn_oxsemi_8_4000000] = {
2447 .flags = FL_BASE0,
2448 .num_ports = 8,
2449 .base_baud = 4000000,
2450 .uart_offset = 0x200,
2451 .first_offset = 0x1000,
2452 },
2453
2454
2455 /*
2456 * EKF addition for i960 Boards form EKF with serial port.
2457 * Max 256 ports.
2458 */
2459 [pbn_intel_i960] = {
2460 .flags = FL_BASE0,
2461 .num_ports = 32,
2462 .base_baud = 921600,
2463 .uart_offset = 8 << 2,
2464 .reg_shift = 2,
2465 .first_offset = 0x10000,
2466 },
2467 [pbn_sgi_ioc3] = {
2468 .flags = FL_BASE0|FL_NOIRQ,
2469 .num_ports = 1,
2470 .base_baud = 458333,
2471 .uart_offset = 8,
2472 .reg_shift = 0,
2473 .first_offset = 0x20178,
2474 },
2475
2476 /*
2477 * Computone - uses IOMEM.
2478 */
2479 [pbn_computone_4] = {
2480 .flags = FL_BASE0,
2481 .num_ports = 4,
2482 .base_baud = 921600,
2483 .uart_offset = 0x40,
2484 .reg_shift = 2,
2485 .first_offset = 0x200,
2486 },
2487 [pbn_computone_6] = {
2488 .flags = FL_BASE0,
2489 .num_ports = 6,
2490 .base_baud = 921600,
2491 .uart_offset = 0x40,
2492 .reg_shift = 2,
2493 .first_offset = 0x200,
2494 },
2495 [pbn_computone_8] = {
2496 .flags = FL_BASE0,
2497 .num_ports = 8,
2498 .base_baud = 921600,
2499 .uart_offset = 0x40,
2500 .reg_shift = 2,
2501 .first_offset = 0x200,
2502 },
2503 [pbn_sbsxrsio] = {
2504 .flags = FL_BASE0,
2505 .num_ports = 8,
2506 .base_baud = 460800,
2507 .uart_offset = 256,
2508 .reg_shift = 4,
2509 },
2510 /*
2511 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2512 * Only basic 16550A support.
2513 * XR17C15[24] are not tested, but they should work.
2514 */
2515 [pbn_exar_XR17C152] = {
2516 .flags = FL_BASE0,
2517 .num_ports = 2,
2518 .base_baud = 921600,
2519 .uart_offset = 0x200,
2520 },
2521 [pbn_exar_XR17C154] = {
2522 .flags = FL_BASE0,
2523 .num_ports = 4,
2524 .base_baud = 921600,
2525 .uart_offset = 0x200,
2526 },
2527 [pbn_exar_XR17C158] = {
2528 .flags = FL_BASE0,
2529 .num_ports = 8,
2530 .base_baud = 921600,
2531 .uart_offset = 0x200,
2532 },
2533 [pbn_exar_ibm_saturn] = {
2534 .flags = FL_BASE0,
2535 .num_ports = 1,
2536 .base_baud = 921600,
2537 .uart_offset = 0x200,
2538 },
2539
2540 /*
2541 * PA Semi PWRficient PA6T-1682M on-chip UART
2542 */
2543 [pbn_pasemi_1682M] = {
2544 .flags = FL_BASE0,
2545 .num_ports = 1,
2546 .base_baud = 8333333,
2547 },
2548 /*
2549 * National Instruments 843x
2550 */
2551 [pbn_ni8430_16] = {
2552 .flags = FL_BASE0,
2553 .num_ports = 16,
2554 .base_baud = 3686400,
2555 .uart_offset = 0x10,
2556 .first_offset = 0x800,
2557 },
2558 [pbn_ni8430_8] = {
2559 .flags = FL_BASE0,
2560 .num_ports = 8,
2561 .base_baud = 3686400,
2562 .uart_offset = 0x10,
2563 .first_offset = 0x800,
2564 },
2565 [pbn_ni8430_4] = {
2566 .flags = FL_BASE0,
2567 .num_ports = 4,
2568 .base_baud = 3686400,
2569 .uart_offset = 0x10,
2570 .first_offset = 0x800,
2571 },
2572 [pbn_ni8430_2] = {
2573 .flags = FL_BASE0,
2574 .num_ports = 2,
2575 .base_baud = 3686400,
2576 .uart_offset = 0x10,
2577 .first_offset = 0x800,
2578 },
2579 /*
2580 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
2581 */
2582 [pbn_ADDIDATA_PCIe_1_3906250] = {
2583 .flags = FL_BASE0,
2584 .num_ports = 1,
2585 .base_baud = 3906250,
2586 .uart_offset = 0x200,
2587 .first_offset = 0x1000,
2588 },
2589 [pbn_ADDIDATA_PCIe_2_3906250] = {
2590 .flags = FL_BASE0,
2591 .num_ports = 2,
2592 .base_baud = 3906250,
2593 .uart_offset = 0x200,
2594 .first_offset = 0x1000,
2595 },
2596 [pbn_ADDIDATA_PCIe_4_3906250] = {
2597 .flags = FL_BASE0,
2598 .num_ports = 4,
2599 .base_baud = 3906250,
2600 .uart_offset = 0x200,
2601 .first_offset = 0x1000,
2602 },
2603 [pbn_ADDIDATA_PCIe_8_3906250] = {
2604 .flags = FL_BASE0,
2605 .num_ports = 8,
2606 .base_baud = 3906250,
2607 .uart_offset = 0x200,
2608 .first_offset = 0x1000,
2609 },
2610 [pbn_ce4100_1_115200] = {
2611 .flags = FL_BASE0,
2612 .num_ports = 1,
2613 .base_baud = 921600,
2614 .reg_shift = 2,
2615 },
2616 [pbn_omegapci] = {
2617 .flags = FL_BASE0,
2618 .num_ports = 8,
2619 .base_baud = 115200,
2620 .uart_offset = 0x200,
2621 },
2622 [pbn_NETMOS9900_2s_115200] = {
2623 .flags = FL_BASE0,
2624 .num_ports = 2,
2625 .base_baud = 115200,
2626 },
2627 };
2628
2629 static const struct pci_device_id softmodem_blacklist[] = {
2630 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
2631 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
2632 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
2633 };
2634
2635 /*
2636 * Given a complete unknown PCI device, try to use some heuristics to
2637 * guess what the configuration might be, based on the pitiful PCI
2638 * serial specs. Returns 0 on success, 1 on failure.
2639 */
2640 static int __devinit
2641 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
2642 {
2643 const struct pci_device_id *blacklist;
2644 int num_iomem, num_port, first_port = -1, i;
2645
2646 /*
2647 * If it is not a communications device or the programming
2648 * interface is greater than 6, give up.
2649 *
2650 * (Should we try to make guesses for multiport serial devices
2651 * later?)
2652 */
2653 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
2654 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
2655 (dev->class & 0xff) > 6)
2656 return -ENODEV;
2657
2658 /*
2659 * Do not access blacklisted devices that are known not to
2660 * feature serial ports.
2661 */
2662 for (blacklist = softmodem_blacklist;
2663 blacklist < softmodem_blacklist + ARRAY_SIZE(softmodem_blacklist);
2664 blacklist++) {
2665 if (dev->vendor == blacklist->vendor &&
2666 dev->device == blacklist->device)
2667 return -ENODEV;
2668 }
2669
2670 num_iomem = num_port = 0;
2671 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2672 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
2673 num_port++;
2674 if (first_port == -1)
2675 first_port = i;
2676 }
2677 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
2678 num_iomem++;
2679 }
2680
2681 /*
2682 * If there is 1 or 0 iomem regions, and exactly one port,
2683 * use it. We guess the number of ports based on the IO
2684 * region size.
2685 */
2686 if (num_iomem <= 1 && num_port == 1) {
2687 board->flags = first_port;
2688 board->num_ports = pci_resource_len(dev, first_port) / 8;
2689 return 0;
2690 }
2691
2692 /*
2693 * Now guess if we've got a board which indexes by BARs.
2694 * Each IO BAR should be 8 bytes, and they should follow
2695 * consecutively.
2696 */
2697 first_port = -1;
2698 num_port = 0;
2699 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2700 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
2701 pci_resource_len(dev, i) == 8 &&
2702 (first_port == -1 || (first_port + num_port) == i)) {
2703 num_port++;
2704 if (first_port == -1)
2705 first_port = i;
2706 }
2707 }
2708
2709 if (num_port > 1) {
2710 board->flags = first_port | FL_BASE_BARS;
2711 board->num_ports = num_port;
2712 return 0;
2713 }
2714
2715 return -ENODEV;
2716 }
2717
2718 static inline int
2719 serial_pci_matches(const struct pciserial_board *board,
2720 const struct pciserial_board *guessed)
2721 {
2722 return
2723 board->num_ports == guessed->num_ports &&
2724 board->base_baud == guessed->base_baud &&
2725 board->uart_offset == guessed->uart_offset &&
2726 board->reg_shift == guessed->reg_shift &&
2727 board->first_offset == guessed->first_offset;
2728 }
2729
2730 struct serial_private *
2731 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
2732 {
2733 struct uart_port serial_port;
2734 struct serial_private *priv;
2735 struct pci_serial_quirk *quirk;
2736 int rc, nr_ports, i;
2737
2738 nr_ports = board->num_ports;
2739
2740 /*
2741 * Find an init and setup quirks.
2742 */
2743 quirk = find_quirk(dev);
2744
2745 /*
2746 * Run the new-style initialization function.
2747 * The initialization function returns:
2748 * <0 - error
2749 * 0 - use board->num_ports
2750 * >0 - number of ports
2751 */
2752 if (quirk->init) {
2753 rc = quirk->init(dev);
2754 if (rc < 0) {
2755 priv = ERR_PTR(rc);
2756 goto err_out;
2757 }
2758 if (rc)
2759 nr_ports = rc;
2760 }
2761
2762 priv = kzalloc(sizeof(struct serial_private) +
2763 sizeof(unsigned int) * nr_ports,
2764 GFP_KERNEL);
2765 if (!priv) {
2766 priv = ERR_PTR(-ENOMEM);
2767 goto err_deinit;
2768 }
2769
2770 priv->dev = dev;
2771 priv->quirk = quirk;
2772
2773 memset(&serial_port, 0, sizeof(struct uart_port));
2774 serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
2775 serial_port.uartclk = board->base_baud * 16;
2776 serial_port.irq = get_pci_irq(dev, board);
2777 serial_port.dev = &dev->dev;
2778
2779 for (i = 0; i < nr_ports; i++) {
2780 if (quirk->setup(priv, board, &serial_port, i))
2781 break;
2782
2783 #ifdef SERIAL_DEBUG_PCI
2784 printk(KERN_DEBUG "Setup PCI port: port %lx, irq %d, type %d\n",
2785 serial_port.iobase, serial_port.irq, serial_port.iotype);
2786 #endif
2787
2788 priv->line[i] = serial8250_register_port(&serial_port);
2789 if (priv->line[i] < 0) {
2790 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
2791 break;
2792 }
2793 }
2794 priv->nr = i;
2795 return priv;
2796
2797 err_deinit:
2798 if (quirk->exit)
2799 quirk->exit(dev);
2800 err_out:
2801 return priv;
2802 }
2803 EXPORT_SYMBOL_GPL(pciserial_init_ports);
2804
2805 void pciserial_remove_ports(struct serial_private *priv)
2806 {
2807 struct pci_serial_quirk *quirk;
2808 int i;
2809
2810 for (i = 0; i < priv->nr; i++)
2811 serial8250_unregister_port(priv->line[i]);
2812
2813 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2814 if (priv->remapped_bar[i])
2815 iounmap(priv->remapped_bar[i]);
2816 priv->remapped_bar[i] = NULL;
2817 }
2818
2819 /*
2820 * Find the exit quirks.
2821 */
2822 quirk = find_quirk(priv->dev);
2823 if (quirk->exit)
2824 quirk->exit(priv->dev);
2825
2826 kfree(priv);
2827 }
2828 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
2829
2830 void pciserial_suspend_ports(struct serial_private *priv)
2831 {
2832 int i;
2833
2834 for (i = 0; i < priv->nr; i++)
2835 if (priv->line[i] >= 0)
2836 serial8250_suspend_port(priv->line[i]);
2837
2838 /*
2839 * Ensure that every init quirk is properly torn down
2840 */
2841 if (priv->quirk->exit)
2842 priv->quirk->exit(priv->dev);
2843 }
2844 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
2845
2846 void pciserial_resume_ports(struct serial_private *priv)
2847 {
2848 int i;
2849
2850 /*
2851 * Ensure that the board is correctly configured.
2852 */
2853 if (priv->quirk->init)
2854 priv->quirk->init(priv->dev);
2855
2856 for (i = 0; i < priv->nr; i++)
2857 if (priv->line[i] >= 0)
2858 serial8250_resume_port(priv->line[i]);
2859 }
2860 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
2861
2862 /*
2863 * Probe one serial board. Unfortunately, there is no rhyme nor reason
2864 * to the arrangement of serial ports on a PCI card.
2865 */
2866 static int __devinit
2867 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
2868 {
2869 struct pci_serial_quirk *quirk;
2870 struct serial_private *priv;
2871 const struct pciserial_board *board;
2872 struct pciserial_board tmp;
2873 int rc;
2874
2875 quirk = find_quirk(dev);
2876 if (quirk->probe) {
2877 rc = quirk->probe(dev);
2878 if (rc)
2879 return rc;
2880 }
2881
2882 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
2883 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
2884 ent->driver_data);
2885 return -EINVAL;
2886 }
2887
2888 board = &pci_boards[ent->driver_data];
2889
2890 rc = pci_enable_device(dev);
2891 pci_save_state(dev);
2892 if (rc)
2893 return rc;
2894
2895 if (ent->driver_data == pbn_default) {
2896 /*
2897 * Use a copy of the pci_board entry for this;
2898 * avoid changing entries in the table.
2899 */
2900 memcpy(&tmp, board, sizeof(struct pciserial_board));
2901 board = &tmp;
2902
2903 /*
2904 * We matched one of our class entries. Try to
2905 * determine the parameters of this board.
2906 */
2907 rc = serial_pci_guess_board(dev, &tmp);
2908 if (rc)
2909 goto disable;
2910 } else {
2911 /*
2912 * We matched an explicit entry. If we are able to
2913 * detect this boards settings with our heuristic,
2914 * then we no longer need this entry.
2915 */
2916 memcpy(&tmp, &pci_boards[pbn_default],
2917 sizeof(struct pciserial_board));
2918 rc = serial_pci_guess_board(dev, &tmp);
2919 if (rc == 0 && serial_pci_matches(board, &tmp))
2920 moan_device("Redundant entry in serial pci_table.",
2921 dev);
2922 }
2923
2924 priv = pciserial_init_ports(dev, board);
2925 if (!IS_ERR(priv)) {
2926 pci_set_drvdata(dev, priv);
2927 return 0;
2928 }
2929
2930 rc = PTR_ERR(priv);
2931
2932 disable:
2933 pci_disable_device(dev);
2934 return rc;
2935 }
2936
2937 static void __devexit pciserial_remove_one(struct pci_dev *dev)
2938 {
2939 struct serial_private *priv = pci_get_drvdata(dev);
2940
2941 pci_set_drvdata(dev, NULL);
2942
2943 pciserial_remove_ports(priv);
2944
2945 pci_disable_device(dev);
2946 }
2947
2948 #ifdef CONFIG_PM
2949 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
2950 {
2951 struct serial_private *priv = pci_get_drvdata(dev);
2952
2953 if (priv)
2954 pciserial_suspend_ports(priv);
2955
2956 pci_save_state(dev);
2957 pci_set_power_state(dev, pci_choose_state(dev, state));
2958 return 0;
2959 }
2960
2961 static int pciserial_resume_one(struct pci_dev *dev)
2962 {
2963 int err;
2964 struct serial_private *priv = pci_get_drvdata(dev);
2965
2966 pci_set_power_state(dev, PCI_D0);
2967 pci_restore_state(dev);
2968
2969 if (priv) {
2970 /*
2971 * The device may have been disabled. Re-enable it.
2972 */
2973 err = pci_enable_device(dev);
2974 /* FIXME: We cannot simply error out here */
2975 if (err)
2976 printk(KERN_ERR "pciserial: Unable to re-enable ports, trying to continue.\n");
2977 pciserial_resume_ports(priv);
2978 }
2979 return 0;
2980 }
2981 #endif
2982
2983 static struct pci_device_id serial_pci_tbl[] = {
2984 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
2985 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
2986 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
2987 pbn_b2_8_921600 },
2988 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2989 PCI_SUBVENDOR_ID_CONNECT_TECH,
2990 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2991 pbn_b1_8_1382400 },
2992 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2993 PCI_SUBVENDOR_ID_CONNECT_TECH,
2994 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2995 pbn_b1_4_1382400 },
2996 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2997 PCI_SUBVENDOR_ID_CONNECT_TECH,
2998 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2999 pbn_b1_2_1382400 },
3000 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3001 PCI_SUBVENDOR_ID_CONNECT_TECH,
3002 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3003 pbn_b1_8_1382400 },
3004 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3005 PCI_SUBVENDOR_ID_CONNECT_TECH,
3006 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3007 pbn_b1_4_1382400 },
3008 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3009 PCI_SUBVENDOR_ID_CONNECT_TECH,
3010 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3011 pbn_b1_2_1382400 },
3012 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3013 PCI_SUBVENDOR_ID_CONNECT_TECH,
3014 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
3015 pbn_b1_8_921600 },
3016 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3017 PCI_SUBVENDOR_ID_CONNECT_TECH,
3018 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
3019 pbn_b1_8_921600 },
3020 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3021 PCI_SUBVENDOR_ID_CONNECT_TECH,
3022 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
3023 pbn_b1_4_921600 },
3024 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3025 PCI_SUBVENDOR_ID_CONNECT_TECH,
3026 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
3027 pbn_b1_4_921600 },
3028 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3029 PCI_SUBVENDOR_ID_CONNECT_TECH,
3030 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
3031 pbn_b1_2_921600 },
3032 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3033 PCI_SUBVENDOR_ID_CONNECT_TECH,
3034 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
3035 pbn_b1_8_921600 },
3036 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3037 PCI_SUBVENDOR_ID_CONNECT_TECH,
3038 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
3039 pbn_b1_8_921600 },
3040 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3041 PCI_SUBVENDOR_ID_CONNECT_TECH,
3042 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
3043 pbn_b1_4_921600 },
3044 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3045 PCI_SUBVENDOR_ID_CONNECT_TECH,
3046 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
3047 pbn_b1_2_1250000 },
3048 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3049 PCI_SUBVENDOR_ID_CONNECT_TECH,
3050 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
3051 pbn_b0_2_1843200 },
3052 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3053 PCI_SUBVENDOR_ID_CONNECT_TECH,
3054 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
3055 pbn_b0_4_1843200 },
3056 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3057 PCI_VENDOR_ID_AFAVLAB,
3058 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
3059 pbn_b0_4_1152000 },
3060 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3061 PCI_SUBVENDOR_ID_CONNECT_TECH,
3062 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
3063 pbn_b0_2_1843200_200 },
3064 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3065 PCI_SUBVENDOR_ID_CONNECT_TECH,
3066 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
3067 pbn_b0_4_1843200_200 },
3068 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3069 PCI_SUBVENDOR_ID_CONNECT_TECH,
3070 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
3071 pbn_b0_8_1843200_200 },
3072 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3073 PCI_SUBVENDOR_ID_CONNECT_TECH,
3074 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
3075 pbn_b0_2_1843200_200 },
3076 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3077 PCI_SUBVENDOR_ID_CONNECT_TECH,
3078 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
3079 pbn_b0_4_1843200_200 },
3080 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3081 PCI_SUBVENDOR_ID_CONNECT_TECH,
3082 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
3083 pbn_b0_8_1843200_200 },
3084 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3085 PCI_SUBVENDOR_ID_CONNECT_TECH,
3086 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
3087 pbn_b0_2_1843200_200 },
3088 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3089 PCI_SUBVENDOR_ID_CONNECT_TECH,
3090 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
3091 pbn_b0_4_1843200_200 },
3092 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3093 PCI_SUBVENDOR_ID_CONNECT_TECH,
3094 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
3095 pbn_b0_8_1843200_200 },
3096 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3097 PCI_SUBVENDOR_ID_CONNECT_TECH,
3098 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
3099 pbn_b0_2_1843200_200 },
3100 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3101 PCI_SUBVENDOR_ID_CONNECT_TECH,
3102 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
3103 pbn_b0_4_1843200_200 },
3104 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3105 PCI_SUBVENDOR_ID_CONNECT_TECH,
3106 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
3107 pbn_b0_8_1843200_200 },
3108 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3109 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
3110 0, 0, pbn_exar_ibm_saturn },
3111
3112 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
3113 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3114 pbn_b2_bt_1_115200 },
3115 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
3116 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3117 pbn_b2_bt_2_115200 },
3118 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
3119 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3120 pbn_b2_bt_4_115200 },
3121 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
3122 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3123 pbn_b2_bt_2_115200 },
3124 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
3125 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3126 pbn_b2_bt_4_115200 },
3127 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
3128 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3129 pbn_b2_8_115200 },
3130 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
3131 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3132 pbn_b2_8_460800 },
3133 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
3134 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3135 pbn_b2_8_115200 },
3136
3137 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
3138 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3139 pbn_b2_bt_2_115200 },
3140 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
3141 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3142 pbn_b2_bt_2_921600 },
3143 /*
3144 * VScom SPCOM800, from sl@s.pl
3145 */
3146 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
3147 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3148 pbn_b2_8_921600 },
3149 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
3150 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3151 pbn_b2_4_921600 },
3152 /* Unknown card - subdevice 0x1584 */
3153 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3154 PCI_VENDOR_ID_PLX,
3155 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
3156 pbn_b0_4_115200 },
3157 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3158 PCI_SUBVENDOR_ID_KEYSPAN,
3159 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
3160 pbn_panacom },
3161 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
3162 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3163 pbn_panacom4 },
3164 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
3165 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3166 pbn_panacom2 },
3167 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3168 PCI_VENDOR_ID_ESDGMBH,
3169 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
3170 pbn_b2_4_115200 },
3171 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3172 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3173 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
3174 pbn_b2_4_460800 },
3175 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3176 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3177 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
3178 pbn_b2_8_460800 },
3179 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3180 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3181 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
3182 pbn_b2_16_460800 },
3183 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3184 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3185 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
3186 pbn_b2_16_460800 },
3187 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3188 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
3189 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
3190 pbn_b2_4_460800 },
3191 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3192 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
3193 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
3194 pbn_b2_8_460800 },
3195 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3196 PCI_SUBVENDOR_ID_EXSYS,
3197 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
3198 pbn_exsys_4055 },
3199 /*
3200 * Megawolf Romulus PCI Serial Card, from Mike Hudson
3201 * (Exoray@isys.ca)
3202 */
3203 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
3204 0x10b5, 0x106a, 0, 0,
3205 pbn_plx_romulus },
3206 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
3207 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3208 pbn_b1_4_115200 },
3209 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
3210 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3211 pbn_b1_2_115200 },
3212 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
3213 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3214 pbn_b1_8_115200 },
3215 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
3216 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3217 pbn_b1_8_115200 },
3218 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
3219 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
3220 0, 0,
3221 pbn_b0_4_921600 },
3222 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3223 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
3224 0, 0,
3225 pbn_b0_4_1152000 },
3226 { PCI_VENDOR_ID_OXSEMI, 0x9505,
3227 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3228 pbn_b0_bt_2_921600 },
3229
3230 /*
3231 * The below card is a little controversial since it is the
3232 * subject of a PCI vendor/device ID clash. (See
3233 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
3234 * For now just used the hex ID 0x950a.
3235 */
3236 { PCI_VENDOR_ID_OXSEMI, 0x950a,
3237 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
3238 0, 0, pbn_b0_2_115200 },
3239 { PCI_VENDOR_ID_OXSEMI, 0x950a,
3240 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
3241 0, 0, pbn_b0_2_115200 },
3242 { PCI_VENDOR_ID_OXSEMI, 0x950a,
3243 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3244 pbn_b0_2_1130000 },
3245 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
3246 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
3247 pbn_b0_1_921600 },
3248 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3249 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3250 pbn_b0_4_115200 },
3251 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
3252 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3253 pbn_b0_bt_2_921600 },
3254 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
3255 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
3256 pbn_b2_8_1152000 },
3257
3258 /*
3259 * Oxford Semiconductor Inc. Tornado PCI express device range.
3260 */
3261 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
3262 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3263 pbn_b0_1_4000000 },
3264 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
3265 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3266 pbn_b0_1_4000000 },
3267 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
3268 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3269 pbn_oxsemi_1_4000000 },
3270 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
3271 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3272 pbn_oxsemi_1_4000000 },
3273 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
3274 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3275 pbn_b0_1_4000000 },
3276 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
3277 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3278 pbn_b0_1_4000000 },
3279 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
3280 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3281 pbn_oxsemi_1_4000000 },
3282 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
3283 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3284 pbn_oxsemi_1_4000000 },
3285 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
3286 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3287 pbn_b0_1_4000000 },
3288 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
3289 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3290 pbn_b0_1_4000000 },
3291 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
3292 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3293 pbn_b0_1_4000000 },
3294 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
3295 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3296 pbn_b0_1_4000000 },
3297 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
3298 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3299 pbn_oxsemi_2_4000000 },
3300 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
3301 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3302 pbn_oxsemi_2_4000000 },
3303 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
3304 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3305 pbn_oxsemi_4_4000000 },
3306 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
3307 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3308 pbn_oxsemi_4_4000000 },
3309 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
3310 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3311 pbn_oxsemi_8_4000000 },
3312 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
3313 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3314 pbn_oxsemi_8_4000000 },
3315 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
3316 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3317 pbn_oxsemi_1_4000000 },
3318 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
3319 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3320 pbn_oxsemi_1_4000000 },
3321 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
3322 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3323 pbn_oxsemi_1_4000000 },
3324 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
3325 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3326 pbn_oxsemi_1_4000000 },
3327 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
3328 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3329 pbn_oxsemi_1_4000000 },
3330 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
3331 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3332 pbn_oxsemi_1_4000000 },
3333 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
3334 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3335 pbn_oxsemi_1_4000000 },
3336 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
3337 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3338 pbn_oxsemi_1_4000000 },
3339 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
3340 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3341 pbn_oxsemi_1_4000000 },
3342 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
3343 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3344 pbn_oxsemi_1_4000000 },
3345 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
3346 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3347 pbn_oxsemi_1_4000000 },
3348 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
3349 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3350 pbn_oxsemi_1_4000000 },
3351 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
3352 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3353 pbn_oxsemi_1_4000000 },
3354 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
3355 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3356 pbn_oxsemi_1_4000000 },
3357 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
3358 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3359 pbn_oxsemi_1_4000000 },
3360 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
3361 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3362 pbn_oxsemi_1_4000000 },
3363 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
3364 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3365 pbn_oxsemi_1_4000000 },
3366 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
3367 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3368 pbn_oxsemi_1_4000000 },
3369 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
3370 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3371 pbn_oxsemi_1_4000000 },
3372 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
3373 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3374 pbn_oxsemi_1_4000000 },
3375 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
3376 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3377 pbn_oxsemi_1_4000000 },
3378 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
3379 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3380 pbn_oxsemi_1_4000000 },
3381 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
3382 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3383 pbn_oxsemi_1_4000000 },
3384 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
3385 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3386 pbn_oxsemi_1_4000000 },
3387 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
3388 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3389 pbn_oxsemi_1_4000000 },
3390 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
3391 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3392 pbn_oxsemi_1_4000000 },
3393 /*
3394 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
3395 */
3396 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
3397 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
3398 pbn_oxsemi_1_4000000 },
3399 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
3400 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
3401 pbn_oxsemi_2_4000000 },
3402 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
3403 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
3404 pbn_oxsemi_4_4000000 },
3405 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
3406 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
3407 pbn_oxsemi_8_4000000 },
3408
3409 /*
3410 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
3411 */
3412 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
3413 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
3414 pbn_oxsemi_2_4000000 },
3415
3416 /*
3417 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
3418 * from skokodyn@yahoo.com
3419 */
3420 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3421 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
3422 pbn_sbsxrsio },
3423 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3424 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
3425 pbn_sbsxrsio },
3426 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3427 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
3428 pbn_sbsxrsio },
3429 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3430 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
3431 pbn_sbsxrsio },
3432
3433 /*
3434 * Digitan DS560-558, from jimd@esoft.com
3435 */
3436 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
3437 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3438 pbn_b1_1_115200 },
3439
3440 /*
3441 * Titan Electronic cards
3442 * The 400L and 800L have a custom setup quirk.
3443 */
3444 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
3445 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3446 pbn_b0_1_921600 },
3447 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
3448 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3449 pbn_b0_2_921600 },
3450 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
3451 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3452 pbn_b0_4_921600 },
3453 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
3454 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3455 pbn_b0_4_921600 },
3456 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
3457 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3458 pbn_b1_1_921600 },
3459 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
3460 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3461 pbn_b1_bt_2_921600 },
3462 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
3463 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3464 pbn_b0_bt_4_921600 },
3465 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
3466 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3467 pbn_b0_bt_8_921600 },
3468 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
3469 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3470 pbn_b4_bt_2_921600 },
3471 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
3472 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3473 pbn_b4_bt_4_921600 },
3474 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
3475 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3476 pbn_b4_bt_8_921600 },
3477 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
3478 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3479 pbn_b0_4_921600 },
3480 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
3481 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3482 pbn_b0_4_921600 },
3483 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
3484 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3485 pbn_b0_4_921600 },
3486 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
3487 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3488 pbn_oxsemi_1_4000000 },
3489 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
3490 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3491 pbn_oxsemi_2_4000000 },
3492 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
3493 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3494 pbn_oxsemi_4_4000000 },
3495 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
3496 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3497 pbn_oxsemi_8_4000000 },
3498 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
3499 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3500 pbn_oxsemi_2_4000000 },
3501 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
3502 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3503 pbn_oxsemi_2_4000000 },
3504 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
3505 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3506 pbn_b0_4_921600 },
3507 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
3508 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3509 pbn_b0_4_921600 },
3510 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
3511 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3512 pbn_b0_4_921600 },
3513 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
3514 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3515 pbn_b0_4_921600 },
3516
3517 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
3518 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3519 pbn_b2_1_460800 },
3520 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
3521 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3522 pbn_b2_1_460800 },
3523 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
3524 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3525 pbn_b2_1_460800 },
3526 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
3527 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3528 pbn_b2_bt_2_921600 },
3529 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
3530 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3531 pbn_b2_bt_2_921600 },
3532 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
3533 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3534 pbn_b2_bt_2_921600 },
3535 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
3536 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3537 pbn_b2_bt_4_921600 },
3538 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
3539 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3540 pbn_b2_bt_4_921600 },
3541 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
3542 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3543 pbn_b2_bt_4_921600 },
3544 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
3545 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3546 pbn_b0_1_921600 },
3547 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
3548 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3549 pbn_b0_1_921600 },
3550 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
3551 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3552 pbn_b0_1_921600 },
3553 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
3554 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3555 pbn_b0_bt_2_921600 },
3556 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
3557 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3558 pbn_b0_bt_2_921600 },
3559 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
3560 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3561 pbn_b0_bt_2_921600 },
3562 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
3563 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3564 pbn_b0_bt_4_921600 },
3565 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
3566 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3567 pbn_b0_bt_4_921600 },
3568 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
3569 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3570 pbn_b0_bt_4_921600 },
3571 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
3572 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3573 pbn_b0_bt_8_921600 },
3574 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
3575 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3576 pbn_b0_bt_8_921600 },
3577 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
3578 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3579 pbn_b0_bt_8_921600 },
3580
3581 /*
3582 * Computone devices submitted by Doug McNash dmcnash@computone.com
3583 */
3584 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3585 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
3586 0, 0, pbn_computone_4 },
3587 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3588 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
3589 0, 0, pbn_computone_8 },
3590 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3591 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
3592 0, 0, pbn_computone_6 },
3593
3594 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
3595 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3596 pbn_oxsemi },
3597 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
3598 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
3599 pbn_b0_bt_1_921600 },
3600
3601 /*
3602 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
3603 */
3604 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
3605 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3606 pbn_b0_bt_8_115200 },
3607 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
3608 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3609 pbn_b0_bt_8_115200 },
3610
3611 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
3612 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3613 pbn_b0_bt_2_115200 },
3614 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
3615 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3616 pbn_b0_bt_2_115200 },
3617 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
3618 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3619 pbn_b0_bt_2_115200 },
3620 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
3621 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3622 pbn_b0_bt_2_115200 },
3623 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
3624 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3625 pbn_b0_bt_2_115200 },
3626 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
3627 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3628 pbn_b0_bt_4_460800 },
3629 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
3630 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3631 pbn_b0_bt_4_460800 },
3632 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
3633 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3634 pbn_b0_bt_2_460800 },
3635 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
3636 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3637 pbn_b0_bt_2_460800 },
3638 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
3639 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3640 pbn_b0_bt_2_460800 },
3641 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
3642 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3643 pbn_b0_bt_1_115200 },
3644 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
3645 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3646 pbn_b0_bt_1_460800 },
3647
3648 /*
3649 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
3650 * Cards are identified by their subsystem vendor IDs, which
3651 * (in hex) match the model number.
3652 *
3653 * Note that JC140x are RS422/485 cards which require ox950
3654 * ACR = 0x10, and as such are not currently fully supported.
3655 */
3656 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3657 0x1204, 0x0004, 0, 0,
3658 pbn_b0_4_921600 },
3659 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3660 0x1208, 0x0004, 0, 0,
3661 pbn_b0_4_921600 },
3662 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3663 0x1402, 0x0002, 0, 0,
3664 pbn_b0_2_921600 }, */
3665 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3666 0x1404, 0x0004, 0, 0,
3667 pbn_b0_4_921600 }, */
3668 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
3669 0x1208, 0x0004, 0, 0,
3670 pbn_b0_4_921600 },
3671
3672 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3673 0x1204, 0x0004, 0, 0,
3674 pbn_b0_4_921600 },
3675 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3676 0x1208, 0x0004, 0, 0,
3677 pbn_b0_4_921600 },
3678 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
3679 0x1208, 0x0004, 0, 0,
3680 pbn_b0_4_921600 },
3681 /*
3682 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
3683 */
3684 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
3685 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3686 pbn_b1_1_1382400 },
3687
3688 /*
3689 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
3690 */
3691 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
3692 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3693 pbn_b1_1_1382400 },
3694
3695 /*
3696 * RAStel 2 port modem, gerg@moreton.com.au
3697 */
3698 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
3699 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3700 pbn_b2_bt_2_115200 },
3701
3702 /*
3703 * EKF addition for i960 Boards form EKF with serial port
3704 */
3705 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
3706 0xE4BF, PCI_ANY_ID, 0, 0,
3707 pbn_intel_i960 },
3708
3709 /*
3710 * Xircom Cardbus/Ethernet combos
3711 */
3712 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
3713 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3714 pbn_b0_1_115200 },
3715 /*
3716 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
3717 */
3718 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
3719 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3720 pbn_b0_1_115200 },
3721
3722 /*
3723 * Untested PCI modems, sent in from various folks...
3724 */
3725
3726 /*
3727 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
3728 */
3729 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
3730 0x1048, 0x1500, 0, 0,
3731 pbn_b1_1_115200 },
3732
3733 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
3734 0xFF00, 0, 0, 0,
3735 pbn_sgi_ioc3 },
3736
3737 /*
3738 * HP Diva card
3739 */
3740 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3741 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
3742 pbn_b1_1_115200 },
3743 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3744 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3745 pbn_b0_5_115200 },
3746 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
3747 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3748 pbn_b2_1_115200 },
3749
3750 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
3751 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3752 pbn_b3_2_115200 },
3753 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
3754 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3755 pbn_b3_4_115200 },
3756 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
3757 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3758 pbn_b3_8_115200 },
3759
3760 /*
3761 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3762 */
3763 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3764 PCI_ANY_ID, PCI_ANY_ID,
3765 0,
3766 0, pbn_exar_XR17C152 },
3767 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3768 PCI_ANY_ID, PCI_ANY_ID,
3769 0,
3770 0, pbn_exar_XR17C154 },
3771 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3772 PCI_ANY_ID, PCI_ANY_ID,
3773 0,
3774 0, pbn_exar_XR17C158 },
3775
3776 /*
3777 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
3778 */
3779 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
3780 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3781 pbn_b0_1_115200 },
3782 /*
3783 * ITE
3784 */
3785 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
3786 PCI_ANY_ID, PCI_ANY_ID,
3787 0, 0,
3788 pbn_b1_bt_1_115200 },
3789
3790 /*
3791 * IntaShield IS-200
3792 */
3793 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
3794 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
3795 pbn_b2_2_115200 },
3796 /*
3797 * IntaShield IS-400
3798 */
3799 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
3800 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
3801 pbn_b2_4_115200 },
3802 /*
3803 * Perle PCI-RAS cards
3804 */
3805 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3806 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
3807 0, 0, pbn_b2_4_921600 },
3808 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3809 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
3810 0, 0, pbn_b2_8_921600 },
3811
3812 /*
3813 * Mainpine series cards: Fairly standard layout but fools
3814 * parts of the autodetect in some cases and uses otherwise
3815 * unmatched communications subclasses in the PCI Express case
3816 */
3817
3818 { /* RockForceDUO */
3819 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3820 PCI_VENDOR_ID_MAINPINE, 0x0200,
3821 0, 0, pbn_b0_2_115200 },
3822 { /* RockForceQUATRO */
3823 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3824 PCI_VENDOR_ID_MAINPINE, 0x0300,
3825 0, 0, pbn_b0_4_115200 },
3826 { /* RockForceDUO+ */
3827 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3828 PCI_VENDOR_ID_MAINPINE, 0x0400,
3829 0, 0, pbn_b0_2_115200 },
3830 { /* RockForceQUATRO+ */
3831 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3832 PCI_VENDOR_ID_MAINPINE, 0x0500,
3833 0, 0, pbn_b0_4_115200 },
3834 { /* RockForce+ */
3835 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3836 PCI_VENDOR_ID_MAINPINE, 0x0600,
3837 0, 0, pbn_b0_2_115200 },
3838 { /* RockForce+ */
3839 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3840 PCI_VENDOR_ID_MAINPINE, 0x0700,
3841 0, 0, pbn_b0_4_115200 },
3842 { /* RockForceOCTO+ */
3843 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3844 PCI_VENDOR_ID_MAINPINE, 0x0800,
3845 0, 0, pbn_b0_8_115200 },
3846 { /* RockForceDUO+ */
3847 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3848 PCI_VENDOR_ID_MAINPINE, 0x0C00,
3849 0, 0, pbn_b0_2_115200 },
3850 { /* RockForceQUARTRO+ */
3851 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3852 PCI_VENDOR_ID_MAINPINE, 0x0D00,
3853 0, 0, pbn_b0_4_115200 },
3854 { /* RockForceOCTO+ */
3855 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3856 PCI_VENDOR_ID_MAINPINE, 0x1D00,
3857 0, 0, pbn_b0_8_115200 },
3858 { /* RockForceD1 */
3859 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3860 PCI_VENDOR_ID_MAINPINE, 0x2000,
3861 0, 0, pbn_b0_1_115200 },
3862 { /* RockForceF1 */
3863 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3864 PCI_VENDOR_ID_MAINPINE, 0x2100,
3865 0, 0, pbn_b0_1_115200 },
3866 { /* RockForceD2 */
3867 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3868 PCI_VENDOR_ID_MAINPINE, 0x2200,
3869 0, 0, pbn_b0_2_115200 },
3870 { /* RockForceF2 */
3871 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3872 PCI_VENDOR_ID_MAINPINE, 0x2300,
3873 0, 0, pbn_b0_2_115200 },
3874 { /* RockForceD4 */
3875 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3876 PCI_VENDOR_ID_MAINPINE, 0x2400,
3877 0, 0, pbn_b0_4_115200 },
3878 { /* RockForceF4 */
3879 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3880 PCI_VENDOR_ID_MAINPINE, 0x2500,
3881 0, 0, pbn_b0_4_115200 },
3882 { /* RockForceD8 */
3883 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3884 PCI_VENDOR_ID_MAINPINE, 0x2600,
3885 0, 0, pbn_b0_8_115200 },
3886 { /* RockForceF8 */
3887 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3888 PCI_VENDOR_ID_MAINPINE, 0x2700,
3889 0, 0, pbn_b0_8_115200 },
3890 { /* IQ Express D1 */
3891 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3892 PCI_VENDOR_ID_MAINPINE, 0x3000,
3893 0, 0, pbn_b0_1_115200 },
3894 { /* IQ Express F1 */
3895 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3896 PCI_VENDOR_ID_MAINPINE, 0x3100,
3897 0, 0, pbn_b0_1_115200 },
3898 { /* IQ Express D2 */
3899 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3900 PCI_VENDOR_ID_MAINPINE, 0x3200,
3901 0, 0, pbn_b0_2_115200 },
3902 { /* IQ Express F2 */
3903 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3904 PCI_VENDOR_ID_MAINPINE, 0x3300,
3905 0, 0, pbn_b0_2_115200 },
3906 { /* IQ Express D4 */
3907 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3908 PCI_VENDOR_ID_MAINPINE, 0x3400,
3909 0, 0, pbn_b0_4_115200 },
3910 { /* IQ Express F4 */
3911 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3912 PCI_VENDOR_ID_MAINPINE, 0x3500,
3913 0, 0, pbn_b0_4_115200 },
3914 { /* IQ Express D8 */
3915 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3916 PCI_VENDOR_ID_MAINPINE, 0x3C00,
3917 0, 0, pbn_b0_8_115200 },
3918 { /* IQ Express F8 */
3919 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3920 PCI_VENDOR_ID_MAINPINE, 0x3D00,
3921 0, 0, pbn_b0_8_115200 },
3922
3923
3924 /*
3925 * PA Semi PA6T-1682M on-chip UART
3926 */
3927 { PCI_VENDOR_ID_PASEMI, 0xa004,
3928 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3929 pbn_pasemi_1682M },
3930
3931 /*
3932 * National Instruments
3933 */
3934 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
3935 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3936 pbn_b1_16_115200 },
3937 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
3938 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3939 pbn_b1_8_115200 },
3940 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
3941 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3942 pbn_b1_bt_4_115200 },
3943 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
3944 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3945 pbn_b1_bt_2_115200 },
3946 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
3947 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3948 pbn_b1_bt_4_115200 },
3949 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
3950 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3951 pbn_b1_bt_2_115200 },
3952 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
3953 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3954 pbn_b1_16_115200 },
3955 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
3956 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3957 pbn_b1_8_115200 },
3958 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
3959 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3960 pbn_b1_bt_4_115200 },
3961 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
3962 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3963 pbn_b1_bt_2_115200 },
3964 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
3965 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3966 pbn_b1_bt_4_115200 },
3967 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
3968 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3969 pbn_b1_bt_2_115200 },
3970 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
3971 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3972 pbn_ni8430_2 },
3973 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
3974 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3975 pbn_ni8430_2 },
3976 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
3977 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3978 pbn_ni8430_4 },
3979 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
3980 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3981 pbn_ni8430_4 },
3982 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
3983 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3984 pbn_ni8430_8 },
3985 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
3986 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3987 pbn_ni8430_8 },
3988 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
3989 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3990 pbn_ni8430_16 },
3991 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
3992 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3993 pbn_ni8430_16 },
3994 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
3995 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3996 pbn_ni8430_2 },
3997 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
3998 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3999 pbn_ni8430_2 },
4000 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
4001 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4002 pbn_ni8430_4 },
4003 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
4004 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4005 pbn_ni8430_4 },
4006
4007 /*
4008 * ADDI-DATA GmbH communication cards <info@addi-data.com>
4009 */
4010 { PCI_VENDOR_ID_ADDIDATA,
4011 PCI_DEVICE_ID_ADDIDATA_APCI7500,
4012 PCI_ANY_ID,
4013 PCI_ANY_ID,
4014 0,
4015 0,
4016 pbn_b0_4_115200 },
4017
4018 { PCI_VENDOR_ID_ADDIDATA,
4019 PCI_DEVICE_ID_ADDIDATA_APCI7420,
4020 PCI_ANY_ID,
4021 PCI_ANY_ID,
4022 0,
4023 0,
4024 pbn_b0_2_115200 },
4025
4026 { PCI_VENDOR_ID_ADDIDATA,
4027 PCI_DEVICE_ID_ADDIDATA_APCI7300,
4028 PCI_ANY_ID,
4029 PCI_ANY_ID,
4030 0,
4031 0,
4032 pbn_b0_1_115200 },
4033
4034 { PCI_VENDOR_ID_ADDIDATA_OLD,
4035 PCI_DEVICE_ID_ADDIDATA_APCI7800,
4036 PCI_ANY_ID,
4037 PCI_ANY_ID,
4038 0,
4039 0,
4040 pbn_b1_8_115200 },
4041
4042 { PCI_VENDOR_ID_ADDIDATA,
4043 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
4044 PCI_ANY_ID,
4045 PCI_ANY_ID,
4046 0,
4047 0,
4048 pbn_b0_4_115200 },
4049
4050 { PCI_VENDOR_ID_ADDIDATA,
4051 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
4052 PCI_ANY_ID,
4053 PCI_ANY_ID,
4054 0,
4055 0,
4056 pbn_b0_2_115200 },
4057
4058 { PCI_VENDOR_ID_ADDIDATA,
4059 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
4060 PCI_ANY_ID,
4061 PCI_ANY_ID,
4062 0,
4063 0,
4064 pbn_b0_1_115200 },
4065
4066 { PCI_VENDOR_ID_ADDIDATA,
4067 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
4068 PCI_ANY_ID,
4069 PCI_ANY_ID,
4070 0,
4071 0,
4072 pbn_b0_4_115200 },
4073
4074 { PCI_VENDOR_ID_ADDIDATA,
4075 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
4076 PCI_ANY_ID,
4077 PCI_ANY_ID,
4078 0,
4079 0,
4080 pbn_b0_2_115200 },
4081
4082 { PCI_VENDOR_ID_ADDIDATA,
4083 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
4084 PCI_ANY_ID,
4085 PCI_ANY_ID,
4086 0,
4087 0,
4088 pbn_b0_1_115200 },
4089
4090 { PCI_VENDOR_ID_ADDIDATA,
4091 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
4092 PCI_ANY_ID,
4093 PCI_ANY_ID,
4094 0,
4095 0,
4096 pbn_b0_8_115200 },
4097
4098 { PCI_VENDOR_ID_ADDIDATA,
4099 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
4100 PCI_ANY_ID,
4101 PCI_ANY_ID,
4102 0,
4103 0,
4104 pbn_ADDIDATA_PCIe_4_3906250 },
4105
4106 { PCI_VENDOR_ID_ADDIDATA,
4107 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
4108 PCI_ANY_ID,
4109 PCI_ANY_ID,
4110 0,
4111 0,
4112 pbn_ADDIDATA_PCIe_2_3906250 },
4113
4114 { PCI_VENDOR_ID_ADDIDATA,
4115 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
4116 PCI_ANY_ID,
4117 PCI_ANY_ID,
4118 0,
4119 0,
4120 pbn_ADDIDATA_PCIe_1_3906250 },
4121
4122 { PCI_VENDOR_ID_ADDIDATA,
4123 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
4124 PCI_ANY_ID,
4125 PCI_ANY_ID,
4126 0,
4127 0,
4128 pbn_ADDIDATA_PCIe_8_3906250 },
4129
4130 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
4131 PCI_VENDOR_ID_IBM, 0x0299,
4132 0, 0, pbn_b0_bt_2_115200 },
4133
4134 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
4135 0xA000, 0x1000,
4136 0, 0, pbn_b0_1_115200 },
4137
4138 /* the 9901 is a rebranded 9912 */
4139 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
4140 0xA000, 0x1000,
4141 0, 0, pbn_b0_1_115200 },
4142
4143 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
4144 0xA000, 0x1000,
4145 0, 0, pbn_b0_1_115200 },
4146
4147 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
4148 0xA000, 0x1000,
4149 0, 0, pbn_b0_1_115200 },
4150
4151 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
4152 0xA000, 0x1000,
4153 0, 0, pbn_b0_1_115200 },
4154
4155 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
4156 0xA000, 0x3002,
4157 0, 0, pbn_NETMOS9900_2s_115200 },
4158
4159 /*
4160 * Best Connectivity and Rosewill PCI Multi I/O cards
4161 */
4162
4163 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4164 0xA000, 0x1000,
4165 0, 0, pbn_b0_1_115200 },
4166
4167 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4168 0xA000, 0x3002,
4169 0, 0, pbn_b0_bt_2_115200 },
4170
4171 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4172 0xA000, 0x3004,
4173 0, 0, pbn_b0_bt_4_115200 },
4174 /* Intel CE4100 */
4175 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
4176 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4177 pbn_ce4100_1_115200 },
4178
4179 /*
4180 * Cronyx Omega PCI
4181 */
4182 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
4183 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4184 pbn_omegapci },
4185
4186 /*
4187 * These entries match devices with class COMMUNICATION_SERIAL,
4188 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
4189 */
4190 { PCI_ANY_ID, PCI_ANY_ID,
4191 PCI_ANY_ID, PCI_ANY_ID,
4192 PCI_CLASS_COMMUNICATION_SERIAL << 8,
4193 0xffff00, pbn_default },
4194 { PCI_ANY_ID, PCI_ANY_ID,
4195 PCI_ANY_ID, PCI_ANY_ID,
4196 PCI_CLASS_COMMUNICATION_MODEM << 8,
4197 0xffff00, pbn_default },
4198 { PCI_ANY_ID, PCI_ANY_ID,
4199 PCI_ANY_ID, PCI_ANY_ID,
4200 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
4201 0xffff00, pbn_default },
4202 { 0, }
4203 };
4204
4205 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
4206 pci_channel_state_t state)
4207 {
4208 struct serial_private *priv = pci_get_drvdata(dev);
4209
4210 if (state == pci_channel_io_perm_failure)
4211 return PCI_ERS_RESULT_DISCONNECT;
4212
4213 if (priv)
4214 pciserial_suspend_ports(priv);
4215
4216 pci_disable_device(dev);
4217
4218 return PCI_ERS_RESULT_NEED_RESET;
4219 }
4220
4221 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
4222 {
4223 int rc;
4224
4225 rc = pci_enable_device(dev);
4226
4227 if (rc)
4228 return PCI_ERS_RESULT_DISCONNECT;
4229
4230 pci_restore_state(dev);
4231 pci_save_state(dev);
4232
4233 return PCI_ERS_RESULT_RECOVERED;
4234 }
4235
4236 static void serial8250_io_resume(struct pci_dev *dev)
4237 {
4238 struct serial_private *priv = pci_get_drvdata(dev);
4239
4240 if (priv)
4241 pciserial_resume_ports(priv);
4242 }
4243
4244 static struct pci_error_handlers serial8250_err_handler = {
4245 .error_detected = serial8250_io_error_detected,
4246 .slot_reset = serial8250_io_slot_reset,
4247 .resume = serial8250_io_resume,
4248 };
4249
4250 static struct pci_driver serial_pci_driver = {
4251 .name = "serial",
4252 .probe = pciserial_init_one,
4253 .remove = __devexit_p(pciserial_remove_one),
4254 #ifdef CONFIG_PM
4255 .suspend = pciserial_suspend_one,
4256 .resume = pciserial_resume_one,
4257 #endif
4258 .id_table = serial_pci_tbl,
4259 .err_handler = &serial8250_err_handler,
4260 };
4261
4262 static int __init serial8250_pci_init(void)
4263 {
4264 return pci_register_driver(&serial_pci_driver);
4265 }
4266
4267 static void __exit serial8250_pci_exit(void)
4268 {
4269 pci_unregister_driver(&serial_pci_driver);
4270 }
4271
4272 module_init(serial8250_pci_init);
4273 module_exit(serial8250_pci_exit);
4274
4275 MODULE_LICENSE("GPL");
4276 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
4277 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
Linux ARM platform port for MOXA ART SoC