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initial commit with v3.6.7
[linux-3.6.7-moxart.git] / drivers / video / exynos / exynos_mipi_dsi_common.c
blob47b533a183be2979ede8a29bb9db0d89b0e309bb
1 /* linux/drivers/video/exynos/exynos_mipi_dsi_common.c
2 *
3 * Samsung SoC MIPI-DSI common driver.
4 *
5 * Copyright (c) 2012 Samsung Electronics Co., Ltd
6 *
7 * InKi Dae, <inki.dae@samsung.com>
8 * Donghwa Lee, <dh09.lee@samsung.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/errno.h>
18 #include <linux/mutex.h>
19 #include <linux/wait.h>
20 #include <linux/fs.h>
21 #include <linux/mm.h>
22 #include <linux/fb.h>
23 #include <linux/ctype.h>
24 #include <linux/platform_device.h>
25 #include <linux/io.h>
26 #include <linux/memory.h>
27 #include <linux/delay.h>
28 #include <linux/kthread.h>
29
30 #include <video/mipi_display.h>
31 #include <video/exynos_mipi_dsim.h>
32
33 #include <mach/map.h>
34
35 #include "exynos_mipi_dsi_regs.h"
36 #include "exynos_mipi_dsi_lowlevel.h"
37 #include "exynos_mipi_dsi_common.h"
38
39 #define MIPI_FIFO_TIMEOUT msecs_to_jiffies(250)
40 #define MIPI_RX_FIFO_READ_DONE 0x30800002
41 #define MIPI_MAX_RX_FIFO 20
42 #define MHZ (1000 * 1000)
43 #define FIN_HZ (24 * MHZ)
44
45 #define DFIN_PLL_MIN_HZ (6 * MHZ)
46 #define DFIN_PLL_MAX_HZ (12 * MHZ)
47
48 #define DFVCO_MIN_HZ (500 * MHZ)
49 #define DFVCO_MAX_HZ (1000 * MHZ)
50
51 #define TRY_GET_FIFO_TIMEOUT (5000 * 2)
52 #define TRY_FIFO_CLEAR (10)
53
54 /* MIPI-DSIM status types. */
55 enum {
56 DSIM_STATE_INIT, /* should be initialized. */
57 DSIM_STATE_STOP, /* CPU and LCDC are LP mode. */
58 DSIM_STATE_HSCLKEN, /* HS clock was enabled. */
59 DSIM_STATE_ULPS
60 };
61
62 /* define DSI lane types. */
63 enum {
64 DSIM_LANE_CLOCK = (1 << 0),
65 DSIM_LANE_DATA0 = (1 << 1),
66 DSIM_LANE_DATA1 = (1 << 2),
67 DSIM_LANE_DATA2 = (1 << 3),
68 DSIM_LANE_DATA3 = (1 << 4)
69 };
70
71 static unsigned int dpll_table[15] = {
72 100, 120, 170, 220, 270,
73 320, 390, 450, 510, 560,
74 640, 690, 770, 870, 950
75 };
76
77 irqreturn_t exynos_mipi_dsi_interrupt_handler(int irq, void *dev_id)
78 {
79 struct mipi_dsim_device *dsim = dev_id;
80 unsigned int intsrc, intmsk;
81
82 if (dsim == NULL) {
83 dev_err(dsim->dev, "%s: wrong parameter\n", __func__);
84 return IRQ_NONE;
85 }
86
87 intsrc = exynos_mipi_dsi_read_interrupt(dsim);
88 intmsk = exynos_mipi_dsi_read_interrupt_mask(dsim);
89 intmsk = ~intmsk & intsrc;
90
91 if (intsrc & INTMSK_RX_DONE) {
92 complete(&dsim_rd_comp);
93 dev_dbg(dsim->dev, "MIPI INTMSK_RX_DONE\n");
94 }
95 if (intsrc & INTMSK_FIFO_EMPTY) {
96 complete(&dsim_wr_comp);
97 dev_dbg(dsim->dev, "MIPI INTMSK_FIFO_EMPTY\n");
98 }
99
100 exynos_mipi_dsi_clear_interrupt(dsim, intmsk);
101
102 return IRQ_HANDLED;
103 }
104
105 /*
106 * write long packet to mipi dsi slave
107 * @dsim: mipi dsim device structure.
108 * @data0: packet data to send.
109 * @data1: size of packet data
110 */
111 static void exynos_mipi_dsi_long_data_wr(struct mipi_dsim_device *dsim,
112 const unsigned char *data0, unsigned int data_size)
113 {
114 unsigned int data_cnt = 0, payload = 0;
115
116 /* in case that data count is more then 4 */
117 for (data_cnt = 0; data_cnt < data_size; data_cnt += 4) {
118 /*
119 * after sending 4bytes per one time,
120 * send remainder data less then 4.
121 */
122 if ((data_size - data_cnt) < 4) {
123 if ((data_size - data_cnt) == 3) {
124 payload = data0[data_cnt] |
125 data0[data_cnt + 1] << 8 |
126 data0[data_cnt + 2] << 16;
127 dev_dbg(dsim->dev, "count = 3 payload = %x, %x %x %x\n",
128 payload, data0[data_cnt],
129 data0[data_cnt + 1],
130 data0[data_cnt + 2]);
131 } else if ((data_size - data_cnt) == 2) {
132 payload = data0[data_cnt] |
133 data0[data_cnt + 1] << 8;
134 dev_dbg(dsim->dev,
135 "count = 2 payload = %x, %x %x\n", payload,
136 data0[data_cnt],
137 data0[data_cnt + 1]);
138 } else if ((data_size - data_cnt) == 1) {
139 payload = data0[data_cnt];
140 }
141
142 exynos_mipi_dsi_wr_tx_data(dsim, payload);
143 /* send 4bytes per one time. */
144 } else {
145 payload = data0[data_cnt] |
146 data0[data_cnt + 1] << 8 |
147 data0[data_cnt + 2] << 16 |
148 data0[data_cnt + 3] << 24;
149
150 dev_dbg(dsim->dev,
151 "count = 4 payload = %x, %x %x %x %x\n",
152 payload, *(u8 *)(data0 + data_cnt),
153 data0[data_cnt + 1],
154 data0[data_cnt + 2],
155 data0[data_cnt + 3]);
156
157 exynos_mipi_dsi_wr_tx_data(dsim, payload);
158 }
159 }
160 }
161
162 int exynos_mipi_dsi_wr_data(struct mipi_dsim_device *dsim, unsigned int data_id,
163 const unsigned char *data0, unsigned int data_size)
164 {
165 unsigned int check_rx_ack = 0;
166
167 if (dsim->state == DSIM_STATE_ULPS) {
168 dev_err(dsim->dev, "state is ULPS.\n");
169
170 return -EINVAL;
171 }
172
173 /* FIXME!!! why does it need this delay? */
174 msleep(20);
175
176 mutex_lock(&dsim->lock);
177
178 switch (data_id) {
179 /* short packet types of packet types for command. */
180 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
181 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
182 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
183 case MIPI_DSI_DCS_SHORT_WRITE:
184 case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
185 case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
186 exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0[0], data0[1]);
187 if (check_rx_ack) {
188 /* process response func should be implemented */
189 mutex_unlock(&dsim->lock);
190 return 0;
191 } else {
192 mutex_unlock(&dsim->lock);
193 return -EINVAL;
194 }
195
196 /* general command */
197 case MIPI_DSI_COLOR_MODE_OFF:
198 case MIPI_DSI_COLOR_MODE_ON:
199 case MIPI_DSI_SHUTDOWN_PERIPHERAL:
200 case MIPI_DSI_TURN_ON_PERIPHERAL:
201 exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0[0], data0[1]);
202 if (check_rx_ack) {
203 /* process response func should be implemented. */
204 mutex_unlock(&dsim->lock);
205 return 0;
206 } else {
207 mutex_unlock(&dsim->lock);
208 return -EINVAL;
209 }
210
211 /* packet types for video data */
212 case MIPI_DSI_V_SYNC_START:
213 case MIPI_DSI_V_SYNC_END:
214 case MIPI_DSI_H_SYNC_START:
215 case MIPI_DSI_H_SYNC_END:
216 case MIPI_DSI_END_OF_TRANSMISSION:
217 mutex_unlock(&dsim->lock);
218 return 0;
219
220 /* long packet type and null packet */
221 case MIPI_DSI_NULL_PACKET:
222 case MIPI_DSI_BLANKING_PACKET:
223 mutex_unlock(&dsim->lock);
224 return 0;
225 case MIPI_DSI_GENERIC_LONG_WRITE:
226 case MIPI_DSI_DCS_LONG_WRITE:
227 {
228 unsigned int size, payload = 0;
229 INIT_COMPLETION(dsim_wr_comp);
230
231 size = data_size * 4;
232
233 /* if data count is less then 4, then send 3bytes data. */
234 if (data_size < 4) {
235 payload = data0[0] |
236 data0[1] << 8 |
237 data0[2] << 16;
238
239 exynos_mipi_dsi_wr_tx_data(dsim, payload);
240
241 dev_dbg(dsim->dev, "count = %d payload = %x,%x %x %x\n",
242 data_size, payload, data0[0],
243 data0[1], data0[2]);
244
245 /* in case that data count is more then 4 */
246 } else
247 exynos_mipi_dsi_long_data_wr(dsim, data0, data_size);
248
249 /* put data into header fifo */
250 exynos_mipi_dsi_wr_tx_header(dsim, data_id, data_size & 0xff,
251 (data_size & 0xff00) >> 8);
252
253 if (!wait_for_completion_interruptible_timeout(&dsim_wr_comp,
254 MIPI_FIFO_TIMEOUT)) {
255 dev_warn(dsim->dev, "command write timeout.\n");
256 mutex_unlock(&dsim->lock);
257 return -EAGAIN;
258 }
259
260 if (check_rx_ack) {
261 /* process response func should be implemented. */
262 mutex_unlock(&dsim->lock);
263 return 0;
264 } else {
265 mutex_unlock(&dsim->lock);
266 return -EINVAL;
267 }
268 }
269
270 /* packet typo for video data */
271 case MIPI_DSI_PACKED_PIXEL_STREAM_16:
272 case MIPI_DSI_PACKED_PIXEL_STREAM_18:
273 case MIPI_DSI_PIXEL_STREAM_3BYTE_18:
274 case MIPI_DSI_PACKED_PIXEL_STREAM_24:
275 if (check_rx_ack) {
276 /* process response func should be implemented. */
277 mutex_unlock(&dsim->lock);
278 return 0;
279 } else {
280 mutex_unlock(&dsim->lock);
281 return -EINVAL;
282 }
283 default:
284 dev_warn(dsim->dev,
285 "data id %x is not supported current DSI spec.\n",
286 data_id);
287
288 mutex_unlock(&dsim->lock);
289 return -EINVAL;
290 }
291
292 mutex_unlock(&dsim->lock);
293 return 0;
294 }
295
296 static unsigned int exynos_mipi_dsi_long_data_rd(struct mipi_dsim_device *dsim,
297 unsigned int req_size, unsigned int rx_data, u8 *rx_buf)
298 {
299 unsigned int rcv_pkt, i, j;
300 u16 rxsize;
301
302 /* for long packet */
303 rxsize = (u16)((rx_data & 0x00ffff00) >> 8);
304 dev_dbg(dsim->dev, "mipi dsi rx size : %d\n", rxsize);
305 if (rxsize != req_size) {
306 dev_dbg(dsim->dev,
307 "received size mismatch received: %d, requested: %d\n",
308 rxsize, req_size);
309 goto err;
310 }
311
312 for (i = 0; i < (rxsize >> 2); i++) {
313 rcv_pkt = exynos_mipi_dsi_rd_rx_fifo(dsim);
314 dev_dbg(dsim->dev, "received pkt : %08x\n", rcv_pkt);
315 for (j = 0; j < 4; j++) {
316 rx_buf[(i * 4) + j] =
317 (u8)(rcv_pkt >> (j * 8)) & 0xff;
318 dev_dbg(dsim->dev, "received value : %02x\n",
319 (rcv_pkt >> (j * 8)) & 0xff);
320 }
321 }
322 if (rxsize % 4) {
323 rcv_pkt = exynos_mipi_dsi_rd_rx_fifo(dsim);
324 dev_dbg(dsim->dev, "received pkt : %08x\n", rcv_pkt);
325 for (j = 0; j < (rxsize % 4); j++) {
326 rx_buf[(i * 4) + j] =
327 (u8)(rcv_pkt >> (j * 8)) & 0xff;
328 dev_dbg(dsim->dev, "received value : %02x\n",
329 (rcv_pkt >> (j * 8)) & 0xff);
330 }
331 }
332
333 return rxsize;
334
335 err:
336 return -EINVAL;
337 }
338
339 static unsigned int exynos_mipi_dsi_response_size(unsigned int req_size)
340 {
341 switch (req_size) {
342 case 1:
343 return MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE;
344 case 2:
345 return MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE;
346 default:
347 return MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE;
348 }
349 }
350
351 int exynos_mipi_dsi_rd_data(struct mipi_dsim_device *dsim, unsigned int data_id,
352 unsigned int data0, unsigned int req_size, u8 *rx_buf)
353 {
354 unsigned int rx_data, rcv_pkt, i;
355 u8 response = 0;
356 u16 rxsize;
357
358 if (dsim->state == DSIM_STATE_ULPS) {
359 dev_err(dsim->dev, "state is ULPS.\n");
360
361 return -EINVAL;
362 }
363
364 /* FIXME!!! */
365 msleep(20);
366
367 mutex_lock(&dsim->lock);
368 INIT_COMPLETION(dsim_rd_comp);
369 exynos_mipi_dsi_rd_tx_header(dsim,
370 MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, req_size);
371
372 response = exynos_mipi_dsi_response_size(req_size);
373
374 switch (data_id) {
375 case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
376 case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
377 case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
378 case MIPI_DSI_DCS_READ:
379 exynos_mipi_dsi_rd_tx_header(dsim,
380 data_id, data0);
381 /* process response func should be implemented. */
382 break;
383 default:
384 dev_warn(dsim->dev,
385 "data id %x is not supported current DSI spec.\n",
386 data_id);
387
388 return -EINVAL;
389 }
390
391 if (!wait_for_completion_interruptible_timeout(&dsim_rd_comp,
392 MIPI_FIFO_TIMEOUT)) {
393 pr_err("RX done interrupt timeout\n");
394 mutex_unlock(&dsim->lock);
395 return 0;
396 }
397
398 msleep(20);
399
400 rx_data = exynos_mipi_dsi_rd_rx_fifo(dsim);
401
402 if ((u8)(rx_data & 0xff) != response) {
403 printk(KERN_ERR
404 "mipi dsi wrong response rx_data : %x, response:%x\n",
405 rx_data, response);
406 goto clear_rx_fifo;
407 }
408
409 if (req_size <= 2) {
410 /* for short packet */
411 for (i = 0; i < req_size; i++)
412 rx_buf[i] = (rx_data >> (8 + (i * 8))) & 0xff;
413 rxsize = req_size;
414 } else {
415 /* for long packet */
416 rxsize = exynos_mipi_dsi_long_data_rd(dsim, req_size, rx_data,
417 rx_buf);
418 if (rxsize != req_size)
419 goto clear_rx_fifo;
420 }
421
422 rcv_pkt = exynos_mipi_dsi_rd_rx_fifo(dsim);
423
424 msleep(20);
425
426 if (rcv_pkt != MIPI_RX_FIFO_READ_DONE) {
427 dev_info(dsim->dev,
428 "Can't found RX FIFO READ DONE FLAG : %x\n", rcv_pkt);
429 goto clear_rx_fifo;
430 }
431
432 mutex_unlock(&dsim->lock);
433
434 return rxsize;
435
436 clear_rx_fifo:
437 i = 0;
438 while (1) {
439 rcv_pkt = exynos_mipi_dsi_rd_rx_fifo(dsim);
440 if ((rcv_pkt == MIPI_RX_FIFO_READ_DONE)
441 || (i > MIPI_MAX_RX_FIFO))
442 break;
443 dev_dbg(dsim->dev,
444 "mipi dsi clear rx fifo : %08x\n", rcv_pkt);
445 i++;
446 }
447 dev_info(dsim->dev,
448 "mipi dsi rx done count : %d, rcv_pkt : %08x\n", i, rcv_pkt);
449
450 mutex_unlock(&dsim->lock);
451
452 return 0;
453 }
454
455 static int exynos_mipi_dsi_pll_on(struct mipi_dsim_device *dsim,
456 unsigned int enable)
457 {
458 int sw_timeout;
459
460 if (enable) {
461 sw_timeout = 1000;
462
463 exynos_mipi_dsi_enable_pll(dsim, 1);
464 while (1) {
465 sw_timeout--;
466 if (exynos_mipi_dsi_is_pll_stable(dsim))
467 return 0;
468 if (sw_timeout == 0)
469 return -EINVAL;
470 }
471 } else
472 exynos_mipi_dsi_enable_pll(dsim, 0);
473
474 return 0;
475 }
476
477 static unsigned long exynos_mipi_dsi_change_pll(struct mipi_dsim_device *dsim,
478 unsigned int pre_divider, unsigned int main_divider,
479 unsigned int scaler)
480 {
481 unsigned long dfin_pll, dfvco, dpll_out;
482 unsigned int i, freq_band = 0xf;
483
484 dfin_pll = (FIN_HZ / pre_divider);
485
486 /******************************************************
487 * Serial Clock(=ByteClk X 8) FreqBand[3:0] *
488 ******************************************************
489 * ~ 99.99 MHz 0000
490 * 100 ~ 119.99 MHz 0001
491 * 120 ~ 159.99 MHz 0010
492 * 160 ~ 199.99 MHz 0011
493 * 200 ~ 239.99 MHz 0100
494 * 140 ~ 319.99 MHz 0101
495 * 320 ~ 389.99 MHz 0110
496 * 390 ~ 449.99 MHz 0111
497 * 450 ~ 509.99 MHz 1000
498 * 510 ~ 559.99 MHz 1001
499 * 560 ~ 639.99 MHz 1010
500 * 640 ~ 689.99 MHz 1011
501 * 690 ~ 769.99 MHz 1100
502 * 770 ~ 869.99 MHz 1101
503 * 870 ~ 949.99 MHz 1110
504 * 950 ~ 1000 MHz 1111
505 ******************************************************/
506 if (dfin_pll < DFIN_PLL_MIN_HZ || dfin_pll > DFIN_PLL_MAX_HZ) {
507 dev_warn(dsim->dev, "fin_pll range should be 6MHz ~ 12MHz\n");
508 exynos_mipi_dsi_enable_afc(dsim, 0, 0);
509 } else {
510 if (dfin_pll < 7 * MHZ)
511 exynos_mipi_dsi_enable_afc(dsim, 1, 0x1);
512 else if (dfin_pll < 8 * MHZ)
513 exynos_mipi_dsi_enable_afc(dsim, 1, 0x0);
514 else if (dfin_pll < 9 * MHZ)
515 exynos_mipi_dsi_enable_afc(dsim, 1, 0x3);
516 else if (dfin_pll < 10 * MHZ)
517 exynos_mipi_dsi_enable_afc(dsim, 1, 0x2);
518 else if (dfin_pll < 11 * MHZ)
519 exynos_mipi_dsi_enable_afc(dsim, 1, 0x5);
520 else
521 exynos_mipi_dsi_enable_afc(dsim, 1, 0x4);
522 }
523
524 dfvco = dfin_pll * main_divider;
525 dev_dbg(dsim->dev, "dfvco = %lu, dfin_pll = %lu, main_divider = %d\n",
526 dfvco, dfin_pll, main_divider);
527 if (dfvco < DFVCO_MIN_HZ || dfvco > DFVCO_MAX_HZ)
528 dev_warn(dsim->dev, "fvco range should be 500MHz ~ 1000MHz\n");
529
530 dpll_out = dfvco / (1 << scaler);
531 dev_dbg(dsim->dev, "dpll_out = %lu, dfvco = %lu, scaler = %d\n",
532 dpll_out, dfvco, scaler);
533
534 for (i = 0; i < ARRAY_SIZE(dpll_table); i++) {
535 if (dpll_out < dpll_table[i] * MHZ) {
536 freq_band = i;
537 break;
538 }
539 }
540
541 dev_dbg(dsim->dev, "freq_band = %d\n", freq_band);
542
543 exynos_mipi_dsi_pll_freq(dsim, pre_divider, main_divider, scaler);
544
545 exynos_mipi_dsi_hs_zero_ctrl(dsim, 0);
546 exynos_mipi_dsi_prep_ctrl(dsim, 0);
547
548 /* Freq Band */
549 exynos_mipi_dsi_pll_freq_band(dsim, freq_band);
550
551 /* Stable time */
552 exynos_mipi_dsi_pll_stable_time(dsim, dsim->dsim_config->pll_stable_time);
553
554 /* Enable PLL */
555 dev_dbg(dsim->dev, "FOUT of mipi dphy pll is %luMHz\n",
556 (dpll_out / MHZ));
557
558 return dpll_out;
559 }
560
561 static int exynos_mipi_dsi_set_clock(struct mipi_dsim_device *dsim,
562 unsigned int byte_clk_sel, unsigned int enable)
563 {
564 unsigned int esc_div;
565 unsigned long esc_clk_error_rate;
566 unsigned long hs_clk = 0, byte_clk = 0, escape_clk = 0;
567
568 if (enable) {
569 dsim->e_clk_src = byte_clk_sel;
570
571 /* Escape mode clock and byte clock source */
572 exynos_mipi_dsi_set_byte_clock_src(dsim, byte_clk_sel);
573
574 /* DPHY, DSIM Link : D-PHY clock out */
575 if (byte_clk_sel == DSIM_PLL_OUT_DIV8) {
576 hs_clk = exynos_mipi_dsi_change_pll(dsim,
577 dsim->dsim_config->p, dsim->dsim_config->m,
578 dsim->dsim_config->s);
579 if (hs_clk == 0) {
580 dev_err(dsim->dev,
581 "failed to get hs clock.\n");
582 return -EINVAL;
583 }
584
585 byte_clk = hs_clk / 8;
586 exynos_mipi_dsi_enable_pll_bypass(dsim, 0);
587 exynos_mipi_dsi_pll_on(dsim, 1);
588 /* DPHY : D-PHY clock out, DSIM link : external clock out */
589 } else if (byte_clk_sel == DSIM_EXT_CLK_DIV8) {
590 dev_warn(dsim->dev, "this project is not support\n");
591 dev_warn(dsim->dev,
592 "external clock source for MIPI DSIM.\n");
593 } else if (byte_clk_sel == DSIM_EXT_CLK_BYPASS) {
594 dev_warn(dsim->dev, "this project is not support\n");
595 dev_warn(dsim->dev,
596 "external clock source for MIPI DSIM\n");
597 }
598
599 /* escape clock divider */
600 esc_div = byte_clk / (dsim->dsim_config->esc_clk);
601 dev_dbg(dsim->dev,
602 "esc_div = %d, byte_clk = %lu, esc_clk = %lu\n",
603 esc_div, byte_clk, dsim->dsim_config->esc_clk);
604 if ((byte_clk / esc_div) >= (20 * MHZ) ||
605 (byte_clk / esc_div) >
606 dsim->dsim_config->esc_clk)
607 esc_div += 1;
608
609 escape_clk = byte_clk / esc_div;
610 dev_dbg(dsim->dev,
611 "escape_clk = %lu, byte_clk = %lu, esc_div = %d\n",
612 escape_clk, byte_clk, esc_div);
613
614 /* enable escape clock. */
615 exynos_mipi_dsi_enable_byte_clock(dsim, 1);
616
617 /* enable byte clk and escape clock */
618 exynos_mipi_dsi_set_esc_clk_prs(dsim, 1, esc_div);
619 /* escape clock on lane */
620 exynos_mipi_dsi_enable_esc_clk_on_lane(dsim,
621 (DSIM_LANE_CLOCK | dsim->data_lane), 1);
622
623 dev_dbg(dsim->dev, "byte clock is %luMHz\n",
624 (byte_clk / MHZ));
625 dev_dbg(dsim->dev, "escape clock that user's need is %lu\n",
626 (dsim->dsim_config->esc_clk / MHZ));
627 dev_dbg(dsim->dev, "escape clock divider is %x\n", esc_div);
628 dev_dbg(dsim->dev, "escape clock is %luMHz\n",
629 ((byte_clk / esc_div) / MHZ));
630
631 if ((byte_clk / esc_div) > escape_clk) {
632 esc_clk_error_rate = escape_clk /
633 (byte_clk / esc_div);
634 dev_warn(dsim->dev, "error rate is %lu over.\n",
635 (esc_clk_error_rate / 100));
636 } else if ((byte_clk / esc_div) < (escape_clk)) {
637 esc_clk_error_rate = (byte_clk / esc_div) /
638 escape_clk;
639 dev_warn(dsim->dev, "error rate is %lu under.\n",
640 (esc_clk_error_rate / 100));
641 }
642 } else {
643 exynos_mipi_dsi_enable_esc_clk_on_lane(dsim,
644 (DSIM_LANE_CLOCK | dsim->data_lane), 0);
645 exynos_mipi_dsi_set_esc_clk_prs(dsim, 0, 0);
646
647 /* disable escape clock. */
648 exynos_mipi_dsi_enable_byte_clock(dsim, 0);
649
650 if (byte_clk_sel == DSIM_PLL_OUT_DIV8)
651 exynos_mipi_dsi_pll_on(dsim, 0);
652 }
653
654 return 0;
655 }
656
657 int exynos_mipi_dsi_init_dsim(struct mipi_dsim_device *dsim)
658 {
659 dsim->state = DSIM_STATE_INIT;
660
661 switch (dsim->dsim_config->e_no_data_lane) {
662 case DSIM_DATA_LANE_1:
663 dsim->data_lane = DSIM_LANE_DATA0;
664 break;
665 case DSIM_DATA_LANE_2:
666 dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1;
667 break;
668 case DSIM_DATA_LANE_3:
669 dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1 |
670 DSIM_LANE_DATA2;
671 break;
672 case DSIM_DATA_LANE_4:
673 dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1 |
674 DSIM_LANE_DATA2 | DSIM_LANE_DATA3;
675 break;
676 default:
677 dev_info(dsim->dev, "data lane is invalid.\n");
678 return -EINVAL;
679 };
680
681 exynos_mipi_dsi_sw_reset(dsim);
682 exynos_mipi_dsi_func_reset(dsim);
683
684 exynos_mipi_dsi_dp_dn_swap(dsim, 0);
685
686 return 0;
687 }
688
689 void exynos_mipi_dsi_init_interrupt(struct mipi_dsim_device *dsim)
690 {
691 unsigned int src = 0;
692
693 src = (INTSRC_SFR_FIFO_EMPTY | INTSRC_RX_DATA_DONE);
694 exynos_mipi_dsi_set_interrupt(dsim, src, 1);
695
696 src = 0;
697 src = ~(INTMSK_RX_DONE | INTMSK_FIFO_EMPTY);
698 exynos_mipi_dsi_set_interrupt_mask(dsim, src, 1);
699 }
700
701 int exynos_mipi_dsi_enable_frame_done_int(struct mipi_dsim_device *dsim,
702 unsigned int enable)
703 {
704 /* enable only frame done interrupt */
705 exynos_mipi_dsi_set_interrupt_mask(dsim, INTMSK_FRAME_DONE, enable);
706
707 return 0;
708 }
709
710 void exynos_mipi_dsi_stand_by(struct mipi_dsim_device *dsim,
711 unsigned int enable)
712 {
713
714 /* consider Main display and Sub display. */
715
716 exynos_mipi_dsi_set_main_stand_by(dsim, enable);
717 }
718
719 int exynos_mipi_dsi_set_display_mode(struct mipi_dsim_device *dsim,
720 struct mipi_dsim_config *dsim_config)
721 {
722 struct mipi_dsim_platform_data *dsim_pd;
723 struct fb_videomode *timing;
724
725 dsim_pd = (struct mipi_dsim_platform_data *)dsim->pd;
726 timing = (struct fb_videomode *)dsim_pd->lcd_panel_info;
727
728 /* in case of VIDEO MODE (RGB INTERFACE), it sets polarities. */
729 if (dsim_config->e_interface == (u32) DSIM_VIDEO) {
730 if (dsim_config->auto_vertical_cnt == 0) {
731 exynos_mipi_dsi_set_main_disp_vporch(dsim,
732 dsim_config->cmd_allow,
733 timing->lower_margin,
734 timing->upper_margin);
735 exynos_mipi_dsi_set_main_disp_hporch(dsim,
736 timing->right_margin,
737 timing->left_margin);
738 exynos_mipi_dsi_set_main_disp_sync_area(dsim,
739 timing->vsync_len,
740 timing->hsync_len);
741 }
742 }
743
744 exynos_mipi_dsi_set_main_disp_resol(dsim, timing->xres,
745 timing->yres);
746
747 exynos_mipi_dsi_display_config(dsim, dsim_config);
748
749 dev_info(dsim->dev, "lcd panel ==> width = %d, height = %d\n",
750 timing->xres, timing->yres);
751
752 return 0;
753 }
754
755 int exynos_mipi_dsi_init_link(struct mipi_dsim_device *dsim)
756 {
757 unsigned int time_out = 100;
758
759 switch (dsim->state) {
760 case DSIM_STATE_INIT:
761 exynos_mipi_dsi_init_fifo_pointer(dsim, 0x1f);
762
763 /* dsi configuration */
764 exynos_mipi_dsi_init_config(dsim);
765 exynos_mipi_dsi_enable_lane(dsim, DSIM_LANE_CLOCK, 1);
766 exynos_mipi_dsi_enable_lane(dsim, dsim->data_lane, 1);
767
768 /* set clock configuration */
769 exynos_mipi_dsi_set_clock(dsim, dsim->dsim_config->e_byte_clk, 1);
770
771 /* check clock and data lane state are stop state */
772 while (!(exynos_mipi_dsi_is_lane_state(dsim))) {
773 time_out--;
774 if (time_out == 0) {
775 dev_err(dsim->dev,
776 "DSI Master is not stop state.\n");
777 dev_err(dsim->dev,
778 "Check initialization process\n");
779
780 return -EINVAL;
781 }
782 }
783 if (time_out != 0) {
784 dev_info(dsim->dev,
785 "DSI Master driver has been completed.\n");
786 dev_info(dsim->dev, "DSI Master state is stop state\n");
787 }
788
789 dsim->state = DSIM_STATE_STOP;
790
791 /* BTA sequence counters */
792 exynos_mipi_dsi_set_stop_state_counter(dsim,
793 dsim->dsim_config->stop_holding_cnt);
794 exynos_mipi_dsi_set_bta_timeout(dsim,
795 dsim->dsim_config->bta_timeout);
796 exynos_mipi_dsi_set_lpdr_timeout(dsim,
797 dsim->dsim_config->rx_timeout);
798
799 return 0;
800 default:
801 dev_info(dsim->dev, "DSI Master is already init.\n");
802 return 0;
803 }
804
805 return 0;
806 }
807
808 int exynos_mipi_dsi_set_hs_enable(struct mipi_dsim_device *dsim)
809 {
810 if (dsim->state != DSIM_STATE_STOP) {
811 dev_warn(dsim->dev, "DSIM is not in stop state.\n");
812 return 0;
813 }
814
815 if (dsim->e_clk_src == DSIM_EXT_CLK_BYPASS) {
816 dev_warn(dsim->dev, "clock source is external bypass.\n");
817 return 0;
818 }
819
820 dsim->state = DSIM_STATE_HSCLKEN;
821
822 /* set LCDC and CPU transfer mode to HS. */
823 exynos_mipi_dsi_set_lcdc_transfer_mode(dsim, 0);
824 exynos_mipi_dsi_set_cpu_transfer_mode(dsim, 0);
825 exynos_mipi_dsi_enable_hs_clock(dsim, 1);
826
827 return 0;
828 }
829
830 int exynos_mipi_dsi_set_data_transfer_mode(struct mipi_dsim_device *dsim,
831 unsigned int mode)
832 {
833 if (mode) {
834 if (dsim->state != DSIM_STATE_HSCLKEN) {
835 dev_err(dsim->dev, "HS Clock lane is not enabled.\n");
836 return -EINVAL;
837 }
838
839 exynos_mipi_dsi_set_lcdc_transfer_mode(dsim, 0);
840 } else {
841 if (dsim->state == DSIM_STATE_INIT || dsim->state ==
842 DSIM_STATE_ULPS) {
843 dev_err(dsim->dev,
844 "DSI Master is not STOP or HSDT state.\n");
845 return -EINVAL;
846 }
847
848 exynos_mipi_dsi_set_cpu_transfer_mode(dsim, 0);
849 }
850
851 return 0;
852 }
853
854 int exynos_mipi_dsi_get_frame_done_status(struct mipi_dsim_device *dsim)
855 {
856 return _exynos_mipi_dsi_get_frame_done_status(dsim);
857 }
858
859 int exynos_mipi_dsi_clear_frame_done(struct mipi_dsim_device *dsim)
860 {
861 _exynos_mipi_dsi_clear_frame_done(dsim);
862
863 return 0;
864 }
865
866 int exynos_mipi_dsi_fifo_clear(struct mipi_dsim_device *dsim,
867 unsigned int val)
868 {
869 int try = TRY_FIFO_CLEAR;
870
871 exynos_mipi_dsi_sw_reset_release(dsim);
872 exynos_mipi_dsi_func_reset(dsim);
873
874 do {
875 if (exynos_mipi_dsi_get_sw_reset_release(dsim)) {
876 exynos_mipi_dsi_init_interrupt(dsim);
877 dev_dbg(dsim->dev, "reset release done.\n");
878 return 0;
879 }
880 } while (--try);
881
882 dev_err(dsim->dev, "failed to clear dsim fifo.\n");
883 return -EAGAIN;
884 }
885
886 MODULE_AUTHOR("InKi Dae <inki.dae@samsung.com>");
887 MODULE_DESCRIPTION("Samusung SoC MIPI-DSI common driver");
888 MODULE_LICENSE("GPL");
Linux ARM platform port for MOXA ART SoC